Anpec APW7046 Dual advanced pwm and source-sink linear controller Datasheet

APW7046
Dual Advanced PWM and Source-Sink Linear Controller
Features
General Description
•
The APW7046 provides the power controls and protec-
3 Regulated Voltages are provided
tions for three output voltages on AGP/PCI Graphic Card
applications. It integrates two PWM controllers , one
− Standard Buck Converter for VCORE
(1.15~1.50V)
SOURCE-SINK linear controller, as well as the monitor
and protection functions into a single package. One PWM
− Standard Buck Converter for VMEM
converter (PWM1) supplies the VCORE(1.5V) for the GPU
with a standard buck converter. The other standard buck
(2.40~3.15V)
−Linear Controller with SOURCE-SINK Regul-
converter (PWM2) regulates the VMEM(2.5V) for the power of DDR memory. The SOURCE-SINK linear controller
ation for VTT(1.25V)
•
control two external MOSFETs to be a linear regulator
with the capability of sourcing and sinking current. It reg-
Simple Single-Loop Control Design
− Voltage-Mode PWM Control
•
ulates the VTT (1.25V) power for DDR Termination voltage.
Excellent Output Voltage Regulation
Additional built-in over-voltage protection (OVP) will be
− VCORE Output : ±1% Over Temperature
− VMEM Output : ±1.5% Over Temperature
− VTT Output : 1/2 VIN ±25mV Over Tempera-
started when the VCORE or VMEM output is above 115%
of each DAC setting (VCORE and VMEM). OVP function will
shutdown the all output voltages until re-powering on the
IC. For each PWM converter, the over-current function
monitors the output current by sensing the voltage drop
ture Min. VIN = 1.7V
•
Fast Transient Response
across the MOSFET‘s rDS(ON) , eliminating the need for a
current sensing resistor.
− Built-in Feedback Compensation
− Full 0% to 100% Duty Ratio
•
•
•
Pin Description
Over-Voltage and Over-Current Fault Monitor
Constant Frequency Operation(200kHz)
24 pins, SOIC Package
VCC
Applications
•
•
•
M/B DDR Power Regulation
AGP/PCI Graphics Power Regulation
SSTL-2 Termination
1
24 BOOT
UGATE 1 2
23 UGATE 2
PHASE1 3
22 PHASE2
SS
4
21 PG ND
SD
5
20 MEM2
SO URCE 6
19 MEM1
SINK
7
18 MEM0
FB
8
17 CORE2
VIN
9
16 CORE1
OCSET1 10
15 CORE0
VSE N1 11
GND 12
14 OCSET2
13 VSE N2
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev.A.2 - Mar., 2002
1
www.anpec.com.tw
APW7046
Ordering and Marking Information
V o lta g e C o d e
A : V C O R E (1 .1 5 ~ 1 .5 0 V ) V M E M (2 .4 0 ~ 2 .7 5 V )
B : V C O R E (1 .1 5 ~ 1 .5 0 V ) V M E M (2 .8 0 ~ 3 .1 5 V )
P ackage Code
K : S O P -2 4
Tem p. R ange
C : 0 to 7 0 ° C
H a n d lin g C o d e
TU : Tube
TR : Tape & Reel
L e a d F re e C o d e
L : L e a d F re e D e v ic e
B la n k : O rig in a l D e v ic e
APW 7046
L e a d F re e C o d e
H a n d lin g C o d e
Tem p. R ange
P ackage Code
V o lta g e C o d e
A PW 7046K :
X X X X X - D a te C o d e
A PW 7046
XXXXX
Block Diagram
VCC
SS
O CSET1
BO OT
200µA
VCC
OC1
28µ A
IN H IB IT
PW M1
P ow er O n
R eset
G a te
C o n tro l
115%
V c o re
4 .5 V
OVP1
UG ATE1
PHASE1
VSEN1
SD
V
EA1
T h e rm a l
P r o t e c t io n
S o ft- S ta rt a n d
F a u lt L o g ic
CO RE
T T L D /A
C o n v e rte r
M EM
T T L D /A
C o n v e rte r
VSEN2
EA2
O s c illa t o r
V
IN H IB IT
M EM 0
M EM 1
M EM 2
BO OT
SOURCE
PW M2
OVP2
IN H IB IT
G a te
C o n tro l
UG ATE2
115%
V MEM
FB
S IN K
CORE0
CORE1
CORE2
PGND
OC2
50%
R e s is t o r
D iv id e r
PHASE2
GND
200uA
B u ffe r
V IN
O CSET2
Absolute Maximum Ratings
Symbol
VCC
VI , VO
Parameter
Supply Voltage
Input , Output or I/O Voltage
Rating
Unit
15
V
GND -0.3 V to VCC +0.3
V
TA
Operating Ambient Temperature
Range 0 to 70
°C
TJ
Junction Temperature
Range 0 to 125
°C
TSTG
Storage Temperature
Range -65 to +150
°C
300 ,10 seconds
°C
TS
Soldering Temperature
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
2
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APW7046
Thermal Characteristics
Symbol
R JA
Parameter
Thermal Resistance in Free Air
SOIC
SOIC (with 3in2 of Copper)
Value
Unit
75
65
°C/W
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=VBOOT=12V and TA=0~70°C.
Typical values refer to TA=25°C.
Sym bol
Param eter
Test Conditions
M in.
A PW 7046
Typ.
M ax.
U nit
Supply C urrent
IC C
I C C SD
N om inal S upply C urrent
SD =0V, UG ATE1,UG ATE 2
, SO U RC E, and SIN K O pen
Shutdow n Supply C urrent
SD =5V
2.7
R ising VC C Threshold
Vocset=3V
4.2
Falling VC C Threshold
Vocset=3V
8
mA
Power-on Reset
SD Input High Voltage
4.6
V
3.6
V
2.0
V
SD Input Low Voltage
0.8
V
215
kH z
O scillator
F O SC
Free Running Frequency
185
∆V O SC R am p Am plitude
PW M Controller R eference Voltage
PW M 1 R eference Voltage
V CORE
Accuracy
C O R E0-C O R E2 Input H igh
Voltage
C O R E0-C O R E2 Input Low
Voltage
PW M 2 R eference Voltage
V M EM
Accuracy
M EM 0-M EM 2 Input H igh
Voltage
M EM 0-M EM 2 Input Low
Voltage
SO U RC E-SIN K Linear Controller
V FB
FB R egulation Voltage
1.9
V
-1
+1
2.0
0.8
V
+1.5
%
2.0
V
0.8
R egulator Sourcing or Sinking
C urrent
0.5VIN
-25
3
%
V
-1.5
V F B accuracy
M ax. SO U RC E Pin Drive
C urrent
M ax. S IN K Pin D rive Current
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
200
V
V
+25
mV
¡0
Ó.8
mA
¡0
Ó.8
mA
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APW7046
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC=VBOOT=12V and TA=0~70°C.
Typical values refer to TA=25°C.
Symbol
Parameter
IVIN
VIN Input Bias Current
PWM Controllers Gate Drivers
Test Conditions
Min.
VIN=2.5V
IUGATE
UGATE1,2 Source
VCC=VBOOT=12V,
VUGATE1,2=6V
RGATE
UGATE Sink
VCC=12V,VUGATE1,2=6V
APW7046
Typ. Max.
2
0.74
Unit
uA
A
3
4
115
120
Ω
Protection
VSEN1,2 OVP trip point
(VSEN1/VCORE and VSEN2/VMEM )
VSEN1,2 O.V. Hysteresis
IOCSET
ISS
Ocset Current Source
VSEN Rising
%
2
Vocset=3V
Soft start Current
170
200
28
230
uA
Functional Pin Description
VCC (Pin 1)
Provide a +12V bias supply for the IC to this pin. This
pin also provides the gate bias charge for the
MOSFETs of the SOURCE-SINK regulator. The voltage at this pin is monitored for Power-On Reset (POR)
purposes.
sets the soft-start interval of all power controls and
preventing the outputs from overshoot as well as limiting the input current .
UGATE1 (Pin 2)
Connect this pin to the MOSFET gate of the PWM1
converter. This pin provides the gate drive for the
MOSFET.
SD (Pin 5)
The pin shuts down all power outputs. A TTL compatible , logic level high signal applied at this pin immediately discharges the soft-start capacitor,disabling all
power outputs. When re-enabled, the IC undergoes a
new soft-start cycle. Left open, this pin is pulled low
by an internal pull-down resistor, enabling operation.
PHASE1 (Pin 3)
Connect this pin to the PWM1 converter’s MOSFET
source.This pin is used to monitor the voltage drop
across the MOSFET for over-current protection.
SOURCE (Pin 6)
Connect this pin to the upper MOSFET gate drive of
the SOURCE-SINK regulator. This pin drives the upper external MOSFET as a sourcing regulator.
SS (Pin 4)
Connect a capacitor from this pin to ground.This
capacitor, along with an internal 28uA current source,
SINK (Pin 7)
Connect this pin to the lower MOSFET gate drive of
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
4
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APW7046
Functional Pin Description (Cont.)
the SOURCE-SINK regulator. This pin drives the lower
external MOSFET as a sinking regulator.
GND (Pin 12)
Signal ground for the IC. All voltage levels are measured with respect to this pin.
FB (Pin 8)
Connect this pin to output of the SOURCE-SINK
regulator. This pin provides the voltage feedback path
for the sourcing and sinking regulators. This pin is internally connected to the negative input of the SOURCE
controller, and also connected to the positive input of
the SINK controller.
VSEN2 (Pin 13)
This pin is connected to the PWM2 converter’s output
voltage to provide the voltage feedback path. The overvoltage protection(OVP) comparator uses this pin to
monitor the output voltage for over- voltage protection.
OCSET2 (Pin 14)
VIN (Pin 9)
Connect this pin to VMEM or a fixed voltage source.
Two voltages, about 0.5VIN, are generated by an internal resistor divider as the reference voltages of the sourcing and sinking regulators. The sinking regulation voltage is higher than the sourcing one to prevent a direct
current path through the upper and lower MOSFETs.
Connect a resistor (ROCSET ) from this pin to the drain of
the PWM2 converter’s MOSFET. The function of this pin is
similar to OCSET1(pin 10) for OC detection and POR
purposes.
CORE0-2 (Pin 15-17)
CORE0-2 are TTL-compatible logic level input pins to
the 3-bit DAC. The states of the three pins set the
internal reference voltage (VCORE) for the PWM1 con-
OCSET1 (Pin 10)
Connect a resistor (ROCSET ) from this pin to the drain of
the PWM1 converter’s MOSFET. ROCSET, an internal
200uA current source (IOCSET ), and the MOSFET’s onresistance(rDS(ON)) set the converter’s over-current (OC)
trip point according to the following equation:
IPEAK =
verter and also set the OVP threshold voltage for
PWM1 converter.
MEM0-2 (Pin 18-20)
MEM0-2 are TTL-compatible logic level input pins to
the other 3-bit DAC. The states of the three pins set
the internal reference voltage (VMEM) for the PWM2
converter and also set the OVP threshold voltage for
PWM2 converter.
I OCSET x RO CS ET
r DS( ON)
An over-current trip cycles the soft-start function. The
voltage at this pin is monitored for Power-On Reset
(POR) purposes.
PGND (Pin 21)
Connect this pin to the anode of the flywheel diodes
of the two PWM converters.
VSEN1 (Pin 11)
This pin is connected to the PWM1 converter’s output
voltage to provide the voltage feedback path. The overvoltage protection(OVP) comparator uses this pin to
monitor the output voltage for over- voltage protection
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
PHASE2 (Pin 22)
Connect this pin to the PWM2 converter’s MOSFET
source.This pin is used to monitor the voltage drop
across the MOSFET for over-current protection.
5
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APW7046
Functional Pin Description
UGATE2 (Pin 23)
Connect this pin to the MOSFET gate of the PWM2
converter. This pin provides the gate drive for the
MOSFET.
BOOT (Pin 24)
Connect this pin to +12V. This pin provides bias voltage to the MOSFET drivers.
Table 1 DAC Table
APW7046 - A
CORE2
Pin Name
CORE1 CORE0
APW7046 - B
V CORE
Voltage
CORE2
Pin Name
CORE1 CORE0
V CORE
Voltage
0
0
0
1.15
0
0
0
1.15
0
0
1
1.20
0
0
1
1.20
0
1
0
1.25
0
1
0
1.25
0
1
1
1.30
0
1
1
1.30
1
0
0
1.35
1
0
0
1.35
1
0
1
1.40
1
0
1
1.40
1
1
0
1.45
1
1
0
1.45
1
1
1.50
1
1.50
MEM0
V MEM
Voltage
MEM2
1
Pin Name
MEM1
1
MEM2
1
Pin Name
MEM1
MEM0
V MEM
Voltage
0
0
0
2.40
0
0
0
2.80
0
0
1
2.45
0
0
1
2.85
0
1
0
2.50
0
1
0
2.90
0
1
1
2.55
0
1
1
2.95
1
0
0
2.60
1
0
0
3.00
1
0
1
2.65
1
0
1
3.05
1
1
0
2.70
1
1
0
3.10
1
1
1
2.75
1
1
1
3.15
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
6
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APW7046
Simplified Power System Diagram
+5V
Q2
S tandard B uck
C o n v erter
(PW M2)
VM EM
APW 7046
+3.3V
Q1
S tandard B uck
C o n v erter
(PW M1)
Q3
V CORE
SOURCE-SINK
Linear C onverter
VTT
Q4
Typical Application Circuit
C2
1uF
+ 12V
L1
1uH
R1
10
C1
1uF
C2
200pF
L3
1uH
C11
200pF
+ 5V
+ 3.3V
C3
10uF
C6
330uF
R4
3
U GA T E1
U GA T E2
PH A SE1
PH A SE2
PGN D
11
R6
10K
C8
330uF
VSEN 1
VSEN 2
14
23
R9
5.1
Q2
A PM9410
R7
NC
Q3
A PM3055
Q4
A PM3055
M EM 1
VIN
M EM 0
C9
0.1uF
C OR E2
6
C OR E1
SOU R C E
C OR E0
7
SIN K
EN
SS
GN D
8
FB
C14
10uF
L4
7.8uH
VMEM
21
R10
0
13
20
9
C13
330uF
D2
MBRD835L
MEM2
MEM1
M EM 2
VMEM
C10
330uF
OC SET 2
OC SET 1
D1
MBRD835L
R5
1K
V TT
24
2
3
V CORE
C7
330uF
10
R3
5.1
Q1
A PM9410
C12
10uF
R8
1.5K
B OOT
L2
4.7uH
R2
1.5K
VC C
C4
330uF
1
C5
10uF
19
18
C15
330uF
R11
NC
MEM0
17
CORE2
CORE1
CORE0
16
15
5
4
12
C16
0.68uF
C4, C6, C7, C8 , C10, C13, C15 : 330uF/6.3V
S M D Low E S R tantalum Capac itor
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
7
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APW7046
Typical Performance
1. SOURCE-SINK Linear Regulator Transient Response
- The output capacitor is 330uF (Low ESR tantalum capacitor)
- Define the output cerrent (IVTT) sourcing from the regulator to be positive.
- The interval of current transitions in figures 1 and 2 are all smaller than 1uS.
- In figure 1, the IVTT transition is from -0.2A to 4A.
- In figure 2, the IVTT transition is from 0.2A to -4A.
Figure 1
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
Figure 2
8
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APW7046
Packaging Information
SO – 300mil ( Reference JEDEC Registration MS-013)
D
N
H
GAUGE
PLANE
E
1
2
3
A
Millimeters
1
A1
B
e
L
Variations- D
Inches
Variations- D
Max. Variation
Min.
Max.
Dim
Min.
Max.
Variations
Min.
Max.
Dim
A
2.35
2.65
SO-16
10.10
10.50
A
0.093 0.1043
SO-16
0.398
0.413
A1
0.10
0.30
SO-18
11.35
11.76
A1
0.004 0.0120
SO-18
0.447
0.463
B
0.33
0.51
SO-20
12.60
13
B
0.013
0.020
SO-20
0.496
0.512
D
See variations
SO-24
15.20
15.60
D
See variations
SO-24
0.599
0.614
E
7.40
SO-28
17.70
18.11
E
0.2914 0.2992
SO-28
0.697
0.713
SO-14
8.80
9.20
e
0.050BSC
SO-14
0.347
0.362
e
7.60
1.27BSC
Min.
H
10
10.65
H
0.394
0.419
L
0.40
1.27
L
0.016
0.050
N
See variations
N
See variations
φ1
0°
φ1
8°
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
9
0°
8°
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APW7046
Physical Specifications
Terminal Material
Lead Solderability
Packaging
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
1000 devices per reel for SO-16 , 2500 devices per reel for SSOP-16.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
C ritical Zone
T L to T P
T e m p e ra tu re
R am p-up
TL
tL
T sm ax
T sm in
R am p-down
ts
Preheat
25
t 25 °C to Peak
T im e
Classificatin Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Large Body
Small Body
Average ramp-up rate
3°C/second max.
(TL to TP)
Preheat
- Temperature Min (Tsmin)
100°C
- Temperature Mix (Tsmax)
150°C
- Time (min to max)(ts)
60-120 seconds
Tsmax to TL
- Ramp-up Rate
Tsmax to TL
- Temperature(TL)
183°C
- Time (tL)
60-150 seconds
Peak Temperature(Tp)
225 +0/-5°C
240 +0/-5°C
Time within 5°C of actual Peak
10-30 seconds
10-30 seconds
Temperature(tp)
Ramp-down Rate
6°C/second max.
6 minutes max.
Time 25°C to Peak Temperature
Pb-Free Assembly
Large Body
Small Body
3°C/second max.
150°C
200°C
60-180 seconds
3°C/second max
217°C
60-150 seconds
245 +0/-5°C
250 +0/-5°C
10-30 seconds
20-40 seconds
6°C/second max.
8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
10
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APW7046
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ao
Ko
D1
T2
J
C
A
B
T1
Application
SOP- 24
A
B
J
T1
T2
W
P
E
62 ±1.5
C
12.75 ±
0.15
330±1
2 ± 0.6
24.4 ± 0.2
2± 0.2
24 ± 0.3
12 ± 0.1
1.75± 0.1
F
D
D1
Po
P1
Ao
Bo
Ko
t
11.5 ± 0.1 1.55 +0.1 1.5+ 0.25
4.0 ± 0.1
2.0 ± 0.1 10.9 ± 0.1 15.9± 0.1
3.1± 0.1 0.35±0.05
(mm)
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
11
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APW7046
Cover Tape Dimensions
Application
SOP- 16 / 20 / 24 / 28
Carrier Width
24
Cover Tape Width
21.3
Devices Per Reel
1000
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.2 - Mar., 2002
12
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