CY62157EV30 MoBL® 8-Mbit (512 K × 16) Static RAM 8-Mbit (512 K × 16) Static RAM Features Functional Description ■ Thin small outline package (TSOP) I package configurable as 512 K × 16 or 1 M × 8 static RAM (SRAM) ■ High speed: 45 ns ■ Temperature ranges ❐ Industrial: –40 °C to +85 °C ❐ Automotive-A: –40 °C to +85 °C ❐ Automotive-E: –40 °C to +125 °C ■ Wide voltage range: 2.20 V to 3.60 V ■ Pin compatible with CY62157DV30 ■ Ultra low standby power ❐ Typical standby current: 2 A ❐ Maximum standby current: 8 A (Industrial) ■ Ultra low active power ❐ Typical active current: 1.8 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE features ■ Automatic power down when deselected ■ Complementary Metal Oxide Semiconductor (CMOS) for optimum speed and power ■ Available in Pb-free and non Pb-free 48-ball very fine-pitch ball grid array (VFBGA), Pb-free 44-pin TSOP II and 48-pin TSOP I packages The CY62157EV30 is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE1HIGH or CE2 LOW), the outputs are disabled (OE HIGH), Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or a write operation is active (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 13 for a complete description of read and write modes. Logic Block Diagram 512 K × 16/1 M x 8 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BYTE BHE WE CE2 CE1 BHE A11 A12 A13 A14 A15 A16 A17 A18 Power Down Circuit OE BLE CE2 CE1 BLE Cypress Semiconductor Corporation Document #: 38-05445 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 30, 2011 [+] Feedback CY62157EV30 MoBL® Contents Pin Configuration .............................................................3 Product Portfolio ..............................................................3 Maximum Ratings .............................................................4 Operating Range ...............................................................4 Electrical Characteristics .................................................4 Capacitance ......................................................................5 Thermal Resistance ..........................................................5 Data Retention Characteristics .......................................6 Data Retention Waveform ................................................6 Switching Characteristics ................................................7 Switching Waveforms ......................................................8 Read Cycle No. 1 (Address Transition Controlled) .....8 Read Cycle No. 2 (OE Controlled) ..............................8 Write Cycle No. 1 (WE Controlled) ..............................9 Write Cycle No. 2 (CE1 or CE2 Controlled) ..............10 Document #: 38-05445 Rev. *I Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) ......................................12 Truth Table ......................................................................13 Ordering Information ......................................................14 Ordering Code Definitions .........................................14 Package Diagrams ..........................................................15 Acronyms ........................................................................18 Document Conventions .................................................18 Units of Measure .......................................................18 Document History Page .................................................19 Sales, Solutions, and Legal Information ......................21 Worldwide Sales and Design Support .......................21 Products ....................................................................21 PSoC Solutions .........................................................21 Page 2 of 21 [+] Feedback CY62157EV30 MoBL® Pin Configuration Figure 1. 48-ball VFBGA (Top View) [1] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE 2 A I/O8 BHE A3 A4 CE 1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C A17 A7 I/O3 VCC D NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F VSS I/O11 VCC I/O12 I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Figure 2. 44-pin TSOP II (Top View) [2] A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13 Figure 3. 48-pin TSOP I (512 K × 16/1 M × 8) (Top View) [1, 3] A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE CE2 NC BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A16 BYTE Vss I/O15/A19 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0 Product Portfolio Power Dissipation Product CY62157EV30LL Range VCC Range (V) Speed (ns) Operating ICC, (mA) f = 1 MHz Min Typ [4] Max Industrial/Auto-A 2.2 3.0 3.6 Auto-E 2.2 3.0 3.6 f = fmax Standby, ISB2 (A) Typ [4] Max Typ [4] Max Typ [4] 45 1.8 3 18 25 2 8 55 1.8 4 18 35 2 30 Max Notes 1. NC pins are not connected on the die. 2. The 44-pin TSOP II package has only one chip enable (CE) pin. 3. The BYTE pin in the 48-pin TSOP I package must be tied HIGH to use the device as a 512 K × 16 SRAM. The 48-pin TSOP I package can also be used as a 1 M × 8 SRAM by tying the BYTE signal LOW. In the 1 M x 8 configuration, Pin 45 is A19, while BHE, BLE and I/O8 to I/O14 pins are not used (NC). 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document #: 38-05445 Rev. *I Page 3 of 21 [+] Feedback CY62157EV30 MoBL® Maximum Ratings Output Current into Outputs (LOW) ............................20 mA Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage Temperature ............................. –65 °C to + 150 °C Ambient Temperature with Power Applied ........................................ –55 °C to + 125 °C Supply Voltage to Ground Potential .............................–0.3 V to 3.9 V (VCCmax + 0.3 V) DC Voltage Applied to Outputs in High Z State [5, 6] ............–0.3 V to 3.9 V (VCCmax + 0.3 V) Static Discharge Voltage ........................................> 2001 V (MIL-STD-883, Method 3015) Latch Up Current ...................................................> 200 mA Operating Range Device Range Ambient Temperature VCC [7] CY62157EV30LL Industrial/ –40 °C to +85 °C 2.2 V to 3.6 V Auto-A Auto-E DC Input Voltage [5, 6] ........ –0.3 V to 3.9 V (VCC max + 0.3 V) –40 °C to +125 °C Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions 45 ns (Industrial/ Auto-A) 55 ns (Auto-E) Unit Min Typ [8] Max Min Typ [8] Max IOH = –0.1 mA 2.0 – – 2.0 – – V IOH = –1.0 mA, VCC > 2.70 V 2.4 – – 2.4 – – V IOL = 0.1 mA – – 0.4 – – 0.4 V IOL = 2.1 mA, VCC > 2.70 V – – 0.4 – – 0.4 V VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 1.8 – VCC + 0.3 V VCC = 2.7 V to 3.6 V 2.2 – VCC + 0.3 2.2 – VCC + 0.3 V VCC = 2.2 V to 2.7 V –0.3 – 0.6 –0.3 – 0.6 V VCC = 2.7 V to 3.6 V –0.3 – 0.8 –0.3 – 0.8 V –1 – +1 –4 – +4 A – +1 –4 – +4 A IIX Input leakage current GND < VI < VCC IOZ Output leakage current GND < VO < VCC, Output Disabled –1 ICC VCC operating supply current – 18 25 – 18 35 – 1.8 3 – 1.8 4 mA f = fmax = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels ISB1 [9] Automatic CE power CE1 > VCC 0.2 V or CE2 < 0.2 V down current — CMOS or (BHE and BLE) > VCC – 0.2 V, inputs VIN > VCC – 0.2 V, VIN < 0.2 V f = fmax (Address and Data Only), f = 0 (OE and WE), VCC = 3.60 V – 2 8 – 2 30 A ISB2 [9] Automatic CE power CE1 > VCC – 0.2 V or CE2 < 0.2 V down current — CMOS or (BHE and BLE) > VCC – 0.2 V, inputs VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V – 2 8 – 2 30 A Notes 5. VIL(min) = –2.0 V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 7. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 9. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE (48-pin TSOP I only) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05445 Rev. *I Page 4 of 21 [+] Feedback CY62157EV30 MoBL® Capacitance Parameter [10] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Thermal Resistance Parameter [10] Description JA Thermal resistance (Junction to Ambient) JC Thermal resistance (Junction to Case) Test Conditions 48-ball BGA Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 72 44-pin TSOP I 44-pin TSOP II Unit 74.88 76.88 C/W 8.86 8.6 13.52 C/W Figure 4. AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE Parameters R1 R2 RTH VTH VCC 10% GND R2 Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V TH 2.5 V 16667 15385 8000 1.20 3.0 V 1103 1554 645 1.75 Unit V Note 10. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05445 Rev. *I Page 5 of 21 [+] Feedback CY62157EV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter Description Min Typ [11] Max Unit 1.5 – – V Industrial/Auto-A – 2 5 A Auto-E – – 30 0 – CY62157EV30LL-45 45 – – CY62157EV30LL-55 55 – – Conditions VCC for data retention VDR ICCDR [12] Data retention current tCDR [13] Chip deselect to data retention time tR [14] Operation recovery time VCC = 1.5 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V, (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V ns ns Data Retention Waveform Figure 5. Data Retention Waveform [15] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5V VCC(min) tR CE1 or BHE.BLE or CE2 Notes 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 12. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE (48-pin TSOP I only) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 13. Tested initially and after any design or process changes that may affect these parameters. 14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 15. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. Document #: 38-05445 Rev. *I Page 6 of 21 [+] Feedback CY62157EV30 MoBL® Switching Characteristics Over the Operating Range Parameter [16, 17] 45 ns (Industrial/ Auto-A) Description 55 ns (Auto-E) Min Max Min Max Unit Read Cycle tRC Read cycle time 45 – 55 – ns tAA Address to data valid – 45 – 55 ns tOHA Data hold from address change 10 – 10 – ns tACE CE1 LOW and CE2 HIGH to data valid – 45 – 55 ns tDOE OE LOW to data valid – 22 – 25 ns tLZOE OE LOW to Low Z[18] 5 – 5 – ns Z[18, 19] – 18 – 20 ns CE1 LOW and CE2 HIGH to Low Z[18] 10 – 10 – ns tHZCE CE1 HIGH and CE2 LOW to High Z[18, 19] – 18 – 20 ns tPU CE1 LOW and CE2 HIGH to power up 0 – 0 – ns tPD CE1 HIGH and CE2 LOW to power down – 45 – 55 ns tDBE BLE/BHE LOW to data valid – 45 – 55 ns ns tHZOE tLZCE OE HIGH to High Z[18, 20] tLZBE BLE/BHE LOW to Low 5 – 10 – tHZBE BLE/BHE HIGH to High Z[18, 19] – 18 – 20 ns Write cycle time 45 – 55 – ns ns Write Cycle[21] tWC tSCE CE1 LOW and CE2 HIGH to write end 35 – 40 – tAW Address setup to write end 35 – 40 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns ns tPWE WE pulse width 35 – 40 – tBW BLE/BHE LOW to write end 35 – 40 – ns tSD Data setup to write end 25 – 25 – ns tHD Data hold from write end 0 – 0 – ns Z[18, 19] – 18 – 20 ns 10 – 10 – ns tHZWE WE LOW to High tLZWE WE HIGH to Low Z[18] Notes 16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 4 on page 5. 17. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 18. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 20. If both byte enables are toggled together, this value is 10 ns. 21. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 38-05445 Rev. *I Page 7 of 21 [+] Feedback CY62157EV30 MoBL® Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [22, 23] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [23, 24] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 22. The device is continuously selected. OE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH. 23. WE is HIGH for read cycle. 24. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05445 Rev. *I Page 8 of 21 [+] Feedback CY62157EV30 MoBL® Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [25, 26, 27] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA I/O NOTE 28 VALID DATA tHZOE Notes 25. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 26. Data I/O is high impedance if OE = VIH. 27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 28. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05445 Rev. *I Page 9 of 21 [+] Feedback CY62157EV30 MoBL® Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 Controlled) [29, 30, 31] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE DATA I/O tSD NOTE 32 tHD VALID DATA tHZOE Notes 29. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 30. Data I/O is high impedance if OE = VIH. 31. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 32. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05445 Rev. *I Page 10 of 21 [+] Feedback CY62157EV30 MoBL® Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [33] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 34 tHD VALID DATA tHZWE tLZWE Notes 33. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 34. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05445 Rev. *I Page 11 of 21 [+] Feedback CY62157EV30 MoBL® Switching Waveforms (continued) Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [35] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 36 tHD VALID DATA Notes 35. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 36. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05445 Rev. *I Page 12 of 21 [+] Feedback CY62157EV30 MoBL® Truth Table CE1 WE OE BHE BLE X [37] Mode Power X X X X X [37] High Z Deselect/power down Standby (ISB) L X X X X [37] X [37] X High Z Deselect/power down Standby (ISB) X X H H High Z Deselect/power down Standby (ISB) L H H L L L Data Out (I/O0–I/O15) Read Active (ICC) L H H L H L Data Out (I/O0 –I/O7 ); High Z (I/O8–I/O15) Read Active (ICC) L H H L L H High Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) L H H H L H High Z Output disabled Active (ICC) L H H H H L High Z Output disabled Active (ICC) L H H H L L High Z Output disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L Data In (I/O0–I/O7); High Z (I/O8–I/O15) Write Active (ICC) L H L X L H High Z (I/O0–I/O7); Data In (I/O8–I/O15) Write Active (ICC) H CE2 Inputs/Outputs Note 37. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted Document #: 38-05445 Rev. *I Page 13 of 21 [+] Feedback CY62157EV30 MoBL® Ordering Information Speed (ns) 45 55 Ordering Code Package Diagram CY62157EV30LL-45BVI 51-85150 48-ball very fine-pitch ball grid array CY62157EV30LL-45BVXI 51-85150 48-ball very fine-pitch ball grid array (Pb-free) CY62157EV30LL-45ZSXI 51-85087 44-pin thin small outline package type II (Pb-free) CY62157EV30LL-45ZXI 51-85183 48-pin thin small outline package type I (Pb-free) CY62157EV30LL-45BVXA 51-85150 48-ball very fine-pitch ball grid array (Pb-free) CY62157EV30LL-45ZSXA 51-85087 44-pin thin small outline package type II (Pb-free) CY62157EV30LL-45ZXA 51-85183 48-pin thin small outline package type I (Pb-free) CY62157EV30LL-55ZSXE 51-85087 44-pin thin small outline package type II (Pb-free) CY62157EV30LL-55ZXE 51-85183 48-pin thin small outline package type I (Pb-free) Package Type Operating Range Industrial Automotive-A Automotive-E Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 5 7 E V30 LL - XX XX X X Temperature Range: X = I or A or E I = Industrial; A = Automotive-A; E = Automotive-E Pb-free Package Type: XX = BV or ZS or Z BV = 48-ball VFBGA ZS = 44-pin TSOP II Z = 48-pin TSOP I Speed Grade: XX = 45 ns or 55 ns Low Power Voltage E = Process Technology 90 nm Buswidth = × 16 Density = 8-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document #: 38-05445 Rev. *I Page 14 of 21 [+] Feedback CY62157EV30 MoBL® Package Diagrams Figure 6. 48-pin VFBGA (6 × 8 × 1 mm) BV48/BZ48, 51-85150 51-85150 *F Document #: 38-05445 Rev. *I Page 15 of 21 [+] Feedback CY62157EV30 MoBL® Package Diagrams (continued) Figure 7. 44-pin TSOP Z44-II, 51-85087 51-85087 *C Document #: 38-05445 Rev. *I Page 16 of 21 [+] Feedback CY62157EV30 MoBL® Package Diagrams (continued) Figure 8. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A, 51-85183 51-85183 *B Document #: 38-05445 Rev. *I Page 17 of 21 [+] Feedback CY62157EV30 MoBL® Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C degree Celcius I/O input/output MHz Mega Hertz OE output enable μA micro Amperes RAM random access memory μs micro seconds SRAM static random access memory mA milli Amperes TSOP thin small outline package mm milli meter VFBGA very fine-pitch ball grid array ns nano seconds WE write enable ohms % percent pF pico Farad V Volts W Watts Document #: 38-05445 Rev. *I Symbol Unit of Measure Page 18 of 21 [+] Feedback CY62157EV30 MoBL® Document History Page Document Title: CY62157EV30 MoBL®, 8-Mbit (512 K × 16) Static RAM Document Number: 38-05445 Rev. ECN No. Orig. of Change Submission Date ** 202940 AJU See ECN New Data Sheet *A 291272 SYT See ECN Converted from Advance Information to Preliminary Removed 48-TSOP I Package and the associated footnote Added footnote stating 44 TSOP II Package has only one CE on Page # 2 Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed ICCDR from 4 to 4.5 A Changed tOHA from 6 to 10 ns for both 35 and 45 ns Speed Bins Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for 35 and 45 ns Speed Bins respectively Changed tHZCE from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns Speed Bins respectively Changed tSCE, tAW and tBW from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns Speed Bins respectively Changed tSD from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns Speed Bins respectively Added Lead-Free Package Information *B 444306 NXR See ECN Converted from Preliminary to Final. Changed ball E3 from DNU to NC Removed redundant footnote on DNU. Removed 35 ns speed bin Removed “L” bin Added 48 pin TSOP I package Added Automotive product information. Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28 mA to 25 mA for test condition f = fax = 1/tRC. Changed the ICC Max value from 2.3 mA to 3 mA for test condition f = 1MHz. Changed the ISB1 and ISB2 Max value from 4.5 A to 8 A and Typ value from 0.9 A to 2 A respectively. Modified ISB1 test condition to include BHE, BLE Updated Thermal Resistance table. Changed Test Load Capacitance from 50 pF to 30 pF. Added Typ value for ICCDR . Changed the ICCDR Max value from 4.5 A to 5 A Corrected tR in Data Retention Characteristics from 100 s to tRC ns. Changed tLZOE from 3 to 5 Changed tLZCE from 6 to 10 Changed tHZCE from 22 to 18 Changed tLZBE from 6 to 5 Changed tPWE from 30 to 35 Changed tSD from 22 to 25 Changed tLZWE from 6 to 10 Added footnote #15 Updated the ordering Information and replaced the Package Name column with Package Diagram. *C 467052 NXR See ECN Modified Data sheet to include x8 configurability. Updated the Ordering Information table *D 925501 VKN See ECN Removed Automotive-E information Added Preliminary Automotive-A information Added footnote #10 related to ISB2 and ICCDR Added footnote #15 related AC timing parameters *E 1045801 VKN See ECN Converted Automotive-A specs from preliminary to final Updated footnote #9 Document #: 38-05445 Rev. *I Description of Change Page 19 of 21 [+] Feedback CY62157EV30 MoBL® Document History Page (continued) Document Title: CY62157EV30 MoBL®, 8-Mbit (512 K × 16) Static RAM Document Number: 38-05445 Rev. ECN No. Orig. of Change Submission Date *F 2724889 NXR/AESA 06/26/09 *G 2927528 VKN *H 3110053 PRAS 12/14/2010 Changed Table Footnotes to Footnotes. Added Ordering Code Definitions. *I 3269771 RAME 05/30/2011 Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated Electrical Characteristics. Updated Data Retention Characteristics. Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. Document #: 38-05445 Rev. *I Description of Change Added Automotive-E information Included -45ZXA/-55ZSXE/-55ZXE parts in the Ordering Information table 05/04/2010 Renamed “DNU” pins as “NC” for 48 TSOP I package Added footnote #24 related to chip enable Updated Package Diagrams Added Contents Updated links in Sales, Solutions, and Legal Information Page 20 of 21 [+] Feedback CY62157EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05445 Rev. *I Revised May 30, 2011 Page 21 of 21 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback