Low Power 3.3 Volt Limiting Amplifier for Applications up to 12.5 Gbps M02140 Low power, high sensitivity 12.5 Gbps limiting amplifier in 4X4 MLF package The M02140 is a high-gain limiting amplifier for applications up to 12.5 Gbps, and incorporates a limiting amplifier, a CML buffer and an input signal level detection circuit. The M02140 also features a fully integrated DC-offset cancellation loop that does not require any external components. > K E Y F E AT U R E S > Wide dynamic range with 5.5 mV typical input sensitivity at 10 Gbps > Received signal strength indicator (RSSI) > Programmable input signal level detect > Operates with +3.3 V supply > CML data outputs with typical 23 ps rise and fall time > Wide -40 to +85 °C operating temperature range > On-chip DC offset cancellation circuit The user is provided with the flexibility to set the output amplitude levels and the signal detect threshold. Optional output buffer disable (squelch/jam) can be implemented The output swing is linearly proportional to the value of using the power down (PWDN) input. RAMPSET. It is possible to set the output voltage swing linearly between 400 mVpp differential and 800 mVpp differential, The data inputs are internally biased to VCC via 50Ω when the outputs are properly terminated. See the applica- resistors, and may be AC or DC-coupled. Note that if the tions information section for further details on setting the inputs are AC-coupled, the coupling capacitor should be of output swing amplitude. sufficient value to pass the lowest frequencies of interest, bearing in mind the number of consecutive identical bits, and The RSSI output voltage is proportional to the log of the the input resistance (The use of a 2 to 10 nF capacitor is input signal amplitude (the RSSI output voltage is linearly recommended). The coupling capacitor should also be of proportional to the optical modulation amplitude (OMA)). An sufficient quality as to pass the high frequency content of external 4.7 nF capacitor must be connected from the RSSI the input data stream. output to VCC. The capacitor integrates the RSSI output and also sets the loss of signal reaction time. The RSSI The M02140 contains internal DC feedback requiring no voltage is compared with a selectable reference to deter- external components to remove the effects of DC offsets mine loss of signal as described in the next section. and to act as a DC auto-zero circuit. This circuit is configured such that the feedback is effective only at frequencies Using an external resistor, RLOS, between pin LOSSET and VCC, well below the lowest frequency of interest. The low the user can program the input signal threshold. The signal frequency cut off is typically less than 50 kHz. detect status is indicated on the LOS and ST open-drain output pins. The LOS signal is active when the signal is below the threshold value, ST is active when the signal is above the threshold value. > RLOS establishes a threshold voltage at the LOSSET pin. The input allow data to propagate only when the signal is above the user's signal develops a voltage at the RSSI pin. This voltage is propor- bit-error-rate requirement. It therefore inhibits the data outputs tional to the input signal peak-to-peak value. The voltage at LOSSET toggling due to noise when there is no signal present ("squelch"). is internally compared to the voltage at the RSSI (V(RSSI)) pin. In order to implement this function, LOS should be connected to When the voltage at V(RSSI) is less than V(LOSSET), LOS is asserted the PWDN pin, thus forcing the data outputs to (ST de-asserted) and will stay asserted until the input signal level VCC when the signal falls below the threshold. increases by a predefined amount of hysteresis. When the input level increases by more than this hysteresis, LOS is The M02140 contains an accurate on-chip bias circuit requiring an de-asserted (ST asserted) external 12.1 k–Ω 1% resistor, RREF, from pin IREF to ground to define an on-chip reference current. When asserted, the active high PWDN pin forces the outputs to a high state. This ensures that no data is propagated through the The output circuit is basically a differential pair with a tail current system. The loss of signal detection circuit can be used to auto- of ITAIL. The load of the differential pair is formed by the parallel matically force the data outputs to a high state when the input combination of ROUT and RLOAD for high frequencies where the signal falls below the threshold. The function is normally used to output AC-coupling capacitor can be considered as a short circuit (50 || 50 = 25Ω). V CCP VCCD AMPSET The required minimum voltage swing sets ITAIL which determines the output power consumption. The minimum voltage swing 50W Amplitude Control 50W D IN P DOUT N DOUT N CMOS Buffer consumption in his own application by setting ITAIL using an external resistor (RAMPSET). PWDN ST Level Detector LOS Comparator Threshold Setting Circuit RSSI depends on the application. Therefore, M02140 provides the user 50 the flexibility to optimize the voltage swing and the output power CML Buffer Limiting Amplifier D IN N 50 Biasing IREF LOS SET M02140 Block Diagram Product Features Applications • STM-64/OC-192 SDH/SONET • SDH/SONET with single or double FEC • 10G Ethernet • 10G Fiber Channel • XFP www.mindspeed.com/salesoffices General Information: (949) 579-3000 Headquarters – Newport Beach 4000 MacArthur Blvd., East Tower Newport Beach, CA 92660-3007 02140-BRF-001-A M04-0935 © 2004 Mindspeed Technologies™. All rights reserved. Mindspeed and the Mindspeed logo are trademarks of Mindspeed Technologies. All other trademarks are the property of their respective owners. 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