Intersil ISL8501 Triple output controller with 1a standard buck pwm and dual ldo Datasheet

ISL8501
®
Data Sheet
July 12, 2007
Triple Output Controller with 1A Standard
Buck PWM and Dual LDOs
The ISL8501 is a high-performance, triple output controller
that provides a single, high frequency power solution for a
variety of point of load applications. The ISL8501 integrates
a 1A standard buck PWM controller and switching MOSFET
with two 500mA LDOs.
FN6500.1
Features
• Standard Buck Controller with Integrated Switching Power
MOSFET and Dual LDOs
• Integrated Boot Diode
• Input Voltage Range
- Fixed 5V ±10%
- Variable 6V to 25V
The PWM controller in the ISL8501 drives an internal
switching N-Channel power MOSFET and requires an
external Schottky diode to generate an output voltage from
0.6V to 20V. The integrated power switch is optimized for
excellent thermal performance up to 1A of output current.
The standard buck input voltage range supports a fixed 5V
or variable 6V to 25V range. The PWM regulator switches at
a fixed frequency of 500kHz and utilizes simple voltage
mode control with input voltage feed forward to provide
flexibility in component selection and minimize solution size.
Protection features include overcurrent, undervoltage, and
thermal overload protection integrated into the IC. The
ISL8501 power good signal output indicates loss of
regulation on the PWM output.
• PWM Output Voltage Adjustable from 0.6V to 20V with
Continuous Output Current up to 1A
The ISL8501 features two adjustable LDO regulators using
internal PMOS transistors as pass devices. Separate enable
pins (EN_LDO1, EN_LDO2) control each LDO output. A
single power good signal output indicates loss of regulation
on either of the two LDO outputs. Independent overcurrent
and thermal fault shutdown monitors are integrated into the
LDO section.
• Thermal Overload Protection
ISL8501 is available in a small 4mmx4mm Quad Flat NoLead (QFN) package.
• Output Undervoltage Protection
• Dual LDO Adjustable Options
- LDO1, 0.6V to 4.2V . . . . . . . . . . . . . . . . . . . . . . 500mA
- LDO2, 0.6V to 4.2V . . . . . . . . . . . . . . . . . . . . . . 500mA
• Individual Enable Inputs
• Two PGOOD Outputs (PWM and both LDOs)
• Overcurrent Protection
• Internal 5V LDO regulator
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• General Purpose
• WLAN Cards-PCMCIA, Cardbus32, MiniPCI CardsCompact Flash Cards
• Hand-Held Instruments
1
SS
EN
24
23
22
21
20
19
FB_LDO1 1
18 VIN
VOUT1 2
17 VIN
VIN_LDO1 3
16 PHASE
25
GND
VIN_LDO2 4
15 PHASE
13 PVCC
7
8
9
10
11
12
VCC
FB_LDO2 6
GND
14 BOOT
EN_LDO2
VOUT2 5
EN_LDO1
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
COMP
*Add “-T” suffix for tape and reel
FB_PWM
-40 to +85 24 Ld 4x4 QFN L24.4x4D
PG_PWM
PKG.
DWG. #
PG_LDO
PACKAGE
(Pb-free)
ISL8501
(24 LD QFN)
TOP VIEW
CC1
ISL8501IRZ* 85 01IRZ
• Externally Adjustable Soft-Start Time
CC2
PART
TEMP.
MARKING RANGE (°C)
• Fixed 500kHz Switching Frequency
Pinout
Ordering Information
PART
NUMBER
(Note)
• Voltage Mode Control with Voltage Feed Forward
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8501
PWM PGOOD
PWM ENABLE
Typical Application Schematics
R3
301
VOUT
COMP
FB_PWM
SS
VIN
R6
5.11k
1.2V
C3
10pF
FB_LDO1
5V
C9
10μF
C6
22μF
UNREGULATED
~2.5V
VIN_LDO1
VOUT1
C7
10μF
BOOT
LDO2
VOUT2
1.8V
C8
22μF
FB_LDO2
C10
0.1μF
L
10μH
D
B340LB
+3.3V
C11
100μF
GND
EN_LDO2
VCC
VIN
LDO2 ENABLE
C14
1 μF
LDO PGOOD
C12
0.1μF
LDO1 ENABLE
R8
2.55k
EN_LDO1
PVCC
PG_LDO
R7
5.11k
VOUT1
PHASE
ISL8501
VIN_LDO2
CC2
LDO1
EN
PG_PWM
CC1
R5
5.11k
C5
0.033μF
R1
10k
C2
10nF
R2
2.21k
R4
20k
C4
0.1μF
C1
100pF
FIGURE 1. VIN RANGE FROM 4.5V TO 5.5V
2
FN6500.1
July 12, 2007
ISL8501
PWM ENABLE
(Continued)
PWM PGOOD
Typical Application Schematics
R3
301
VOUT
R2
2.21k
COMP
FB_PWM
SS
VIN
R6
5.11k
1.2V
C3
10pF
FB_LDO1
5V
C9
10uF
C6
22μF
VIN_LDO1
L
10μH
VOUT1
C7
10μF
PHASE
ISL8501
VIN_LDO2
BOOT
LDO2
VOUT2
1.8V
C8
22μF
FB_LDO2
C10
0.1μF
VOUT1
C11
100μF
D
B340LB
VCC
GND
EN_LDO2
LDO2 ENABLE
C14
1 μF
LDO PGOOD
C12
0.1μF
LDO1 ENABLE
R8
2.55k
EN_LDO1
PVCC
PG_LDO
R7
5.11k
CC2
LDO1
EN
PG_PWM
CC1
R5
5.11k
C5
0.033μF
R1
10k
C2
10nF
R4
20k
C4
0.1μF
C1
100pF
FIGURE 2. VIN RANGE FROM 6V TO 25V
3
FN6500.1
July 12, 2007
ISL8501
VCC
BOOT
PVCC
FB
COMP
Functional Block Diagram
SOFT-START
CONTROL
VIN (x2)
30μA
OC
MONITOR
PWM
+
-
+
-
VOLTAGE
MONITOR
EA
SS
0.6V
REFERENCE
EN
FAULT
MONITOR
EN_LDO1
THERMAL
MONITOR
+150oC
EN_LDO2
RAMP
GENERATOR
VIN
GATE
DRIVE
PHASE (x2)
OSCILLATOR
OC
MONITOR
POR
VIN
LDO
PVCC
POWER-ON
RESET
MONITOR
VCC
VIN_LDO1
VIN_LDO2
PG_PWM
Gm
CC1
REF
POR
LDO1
CONTROL
LOGIC
VIN_LDO1
FAULT
+
LDO1
VOUT1
-15% COMP.
FB_LDO1
PG_LDO
Gm
CC2
REF
POR
LDO2
CONTROL
LOGIC
VIN_LDO2
FAULT
+
LDO2
GND
-15% COMP.
VOUT2
FB_LDO2
4
FN6500.1
July 12, 2007
ISL8501
Absolute Maximum Ratings (Note 1)
Thermal Information
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +26V
VIN_LDOx to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
PHASE to BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +0.3V
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
VOUT, LDO1, LDO2 to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
FB_PWM, FB_LDOx to GND. . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
PG_PWM, PG_LDOx to GND . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
EN, EN_LDOx to GND. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
CC1, CC2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
VCC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Thermal Resistance
θJA (°C/W)
θJC (°C/W)
QFN Package (Notes 1, 2). . . . . . . . . .
36
5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
*An accidental short between VCC and GND may cause excessive heating and permanent damage to the device.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379 for details.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
Electrical Specifications
Unless Otherwise Noted, All Parameter Limits are Guaranteed Over the Recommended Operating Conditions
and the Typical Specifications are Measured at the Following Conditions: TA = -40°C To +85°C (Note 7),
VIN = 6V to 25V, Unless Otherwise Noted. Typical Values are at TA = +25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
25
V
5.0
5.5
V
4.6
V
SUPPLY VOLTAGE
VIN Voltage Range
VIN
VIN_LDOx Voltage Range
6
VIN connected to VCC
4.5
(Note 6)
1.8
VIN Operating Supply Current
IOP
(Note 3)
2.5
3.5
mA
VIN Shutdown Supply Current
ISD
EN = EN_LDOx = GND
70
100
μA
4.40
4.50
POWER-ON RESET
VCC POR Threshold
Rising Edge
VIN_LDOx POR Threshold
4.25
V
Hysteresis
260
mV
Rising Edge
1.2
V
Hysteresis
200
mV
INTERNAL VCC LDO
VCC Output Voltage Range
VIN = 6V to 25V, IVCC = 0mA to 50mA
4.5
5.00
5.5
V
0.590
0.6
0.609
V
0.5
%
REFERENCE
Reference Voltage
VFB
VIN = 6V to 25V, IREF = 0
STANDARD BUCK PWM REGULATOR
FB_PWM Line Regulation
IOUT = 0mA, VIN = 6V to 25V
FB_PWM Leakage Current
VFB = 0.6V
-0.5
0
50
100
nA
TA = -40°C to +85°C, VCC = 5V
450
500
550
kHz
0.73
0.86
0.99
V/V
OSCILLATOR AND PWM MODULATOR
Nominal Switching Frequency
fSW
Modulator Gain
AMOD
VIN = 12V (AMOD = 10/VIN)
Peak-to-Peak Sawtooth Amplitude
VRAMP
VIN = 12V (VPP = VIN/10)
PWM Ramp Offset Voltage
VOFFSET
Maximum Duty Cycle
DCMAX
COMP >4V
1.2
0.70
0.8
80
83
V
0.91
V
%
ERROR AMPLIFIER
Open-Loop Gain
Gain Bandwidth Product
GBWP
Slew Rate
SR
5
COMP = 10pF
88
dB
15
MHz
5
V/μs
FN6500.1
July 12, 2007
ISL8501
Electrical Specifications
Unless Otherwise Noted, All Parameter Limits are Guaranteed Over the Recommended Operating Conditions
and the Typical Specifications are Measured at the Following Conditions: TA = -40°C To +85°C (Note 7),
VIN = 6V to 25V, Unless Otherwise Noted. Typical Values are at TA = +25°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.7
2.2
UNITS
ENABLE SECTION
EN Threshold
Rising Edge
1.2
Hysteresis
EN_LDOx Logic Input Threshold
Rising Edge
1.2
Hysteresis
EN_LDOx Logic Input Current
V
350
1.7
mV
2.2
V
400
mV
-1
μA
1
FAULT PROTECTION
Thermal Shutdown Temperature
TSD
PWM UV Trip Level
Rising Threshold
150
°C
THYS
Hysteresis
15
°C
VUV
Referred to Nominal VOUT
65
PWM UVP Propagation Delay
70
75
%
360
PWM OCP Threshold
(Note 4)
1.85
OCP Blanking Time
2.7
ns
3.00
A
150
ns
POWER GOOD
PG_PWM Trip Level Referred to Nominal
VOUT
Falling Edge, 15mV Hysteresis
84
88
92
%
Rising Edge, 15mV Hysteresis
107
110
113
%
PG_PWM and PG_LDOx Propagation
Delay
160
PG_PWM Low Voltage
ISINK = 4mA
PG_PWM Leakage Current
VPG_PWM = 5V, VFB_PWM = 600mV
-1
PG_LDOx Trip Level Referred to Nominal
VOUT
Falling Edge, 15mV Hysteresis
81
PG_LDOx Low Voltage
ISINK = 4mA
PG_LDOx Leakage Current
VPG_LDOx = 5V, VFB_LDOx = 600mV
85
ns
0.3
V
1
μA
88
%
0.3
V
1
μA
-1
SOFT-START SECTION
Soft-Start Threshold to Enable Buck
0.8
1.0
1.2
V
Soft-Start Threshold to Enable PG
2.8
2.95
3.1
V
35
μA
Soft-Start Voltage High
3.3
Soft-Start Charging Current
25
Soft-Start Pull-down
30
VSS = 3.0V
25
IOUT = 100mA
120
V
mA
POWER MOSFET
rDS(ON)
350
mΩ
LDOx
FB_LDOx Voltage Accuracy
IOUT = 10mA
-1.5
FB Leakage Current
VFB = 0.6V
-200
-80
550
800
1000
150
300
mV
0.6
%/V
Output Current Limit
Dropout Voltage
IOUT = 450mA, VOUT > 2V (Note 5)
FB_LDOx Line Regulation
IOUT = 0mA, VIN_LDO1 = 2.0 ~4.6V
FB_LDOx Load Regulation
IOUT = 10mA to 500mA
1.5
-0.6
%
nA
±0.5
mA
%
NOTES:
3. Test Condition: VIN = 15V, FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included.
4. Limits established by characterization and are not production tested.
5. The dropout voltage is defined as minimum amount VIN must exceed a desired VOUT operating point. VLDO = VIN_LDO - VOUT.
6. The input voltage VCC must be higher than VIN_LDO or the LDO will not function.
7. Specifications at -40°C to +85°C are guaranteed by +25°C test with margin limits.
6
FN6500.1
July 12, 2007
ISL8501
Pin Descriptions
EN
VIN
The input supply for the PWM regulator power stage and the
source for the internal linear regulator that provides bias for
the IC. Place a ceramic capacitor from VIN to GND, close to
the IC for decoupling (typical 1μF).
SS
Program pin for soft-start duration. A regulated 30μA pull-up
current source charges a capacitor connected from the pin to
GND. The output voltage of the converter follows the
ramping voltage on the SS pin.
PVCC
Connect this pin to VCC.
GND
Ground connect for the IC and thermal relief for the package.
The exposed pad must be connected to GND and soldered
to the PCB. All voltage levels are measured with respect to
this pin.
VCC
Internal 5V linear regulator output provides bias to all the
internal control logic. The ISL8501 may be powered directly
from a 5V (±10%) supply at this pin. When used as a 5V
supply input, this pin must be externally connected to VIN.
The VCC pin must always be decoupled to GND with a
ceramic bypass capacitor (minimum 1μF) located close to
the pin.
TABLE 1. INPUT SUPPLY CONFIGURATION
INPUT
PWM controller enable input. The PWM converter and
LDO's outputs are held off when the pin is pulled to ground.
When the voltage on this pin rises above 1.7V, the chip is
enabled.
PIN CONFIGURATION
6V to 25V
Connect the input supply to the VIN pin only. The
VCC pin will provide a 5V output from the internal
linear regulator.
5V ±10%
Connect the input supply to the VIN and VCC pins.
VIN_LDO1, VIN_LDO2
Input voltage pin for each LDO.
VOUT1, VOUT2
LDO output pins. Bypass with a minimum of 2.2μF, low ESR
capacitor to GND for stable operation.
FB_LDO1, FB_LDO2
Used to set the output of LDO with the proper selection of
resistor divider. The resistors should be selected to provide a
minimum current of 200nA load for the LDO.
CC1, CC2
Compensation capacitor connection for each LDO. Connect
a 0.033μF capacitor from each pin to ground.
EN_LDO1, EN_LDO2
These pins are threshold-sensitive enable inputs for the
individual LDOs. Held low, this pin disables the respective
LDO.
PG_PWM
FB and COMP
The standard buck regulator employs a single voltage
control loop. FB is the negative input to the voltage loop error
amplifier. COMP is the output of the error amplifier. The
output voltage is set by an external resistor divider
connected to FB. With a properly selected divider, the output
voltage can be set to any voltage between the power rail
(reduced by converter losses) and the 0.6V reference.
Connecting an AC network across COMP and FB provide
loop compensation to the amplifier.
PWM converter power good output. Open drain logic output
that is pulled to ground when the output voltage is outside
regulation limits. Connect a 100kΩ resistor from this pin to
VCC. Pin is low when the buck regulator output voltage is
not within 10% of the respective nominal voltage, or during
the soft-start interval. Pin is high impedance when the output
is within regulation.
PG_LDO
Combined LDO power good output. Connect a 100kΩ
resistor from this pin to VCC.
In addition, the PWM regulator power good and undervoltage protection circuitry use FB to monitor the regulator
output voltage.
PHASE
Switch node connections to internal power MOSFET source,
external output inductor, and external diode cathode.
BOOT
Floating bootstrap supply pin for the power MOSFET gate
driver. The bootstrap capacitor provides the necessary
charge to turn and hold on the internal N-Channel MOSFET.
Connect an external capacitor from this pin to PHASE.
7
FN6500.1
July 12, 2007
ISL8501
Typical Performance Curves Circuit of Figure 2. VIN = 12V, VIN_LDO1 = VIN_LDO2 = VOUT1 = 3.3V, IOUT1 = 1A, VLDO1 = 1.2V,
100
100
90
90
80
80
70
1.8VOUT
60
2.5VOUT
3.3VOUT
1.5VOUT
50
EFFICIENCY (%)
EFFICIENCY (%)
ILDO1 = 450mA, VLDO2 = 1.8V, ILDO2 = 450mA, TA = -40°C to +85°C unless otherwise noted.
Typical values are at TA = +25°C.
5.0VOUT
40
1.2VOUT
30
70
50
40
20
10
10
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
0
0.00
1.50
FIGURE 3. EFFICIENCY vs LOAD, VIN = 7V
1.2VOUT
1.8VOUT
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.50
OUTPUT VOLTAGE (V)
1.217
70
60
50
1.8VOUT
40
2.5VOUT
3.3VOUT
5.0VOUT
1.5VOUT
30
20
1.2VOUT
7VIN
1.216
1.215
1.214
12VIN
25VIN
1.213
10
0
0.00
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
1.212
0.00
1.50
FIGURE 5. EFFICIENCY vs LOAD, VIN = 25V
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
1.50
FIGURE 6. VOUT REGULATION vs LOAD, 500kHz 1.2VOUT
1.809
1.508
1.508
1.809
7VIN
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.25
1.218
80
1.507
1.507
12VIN
1.506
25VIN
1.506
1.505
0.00
5.0VOUT
FIGURE 4. EFFICIENCY vs LOAD, VIN = 12V
90
EFFICIENCY (%)
1.5VOUT
30
20
0
0.00
3.3VOUT
2.5VOUT
60
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
1.50
FIGURE 7. VOUT REGULATION vs LOAD, 500kHz 1.2VOUT
8
7VIN
1.808
1.808
12VIN
1.807
25VIN
1.807
1.806
0.00
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
1.50
FIGURE 8. VOUT REGULATION vs LOAD, 500kHz 1.8VOUT
FN6500.1
July 12, 2007
ISL8501
Typical Performance Curves Circuit of Figure 2. VIN = 12V, VIN_LDO1 = VIN_LDO2 = VOUT1 = 3.3V, IOUT1 = 1A, VLDO1 = 1.2V,
ILDO1 = 450mA, VLDO2 = 1.8V, ILDO2 = 450mA, TA = -40°C to +85°C unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
3.320
2.503
3.318
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.503
7VIN
2.502
2.502
2.501
12VIN
25VIN
2.501
2.500
0.00
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
3.313
3.310
12VIN
3.308
3.300
0.00
1.50
0.25
0.50
0.75
1.00
1.25
1.50
OUTPUT LOAD (A)
FIGURE 10. VOUT REGULATION vs LOAD, 500kHz 3.3VOUT
5.015
1.6
5.013
POWER DISSIPATION (W)
5.014
7VIN
5.012
5.011
5.010
5.009
5.008
12VIN
5.007
25VIN
5.006
5.005
0.00
0.25
0.50
0.75
1.00
1.25
1.4
1.2
1.0
25VIN
0.8
0.6
12VIN
0.4
0.2
7VIN
0
0.00
1.50
0.25
0.50
0.75
1.00
1.25
1.50
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 11. VOUT REGULATION vs LOAD, 5VOUT
FIGURE 12. POWER DISSIPATION vs LOAD, 3.3VOUT
0.12
3.320
2A LOAD
OUTPUT VOLTAGE (V)
0.10
INPUT POWER (W)
25VIN
3.305
3.303
FIGURE 9. VOUT REGULATION vs LOAD, 500kHz 2.5VOUT
OUTPUT VOLTAGE (V)
7VIN
3.315
0.08
0.06
0.04
NO LOAD
0.02
0.00
5
7
9
11
13
15
17
19
21
23
INPUT VOLTAGE (V)
FIGURE 13. INPUT POWER vs VIN, VOUT = 3.3V
9
25
3.318
3.316
3.314
1A LOAD
NO LOAD
3.312
3.310
5
7
9
11
13
15
17
19
21
23
25
INPUT VOLTAGE (V)
FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN
FN6500.1
July 12, 2007
ISL8501
Typical Performance Curves Circuit of Figure 2. VIN = 12V, VIN_LDO1 = VIN_LDO2 = VOUT1 = 3.3V, IOUT1 = 1A, VLDO1 = 1.2V,
ILDO1 = 450mA, VLDO2 = 1.8V, ILDO2 = 450mA, TA = -40°C to +85°C unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
5.1
6
5.0
5
4.9
VCC (V)
VCC (V)
4
4.8
4.7
50mA LOAD
3
4.6
2
4.5
1
4.4
0
50
100
I VCC (mA)
150
NO LOAD
0
200
0
FIGURE 15. VCC LOAD REGULATION
15
VIN (V)
20
25
30
1.90
1.28
1.26
1.24
7VIN
1.88
7VIN
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
10
FIGURE 16. VCC REGULATION WITH VIN
1.30
12VIN
1.22
1.20
1.18
1.16
1.14
25VIN
1.86
1.84
1.82
1.80
1.78
1.76
1.74
25VIN
12VIN
1.72
1.12
1.10
0
5
100
200
300
400
500
600
700
1.70
0
100
FIGURE 17. LDO1 vs LOAD, 500kHz, VIN_LDO1 = 3.3V
200
300
400
500
600
700
OUTPUT LOAD (mA)
OUTPUT LOAD (mA)
FIGURE 18. LDO2 vs LOAD, 500kHz VIN_LDO2 = 3.3V
PHASE 10V/DIV
PHASE 10V/DIV
VOUT1 RIPPLE
20mV/DIV
VOUT1 RIPPLE
20mV/DIV
IL 1A/DIV
IL 0.2A/DIV
LDO1 RIPPLE
20mV/DIV
LDO1 RIPPLE
20mV/DIV
LDO2 RIPPLE
20mV/DIV
FIGURE 19. STEADY STATE OPERATION AT NO LOAD, 5µs/DIV
10
LDO2 RIPPLE
20mV/DIV
FIGURE 20. STEADY STATE OPERATION AT FULL LOAD,
1µs/DIV
FN6500.1
July 12, 2007
ISL8501
Typical Performance Curves Circuit of Figure 2. VIN = 12V, VIN_LDO1 = VIN_LDO2 = VOUT1 = 3.3V, IOUT1 = 1A, VLDO1 = 1.2V,
ILDO1 = 450mA, VLDO2 = 1.8V, ILDO2 = 450mA, TA = -40°C to +85°C unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
PHASE 10V/DIV
EN 5V/DIV
VOUT1 2V/DIV
SS 2V/DIV
VOUT1 RIPPLE
100mV/DIV
IL 1A/DIV
PG_PWM 5V/DIV
LDO1 RIPPLE
20mV/DIV
LDO1
1V/DIV
LDO2
1V/DIV
LDO2 RIPPLE
20mV/DIV
FIGURE 21. LOAD TRANSIENT, 200µs/DIV
EN 5V/DIV
VOUT1 2V/DIV
FIGURE 22. SOFT-START AT NO LOAD, 500µs/DIV
EN 5V/DIV
LDO1 2V/DIV
PG_LDO 5V/DIV
IL 1A/DIV
PG_PWM 2V/DIV
LDO2 2V/DIV
SS 2V/DIV
FIGURE 23. SOFT-START AT FULL LOAD, 500µs/DIV
FIGURE 24. SOFT-START AT FULL LOAD, 500µs/DIV
EN 5V/DIV
EN 5V/DIV
VOUT1 2V/DIV
IL 1A/DIV
LDO1 1V/DIV
PG_LDO 5V/DIV
PG_PWM 5V/DIV
LDO2 1V/DIV
FIGURE 25. SHUT DOWN CIRCUIT AT FULL LOAD, 100µs/DIV
11
FIGURE 26. SHUT DOWN CIRCUIT AT FULL LOAD, 100µs/DIV
FN6500.1
July 12, 2007
ISL8501
Typical Performance Curves Circuit of Figure 2. VIN = 12V, VIN_LDO1 = VIN_LDO2 = VOUT1 = 3.3V, IOUT1 = 1A, VLDO1 = 1.2V,
ILDO1 = 450mA, VLDO2 = 1.8V, ILDO2 = 450mA, TA = -40°C to +85°C unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
VOUT1 1V/DIV
PHASE 10V/DIV
VOUT1 2V/DIV
IL 2A/DIV
IL 1A/DIV
PG_PWM 5V/DIV
PG_PWM
FIGURE 27. OUTPUT SHORT CIRCUIT, 5µs/DIV
FIGURE 28. OUTPUT SHORT CIRCUIT RECOVERY, 200µs/DIV
LDO2 1V/DIV
LDO1 500mV/DIV
ILDO1 1A/DIV
PG_LDO 5V/DIV
FIGURE 29. LDO1 SHORT CIRCUIT AND RECOVERY,
200µs/DIV
ILDO2 1A/DIV
PG_LDO 5V/DIV
FIGURE 30. LDO2 SHORT CIRCUIT AND RECOVERY,
200µs/DIV
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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12
FN6500.1
July 12, 2007
ISL8501
Detailed Description
The ISL8501 combines a standard buck PWM controller with
an integrated switching MOSFET and two low dropout (LDO)
linear regulators with internal pass devices. The buck
controller drives an internal N-Channel MOSFET and
requires an external diode to deliver load current up to 1A.
A Schottky diode is recommended for improved efficiency
and performance over a standard diode. The standard buck
regulator can operate from either an unregulated DC source,
such as a battery, with a voltage ranging from +6.0V to +25V,
or from a regulated system rail of +5V. When operating from
+6V or greater, the controller is biased from an internal +5V
LDO voltage regulator. The converter output is regulated
down to 0.6V from either input source. Each LDO linear
regulator can source up to 500mA continuous output current
with +2V or greater input supply and +1.0V or higher output
voltage. These features make the ISL8501 ideally suited for
FPGA and wireless chipset power applications.
The PWM control loop uses a single output voltage loop with
input voltage feed forward which simplifies feedback loop
compensation and rejects input voltage variation. External
feedback loop compensation allows flexibility in output filter
component selection. The regulator switches at a fixed
500kHz.
The buck regulator and LDOs are provided with independent
current limits. The current limit in the buck regulator is
achieved by monitoring the drain-to-source voltage drop of
the internal switching power MOSFET. The current limit
threshold is internally set at 2A. The part also features
undervoltage protection by latching the switching MOSFET
driver to the OFF state during an overcurrent, when the
output voltage is lower than 70% of the regulated output.
This helps minimize power dissipation during a short-circuit
condition. Due to only the switching power MOSFET
integration, there is no overvoltage protection feature for this
part.
The ISL8501 monitors and controls the pass transistor’s
gate voltage to limit the output current. The current limits for
both LDOs is 800mA typical. Neither LDO has overvoltage or
undervoltage protection. When the current limit in either
output is reached, the output no longer regulates the voltage,
but regulates the current to the value of the current limit.
+5V Internal Bias Supply (VCC)
Voltage applied to the VIN pin with respect to GND is
regulated to +5V DC by an internal LDO regulator. The
output of the LDO, VCC, is the bias voltage used by all the
internal control and protection circuitry. The VCC pin
requires a ceramic capacitor connected to GND. The
capacitor serves to stabilize the LDO and to decouple load
transients.
The input voltage range for the ISL8501 is specified as +6V
to +25V or +5V ±10%. In the case of an unregulated supply
case, the power supply is connected to VIN only. Once
13
enabled, the linear regulator will turn-on and rise to +5V on
VCC. In the +5V supply case, the VCC and VIN pins must be
tied together to bypass the LDO. The external decoupling
capacitor is still required in this mode. Do not short VCC to
GND.
Operation Initialization
The power-on reset circuitry and enable inputs prevent false
startup of the PWM regulator and LDO outputs. Once all the
input criteria are met, the controller soft-starts the output
voltage to the programmed level.
Power-On Reset and Undervoltage Lockout
The PWM portion of the ISL8501 automatically initializes
upon receipt of input power. The power-on reset (POR)
function continually monitors the VCC and PVCC voltages.
While both are below their POR thresholds, the controller
inhibits switching of the internal power MOSFET. Once
exceeded, the controller initializes the internal soft-start
circuitry. If either input supply drops below their falling POR
threshold during soft-start or operation, the buck regulator
latches off.
Independent LDO supply inputs (VIN_LDO1 and VIN_LDO2)
allow flexibility in partitioning linear regulator power. Power
supplies connected to either LDO supply input must exceed
the undervoltage lockout (UVLO) threshold before that LDO
is initialized. If the input supply drops below the falling UVLO
threshold during operation, the low dropout voltage regulator
latches off.
Enable and Disable
All internal power devices are held in a high-impedance
state, which ensures they remain off while in shutdown
mode. Typically the enable input for a specific output is
toggled high after the input supply to that regulator is active
and the internal LDO has exceeded its POR threshold.
The EN pin enables the buck controller portion of the
ISL8501. When the voltage on the EN pin exceeds the POR
rising threshold, the controller initiates the soft-start function
for the PWM regulator. If the voltage on the EN pin drops
below the POR falling threshold, the buck regulator shuts
down.
Individual LDO enable inputs (EN_LDO1 and EN_LDO2)
allow independent control of each regulator. Make sure EN
is on, when the voltage on either pin exceeds the POR rising
threshold, linear regulator operation is initiated for that
controller. If the voltage then drops below the hysteresis
level for the enable pin, the LDO shuts down.
Pulling the EN low simultaneously puts all outputs into
shutdown mode, and supply current drops to 10μA typical.
Soft-Start
Once the input supply latch and enable threshold are met,
the soft-start function is initialized. The soft-start circuitry
begins sourcing 30μA, from an internal current source, which
FN6500.1
July 12, 2007
ISL8501
C SS [ μF ] = 50 ⋅ t SS [ S ]
(EQ. 1)
Upon disable, SS pin voltage will discharge to zero voltage.
Power Good
PG_PWM is an open-drain output of a window comparator
that continuously monitors the buck regulator output voltage.
PG_PWM is actively held low when EN is low and during the
buck regulator soft-start period. After the soft-start period
terminates, PG_PWM becomes high impedance as long as
the output voltage is within ±10% of the nominal regulation
voltage set by FB_PWM. When VOUT drops 10% below or
rises 10% above the nominal regulation voltage, the
ISL8501 pulls PG_PWM low. Any fault condition forces
PG_PWM low until the fault condition is cleared by attempts
to soft-start. For logic level output voltages, connect an
external pull-up resistor between PG_PWM and VCC. A
100k resistor works well in most applications. Note that the
PG_PWM window detector is completely independent of the
undervoltage protection fault detectors and the state of
LDO1 and LDO2 outputs.
PG_LDO is an open drain pull-down NMOS output that will
sink 1mA at 0.3V max. PG_LDO monitors both LDO1 and
LDO2 output. It goes to the active low state if either LDO
output is below regulation by a value greater than 15%.
When the one of the LDO is disabled, the PG_LDO switch to
only monitor the active LDO output.
Output Voltage Selection
All three regulator output voltages can be programmed using
external resistor dividers that scale the voltage feedback
relative to the internal reference voltage. The scaled voltage
is fed back to the inverting input of the error amplifier. Refer
to Figure 3.
The output voltage programming resistor, R2, will depend on
the value chosen for the feedback resistor, R1, and the
desired output voltage, VOUT, of the regulator. See Equation 1.
The value for the feedback resistor is typically between 1kΩ
and 10kΩ.
R1 ⋅ 0.6V
R2 = ---------------------------------V OUT – 0.6V
(EQ. 2)
If the output voltage desired is 0.6V, then R2 is left
unpopulated.
14
VOUT
R1
+
-
charges the external soft-start capacitor. The voltage on SS
begins ramping linearly from ground until the voltage across
the soft-start capacitor reaches 3.0V. This linear ramp is
applied to the non-inverting input of the internal error
amplifier and overrides the nominal 0.6V reference. The
output voltage reaches its regulation value when the softstart capacitor voltage reaches 1.6V. Connect a capacitor
from SS pin to ground. This capacitor, along with an internal
30μA current source sets the soft-start interval of the
converter, tSS.
EA
R2
0.6V
REFERENCE
FIGURE 31. EXTERNAL RESISTOR DIVIDER
The buck output can be program as high as 20V. Proper
heatsinking must be provided to insure that the junction
temperature do not exceed +125°C.
When the output is set greater than 3.6V, it is recommended
to pre-load at least 1mA and make sure that the input rise
time is >> faster than the VOUT1 rise time. This allows the
BOOT capacitor adequate time to charge for proper
operation.
Protection Features
The ISL8501 limits current in all on-chip power devices to
limit on-chip power dissipation. Overcurrent limits on all three
regulators protect internal power devices from excessive
thermal damage. Undervoltage protection circuitry on the
buck regulator provides a second layer of protection for the
internal power device under high current conditions.
Buck Regulator Overcurrent Protection
During the PWM on-time, the current through the internal
switching MOSFET is sampled and scaled through an
internal pilot device. The sampled current is compared to a
nominal 2A overcurrent limit. If the sampled current exceeds
the overcurrent limit reference level, an internal overcurrent
fault counter is set to 1 and an internal flag is set. The
internal power MOSFET is immediately turned off and will
not be turned on again until the next switching cycle.
The protection circuitry continues to monitor the current and
turns off the internal MOSFET as described. If the overcurrent condition persists for four sequential clock cycles,
the over-current fault counter overflows indicating an
overcurrent fault condition exists. The regulator is shut down
and power good goes low. If the overcurrent condition clears
prior to the counter reaching four consecutive cycles, the
internal flag and counter are reset.
The protection circuitry attempts to recover from the
overcurrent condition after waiting 4 soft-start cycles. The
internal overcurrent flag and counter are reset. A normal
soft-start cycle is attempted and normal operation continues
if the fault condition has cleared. If the overcurrent fault
counter overflows during soft-start, the converter shuts down
and this hiccup mode operation repeats.
FN6500.1
July 12, 2007
ISL8501
LDO Current Limit
The ISL8501 monitors and controls the pass transistor’s
gate voltage to limit output current. The current limit for both
LDO1 and LDO2 is 700mA typical. The output can be
shorted to ground without damaging the part due to the
current limit and thermal protection features.
Undervoltage Protection
If the voltage detected on the buck regulator FB pin falls 15%
below the internal reference voltage, the undervoltage fault
condition flag is set. The fault protection circuitry checks the
overcurrent flag. If the overcurrent flag is set, the fault
monitor latches off the internal power MOSFET. The
regulator will not restart until either a POR restart or the EN
pin is cycled.
If the overcurrent flag is not set, an internal undervoltage
counter is set to 1. The fault controller continues to monitor
the FB pin for 4 clock cycles. If the fault condition persists,
the regulator is shutdown. The controller enters a recovery
mode similar to the overcurrent hiccup mode. No action is
taken for 4 soft-start cycles and the internal undervoltage
counter and fault condition flag are reset. A normal soft-start
cycle is attempted and normal operation continues if the fault
condition has cleared. If the undervoltage counter overflows
during soft-start, the converter is shut down and this hiccup
mode operation repeats.
Under-voltage protection only applies to the buck regulator
output, the two LDO outputs do not have undervoltage
protection.
Thermal Overload Protection
Thermal overload protection limits total power dissipation in
the ISL8501. There are three sensors on the chip to monitor
the junction temperature of the internal LDO, PWM switching
power N-Channel MOSFET, and LDO pass transistors.
When the junction temperature (TJ) of any of the three
sensors exceeds +150°C, the thermal sensor sends a signal
to the fault monitor.
The fault monitor commands the buck regulator to shut down
and the LDOs to turn off their pass transistors. The buck
regulator soft-starts and the LDO pass transistors turn on
again after the IC’s junction temperature cools by +20°C.
The buck regulator experiences hiccup mode operation and
the LDOs a pulsed output during continuous thermal
overload conditions. For continuous operation, do not
exceed the +125°C junction temperature rating.
Low Dropout Regulators
Each regulator consists of a 0.6V reference, error amplifier,
MOSFET driver, P-Channel pass transistor, and dual-mode
comparator. The voltage is set by means of an external
resistor divider on the FB_LDOx pins. The 0.6V band gap
reference is connected to the error amplifier’s inverting input.
The error amplifier compares this reference to the selected
feedback voltage and amplifies the difference. The MOSFET
15
driver reads the error signal and applies the appropriate
drive to the P-Channel pass transistor. If the feedback
voltage is lower than the reference voltage, the pass
transistor gate is pulled lower, allowing more current to pass
and increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the pass transistor gate is
driven higher, allowing less current to pass to the output.
Internal P-Channel Pass Transistor
Both the LDO regulators in the ISL8501 feature a typical
0.33Ω rDS(ON) P-Channel MOSFET pass transistor. This
provides several advantages over similar designs using PNP
bipolar pass transistors. The
P-Channel MOSFET requires no base drive, which reduces
quiescent current considerably. PNP based regulators waste
considerable current in dropout when the pass transistor
saturates. They also use high base drive currents under
large loads. The ISL8501 does not have these drawbacks.
Integrator Circuitry
The ISL8501 uses external compensation capacitors for
minimizing load and line regulation errors and for lowering
output noise. When the output voltage shifts due to varying
load current or input voltage, the integrator capacitor voltage
is raised or lowered to compensate for the systematic offset
at the error amplifier. Compensation is limited to ±5% to
minimize transient overshoot when the device goes out of
dropout, current limit, or thermal shutdown. Place a 33nF
capacitor to GND from CC1 and CC2.
Application Guidelines
Operating Frequency
The ISL8501 operates at a fixed switching frequency of
500kHz.
LDO Regulator Capacitor Selection
Capacitors are required at the ISL8501 LDO Regulators’
input and output for stable operation over the entire load
range and the full temperature range. Use >1µF capacitor at
the input of LDO Regulators, VIN_LDO pins. The input
capacitor lowers the source impedance of the input supply.
Larger capacitor values and lower ESR provides better
PSRR and line transient response. The input capacitor must
be located at a distance of not more then 0.5 inches from the
VIN_LDO pins of the IC and returned to a clean analog
ground. Any good quality ceramic capacitor can be used as
an input capacitor.
The output capacitors used in LDO regulators are used to
provide dynamic load current. The amount of capacitance
and type of capacitor should be chosen with this criteria in
mind. The output capacitor selected must meet the
requirements of minimum amount of capacitance and ESR
for both LDOs. The ISL8501 is specifically designed to work
with small ceramic output capacitors. The output capacitor’s
ESR affects stability and output noise. Use an output
capacitor with an ESR of 50mΩ or less to insure stability and
FN6500.1
July 12, 2007
ISL8501
optimum transient response. For stable operation, a ceramic
capacitor, with a minimum value of 10µF, is recommended
for both LDO outputs. There is no upper limit to the output
capacitor value. Larger capacitor can reduce noise and
improve load transient response, stability and PSRR. The
output capacitor should be located very close to VOUT pins
to minimize impact of PC board inductances and the other
end of the capacitor should be returned to a clean analog
ground.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current
and supply the load transient current. The filtering
requirements are a function of the switching frequency and
the ripple current. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the
transient load current. These requirements are generally met
with a mix of capacitors and careful layout.
Embedded processor systems are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements, rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
ΔI =
VIN - VOUT
Fs x L
x
VOUT
ΔVOUT = ΔI x ESR
VIN
(EQ. 3)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient. The
recommended ΔI is 30% of the maximum output current.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL8501 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
(EQ. 4)
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Rectifier Selection
Current circulates from ground to the junction of the
MOSFET and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is
negative with respect to ground. This voltage is
approximately -0.5V (a Schottky diode drop) during the off
time. The rectifier's rated reverse breakdown voltage must
be at least equal to the maximum input voltage, preferably
with a 20% derating factor. The power dissipation is:
V OUT⎞
⎛
P D [ W ] = I OUT ⋅ V D ⋅ ⎜ 1 – ----------------⎟
V IN ⎠
⎝
(EQ. 5)
where VD is the voltage of the Schottky diode = 0.5V to 0.7V
Output Inductor Selection
Input Capacitor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time the switching
MOSFET turns on. Place the small ceramic capacitors
physically close to the MOSFET VIN pins (switching
MOSFET drain) and the Schottky diode anode.
16
FN6500.1
July 12, 2007
ISL8501
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through the Equation 6:
I RMS
MAX
=
V OUT ⎛
V IN – V OUT V OUT 2
2
1
-------------- × I OUT
+ ------ × ⎛ ----------------------------- × --------------⎞ ⎞
⎝
V IN
V IN ⎠ ⎠
12 ⎝ L × f s
MAX
(EQ. 6)
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised wih
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 2 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at fLC and a zero at fESR . The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ΔVOSC .
Modulator Break Frequency Equations
1
f LC = ------------------------------------------2π x L O x C O
2. Place1st Zero Below Filter’s Double Pole (~75% fLC).
3. Place 2nd Zero at Filter’s Double Pole.
4. Place 1st Pole at the ESR Zero.
5. Place 2nd Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
1
f Z1 = -----------------------------------2π x R 4 x C 2
1
f P1 = --------------------------------------------------------⎛ C 3 x C 2⎞
2π x R 4 x ⎜ ----------------------⎟
⎝ C3 + C2 ⎠
1
f Z2 = ------------------------------------------------------2π x ( R 1 + R 3 ) x C 1
1
f P2 = -----------------------------------2π x R 3 x C 1
Figure 3 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 3. Using the guidelines from “Modulator
Break Frequency Equations” on page 17 should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at fP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 33 by adding the Modulator Gain (in dB)
to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
VIN
DRIVER
OSC
PWM
COMPARATOR
LO
-
ΔVOSC
DRIVER
+
PHASE
VDDQ
CO
ESR
(PARASITIC)
ZFB
VE/A
ZIN
-
+
REFERENCE
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
1
f ESR = -------------------------------------------2π x ESR x C O
The compensation network consists of the error amplifier
(internal to the ISL8501) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180°. The following equations relate the compensation
network’s poles, zeros and gain to the components (R1 , R2 ,
R4, C1 , C2 , and C3) in Figure 2. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
ZFB
C3
(EQ. 7)
17
(EQ. 8)
C2
VDDQ
ZIN
C1
R4
R3
R1
COMP
+
FB
R2
ISL8501
REFERENCE
FIGURE 32. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
FN6500.1
July 12, 2007
ISL8501
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
A more detailed explanation of voltage mode control of a
buck regulator can be found in Tech Brief TB417, titled
“Designing Stable Compensation Networks for Single Phase
Voltage Mode Buck Regulators.”
100
fZ1 fZ2
fP1
fP2
80
OPEN LOOP
ERROR AMP GAIN
GAIN (dB)
60
40
20
20LOG
(R2/R1)
20LOG
(VIN/ΔVOSC)
0
-20
COMPENSATION
GAIN
CLOSED LOOP
GAIN
MODULATOR
GAIN
-40
fLC
fESR
-60
10
100
1k
10k
100k
1M
10M
represent numerous physical capacitors. Dedicate one solid
layer (usually a middle layer of the PC board) for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring.
In order to dissipate heat generated by the internal LDO and
MOSFET, the ground pad, pin 29, should be connected to
the internal ground plane through at least four vias. This
allows the heat to move away from the IC and also ties the
pad to the ground plane through a low impedance path.
The switching components should be placed close to the
ISL8501 first. Minimize the length of the connections
between the input capacitors, CIN, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load.
FREQUENCY (Hz)
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
500kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes these
voltage spikes.
As an example, consider the turn-off transition of the upper
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the Schottky diode. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
VIN
PVCC
5V
VIN
CIN
CBP1
ISL8501
L
RBP
VOUT1
PHASE
VCC
CBP2
D
LOAD
FIGURE 33. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
COUT1
PGND
COMP
C2
C1
R2
R1
FB
R4
C3
R3
GND PAD
There are two sets of critical components in the ISL8501
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components, which connect to sensitive
nodes or supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 34
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
18
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 34. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
FN6500.1
July 12, 2007
ISL8501
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4X 2.5
4.00
A
20X 0.50
B
PIN 1
INDEX AREA
PIN #1 CORNER
(C 0 . 25)
24
19
1
4.00
18
2 . 50 ± 0 . 15
13
0.15
(4X)
12
7
0.10 M C A B
0 . 07
24X 0 . 23 +- 0
. 05 4
24X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0 . 1
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 50 )
( 20X 0 . 5 )
C
0 . 2 REF
5
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
19
FN6500.1
July 12, 2007