AD AD5757 Quad channel, 16-bit,serial input, 4 ma to 20 ma output dac, dynamic power control Datasheet

Quad Channel, 16-Bit,
Serial Input, 4 mA to 20 mA Output DAC,
Dynamic Power Control, HART Connectivity
AD5757
a dc-to-dc boost converter optimized for minimum on-chip
power dissipation.
FEATURES
16-bit resolution and monotonicity
Dynamic power control for thermal management
or external PMOS mode
Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,
or 0 mA to 24 mA
±0.05% total unadjusted error (TUE) maximum
User programmable offset and gain
On-chip diagnostics
On-chip reference (±10 ppm/°C maximum)
−40°C to +105°C temperature range
Each channel has a corresponding CHART pin so that HART
signals can be coupled onto the current output of the AD5757.
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 30 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, DSP, and microcontroller interface
standards. The interface also features optional CRC-8 packet
error checking, as well as a watchdog timer that monitors
activity on the interface.
PRODUCT HIGHLIGHTS
APPLICATIONS
1.
2.
3.
4.
Process control
Actuator control
PLCs
HART network connectivity
Dynamic power control for thermal management.
16-bit performance.
Multichannel.
HART compliant.
COMPANION PRODUCTS
GENERAL DESCRIPTION
Product Family: AD5755-1, AD5755
External References: ADR445, ADR02
Digital Isolators: ADuM1410, ADuM1411
Power: ADP2302, ADP2303
Additional companion products on the AD5757 product page
The AD5757 is a quad, current output DAC that operates with a
power supply range from 10.8 V to 33 V. On-chip dynamic
power control minimizes package power dissipation by regulating the voltage on the output driver from 7.4 V to 29.5 V using
FUNCTIONAL BLOCK DIAGRAM
AVCC
5.0V
AGND
AVDD
+15V
SWx
DVDD
VBOOST_x
7.4V TO 29.5V
DGND
LDAC
DC-TO-DC
CONVERTER
SCLK
SDIN
SYNC
SDO
CLEAR
DIGITAL
INTERFACE
IOUT_x
+
FAULT
ALERT
GAIN REG A
OFFSET REG A
AD1
AD0
REFIN
CURRENT AND
VOLTAGE
OUTPUT RANGE
SCALING
RSET_x
CHARTx
DAC CHANNEL A
REFERENCE
DAC CHANNEL B
DAC CHANNEL C
AD5757
DAC CHANNEL D
09225-101
REFOUT
DAC A
NOTES
1. x = A, B, C, AND D.
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD5757
TABLE OF CONTENTS
Features .............................................................................................. 1
Control Registers........................................................................ 28
Applications....................................................................................... 1
Readback Operation .................................................................. 31
General Description ......................................................................... 1
Device Features............................................................................... 33
Product Highlights ........................................................................... 1
Output Fault................................................................................ 33
Companion Products ....................................................................... 1
Digital Offset and Gain Control............................................... 33
Functional Block Diagram .............................................................. 1
Status Readback During a Write .............................................. 33
Revision History ............................................................................... 2
Asynchronous Clear................................................................... 33
Detailed Functional Block Diagram .............................................. 3
Packet Error Checking............................................................... 33
Specifications..................................................................................... 4
Watchdog Timer......................................................................... 34
AC Performance Characteristics ................................................ 6
Output Alert................................................................................ 34
Timing Characteristics ................................................................ 6
Internal Reference ...................................................................... 34
Absolute Maximum Ratings............................................................ 9
External Current Setting Resistor ............................................ 34
ESD Caution.................................................................................. 9
HART ........................................................................................... 34
Pin Configuration and Function Descriptions........................... 10
Digital Slew Rate Control.......................................................... 35
Typical Performance Characteristics ........................................... 13
Power Dissipation Control........................................................ 35
Current Outputs ......................................................................... 13
DC-to-DC Converters............................................................... 35
DC-to-DC Block......................................................................... 18
AICC Supply Requirements—Static .......................................... 37
Reference ..................................................................................... 19
AICC Supply Requirements—Slewing ...................................... 37
General......................................................................................... 20
External PMOS Mode................................................................ 38
Terminology .................................................................................... 21
Applications Information .............................................................. 39
Theory of Operation ...................................................................... 22
Current Output Mode with Internal RSET ................................ 39
DAC Architecture....................................................................... 22
Precision Voltage Reference Selection..................................... 39
Power-On State of the AD5757 ................................................ 22
Driving Inductive Loads............................................................ 39
Serial Interface ............................................................................ 22
Transient Voltage Protection .................................................... 40
Transfer Function ....................................................................... 23
Microprocessor Interfacing....................................................... 40
Registers ........................................................................................... 24
Layout Guidelines....................................................................... 40
Programming Sequence to Write/Enable the Output
Correctly ...................................................................................... 25
Galvanically Isolated Interface ................................................. 41
Outline Dimensions ....................................................................... 42
Changing and Reprogramming the Range ............................. 25
Ordering Guide .......................................................................... 42
Data Registers ............................................................................. 26
REVISION HISTORY
4/11—Revision 0: Initial Version
5/11—Rev. 0 to Rev. A
Changes Features Section ................................................................ 1
Changes to Figure 2.......................................................................... 3
Changed AVDD Min Parameter from 10.8 V to 9 V ..................... 5
Changes to Pin 22, Pin31, Pin 49 Descriptions .......................... 11
Changes to Pin 58 Descriptions.................................................... 12
Changes to Figure 8, Figure 9, and Figure 10 ............................. 13
Added Figure 23, Renumbered Sequentially .............................. 15
Added Figure 29.............................................................................. 16
Added External PMOS Mode Section and Figure 62 ................ 38
Rev. A | Page 2 of 44
AD5757
DETAILED FUNCTIONAL BLOCK DIAGRAM
AVCC
5.0V
AGND
DVDD
DGND
LDAC
CLEAR
SCLK
SDIN
SYNC
SDO
INPUT
SHIFT
REGISTER
AND
CONTROL
STATUS
REGISTER
REFOUT
SWA
POWER-ON
RESET
FAULT
ALERT
AVDD
+15V
VBOOST_A
DC-TO-DC
CONVERTER
POWER
CONTROL
16
INPUT
REG A
+
DAC
REG A
16
7.4V TO 29.5V VSEN1
REG
R2
DAC A
VSEN2
R3
GAIN REG A
OFFSET REG A
IOUT_A
R1
WATCHDOG
TIMER
(SPI ACTIVITY)
RSET_A
CHARTA
VREF
DAC CHANNEL A
AD1
AD0
REFERENCE
BUFFERS
AD5757
IOUT_B, IOUT_C, IOUT_D
RSET_B, RSET_C, RSET_D
DAC CHANNEL B
DAC CHANNEL C
CHARTB, CHARTC, CHARTD
DAC CHANNEL D
SWB, SWC, SWD
Figure 2.
Rev. A | Page 3 of 44
VBOOST_B, VBOOST_C, VBOOST_D
09225-001
REFIN
AD5757
SPECIFICATIONS
AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter 1
CURRENT OUTPUT
Output Current Ranges
Resolution
ACCURACY (EXTERNAL RSET)
Total Unadjusted Error (TUE)
Min
0
0
4
16
TUE Long-Term Stability
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Offset Error3, 4
Offset Error Drift2
Gain Error
Gain TC2
Full-Scale Error3, 4
Max
Unit
24
20
20
mA
mA
mA
Bits
−0.006
−1
−0.05
−0.05
−0.05
−0.14
−0.11
−0.006
−0.004
−1
−0.05
−0.04
−0.12
−0.06
−0.14
−0.1
Full-Scale TC2
DC Crosstalk4
OUTPUT CHARACTERISTICS2
Current Loop Compliance Voltage
±0.009
100
±0.005
±4
±0.004
±3
±0.008
±5
0.0005
±0.009
180
±0.007
±6
±0.002
±9
±0.007
±14
−0.011
VBOOST_x −
2.4
+0.05
+0.006
+1
+0.05
+0.05
+0.05
+0.14
+0.11
+0.006
+0.004
+1
+0.05
+0.04
+0.12
+0.06
+0.14
+0.1
VBOOST_x −
2.7
% FSR
ppm FSR
% FSR
LSB
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR
% FSR
% FSR
LSB
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
% FSR
90
140
Resistive Load
100
0.02
4.95
45
5
150
1000
ppm FSR
ppm FSR
Ω
1
MΩ
μA/V
5.05
Rev. A | Page 4 of 44
Drift after 1000 hours, TJ = 150°C
Guaranteed monotonic
External RSET
TA = 25°C
Drift after 1000 hours, TJ = 150°C
TA = 25°C
Guaranteed monotonic
TA = 25°C
TA = 25°C
TA = 25°C
Internal RSET
V
Output Current Drift vs. Time
Output Impedance
DC PSRR
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Test Conditions/Comments
Assumes ideal resistor
−0.05
TUE Long-Term Stability
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Offset Error
Offset Error Drift 2
Gain Error
Gain TC2
Full-Scale Error
Full-Scale TC2
DC Crosstalk
ACCURACY (INTERNAL RSET)
Total Unadjusted Error (TUE) 3 , 4
Typ
V
MΩ
Drift after 1000 hours, ¾ scale output, TJ = 150°C
External RSET
Internal RSET
The dc-to-dc converter has been characterized
with a maximum load of 1 kΩ, chosen such that
compliance is not exceeded; see Figure 31 and
DC-DC MaxV bits in Table 24
For specified performance
AD5757
Parameter 1
Reference Output
Output Voltage
Reference TC2
Output Noise (0.1 Hz to 10 Hz)2
Noise Spectral Density2
Output Voltage Drift vs. Time2
Capacitive Load2
Load Current
Min
Typ
Max
Unit
Test Conditions/Comments
4.995
−10
5
±5
7
100
180
1000
9
5.005
+10
V
ppm/°C
μV p-p
nV/√Hz
ppm
nF
mA
TA = 25°C
Short-Circuit Current
Line Regulation2
10
3
mA
ppm/V
Load Regulation2
95
ppm/mA
Thermal Hysteresis2
160
5
ppm
ppm
0.425
10
0.8
Ω
nA
A
DC-TO-DC
Switch
Switch On Resistance
Switch Leakage Current
Peak Current Limit
Oscillator
Oscillator Frequency
Maximum Duty Cycle
DIGITAL INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
DIGITAL OUTPUTS2
SDO, ALERT
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage Current
High Impedance Output
Capacitance
FAULT
VOL, Output Low Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
POWER REQUIREMENTS
AVDD
DVDD
AVCC
AIDD
DICC
AICC
IBOOST 5
Power Dissipation
11.5
13
14.5
89.6
%
2
0.8
+1
−1
2.6
0.4
DVDD − 0.5
−1
See Figure 43
See Figure 42
First temperature cycle
Second temperature cycle
This oscillator is divided down to give the dc-to-dc
converter switching frequency
At 410 kHz dc-to-dc switching frequency
JEDEC compliant
Per pin
Per pin
Sinking 200 μA
Sourcing 200 μA
0.4
V
V
V
10 kΩ pull-up resistor to DVDD
At 2.5 mA
10 kΩ pull-up resistor to DVDD
33
5.5
5.5
7.5
11
V
V
V
mA
mA
1
1
mA
mA
mW
+1
0.6
3.6
7
9.2
V
V
μA
pF
See Figure 42
V
V
μA
pF
2.5
9
2.7
4.5
MHz
At 10 kHz
Drift after 1000 hours, TJ = 150°C
155
1
VIH = DVDD, VIL = DGND, internal oscillator running,
over supplies
Over supplies
Per channel, current output mode, 0 mA output
AVDD = 15 V, DVCC = 5 V, dc-to-dc converter enable,
current output mode, outputs disabled
Temperature range: −40°C to +105°C; typical at +25°C.
Guaranteed by design and characterization; not production tested.
3
For current outputs with internal RSET, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled
loaded with the same code.
4
See the Current Output Mode with Internal RSET section for more explanation of the dc crosstalk.
5
Efficiency plots in Figure 33, Figure 34, Figure 35, and Figure 36 include the IBOOST quiescent current.
2
Rev. A | Page 5 of 44
AD5757
AC PERFORMANCE CHARACTERISTICS
AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
DYNAMIC PERFORMANCE
Current Output
Output Current Settling Time
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
Output Noise Spectral Density
1
Min
Typ
Max
Unit
Test Conditions/Comments
15
See test conditions/
comments
0.15
μs
ms
To 0.1% FSR (0 mA to 24 mA)
See Figure 26, Figure 27, and Figure 28
LSB p-p
16-bit LSB, 0 mA to 24 mA range
0.5
nA/√Hz
Measured at 10 kHz, midscale output, 0
mA to 24 mA range
Guaranteed by design and characterization; not production tested.
TIMING CHARACTERISTICS
AVDD = VBOOST_x= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19 4
Limit at TMIN, TMAX
33
13
13
13
13
198
5
5
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
5
10
500
See the AC Performance
Characteristics section
10
5
40
21
5
500
800
20
5
μs min
ns min
ns max
μs max
ns min
μs max
ns max
μs min
μs min
ns min
ns min
μs min
μs min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th/32nd SCLK falling edge to SYNC rising edge (see Figure 54)
SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated or any channel has
digital slew rate control enabled)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLEAR high time
CLEAR activation time
SCLK rising edge to SDO valid
SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated)
SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated)
LDAC falling edge to SYNC rising edge
RESET pulse width
SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated)
SYNC high to next SYNC low (digital slew rate control disabled) (single DAC
updated)
1
Guaranteed by design and characterization; not production tested.
All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3
See Figure 3, Figure 4, Figure 5, and Figure 6.
4
This specification applies if LDAC is held low during the write cycle; otherwise, see t9.
2
Rev. A | Page 6 of 44
AD5757
Timing Diagrams
t1
SCLK
1
2
24
t3
t6
t2
t4
t5
SYNC
t8
t7
SDIN
t19
LSB
MSB
t10
t10
t9
LDAC
t17
t12
t11
IOUT_x
LDAC = 0
t12
t16
IOUT_x
t13
CLEAR
t14
IOUT_x
09225-002
t18
RESET
Figure 3. Serial Interface Timing Diagram
SCLK
1
1
24
24
t6
SYNC
MSB
LSB
MSB
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
MSB
LSB
NOP CONDITION
LSB
MSB
UNDEFINDED
LSB
SELECTED REGISTER DATA
CLOCKED OUT
t15
Figure 4. Readback Timing Diagram
Rev. A | Page 7 of 44
09225-003
SDIN
AD5757
1
2
MSB
SCLK
SDO
R/W
DUT_
AD1
DUT_
AD0
SDO DISABLED
X
X
X
DB15
DB14
DB1
DB0
SDO_
ENAB
STATUS
STATUS
STATUS
STATUS
Figure 5. Status Readback During Write
200µA
TO OUTPUT
PIN
IOL
VOH (MIN) OR
VOL (MAX)
CL
50pF
200µA
IOH
Figure 6. Load Circuit for SDO Timing Diagram
Rev. A | Page 8 of 44
09225-005
SDIN
09225-004
SYNC
AD5757
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter
AVDD, VBOOST_x to AGND, DGND
AVCC to AGND
DVDD to DGND
Digital Inputs to DGND
Digital Outputs to DGND
REFIN, REFOUT to AGND
IOUT_x to AGND
SWx to AGND
AGND, GNDSWx to DGND
Operating Temperature Range (TA)
Industrial1
Storage Temperature Range
Junction Temperature (TJ max)
64-Lead LFCSP
θJA Thermal Impedance2
Power Dissipation
Lead Temperature
Soldering
1
2
Rating
−0.3 V to +33 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to DVDD + 0.3 V or +7 V
(whichever is less)
−0.3 V to DVDD + 0.3 V or +7 V
(whichever is less)
−0.3 V to AVDD + 0.3 V or +7 V
(whichever is less)
AGND to VBOOST_x or 33 V if using
the dc-to-dc circuitry
−0.3 V to +33 V
−0.3 V to +0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +105°C
−65°C to +150°C
125°C
20°C/W
(TJ max – TA)/θJA
JEDEC industry standard
J-STD-020
Power dissipated on chip must be derated to keep the junction temperature
below 125°C.
Based on a JEDEC 4-layer test board.
Rev. A | Page 9 of 44
AD5757
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RSET_C
RSET_D
REFOUT
REFIN
NC
CHARTD
IGATED
COMPDCDC_D
VBOOST_D
NC
IOUT_D
AGND
NC
CHARTC
NC
IGATEC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD5757
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMPDCDC_C
IOUT_C
VBOOST_C
AVCC
SWC
GNDSWC
GNDSWD
SWD
AGND
SWA
GNDSWA
GNDSWB
SWB
AGND
VBOOST_B
IOUT_B
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD SHOULD BE CONNECTED TO AGND, OR ALTERNATIVELY,
IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT
THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
09225-006
DGND
RESET
AVDD
NC
CHARTA
IGATEA
COMPDCDC_A
VBOOST_A
NC
IOUT_A
AGND
NC
CHARTB
NC
IGATEB
COMPDCDC_B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RSET_B
RSET_A
REFGND
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DVDD
DGND
LDAC
CLEAR
ALERT
FAULT
Figure 7. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
RSET_B
2
RSET_A
3, 4
5
6
7
REFGND
AD0
AD1
SYNC
8
SCLK
9
10
11
12, 17
13
SDIN
SDO
DVDD
DGND
LDAC
14
CLEAR
Description
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_B
temperature drift performance. See the Device Features section.
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_A
temperature drift performance. See the Device Features section.
Ground Reference Point for Internal Reference.
Address Decode for the Device Under Test (DUT) on the Board.
Address Decode for the DUT on the Board.
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the input shift register on the rising edge of SCLK. This pin operates at
clock speeds of up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5.
Digital Supply. The voltage range is from 2.7 V to 5.5 V.
Digital Ground.
Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When
tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held
high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at
the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The
LDAC pin must not be left unconnected.
Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed
clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more
information. When CLEAR is active, the DAC output register cannot be written to.
Rev. A | Page 10 of 44
AD5757
Pin No.
15
Mnemonic
ALERT
16
FAULT
18
19
20, 25,
28, 30,
50, 52,
55, 60
21
22
RESET
AVDD
NC
CHARTA
IGATEA
23
COMPDCDC_A
24
VBOOST_A
26
27, 40, 53
29
31
IOUT_A
AGND
CHARTB
IGATEB
32
COMPDCDC_B
33
34
IOUT_B
VBOOST_B
35
36
AGND
SWB
37
38
39
GNDSWB
GNDSWA
SWA
41
SWD
42
43
44
GNDSWD
GNDSWC
SWC
45
46
AVCC
VBOOST_C
47
48
IOUT_C
COMPDCDC_C
49
IGATEC
Description
Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a
predetermined time. See the Device Features section for more information.
Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in
voltage mode is detected, a PEC error is detected, or an overtemperature is detected (see the Device Features
section). Open-drain output.
Hardware Reset. Active Low Input.
Positive Analog Supply. The voltage range is from 10.8 V to 33 V.
No Connect. Do not connect to this pin.
HART Input Connection for DAC Channel A.
Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter. See
the External PMOS Mode section for more information.
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation
Capacitors and the AICC Supply Requirements—Slewing sections in the Device Features section for more
information).
Supply for Channel A Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as
shown in Figure 56.
Current Output Pin for DAC Channel A.
Ground Reference Point for Analog Circuitry. This must be connected to 0 V.
HART Input Connection for DAC Channel B.
Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter.
See the External PMOS Mode section for more information.
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation
Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more
information).
Current Output Pin for DAC Channel B.
Supply for Channel B Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as
shown in Figure 56.
Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V.
Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown
in Figure 56.
Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground.
Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground.
Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown
in Figure 56.
Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown
in Figure 56.
Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground.
Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground.
Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown
in Figure 56.
Supply for DC-to-DC Circuitry.
Supply for Channel C Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as
shown in Figure 56.
Current Output Pin for DAC Channel C.
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation
Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more
information).
Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter. See
the External PMOS Mode section for more information.
Rev. A | Page 11 of 44
AD5757
Pin No.
51
54
56
Mnemonic
CHARTC
IOUT_D
VBOOST_D
57
COMPDCDC_D
58
IGATED
59
61
62
CHARTD
REFIN
REFOUT
63
RSET_D
64
RSET_C
EPAD
Description
HART Input Connection for DAC Channel C.
Current Output Pin for DAC Channel D.
Supply for Channel D Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as
shown in Figure 56.
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation
Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more
information).
Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter.
See the External PMOS Mode section for more information.
HART Input Connection for DAC Channel D.
External Reference Voltage Input.
Internal Reference Voltage Output. It is recommended to place a 0.1 μF capacitor between REFOUT and
REFGND.
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_D
temperature drift performance. See the Device Features section.
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_C
temperature drift performance. See the Device Features section.
Exposed Pad. This exposed pad should be connected to AGND, or, alternatively, it can be left electrically
unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal
performance.
Rev. A | Page 12 of 44
AD5757
TYPICAL PERFORMANCE CHARACTERISTICS
CURRENT OUTPUTS
0.0025
0.0010
AV DD = 15V
TA = 25°C
0.0008
0.0006
0.0010
0.0004
INL ERROR (%FSR)
0.0015
0.0005
0
–0.0005
–0.0010
–0.0020
20mA,
20mA,
20mA,
20mA,
20mA,
–0.0025
0
10000
EXTERNAL R SET
EXTERNAL R SET , WITH DC-TO-DC CONVERTER
INTERNAL R SET
INTERNAL R SET, WITH DC-TO-DC CONVERTER
EXTERNAL R SET , EXTERNAL PMOS MODE
20000
30000
40000
50000
0
–0.0002
20mA RANGE MAX INL
24mA RANGE MAX INL
20mA RANGE MIN INL
20mA RANGE MAX INL
20mA RANGE MAX INL
24mA RANGE MIN INL
AVDD = 15V
–0.0004
–0.0006
–0.0008
60000
CODE
–0.0010
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 11. Integral Nonlinearity vs. Temperature, Internal RSET
Figure 8. Integral Nonlinearity vs. Code
0.0020
1.0
4mA TO
4mA TO
4mA TO
4mA TO
4mA TO
0.8
0.6
20mA,
20mA,
20mA,
20mA,
20mA,
EXTERNAL R SET
EXTERNAL R SET , WITH DC-TO-DC CONVERTER
INTERNAL R SET
INTERNAL R SET, WITH DC-TO-DC CONVERTER
EXTERNAL R SET , EXTERNAL PMOS MODE
4mA TO 20mA RANGE MAX INL
0mA TO 24mA RANGE MAX INL
0mA TO 20mA RANGE MIN INL
0.0015
0.0010
0.4
INL ERROR (%FSR)
DNL ERROR (LSB)
4mA TO
0mA TO
0mA TO
0mA TO
4mA TO
0mA TO
0.0002
09225-152
4mA TO
4mA TO
4mA TO
4mA TO
4mA TO
–0.0015
09225-149
INL ERROR (%FSR)
0.0020
0.2
0
–0.2
–0.4
0.0005
0mA TO 20mA RANGE MAX INL
4mA TO 20mA RANGE MIN INL
0mA TO 24mA RANGE MIN INL
0
–0.0005
–0.0010
–0.6
20000
30000
40000
50000
60000
CODE
–0.0020
–40
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 12. Integral Nonlinearity vs. Temperature, External RSET
Figure 9. Differential Nonlinearity vs. Code
1.0
0.035
AV DD = 15V
0.030 TA = 25°C
ALL CHANNELS ENABLED
0.025
0.8
0.010
20mA,
20mA,
20mA,
20mA,
20mA,
EXTERNAL R SET
EXTERNAL R SET , WITH DC-TO-DC CONVERTER
INTERNAL R SET
INTERNAL R SET , WITH DC-TO-DC CONVERTER
EXTERNAL R SET , EXTERNAL PMOS MODE
0.005
0
0.4
0.2
–0.2
–0.4
–0.005
–0.6
–0.010
–0.8
–0.015
0
10000
20000
30000
40000
50000
CODE
60000
DNL ERROR MAX
DNL ERROR MIN
0
–1.0
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
Figure 13. Differential Nonlinearity vs. Temperature
Figure 10. Total Unadjusted Error vs. Code
Rev. A | Page 13 of 44
100
09225-154
4mA TO
4mA TO
4mA TO
4mA TO
4mA TO
DNL ERROR (%FSR)
0.020
0.015
AVDD = 15V
ALL RANGES
INTERNAL AND EXTERNAL R SET
0.6
09225-151
TOTAL UNADJUSTED ERROR (%FSR)
–20
09225-153
10000
09225-150
–1.0
0
AVDD = 15V
–0.0015
AV DD = 15V
TA = 25°C
–0.8
AD5757
0.02
0.03
0.01
0.01
0
–0.01
–0.02
–0.03
AVDD = 15V
4mA TO
0mA TO
0mA TO
4mA TO
0mA TO
0mA TO
–0.04
–0.05
–0.06
–0.07
–0.08
–40
–20
0
20mA INTERNAL RSET
20mA INTERNAL RSET
24mA INTERNAL RSET
20mA EXTERNAL R SET
20mA EXTERNAL R SET
24mA EXTERNAL R SET
20
40
60
TEMPERATURE (°C)
–0.01
–0.02
AVDD = 15V
–0.03
4mA TO
0mA TO
0mA TO
4mA TO
0mA TO
0mA TO
–0.04
–0.05
80
100
–0.06
–40
0.03
20
40
60
TEMPERATURE (°C)
80
100
0.0025
0.02
0.0020
0.01
4mA TO 20mA RANGE MAX INL
4mA TO 20mA RANGE MIN INL
TA = 25°C
0.0015
INL ERROR (%FSR)
0
–0.01
–0.02
AVDD = 15V
–0.05
–0.06
–0.07
–0.08
–40
–20
0
20mA INTERNAL RSET
20mA INTERNAL RSET
24mA INTERNAL RSET
20mA EXTERNAL R SET
20mA EXTERNAL R SET
24mA EXTERNAL R SET
20
40
60
TEMPERATURE (°C)
0.0005
0
–0.0005
–0.0010
–0.0015
80
100
–0.0020
10
0.0015
0.015
0.0010
0.010
0.0005
INL ERROR (%FSR)
0.020
0.005
0
AVDD = 15V
–0.010
–0.015
–0.020
–40
–20
0
20mA INTERNAL RSET
20mA INTERNAL RSET
24mA INTERNAL RSET
20mA EXTERNAL RSET
20mA EXTERNAL RSET
24mA EXTERNAL RSET
20
40
60
TEMPERATURE (°C)
80
25
30
0
–0.0005
–0.0010
–0.0015
–0.0020
100
09225-158
4mA TO
0mA TO
0mA TO
4mA TO
0mA TO
0mA TO
20
SUPPLY (V)
Figure 18. Integral Nonlinearity Error vs. AVDD,
Over Supply, External RSET
Figure 15. Full-Scale Error vs. Temperature
–0.005
15
09225-056
4mA TO
0mA TO
0mA TO
4mA TO
0mA TO
0mA TO
–0.04
0.0010
Figure 16. Offset Error vs. Temperature
–0.0025
10
4mA TO 20mA RANGE MAX INL
4mA TO 20mA RANGE MIN INL
TA = 25°C
15
20
SUPPLY (V)
25
Figure 19. Integral Nonlinearity Error vs. AVDD,
Over Supply, Internal RSET
Rev. A | Page 14 of 44
30
09225-057
–0.03
09225-157
FULL-SCALE ERROR (%FSR)
0
Figure 17. Gain Error vs. Temperature
Figure 14. Total Unadjusted Error vs. Temperature
OFFSET ERROR (%FSR)
–20
20mA INTERNAL RSET
20mA INTERNAL RSET
24mA INTERNAL RSET
20mA EXTERNAL R SET
20mA EXTERNAL R SET
24mA EXTERNAL R SET
09225-159
GAIN ERROR (%FSR)
0
09225-155
TOTAL UNADJSUTED ERROR (%FSR)
0.02
AD5757
0.006
DNL ERROR (%FSR)
0.6
0.4
0.2
DNL ERROR MAX
DNL ERROR MIN
0
–0.2
–0.4
–0.6
–0.8
15
20
25
30
SUPPLY (V)
0
–0.002
–0.006
–0.008
10
20
25
30
0.008
4
CURRENT (µA)
5
0.006
0.004
4mA TO 20mA RANGE MAX TUE
4mA TO 20mA RANGE MIN TUE
TA = 25°C
20
SUPPLY (V)
3
2
1
25
30
0
09225-060
15
AVDD = 15V
TA = 25°C
RLOAD = 300Ω
0
5
10
15
20
TIME (µs)
Figure 21. Total Unadjusted Error vs. AVDD, External RSET
Figure 24. Output Current vs. Time on Power-Up
0
4
–0.002
2
–0.004
0
–0.010
VOLTAGE (µA)
–0.008
4mA TO 20mA RANGE MAX TUE
4mA TO 20mA RANGE MIN TUE
TA = 25°C
–0.012
–0.014
–2
–4
–6
AVDD = 15V
TA = 25°C
RLOAD = 300Ω
INT_ENABLE
–0.016
–8
–0.018
–0.020
10
15
20
SUPPLY (V)
25
30
Figure 22. Total Unadjusted Error vs. AVDD, Internal RSET
–10
0
1
2
3
4
5
TIME (µs)
Figure 25. Output Current vs. Time on Output Enable
Rev. A | Page 15 of 44
6
09225-063
–0.006
09225-061
TOTAL UNADJUSTED ERROR (%FSR)
15
6
0.010
0
10
MIN OF TUE
–0.010
Figure 23. Total Unadjusted Error vs. VBOOST_X, Using External PMOS Mode
0.012
0.002
TA = 25°C
EXTERNAL PMOS (NTLJS4149)
4mA TO 20mA RANGE
RLOAD = 300Ω
–0.004
VBOOST_X SUPPLY (V)
Figure 20. Differential Nonlinearity Error vs. AVDD
TOTAL UNADJUSTED ERROR (%FSR)
0.002
–0.012
09225-162
–1.0
10
MAX OF TUE
0.004
09225-188
0.8
TOTAL UNADJUSTED ERROR (%FSR)
ALL RANGES
INTERNAL AND EXTERNAL R SET
TA = 25°C
09225-062
1.0
30
25
25
20
IOUT
VBOOST
15
10
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
AVCC = 5V
TA = 25°C
5
0
–0.50 –0.25
0
0.25
0.50
0.75
1.00 1.25
1.50 1.75 2.00
TIME (ms)
10
0
–0.25
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
TIME (ms)
Figure 28. Output Current Settling with DC-to-DC Converter vs. Time and
AVCC (See Figure 56)
25
25
20
IOUT,
IOUT,
IOUT,
15
TA = –40°C
TA = +25°C
TA = +105°C
10
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
AVCC = 5V
0
0.25
0.50
0.75
1.00
TIME (ms)
1.25
1.50
1.75
15
TA = 25°C
EXTERNAL PMOS (NTLJS4149)
4mA TO 20mA RANGE
RLOAD = 300Ω
VBOOST_X = 24V
10
IOUT (20mA TO 4mA STEP)
5
0
–5
09225-168
5
IOUT (4mA TO 20mA STEP)
20
0
5
10
TIME (µs)
Figure 27. Output Current Settling with DC-to-DC Converter vs. Time and
Temperature (See Figure 56)
15
20
09225-189
TOTAL UNADJUSTED ERROR (%FSR)
30
OUTPUT CURRENT (mA)
IOUT, AVCC = 4.5V
IOUT, AVCC = 5.0V
IOUT, AVCC = 5.5V
15
5
Figure 26. Output Current and VBOOST_x Settling Time with DC-to-DC
Converter (See Figure 56)
0
–0.25
20
09225-169
OUTPUT CURRENT (mA)
30
09225-167
OUTPUT CURRENT (mA)
AD5757
Figure 29. Output Current Settling Time with External PMOS Transistor
Rev. A | Page 16 of 44
AD5757
8
–20
6
IOUT_x PSRR (dB)
4
2
0
–2
–4
–6
AVCC = 5V
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
–8
–10
0
2
4
6
8
10
12
14
TIME (µs)
Figure 30. Output Current vs. Time with DC-to-DC Converter (See Figure 56)
8
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
HEADROOM VOLTAGE (V)
7
6
5
4
3
2
0
5
10
CURRENT (mA)
15
20
09225-067
1
0
AVDD = 15V
VBOOST = 15V
TA = 25°C
–40
–60
–80
–100
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNAL R SET
TA = 25°C
09225-170
CURRENT (AC COUPLED) (µA)
0
20mA OUTPUT
10mA OUTPUT
Figure 31. DC-to-DC Converter Headroom vs. Output Current (See Figure 56)
Rev. A | Page 17 of 44
–120
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 32. IOUT_x PSRR vs. Frequency
1M
10M
09225-068
10
AD5757
DC-TO-DC BLOCK
90
80
AVCC = 4.5V
AVCC = 5V
AVCC = 5.5V
20mA
70
IOUT_x EFFICIENCY (%)
VBOOST_x EFFICIENCY (%)
80
75
70
65
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNAL RSET
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
55
50
0
4
8
12
16
24
20
50
40
30
CURRENT (mA)
20
–40
09225-016
60
60
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNAL RSET
AVCC = 5V
fSW = 410 kHz
INDUCTOR = 10µH (XAL4040-103)
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 33. Efficiency at VBOOST_x vs. Output Current (See Figure 56)
09225-019
85
Figure 36. Output Efficiency vs. Temperature (See Figure 56)
0.6
90
20mA
0.5
SWITCH RESISTANCE (Ω)
80
75
70
60
55
50
–40
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNAL RSET
AVCC = 5V
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
–20
0
20
40
60
80
100
Figure 34. Efficiency at VBOOST_x vs. Temperature (See Figure 56)
AVCC = 4.5V
AVCC = 5V
AVCC = 5.5V
50
0mA TO 24mA RANGE
1kΩ LOAD
EXTERNAL RSET
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
20
0
4
8
12
16
20
24
CURRENT (mA)
09225-018
IOUT_x EFFICIENCY (%)
60
30
0.2
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 37. Switch Resistance vs. Temperature
80
40
0.3
0.1
TEMPERATURE (°C)
70
0.4
Figure 35. Output Efficiency vs. Output Current (See Figure 56)
Rev. A | Page 18 of 44
100
09225-123
65
09225-017
VBOOST_x EFFICIENCY (%)
85
AD5757
REFERENCE
5.0050
16
AVDD
REFOUT
TA = 25°C
14
12
5.0040
5.0035
REFOUT (V)
8
6
4
5.0025
5.0020
5.0015
2
5.0010
0
0.2
0.4
0.6
0.8
1.0
1.2
5.0000
–40
09225-010
0
Figure 38. REFOUT Turn-On Transient
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 41. REFOUT vs. Temperature (When the AD5757 is soldered onto a
PCB, the reference shifts due to thermal shock on the package. The average
output voltage shift is –4 mV. Measurement of these parts after seven days
shows that the outputs typically shift back 2 mV toward their initial values.
This second shift is due to the relaxation of stress incurred during soldering.)
4
5.002
AVDD = 15V
TA = 25°C
3
AVDD = 15V
TA = 25°C
5.001
5.000
REFOUT (V)
2
1
0
4.999
4.998
–1
4.997
–2
4.996
0
2
4
6
8
10
TIME (s)
4.995
09225-011
–3
–20
09225-163
5.0005
TIME (ms)
REFOUT (µV)
5.0030
0
2
4
6
8
10
LOAD CURRENT (mA)
Figure 39. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)
09225-014
VOLTAGE (V)
10
–2
30 DEVICES SHOWN
AVDD = 15V
5.0045
Figure 42. REFOUT vs. Load Current
150
5.00000
AVDD = 15V
TA = 25°C
TA = 25°C
4.99995
100
4.99990
REFOUT (V)
0
–50
4.99985
4.99980
4.99975
4.99970
–100
0
5
10
15
TIME (ms)
20
Figure 40. REFOUT Output Noise (100 kHz Bandwidth)
4.99960
10
15
20
25
AVDD (V)
Figure 43. REFOUT vs. Supply
Rev. A | Page 19 of 44
30
09225-015
–150
4.99965
09225-012
REFOUT (µV)
50
AD5757
GENERAL
13.4
450
DVCC = 5V
TA = 25°C
400
13.3
350
13.2
250
200
150
13.0
12.9
100
12.8
50
12.7
1
2
3
5
4
SDIN VOLTAGE (V)
12.6
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 44. DICC vs. Logic Input Voltage
Figure 46. Internal Oscillator Frequency vs. Temperature
8
14.4
7
14.2
6
FREQUENCY (MHz)
14.0
5
4
3
2
AIDD
TA = 25°C
IOUT = 0mA
15
20
25
VOLTAGE (V)
30
13.8
13.6
13.4
13.2
09225-009
1
0
10
DVCC = 5.5V
13.0
2.5
DVCC = 5.5V
TA = 25°C
3.0
3.5
4.0
4.5
5.0
5.5
VOLTAGE (V)
Figure 47. Internal Oscillator Frequency vs. DVCC Supply Voltage
Figure 45. AIDD vs. AVDD
Rev. A | Page 20 of 44
09225-021
0
09225-007
0
CURRENT (mA)
13.1
09225-020
FREQUENCY (MHz)
DICC (µA)
300
AD5757
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy, or integral nonlinearity, is a
measure of the maximum deviation, in LSBs, from the best fit
line through the DAC transfer function. A typical INL vs. code
plot is shown in Figure 8.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot is shown in
Figure 9.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5757 is
monotonic over its full operating temperature range.
Offset Error
Offset error is the deviation of the analog output from the ideal
zero-scale output when all DAC registers are loaded with
0x0000.
Gain Error
This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal,
expressed in % FSR.
Gain TC
This is a measure of the change in gain error with changes in
temperature. Gain TC is expressed in ppm FSR/°C.
Full-Scale Error
Full-Scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output should be
full-scale − 1 LSB. Full-scale error is expressed in percent of
full-scale range (% FSR).
Full-Scale TC
Full-scale TC is a measure of the change in full-scale error with
changes in temperature and is expressed in ppm FSR/°C.
Total Unadjusted Error
Total unadjusted error (TUE) is a measure of the output error
taking all the various errors into account, including INL error,
offset error, gain error, temperature, and time. TUE is expressed
in % FSR.
DC Crosstalk
This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC, which is at midscale.
Current Loop Compliance Voltage
The maximum voltage at the IOUT_x pin for which the output
current is equal to the programmed value.
Voltage Reference Thermal Hysteresis
Voltage reference thermal hysteresis is the difference in output
voltage measured at +25°C compared to the output voltage
measured at +25°C after cycling the temperature from +25°C to
−40°C to +105°C and back to +25°C. The hysteresis is specified
for the first and second temperature cycles and is expressed in ppm.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5757 is powered-on. It is specified as the area
of the glitch in nV-sec. See Figure 24.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by
changes in the power supply voltage.
Reference TC
Reference TC is a measure of the change in the reference output
voltage with a change in temperature. It is expressed in ppm/°C.
Line Regulation
Line regulation is the change in reference output voltage due to
a specified change in supply voltage. It is expressed in ppm/V.
Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/mA.
DC-to-DC Converter Headroom
This is the difference between the voltage required at the
current output and the voltage supplied by the dc-to-dc
converter. See Figure 31.
Output Efficiency
I 2OUT × R LOAD
AVCC × AI CC
This is defined as the power delivered to a channel’s load vs. the
power delivered to the channel’s dc-to-dc input.
Efficiency at VBOOST_x
I OUT × V BOOST _ x
AVCC × AI CC
This is defined as the power delivered to a channel’s VBOOST_x
supply vs. the power delivered to the channel’s dc-to-dc input.
The VBOOST_x quiescent current is considered part of the dc-todc converter’s losses.
Rev. A | Page 21 of 44
AD5757
THEORY OF OPERATION
The AD5757 is a quad, precision digital-to-current loop
converter designed to meet the requirements of industrial
process control applications. It provides a high precision, fully
integrated, low cost, single-chip solution for generating current
loop outputs. The current ranges available are 0 mA to 20 mA,
0 mA to 24 mA, and 4 mA to 20 mA. The desired output
configuration is user selectable via the DAC control register.
On-chip dynamic power control minimizes package power
dissipation in current mode.
The DAC core architecture of the AD5757 consists of two
matched DAC sections. A simplified circuit diagram is shown
in Figure 48. The four MSBs of the 16-bit data-word are
decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either ground or the
reference buffer output. The remaining 12 bits of the data-word
drive Switch S0 to Switch S11 of a 12-bit voltage mode R-2R
ladder network.
VOUT
2R
2R
2R
2R
2R
S0
S1
S7/S11
E1
E2
E15
8-/12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
SERIAL INTERFACE
The AD5757 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards. Data coding
is always straight binary.
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If packet error checking, or PEC (see the Device Features
section), is enabled, an additional eight bits must be written to
the AD5757, creating a 32-bit serial interface.
There are two ways in which the DAC outputs can be updated:
individual updating or simultaneous updating of all DACs.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the DAC data register. The addressed DAC output is updated on
the rising edge of SYNC. See Table 3 and Figure 3 for timing
information.
09225-069
2R
On power-up of the AD5757, the IOUT_x pins are in tristate mode.
Input Shift Register
DAC ARCHITECTURE
2R
POWER-ON STATE OF THE AD5757
Figure 48. DAC Ladder Structure
The voltage output from the DAC core is converted to a current
(see Figure 49), which is then mirrored to the supply rail so that
the application simply sees a current source output. The current
outputs are supplied by VBOOST_x.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the DAC data register. Only the first write to each channel’s
DAC data register is valid after LDAC is brought high. Any subsequent writes while LDAC is still held high are ignored, although
they are loaded into the DAC data register. All the DAC outputs
are updated by taking LDAC low after SYNC is taken high.
OUTPUT
I/V AMPLIFIER
VBOOST_x
VREFIN
R2
VOUT_x
R3
T2
LDAC
A2
16-BIT
DAC
16-BIT
DAC
DAC
REGISTER
T1
IOUT_x
A1
DAC INPUT
REGISTER
OFFSET
AND GAIN
CALIBRATION
09225-071
RSET
DAC DATA
REGISTER
Reference Buffers
SCLK
SYNC
SDIN
The AD5757 can operate with either an external or internal
reference. The reference input requires a 5 V reference for
specified performance. This input voltage is then buffered
before it is applied to the DAC.
INTERFACE
LOGIC
SDO
09225-072
Figure 49. Voltage-to-Current Conversion Circuitry
Figure 50. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
Rev. A | Page 22 of 44
AD5757
TRANSFER FUNCTION
For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA
current output ranges, the output current is respectively
expressed as
⎡ 20 mA ⎤
I OUT = ⎢ N ⎥ × D
⎣ 2
⎦
⎡ 24 mA ⎤
I OUT = ⎢ N ⎥ × D
⎦
⎣ 2
⎡ 16 mA ⎤
I OUT = ⎢ N ⎥ × D + 4 mA
⎦
⎣ 2
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
Rev. A | Page 23 of 44
AD5757
REGISTERS
Table 6 shows an overview of the registers for the AD5757.
Table 6. Data, Control, and Readback Registers for the AD5757
Register
Data
DAC Data Register (×4)
Gain Register (×4)
Offset Register (×4)
Clear Code Register (×4)
Control
Main Control Register
Software Register
Slew Rate Control Register (×4)
DAC Control Register (×4)
DC-to-DC Control Register
Readback
Status Register
Description
Used to write a DAC code to each DAC channel. AD5757 data bits = D15 to D0. There are four DAC
data registers, one per DAC channel.
Used to program gain trim, on a per channel basis. AD5757 data bits = D15 to D0. There are four gain
registers, one per DAC channel.
Used to program offset trim, on a per channel basis. AD5757 data bits = D15 to D0. There are four
offset registers, one per DAC channel.
Used to program clear code on a per channel basis. AD5757 data bits = D15 to D0. There are four clear
code registers, one per DAC channel.
Used to configure the part for main operation. Sets functions such as status readback during write,
enables output on all channels simultaneously, powers on all dc-to-dc converter blocks
simultaneously, and enables and sets conditions of the watchdog timer. See the Device Features
section for more details.
Has three functions. Used to perform a reset, to toggle the user bit and, as part of the watchdog timer
feature, to verify correct data communication operation.
Used to program the slew rate of the output. There are four slew rate control registers, one per
channel.
These registers are used to control the following:
Set the output range, for example, 4 mA to 20 mA.
Set whether an internal/external sense resistor is used.
Enable/disable a channel for CLEAR.
Enable/disable internal circuitry on a per channel basis.
Enable/disable output on a per channel basis.
Power on dc-to-dc converters on a per channel basis.
There are four DAC control registers, one per DAC channel.
Use to set the dc-to-dc control parameters. Can control dc-to-dc maximum voltage, phase, and
frequency.
This contains any fault information, as well as a user toggle bit.
Rev. A | Page 24 of 44
AD5757
CHANGING AND REPROGRAMMING THE RANGE
To correctly write to and set up the part from a power-on
condition, use the following sequence:
1.
2.
3.
4.
5.
Perform a hardware or software reset after initial power-on.
The dc-to-dc converter supply block must be configured.
Set the dc-to-dc switching frequency, maximum output
voltage allowed, and the phase that the four dc-to-dc
channels clock at.
Configure the DAC control register on a per channel basis.
The output range is selected, and the dc-to-dc converter
block is enabled (DC_DC bit). Other control bits can be
configured at this point. Set the INT_ENABLE bit;
however, the output enable bit (OUTEN) should not be set.
Write the required code to the DAC data register. This
implements a full DAC calibration internally. Allow at least
200 μs before Step 5 for reduced output glitch.
Write to the DAC control register again to enable the
output (set the OUTEN bit).
When changing between ranges, the same sequence as
described in the Programming Sequence to Write/Enable the
Output Correctly section should be used. It is recommended to
set the range to zero scale prior to disabling the output. Because
the dc-to-dc switching frequency, maximum voltage, and phase
have already been selected, there is no need to reprogram these.
A flowchart of this sequence is shown in Figure 52.
A flowchart of this sequence is shown in Figure 51.
CHANNEL’S OUTPUT IS ENABLED.
STEP 1: WRITE TO CHANNEL’S DAC DATA
REGISTER. SET THE OUTPUT
TO 0V (ZERO OR MIDSCALE).
STEP 2: WRITE TO DAC CONTROL REGISTER.
DISABLE THE OUTPUT (OUTEN = 0), AND
SET THE NEW OUTPUT RANGE. KEEP THE
DC_DC BIT AND THE INT_ENABLE BIT SET.
STEP 3: WRITE VALUE TO THE DAC DATA REGISTER.
STEP 4: WRITE TO DAC CONTROL REGISTER.
RELOAD SEQUENCE AS IN STEP 2 ABOVE.
THIS TIME SELECT THE OUTEN BIT TO
ENABLE THE OUTPUT.
POWER ON.
Figure 52. Steps for Changing the Output Range
STEP 1: PERFORM A SOFTWARE/HARDWARE RESET.
STEP 2: WRITE TO DC-TO-DC CONTROL REGISTER TO
SET DC-TO-DC CLOCK FREQUENCY, PHASE,
AND MAXIMUM VOLTAGE.
STEP 3: WRITE TO DAC CONTROL REGISTER. SELECT
THE DAC CHANNEL AND OUTPUT RANGE.
SET THE DC_DC BIT AND OTHER CONTROL
BITS AS REQUIRED. SET THE INT_ENABLE BIT
BUT DO NOT SELECT THE OUTEN BIT.
STEP 5: WRITE TO DAC CONTROL REGISTER. RELOAD
SEQUENCE AS IN STEP 3 ABOVE. THIS TIME
SELECT THE OUTEN BIT TO ENABLE
THE OUTPUT.
09225-073
STEP 4: WRITE TO EACH/ALL DAC DATA REGISTERS.
ALLOW AT LEAST 200µs BETWEEN STEP 3
AND STEP 5 FOR REDUCED OUTPUT GLITCH.
Figure 51. Programming Sequence for Enabling the Output Correctly
Rev. A | Page 25 of 44
09225-074
PROGRAMMING SEQUENCE TO WRITE/ENABLE
THE OUTPUT CORRECTLY
AD5757
DATA REGISTERS
The input register is 24 bits wide. When PEC is enabled, the
input register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for
more information on PEC). When writing to a data register, the
format in Table 7 must be used.
DAC Data Register
When writing to the AD5757 DAC data registers, D15 to D0 are
used for the DAC data bits. Table 9 shows the register format
and Table 8 describes the function of Bit D23 to Bit D16.
Table 7. Writing to a Data Register
MSB
D23
R/W
D22
DUT_AD1
D21
DUT_AD0
D20
DREG2
D19
DREG1
D18
DREG0
D17
DAC_AD1
D16
DAC_AD0
LSB
D15 to D0
Data
Table 8. Input Register Decode
Bit
R/W
Description
Indicates a read from or a write to the addressed register.
DUT_AD1, DUT_AD0
Used in association with the external pins, AD1 and AD0, to determine which AD5757 device is being addressed
by the system controller.
DUT_AD1
DUT_AD0
Function
0
0
Addresses part with Pin AD1 = 0, Pin AD0 = 0
0
1
Addresses part with Pin AD1 = 0, Pin AD0 = 1
1
0
Addresses part with Pin AD1 = 1, Pin AD0 = 0
1
1
Addresses part with Pin AD1 = 1, Pin AD0 = 1
Selects whether a data register or a control register is written to. If a control register is selected, a further decode
of CREG bits (see Table 16) is required to select the particular control register, as follows.
DREG2
DREG1
DREG0
Function
DREG2, DREG1, DREG0
0
0
0
1
1
1
1
DAC_AD1, DAC_AD0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
Write to DAC data register (individual channel write)
Write to gain register
Write to gain register (all DACs)
Write to offset register
Write to offset register (all DACs)
Write to clear code register
Write to a control register
These bits are used to decode the DAC channel.
DAC_AD1
DAC_AD0
DAC Channel/Register Address
0
0
DAC A
0
1
DAC B
1
0
DAC C
1
1
DAC D
X
X
These are don’t cares if they are not relevant to the operation being performed.
Table 9. Programming the DAC Data Registers
MSB
D23
R/W
D22
DUT_AD1
D21
DUT_AD0
D20
DREG2
D19
DREG1
D18
DREG0
Rev. A | Page 26 of 44
D17
DAC_AD1
D16
DAC_AD0
LSB
D15 to D0
DAC data
AD5757
Gain Register
Offset Register
The 16-bit gain register, as shown in Table 10, allows the user to
adjust the gain of each channel in steps of 1 LSB. This is done by
setting the DREG[2:0] bits to 010. It is possible to write the
same gain code to all four DAC channels at the same time by
setting the DREG[2:0] bits to 011. The gain register coding is
straight binary as shown in Table 11. The default code in the
gain register is 0xFFFF. In theory, the gain can be tuned across
the full range of the output. In practice, the maximum recommended gain trim is about 50% of programmed range to maintain
accuracy. See the Digital Offset and Gain Control section for
more information.
The 16-bit offset register, as shown in Table 12, allows the user to
adjust the offset of each channel by −32,768 LSBs to +32,767 LSBs
in steps of 1 LSB. This is done by setting the DREG[2:0] bits to
100. It is possible to write the same offset code to all four DAC
channels at the same time by setting the DREG[2:0] bits to 101.
The offset register coding is straight binary as shown in Table 13.
The default code in the offset register is 0x8000, which results in
zero offset programmed to the output. See the Digital Offset
and Gain Control section for more information.
Clear Code Register
The 16-bit clear code register allows the user to set the clear
value of each channel as shown in Table 14. It is possible, via
software, to enable or disable on a per channel basis which
channels are cleared when the CLEAR pin is activated. The
default clear code is 0x0000. See the Asynchronous Clear
section for more information.
Table 10. Programming the Gain Register
R/W
0
DUT_AD1
DUT_AD0
Device address
DREG2
0
DREG1
1
DREG0
0
DAC_AD1
DAC_AD0
DAC channel address
D15 to D0
Gain adjustment
G15
1
1
…
0
0
G14
1
1
…
0
0
G13
1
1
…
0
0
G12 to G4
1
1
…
0
0
G2
1
1
…
0
0
DREG2
1
DREG1
0
DREG0
0
DAC_AD1
DAC_AD0
DAC channel address
D15 to D0
Offset adjustment
OF14
1
1
…
0
…
0
0
OF13
1
1
…
0
…
0
0
OF12 to OF4
1
1
…
0
…
0
0
OF3
1
1
…
0
…
0
0
OF1
1
0
…
0
…
0
0
Table 11. Gain Register
Gain Adjustment
+65,535 LSBs
+65,534 LSBs
…
1 LSB
0 LSBs
G3
1
1
…
0
0
G1
1
0
…
0
0
G0
1
0
…
1
0
Table 12. Programming the Offset Register
R/W
0
DUT_AD1
DUT_AD0
Device address
Table 13. Offset Register Options
Offset Adjustment
+32,767 LSBs
+32,766 LSBs
…
No Adjustment (Default)
…
−32,767 LSBs
−32,768 LSBs
OF15
1
1
…
1
…
0
0
OF2
1
1
…
0
…
0
0
OF0
1
0
…
0
…
0
0
Table 14. Programming the Clear Code Register
R/W
0
DUT_AD1
DUT_AD0
Device address
DREG2
1
DREG1
1
DREG0
0
Rev. A | Page 27 of 44
DAC_AD1
DAC_AD0
DAC channel address
D15 to D0
Clear code
AD5757
CONTROL REGISTERS
Main Control Register
When writing to a control register, the format shown in Table 15
must be used. See Table 8 for information on the configuration
of Bit D23 to Bit D16. The control registers are addressed by setting
the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits
to the appropriate decode address for that register, according to
Table 16. These CREG bits select among the various control
registers.
The main control register options are shown in Table 17 and
Table 18. See the Device Features section for more information
on the features controlled by the main Control Register.
Table 15. Writing to a Control Register
MSB
D23
R/W
D22
DUT_AD1
D21
DUT_AD0
D20
1
D19
1
D18
1
D17
DAC_AD1
D16
DAC_AD0
D15
CREG2
D14
CREG1
D13
CREG0
LSB
D12 to D0
Data
Table 16. Register Access Decode
CREG2 (D15)
0
0
0
0
1
CREG1 (D14)
0
0
1
1
0
CREG0 (D13)
0
1
0
1
0
Function
Slew rate control register (one per channel)
Main control register
DAC control register (one per channel)
DC-to-dc control register
Software register (one per channel)
Table 17. Programming the Main Control Register
MSB
D15
0
1
D14
0
D13
1
D12
0
D11
STATREAD
D10
EWD
D9
WD1
D8
WD0
D7
X1
D6
X1
D5
OUTEN_ALL
X = don’t care.
Table 18. Main Control Register Functions
Bit
STATREAD
EWD
WD1, WD0
OUTEN_ALL
DCDC_ALL
Description
Enable status readback during a write. See the Device Features section.
STATREAD = 1, enable.
STATREAD = 0, disable (default).
Enable watchdog timer. See the Device Features section for more information.
EWD = 1, enable watchdog.
EWD = 0, disable watchdog (default).
Timeout select bits. Used to select the timeout period for the watchdog timer.
WD1
WD0
Timeout Period (ms)
0
0
5
0
1
10
1
0
100
1
1
200
Enables the output on all four DACs simultaneously.
Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register.
When set, powers up the dc-to-dc converter on all four channels simultaneously.
To power down the dc-to-dc converters, all channel outputs must first be disabled.
Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register.
Rev. A | Page 28 of 44
D4
DCDC_ALL
LSB
D3 to D0
X1
AD5757
DAC Control Register
The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 19 and Table 20.
Table 19. Programming DAC Control Register
D15
0
1
D14
1
D13
0
D12
X1
D11
X1
D10
X1
D9
X1
D8
INT_ENABLE
D7
CLR_EN
D6
OUTEN
D5
RSET
D4
DC_DC
D3
X1
D2
R2
D1
R1
D0
R0
X = don’t care.
Table 20. DAC Control Register Functions
Bit
INT_ENABLE
CLR_EN
OUTEN
RSET
DC_DC
R2, R1, R0
Description
Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. Does not enable the output. Can
only be done on a per channel basis. It is recommended to set this bit and allow a >200 μs delay before enabling the
output because this results in a reduced output enable glitch. Plots of this glitch can be found in Figure 25.
Per channel clear enable bit. Selects if this channel clears when the CLEAR pin is activated.
CLR_EN = 1, channel clears when the part is cleared.
CLR_EN = 0, channel does not clear when the part is cleared (default).
Enables/disables the selected output channel.
OUTEN = 1, enables the channel.
OUTEN = 0, disables the channel (default).
Selects an internal or external current sense resistor for the selected DAC channel.
RSET = 0, selects the external resistor (default).
RSET = 1, selects the internal resistor.
Powers the dc-to-dc converter on the selected channel.
DC_DC = 1, power up the dc-to-dc converter.
DC_DC = 0, power down the dc-to-dc converter (default).
This allows per channel dc-to-dc converter power-up/power-down. To power down the dc-to-dc converter, the OUTEN and
INT_ENABLE bits must also be set to 0.
All dc-to-dc converters can also be powered up simultaneously using the DCDC_ALL bit in the main control register.
Selects the output range to be enabled.
R2
R1
R0
Output Range Selected
1
0
0
4 mA to 20 mA current range
1
0
1
0 mA to 20 mA current range
1
1
0
0 mA to 24 mA current range
Rev. A | Page 29 of 44
AD5757
Software Register
The software register has three functions. It allows the user to
perform a software reset to the part. It can be used to set the
user toggle bit, D11, in the status register. It is also used as part
of the watchdog feature when it is enabled. This feature is useful
to ensure that communication has not been lost between the
MCU and the AD5757 and that the datapath lines are working
properly (that is, SDIN, SCLK, and SYNC).
When the watchdog feature is enabled, the user must write
0x195 to the software register within the timeout period. If this
command is not received within the timeout period, the ALERT
pin signals a fault condition. This is only required when the
watchdog timer function is enabled.
DC-to-DC Control Register
The dc-to-dc control register allows the user control over
the dc-to-dc switching frequency and phase, as well as the
maximum allowable dc-to-dc output voltage. The dc-to-dc
control register options are shown in Table 23 and Table 24.
Table 21. Programming the Software Register
MSB
D15
1
D14
0
D13
0
LSB
D11 to D0
Reset code/SPI code
D12
User program
Table 22. Software Register Functions
Bit
User Program
Reset Code/SPI Code
Description
This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is set
to 1. Likewise, when D12 is set to 0, Bit D11 of the status register is also set to zero. This feature can be used to
ensure that the SPI pins are working correctly by writing a known bit value to this register and reading back
the corresponding bit from the status register.
Option
Description
Reset code
Writing 0x555 to D[11:0] performs a reset of the AD5757.
SPI code
If the watchdog timer feature is enabled, 0x195 must be written to the software
register (D11 to D0) within the programmed timeout period.
Table 23. Programming the DC-to-DC Control Register
MSB
D15
0
1
D14
1
D13
1
D12 to D7
X1
D6
DC-DC Comp
D5 to D4
DC-DC phase
D3 to D2
DC-DC Freq
LSB
D1 to D0
DC-DC MaxV
X = don’t care.
Table 24. DC-to-DC Control Register Options
Bit
DC-DC Comp
DC-DC Phase
DC-DC Freq
DC-DC MaxV
Description
Selects between an internal and external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter
Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more
information.
0 = selects the internal 150 kΩ compensation resistor (default).
1 = bypasses the internal compensation resistor for the dc-to-dc converter. In this mode, an external dc-to-dc
compensation resistor must be used; this is placed at the COMPDCDC_x pin in series with the 10 nF dc-to-dc compensation
capacitor to ground. Typically, a ~50 kΩ resistor is recommended.
User programmable dc-to-dc converter phase (between channels).
00 = all dc-to-dc converters clock on the same edge (default).
01 = Channel A and Channel B clock on the same edge, Channel C and Channel D clock on opposite edges.
10 = Channel A and Channel C clock on the same edge, Channel B and Channel D clock on opposite edges.
11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other.
DC-to-dc switching frequency; these are divided down from the internal 13 MHz oscillator (see Figure 46 and Figure 47).
00 = 250 ± 10% kHz.
01 = 410 ± 10% kHz (default).
10 = 650 ± 10% kHz.
Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter.
00 = 23 V + 1 V/−1.5 V (default).
01 = 24.5 V ± 1 V.
10 = 27 V ± 1 V.
11 = 29.5 V ± 1V.
Rev. A | Page 30 of 44
AD5757
Slew Rate Control Register
request to read yet another register on a third data transfer or
0x1CE000, which is the no operation command.
This register is used to program the slew rate control for the
selected DAC channel. The slew rate control is enabled/
disabled and programmed on a per channel basis. See Table 25
and the Digital Slew Rate Control section for more information.
Readback Example
To read back the gain register of Device 1, Channel A on the
AD5757, implement the following sequence:
READBACK OPERATION
Write 0xA80000 to the AD5757 input register. This
configures the AD5757 Device Address 1 for read mode
with the gain register of Channel A selected. All the data
bits, D15 to D0, are don’t cares.
Follow with another read command or a no operation
command (0x1CE000). During this command, the data
from the Channel A gain register is clocked out on the
SDO line.
1.
Readback mode is invoked by setting the R/W bit = 1 in the
serial input register write. See Table 26 for the bits associated
with a readback operation. The DUT_AD1 and DUT_AD0 bits,
in association with Bits RD[4:0], select the register to be read.
The remaining data bits in the write sequence are don’t cares.
During the next SPI transfer (see Figure 4), the data appearing
on the SDO output contains the data from the previously
addressed register. This second SPI transfer should either be a
2.
Table 25. Programming the Slew Rate Control Register
D15
0
1
D14
0
D13
0
D12
SE
D11 to D7
X1
D6 to D3
SR_CLOCK
D2 to D0
SR_STEP
X = don’t care.
Table 26. Input Shift Register Contents for a Read Operation
D23
R/W
1
D22
DUT_AD1
D21
DUT_AD0
D20
RD4
D19
RD3
D18
RD2
D17
RD1
X = don’t care.
Table 27. Read Address Decoding
RD4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
RD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
RD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
RD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
RD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Function
Read DAC A data register
Read DAC B data register
Read DAC C data register
Read DAC D data register
Read DAC A control register
Read DAC B control register
Read DAC C control register
Read DAC D control register
Read DAC A gain register
Read DAC B gain register
Read DAC C gain register
Read DAC D gain register
Read DACA offset register
Read DAC B offset register
Read DAC C offset register
Read DAC D offset register
Clear DAC A code register
Clear DAC B code register
Clear DAC C code register
Clear DAC D code register
DAC A slew rate control register
DAC B slew rate control register
DAC C slew rate control register
DAC D slew rate control register
Read status register
Read main control register
Read dc-to-dc control register
Rev. A | Page 31 of 44
D16
RD0
D15 to D0
X1
AD5757
register is set, the status register contents can be read back on
the SDO pin during every write sequence. Alternatively, if the
STATREAD bit is not set, the status register can be read using
the normal readback operation.
Status Register
The status register is a read only register. This register contains
any fault information as a well as a ramp active bit and a user
toggle bit. When the STATREAD bit in the main control
Table 28. Decoding the Status Register
MSB
D15
DCDCD
1
D14
DCDCC
D13
DCDCB
D12
DCDCA
D11
User
toggle
D10
PEC
error
D9
Ramp
active
D8
Over
TEMP
D7
X1
D6
X1
D5
X1
D4
X1
D3
IOUT_D
fault
D2
IOUT_C
fault
D1
IOUT_B
fault
LSB
D0
IOUT_A
fault
X = don’t care.
Table 29. Status Register Options
Bit
DC-DCD
DC-DCC
DC-DCB
DC-DCA
User toggle
PEC Error
Ramp Active
Over TEMP
IOUT_D Fault
IOUT_C Fault
IOUT_B Fault
IOUT_A Fault
Description
This bit is set on Channel D if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX
voltage). In this case, the IOUT_D fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more
information on this bit’s operation under this condition.
This bit is set on Channel C if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX
voltage). In this case, the IOUT_C fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more
information on this bit’s operation under this condition.
This bit is set on Channel B if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX
voltage). In this case, the IOUT_B fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more
information on this bit’s operation under this condition.
This bit is set on Channel A if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX
voltage). In this case, the IOUT_A fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more
information on this bit’s operation under this condition.
User toggle bit. This bit is set or cleared via the software register. This can be used to verify data communications if
needed.
Denotes a PEC error on the last data-word received over the SPI interface.
This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel).
This bit is set if the AD5757 core temperature exceeds approximately 150°C.
This bit is set if a fault is detected on the IOUT_D pin.
This bit is set if a fault is detected on the IOUT_C pin.
This bit is set if a fault is detected on the IOUT_B pin.
This bit is set if a fault is detected on the IOUT_A pin.
Rev. A | Page 32 of 44
AD5757
DEVICE FEATURES
OUTPUT FAULT
The AD5757 is equipped with a FAULT pin, an active low opendrain output allowing several AD5757 devices to be connected
together to one pull-up resistor for global fault detection. The
FAULT pin is forced active by any one of the following fault
scenarios:
•
•
•
The voltage at IOUT_x attempts to rise above the compliance
range, due to an open-loop circuit or insufficient power
supply voltage. The internal circuitry that develops the
fault output avoids using a comparator with windowed
limits because this requires an actual output error before
the FAULT output becomes active. Instead, the signal is
generated when the internal amplifier in the output stage
has less than approximately 1 V of remaining drive
capability. Thus, the FAULT output activates slightly before
the compliance limit is reached.
An interface error is detected due to a PEC failure. See the
Packet Error Checking section.
If the core temperature of the AD5757 exceeds
approximately 150°C.
The IOUT_x fault, PEC error, and over TEMP bits of the status
register are used in conjunction with the FAULT output to
inform the user which one of the fault conditions caused the
FAULT output to be activated.
DIGITAL OFFSET AND GAIN CONTROL
Each DAC channel has a gain (M) and offset (C) register, which
allow trimming out of the gain and offset errors of the entire
signal chain. Data from the DAC data register is operated on by
a digital multiplier and adder controlled by the contents of the
M and C registers. The calibrated DAC data is then stored in the
DAC input register.
Theory of Operation section. Both the gain register and the
offset register have 16 bits of resolution. The correct method to
calibrate the gain/offset is to first calibrate out the gain and then
calibrate the offset.
The value (in decimal) that is written to the DAC input register
can be calculated by
Code DACRegister = D ×
( M + 1)
216
+ C − 215
(1)
where:
D is the code loaded to the DAC channel’s input register.
M is the code in the gain register (default code = 216 – 1).
C is the code in the offset register (default code = 215).
STATUS READBACK DURING A WRITE
The AD5757 has the ability to read back the status register
contents during every write sequence. This feature is enabled
via the STATREAD bit in the main control register. This allows
the user to continuously monitor the status register and act
quickly in the case of a fault.
When status readback during a write is enabled, the contents of
the 16-bit status register (see Table 29) are output on the SDO
pin, as shown in Figure 5.
The AD5757 powers up with this feature disabled. When this is
enabled, the normal readback feature is not available, except for
the status register. To read back any other register, clear the
STATREAD bit first before following the readback sequence.
STATREAD can be set high again after the register read.
ASYNCHRONOUS CLEAR
CLEAR is an active high, edge-sensitive input that allows the
output to be cleared to a preprogrammed 16-bit code. This code
is user programmable via a per channel 16-bit clear code register.
M
REGISTER
For a channel to clear, that channel must be enabled to be
cleared via the CLR_EN bit in the channel’s DAC control
register. If the channel is not enabled to be cleared, the output
remains in its current state independent of the CLEAR pin level.
C
REGISTER
When the CLEAR signal is returned low, the relevant outputs
remain cleared until a new value is programmed.
DAC
REGISTER
DAC
09225-075
INPUT
REGISTER
Figure 53. Digital Offset and Gain control
PACKET ERROR CHECKING
Although Figure 53 indicates a multiplier and adder for each
channel, there is only one multiplier and one adder in the device,
and they are shared among all four channels. This has
implications for the update speed when several channels are
updated at once (see Table 3).
Each time data is written to the M or C register, the output is
not automatically updated. Instead, the next write to the DAC
channel uses these M and C values to perform a new calibration
and automatically updates the channel.
The output data from the calibration is routed to the DAC input
register. This is then loaded to the DAC as described in the
To verify that data has been received correctly in noisy environments, the AD5757 offers the option of packet error checking
based on an 8-bit cyclic redundancy check (CRC-8). The device
controlling the AD5757 should generate an 8-bit frame check
sequence using the polynomial
C(x) = x8 + x2 + x1 + 1
This is added to the end of the data-word, and 32 bits are sent
to the AD5757 before taking SYNC high. If the AD5757 sees a
32-bit frame, it performs the error check when SYNC goes high.
If the check is valid, the data is written to the selected register.
Rev. A | Page 33 of 44
AD5757
If the error check fails, the FAULT pin goes low and the PEC
error bit in the status register is set. After reading the status
register, FAULT returns high (assuming there are no other
faults), and the PEC error bit is cleared automatically.
INTERNAL REFERENCE
The AD5757 contains an integrated 5 V voltage reference with
initial accuracy of ±5 mV maximum and a temperature drift
coefficient of ±10 ppm maximum. The reference voltage
is buffered and externally available for use elsewhere within
the system.
UPDATE ON SYNC HIGH
SYNC
EXTERNAL CURRENT SETTING RESISTOR
SCLK
SDIN
Referring to Figure 49, RSET is an internal sense resistor as part
of the voltage to current conversion circuitry. The stability of
the output current value over temperature is dependent on the
stability of the value of RSET. As a method of improving the
stability of the output current over temperature, an external
15 kΩ low drift resistor can be connected to the RSET_x pin of
the AD5757 to be used instead of the internal resistor, R1.
The external resistor is selected via the DAC control register
(see Table 19).
LSB
D0
24-BIT DATA
24-BIT DATA TRANSFER—NO ERROR CHECKING
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
SYNC
SCLK
MSB
D31
SDIN
LSB
D8
24-BIT DATA
D7
D0
8-BIT CRC
09225-180
FAULT PIN GOES HIGH
IF ERROR CHECK FAILS
FAULT
32-BIT DATA TRANSFER WITH ERROR CHECKING
Figure 54. PEC Timing
The PEC can be used for both transmit and receive of data
packets. If status readback during a write is enabled, the PEC
values returned during the status readback during a write
operation should be ignored. If status readback during a write is
disabled, the user can still use the normal readback operation to
monitor status register activity with PEC.
WATCHDOG TIMER
When enabled, an on-chip watchdog timer generates an alert
signal if 0x195 has not been written to the software register
within the programmed timeout period. This feature is useful
to ensure that communication has not been lost between the
MCU and the AD5757 and that these datapath lines are working
properly (that is, SDIN, SCLK, and SYNC). If 0x195 is not
received by the software register within the timeout period,
the ALERT pin signals a fault condition. The ALERT signal is
active high and can be connected directly to the CLEAR pin to
enable a CLEAR in the event that communication from the
MCU is lost.
The watchdog timer is enabled, and the timeout period (5 ms,
10 ms, 100 ms, or 200 ms) is set in the main control register (see
Table 17 and Table 18).
Table 1 outlines the performance specifications of the AD5757
with both the internal RSET resistor and an external, 15 kΩ RSET
resistor. Using an external RSET resistor allows for improved
performance over the internal RSET resistor option. The external
RSET resistor specification assumes an ideal resistor; the actual
performance depends on the absolute value and temperature
coefficient of the resistor used. This directly affects the gain error
of the output, and thus the total unadjusted error. To arrive at
the gain/TUE error of the output with a particular external RSET
resistor, add the percentage absolute error of the RSET resistor
directly to the gain/TUE error of the AD5757 with the external
RSET resistor, shown in Table 1 (expressed in % FSR).
HART
The AD5757 has four CHART pins, one corresponding to each
output channels. A HART signal can be coupled into these pins.
The HART signal appears on the corresponding current output,
if the output is enabled. Table 30 shows the recommended input
voltages for the HART signal at the CHART pin. If these
voltages are used, the current output should meet the HART
amplitude specifications. Figure 55 shows the recommended
circuit for attenuating and coupling in the HART signal.
Table 30. CHART Input Voltage to HART Output Current
RSET
Internal RSET
External RSET
Current Output
(HART)
1 mA p-p
1 mA p-p
C1
CHARTx
HART MODEM
OUTPUT
OUTPUT ALERT
The AD5757 is equipped with an ALERT pin. This is an active
high CMOS output. The AD5757 also has an internal watchdog
timer. When enabled, it monitors SPI communications. If 0x195
is not received by the software register within the timeout period,
the ALERT pin goes active.
CHART Input
Voltage
150 mV p-p
170 mV p-p
C2
09225-076
MSB
D23
Figure 55. Coupling HART Signal
A minimum capacitance of C1 + C2 is required to ensure that
the 1.2 kHz and 2.2 kHz HART frequencies are not significantly
attenuated at the output. The recommended values are C1 =
22 nF, C2 = 47 nF.
Rev. A | Page 34 of 44
AD5757
Digitally controlling the slew rate of the output is necessary to
meet the analog rate of change requirements for HART.
The following equation describes the slew rate as a function of
the step size, the update clock frequency, and the LSB size:
DIGITAL SLEW RATE CONTROL
Slew Time =
The slew rate control feature of the AD5757 allows the user to
control the rate at which the output value changes. With the
slew rate control feature disabled, the output value changes at a
rate limited by the output drive circuitry and the attached load.
To reduce the slew rate, this can be achieved by enabling the
slew rate control feature. With the feature enabled via the SREN
bit of the slew rate control register (see Table 25), the output,
instead of slewing directly between two values, steps digitally at
a rate defined by two parameters accessible via the slew rate
control register, as shown in Table 25. The parameters are
SR_CLOCK and SR_STEP. SR_CLOCK defines the rate at
which the digital slew is updated, for example, if the selected
update rate is 8 kHz, the output updates every 125 μs. In conjunction with this, SR_STEP defines by how much the output value
changes at each update. Together, both parameters define the
rate of change of the output value. Table 31 and Table 32 outline
the range of values for both the SR_CLOCK and SR_STEP
parameters.
SR_CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
Update Clock Frequency (Hz)1
64 k
32 k
16 k
8k
4k
2k
1k
500
250
125
64
32
16
8
4
0.5
These clock frequencies are divided down from the 13 MHz internal
oscillator. See Table 1, Figure 46, and Figure 47.
Table 32. Slew Rate Step Size Options
SR_STEP
000
001
010
011
100
101
110
111
Step Size (LSBs)
1
2
4
16
32
64
128
256
Step Size × Update Clock Frequency × LSB Size
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps for IOUT_x.
When the slew rate control feature is enabled, all output
changes occur at the programmed slew rate (see the DC-to-DC
Converter Settling Time section for additional information).
For example, if the CLEAR pin is asserted, the output slews to
the clear value at the programmed slew rate (assuming that the
clear channel is enabled to be cleared). If a number of channels
are enabled for slew, care must be taken when asserting the
CLEAR pin. If one of the channels is slewing when CLEAR is
asserted, other channels may change directly to their clear
values not under slew rate control. The update clock frequency
for any given value is the same for all output ranges. The step
size, however, varies across output ranges for a given value of
step size because the LSB size is different for each output range.
POWER DISSIPATION CONTROL
The AD5757 contains integrated dynamic power control using
a dc-to-dc boost converter circuit, allowing reductions in power
consumption from standard designs.
In standard current input module designs, the load resistor
values can range from typically 50 Ω to 750 Ω. Output module
systems must source enough voltage to meet the compliance
voltage requirement across the full range of load resistor values.
For example, in a 4 mA to 20 mA loop when driving 20 mA, a
compliance voltage of >15 V is required. When driving 20 mA
into a 50 Ω load, only 1 V compliance is required.
The AD5757 circuitry senses the output voltage and regulates
this voltage to meet compliance requirements plus a small
headroom voltage. The AD5757 is capable of driving up to
24 mA through a 1 kΩ load.
DC-TO-DC CONVERTERS
The AD5757 contains four independent dc-to-dc converters.
These are used to provide dynamic control of the VBOOST supply
voltage for each channel (see Figure 49). Figure 56 shows the
discreet components needed for the dc-to-dc circuitry, and the
following sections describe component selection and operation
of this circuitry.
AVCC
CIN
≥10µF
LDCDC
DDCDC
10µH
CDCDC
4.7µF
RFILTER
10Ω
SWx
Figure 56. DC-to-DC Circuit
Rev. A | Page 35 of 44
VBOOST_X
CFILTER
0.1µF
09225-077
Table 31. Slew Rate Update Clock Options
Output Change
AD5757
Table 33. Recommended DC-to-DC Components
29.6
Symbol
LDCDC
CDCDC
DDCDC
29.5
Manufacturer
Coilcraft®
Murata
NXP
It is recommended to place a 10 Ω, 100 nF low-pass RC filter
after CDCDC. This consumes a small amount of power but
reduces the amount of ripple on the VBOOST_x supply.
DC-to-DC Converter Operation
VMAX
DC_DC BIT
0mA TO 24mA RANGE, 24mA OUTPUT
OUTPUT UNLOADED
DC-DCx BIT = 1
DC-DCMaxV = 29.5V
29.4
29.3
29.2
29.1
29.0
fSW = 410kHz
TA = 25°C
28.9
28.8
The on-board dc-to-dc converters use a constant frequency,
peak current mode control scheme to step up an AVCC input of
4.5 V to 5.5 V to drive the AD5757 output channel. These are
designed to operate in discontinuous conduction mode (DCM)
with a duty cycle of <90% typical. Discontinuous conduction
mode refers to a mode of operation where the inductor current
goes to zero for an appreciable percentage of the switching
cycle. The dc-to-dc converters are nonsynchronous; that is,
they require an external Schottky diode.
As shown in Figure 57, the DC-DCx bit in the status register
asserts when the AD5757 is ramping to the VMAX value but
deasserts when the voltage is decaying to VMAX − ~0.4 V.
DC-to-DC Converter Output Voltage
DC-to-DC Converter On-Board Switch
When a channel current output is enabled, the converter regulates
the VBOOST_x supply to 7.4 V (±5%) or (IOUT × RLOAD + Headroom),
whichever is greater (see Figure 31 for a plot of headroom
supplied vs. output current). When the output is disabled, the
converter regulates the VBOOST_x supply to 7.4 V (±5%).
The AD5757 contains a 0.425 Ω internal switch. The switch
current is monitored on a pulse by pulse basis and is limited to
0.8 A peak current.
DC-to-DC Converter Settling Time
The settling time for a step greater than ~1 V (IOUT × RLOAD ) is
dominated by the settling time of the dc-to-dc converter. The
exception to this is when the required voltage at the IOUT_x pin plus
the compliance voltage is below 7.4 V (±5%). A typical plot of the
output settling time can be found in Figure 26. This plot is for a
1 kΩ load. The settling time for smaller loads is faster. The
settling time for current steps less than 24 mA is also faster.
DC-to-DC Converter VMAX Functionality
The maximum VBOOST_x voltage is set in the dc-to-dc control
register (23 V, 24.5 V, 27 V, or 29.5 V; see Table 24). On reaching
this maximum voltage, the dc-to-dc converter is disabled, and
the VBOOST_x voltage is allowed to decay by ~0.4 V. After the
VBOOST_x voltage has decayed by ~0.4 V, the dc-to-dc converter
is reenabled, and the voltage ramps up again to VMAX, if still
required. This operation is shown in Figure 57.
28.7
DC-DCx BIT = 0
28.6
0
0.5
1.0
1.5
2.0
2.5
TIME (ms)
3.0
3.5
4.0
09225-183
Value
10 μH
4.7 μF
0.38 VF
VBOOST VOLTAGE (mV)
Component
XAL4040-103
GRM32ER71H475KA88L
PMEG3010BEA
Figure 57. Operation on Reaching VMAX
DC-to-DC Converter Switching Frequency and Phase
The AD5757 dc-to-dc converter switching frequency can be
selected from the dc-to-dc control register. The phasing of the
channels can also be adjusted so that the dc-to-dc converter can
clock on different edges (see Table 24). For typical applications,
a 410 kHz frequency is recommended. At light loads (low output
current and small load resistor), the dc-to-dc converter enters a
pulse-skipping mode to minimize switching power dissipation.
DC-to-DC Converter Inductor Selection
For typical 4 mA to 20 mA applications, a 10 μH inductor (such
as the XAL4040-103 from Coilcraft), combined with a switching frequency of 410 kHz, allows up to 24 mA to be driven into a
load resistance of up to 1 kΩ with an AVCC supply of 4.5 V to
5.5 V. It is important to ensure that the inductor is able to handle
the peak current without saturating, especially at the maximum
ambient temperature. If the inductor enters into saturation mode,
it results in a decrease in efficiency. The inductance value also
drops during saturation and may result in the dc-to-dc converter
circuit not being able to supply the required output power.
DC-to-DC Converter External Schottky Selection
The AD5757 requires an external Schottky for correct
operation. Ensure that the Schottky is rated to handle the
maximum reverse breakdown expected in operation and that
the rectifier maximum junction temperature is not exceeded.
The diode average current is approximately equal to the ILOAD
current. Diodes with larger forward voltage drops result in a
decrease in efficiency.
Rev. A | Page 36 of 44
AD5757
DC-to-DC Converter Compensation Capacitors
AICC SUPPLY REQUIREMENTS—SLEWING
As the dc-to-dc converter operates in DCM, the uncompensated
transfer function is essentially a single-pole transfer function.
The pole frequency of the transfer function is determined by
the dc-to-dc converter’s output capacitance, input and output
voltage, and output load. The AD5757 uses an external capacitor in conjunction with an internal 150 kΩ resistor to compensate
the regulator loop. Alternatively, an external compensation
resistor can be used in series with the compensation capacitor
by setting the DC-DC Comp bit in the dc-to-dc control register.
In this case, a ~50 kΩ resistor is recommended. A description
of the advantages of this can be found in the AICC Supply
Requirements—Slewing section. For typical applications, a
10 nF dc-to-dc compensation capacitor is recommended.
The AICC current requirement while slewing is greater than in
static operation because the output power increases to charge
the output capacitance of the dc-to-dc converter. This transient
current can be quite large (see Figure 58), although the methods
described in the Reducing AICC Current Requirements section
can reduce the requirements on the AVCC supply. If not enough
AICC current can be provided, the AVCC voltage drops. Due to
this AVCC drop, the AICC current required to slew increases
further. This means that the voltage at AVCC drops further (see
Equation 3) and the VBOOST_x voltage, and thus the output voltage, may never reach its intended value. Because this AVCC
voltage is common to all channels, this may also affect other
channels.
The input capacitor provides much of the dynamic current
required for the dc-to-dc converter and should be a low ESR
component. For the AD5757, a low ESR tantalum or ceramic
capacitor of 10 μF is recommended for typical applications.
Ceramic capacitors must be chosen carefully because they can
exhibit a large sensitivity to dc bias voltages and temperature.
X5R or X7R dielectrics are preferred because these capacitors
remain stable over wider operating voltage and temperature
ranges. Care must be taken if selecting a tantalum capacitor to
ensure a low ESR value.
AICC SUPPLY REQUIREMENTS—STATIC
The dc-to-dc converter is designed to supply a VBOOST_x voltage of
VBOOST = IOUT × RLOAD + Headroom
(2)
See Figure 31 for a plot of headroom supplied vs. output
voltage. This means that, for a fixed load and output voltage,
the dc-to-dc converter output current can be calculated by
the following formula:
AI CC =
Power Out
Efficiency × AVCC
=
I OUT × VBOOST
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
0.5
0.4
20
15
0.3
10
0.2
AICC
IOUT
VBOOST
0.1
0
0
0.5
5
1.0
1.5
TIME (ms)
2.0
2.5
0
Figure 58. AICC Current vs. Time for 24 mA Slew with Internal Compensation
Resistor
Reducing AICC Current Requirements
There are two main methods that can be used to reduce the
AICC current requirements. One method is to add an external
compensation resistor, and the other is to use slew rate control.
Both of these methods can be used in conjunction.
A compensation resistor can be placed at the COMPDCDC_x pin
in series with the 10 nF compensation capacitor. A 51 kΩ external
compensation resistor is recommended. This compensation
increases the slew time of the current output but eases the AICC
transient current requirements. Figure 59 shows a plot of AICC
current for a 24 mA step through a 1 kΩ load when using a
51 kΩ compensation resistor. This method eases the current
requirements through smaller loads even further, as shown in
Figure 60.
(3)
ηVBOOST × AVCC
25
0.6
AICC CURRENT (A)
The output capacitor affects ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which the
channel output current can rise. The ripple voltage is caused by
a combination of the capacitance and equivalent series resistance
(ESR) of the capacitor. For the AD5757, a ceramic capacitor
of 4.7 μF is recommended for typical applications. Larger
capacitors or paralleled capacitors improve the ripple at the
expense of reduced slew rate. Larger capacitors also impact
the AVCC supplies current requirements while slewing (see the
AICC Supply Requirements—Slewing section). This capacitance
at the output of the dc-to-dc converter should be >3 μF under
all operating conditions.
09225-184
30
0.7
IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V)
0.8
DC-to-DC Converter Input and Output Capacitor
Selection
where:
IOUT is the output current from IOUT_x in amps.
ηVBOOST is the efficiency at VBOOST_x as a fraction (see Figure 33
and Figure 34).
Rev. A | Page 37 of 44
AD5757
0.5
20
0.4
16
0.3
12
0.2
8
AICC
IOUT
VBOOST
0
0
0.5
1.0
4
1.5
TIME (ms)
2.0
2.5
0
0.6
0mA TO 24mA RANGE
500Ω LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
24
0.5
20
0.4
16
0.3
12
0.2
8
0.1
4
0
0
0.5
1.0
1.5
TIME (ms)
2.0
2.5
0
16
0.3
12
0.2
8
0.1
4
1
2
3
TIME (ms)
R2
5
6
0
In this configuration the SWx pin are left floating and the
GNDSWx pin is grounded. The VBOOST_x pin is connected to a
minimum supply of 7.5 V and a maximum supply of 33 V. This
supply can be sized according to the maximum load required to
be driven.
The IGATE functionality works by holding the gate of the
external PMOS transistor at (VBOOST_x − 5 V). This means that
the majority of the channels power dissipation will take place in
this external PMOS transistor.
The external PMOS transistor should be chosen tolerate a VDS
voltage of at least −VBOOST_x, as well as to handle the power
dissipation required. This external PMOS transistor typically
has minimal effect on the current output performance.
VBOOST_A
(LEFT FLOATING)
4
The AD5757 can also be used with an external PMOS transistor
per channel, as shown in Figure 62. This mode can be used to
limit the on-chip power dissipation of the AD5757, though this
will not reduce the power dissipation of the total system. The
IGATE functionality is not typically required when using the
dynamic power control feature so Figure 62 shows the
configuration of the device for a fixed VBOOST_x supply.
Using slew rate control can greatly reduce the AVCC supplies
current requirements, as shown in Figure 61. When using slew
rate control, attention should be paid to the fact that the output
cannot slew faster than the dc-to-dc converter. The dc-to-dc
converter slews slowest at higher currents through large (for
example, 1 kΩ) loads. This slew rate is also dependent on the
configuration of the dc-to-dc converter. Two examples of the
dc-to-dc converter’s output slew are shown in Figure 59 and
SWA
0
EXTERNAL PMOS MODE
Figure 60. AICC Current vs. Time for 24 mA Through 500 Ω Slew with External
51 kΩ Compensation Resistor
R3
DAC A
IOUT_A
(VBOOST_A –5V)
IGATEA
CURRENT OUTPUT
R1
RLOAD
RSET_A
CHARTA
DAC CHANNEL A
09225-190
AVCC
5.0V
20
Figure 61. AICC Current vs. Time for 24 mA Slew with Slew Rate Control
09225-186
AICC CURRENT (A)
0.6
28
IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V)
0.7
24
0.4
0
32
AICC
IOUT
VBOOST
28
AICC
IOUT
VBOOST
0.5
Figure 59. AICC Current vs. Time for 24 mA Through 1 kΩ Slew with External
51 kΩ Compensation Resistor
0.8
32
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
0.7
09225-185
0.1
0.8
IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V)
24
09225-187
0.6
28
Figure 60 (VBOOST corresponds to the dc-to-dc converter’s output
voltage).
AICC CURRENT (A)
0.7
AICC CURRENT (A)
32
0mA TO 24mA RANGE
1kΩ LOAD
fSW = 410kHz
INDUCTOR = 10µH (XAL4040-103)
TA = 25°C
IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V)
0.8
SWGNDA
Figure 62. Configuration off a Particular Channel Using IGATE
Rev. A | Page 38 of 44
AD5757
APPLICATIONS INFORMATION
CURRENT OUTPUT MODE WITH INTERNAL RSET
When using the internal RSET resistor in current output mode,
the output is significantly affected by how many other channels
using the internal RSET are enabled and by the dc crosstalk from
these channels. The internal RSET specifications in Table 1 are
for all channels enabled with the internal RSET selected and
outputting the same code.
For every channel enabled with the internal RSET, the offset error
decreases. For example, with one current output enabled using
the internal RSET, the offset error is 0.075% FSR. This value
decreases proportionally as more current channels are enabled;
the offset error is 0.056% FSR on each of two channels, 0.029%
on each of three channels, and 0.01% on each of four channels.
Similarly, the dc crosstalk when using the internal RSET is proportional to the number of current output channels enabled with
the internal RSET. For example, with the measured channel at
0x8000 and one channel going from zero to full scale, the dc
crosstalk is −0.011% FSR. With two channels going from zero to
full scale, it is −0.019% FSR, and with all three other channels
going from zero to full scale, it is −0.025% FSR.
For the full-scale error measurement in Table 1, all channels are
at 0xFFFF. This means that, as any channel goes to zero scale,
the full-scale error increases due to the dc crosstalk. For example,
with the measured channel at 0xFFFF and three channels at
zero scale, the full-scale error is 0.025%. Similarly, if only one
channel is enabled in current output mode with the internal
RSET, the full-scale error is 0.025% FSR + 0.075% FSR = 0.1% FSR.
PRECISION VOLTAGE REFERENCE SELECTION
To achieve the optimum performance from the AD5757 over its
full operating temperature range, a precision voltage reference
must be used. Thought should be given to the selection of a
precision voltage reference. The voltage applied to the reference
inputs is used to provide a buffered reference for the DAC cores.
Therefore, any error in the voltage reference is reflected in the
outputs of the device.
There are four possible sources of error to consider when choosing
a voltage reference for high accuracy applications: initial
accuracy, temperature coefficient of the output voltage, longterm drift, and output voltage noise.
Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR425, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjustment can be used at any temperature to trim out any error.
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
The temperature coefficient of a reference’s output voltage affects
INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce the dependence of the DAC output voltage to ambient temperature.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise must be considered.
Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision
voltage references such as the ADR435 (XFET design) produce
low output noise in the 0.1 Hz to 10 Hz region. However, as the
circuit bandwidth increases, filtering the output of the reference
may be required to minimize the output noise.
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, a capacitor
may be required between IOUT_x and AGND to ensure stability. A
0.01 μF capacitor between IOUT_x and AGND ensures stability of
a load of 50 mH. The capacitive component of the load may
cause slower settling, although this may be masked by the settling time of the AD5757. There is no maximum capacitance
limit for the current output of the AD5757.
Table 34. Recommended Precision References
Part No.
ADR445
ADR02
ADR435
ADR395
AD586
Initial Accuracy
(mV Maximum)
±2
±3
±2
±5
±2.5
Long-Term Drift
(ppm Typical)
50
50
40
50
15
Temperature Drift (ppm/°C Maximum)
3
3
3
9
10
Rev. A | Page 39 of 44
0.1 Hz to 10 Hz Noise
(μV p-p Typical)
2.25
10
8
8
4
AD5757
TRANSIENT VOLTAGE PROTECTION
LAYOUT GUIDELINES
The AD5757 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment
can, however, subject I/O circuits to much higher transients. To
protect the AD5757 from excessively high voltage transients,
external power diodes and a surge current limiting resistor are
required, as shown in Figure 63. The two protection diodes and
resistor must have appropriate power ratings. Further protection
can be provided with transient voltage suppressors or transorbs;
these are available as both unidirectional suppressors (protect
against positive high voltage transients) and bidirectional suppressors (protect against both positive and negative high voltage
transients) and are available in a wide range of standoff and
breakdown voltage ratings. It is recommended that all field
connected nodes be protected.
Grounding
VBOOST_x
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5757 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board. If the AD5757 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device.
The GNDSWx and ground connection for the AVCC supply are
referred to as PGND. PGND should be confined to certain areas
of the board, and the PGND-to-AGND connection should be
made at one point only.
Supply Decoupling
VBOOST_x
IOUT_x
RP
GND
RLOAD
09225-079
AD5757
Figure 63. Output Transient Voltage Protection
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5757 is via a serial bus that
uses a protocol compatible with microcontrollers and DSP
processors. The communications channel is a 3-wire minimum
interface consisting of a clock signal, a data signal, and a latch
signal. The AD5757 requires a 24-bit data-word with data valid
on the falling edge of SCLK.
The DAC output update is initiated on either the rising edge of
LDAC or, if LDAC is held low, on the rising edge of SYNC. The
contents of the registers can be read using the readback function.
AD5757-TO-ADSP-BF527 INTERFACE
The AD5757 can be connected directly to the SPORT interface
of the ADSP-BF527, an Analog Devices, Inc., Blackfin® DSP.
Figure 64 shows how the SPORT interface can be connected to
control the AD5757.
AD5757
SPORT_TFS
SYNC
SPORT_TSCK
SCLK
SDIN
ADSP-BF527
GPIO0
LDAC
Traces
The power supply lines of the AD5757 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching signals
such as clocks should be shielded with digital ground to prevent
radiating noise to other parts of the board and should never be
run near the reference inputs. A ground line routed between the
SDIN and SCLK lines helps reduce crosstalk between them (not
required on a multilayer board that has a separate ground plane,
but separating the lines helps). It is essential to minimize noise
on the REFIN line because it couples through to the DAC output.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board. A
microstrip technique is by far the best but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground plane, whereas signal
traces are placed on the solder side.
09225-080
SPORT_DTO
The AD5757 should have ample supply bypassing of 10 μF
in parallel with 0.1 μF on each supply located as close to the
package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and low
effective series inductance (ESL), such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
Figure 64. AD5757-to-ADSP-BF527 SPORT Interface
Rev. A | Page 40 of 44
AD5757
DC-to-DC Converters
GALVANICALLY ISOLATED INTERFACE
To achieve high efficiency, good regulation, and stability, a welldesigned printed circuit board layout is required.
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur.
Isocouplers provide voltage isolation in excess of 2.5 kV. The
serial loading structure of the AD5757 makes it ideal for
isolated interfaces because the number of interface lines is kept
to a minimum. Figure 65 shows a 4-channel isolated interface to
the AD5757 using an ADuM1400. For more information, visit
www.analog.com.
•
•
•
•
•
•
Keep the low ESR input capacitor, CIN, close to AVCC
and PGND.
Keep the high current path from CIN through the inductor,
LDCDC, to SWX and PGND as short as possible.
Keep the high current path from CIN through LDCDC and the
rectifier, DDCDC, to the output capacitor, CDCDC, as short as
possible.
Keep high current traces as short and as wide as possible.
The path from CIN through the inductor, LDCDC, to SWX and
PGND should be able to handle a minimum of 1 A.
Place the compensation components as close as possible to
COMPDCDC_x.
Avoid routing high impedance traces near any node
connected to SWx or near the inductor to prevent radiated
noise injection.
MICROCONTROLLER
ADuM1400*
SERIAL CLOCK
OUT
VIA
SERIAL DATA
OUT
VIB
SYNC OUT
CONTROL OUT
VIC
VID
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
*ADDITIONAL PINS OMITTED FOR CLARITY.
Rev. A | Page 41 of 44
Figure 65. Isolated Interface
VOA
VOB
VOC
VOD
TO SCLK
TO SDIN
TO SYNC
TO LDAC
09225-081
Follow these guidelines when designing printed circuit boards
(see Figure 56):
AD5757
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
48
64 1
49
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
(BOTTOM VIEW)
0.50
0.40
0.30
1.00
0.85
0.80
16
17
33
32
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
7.25
7.10 SQ
6.95
EXPOSED PAD
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
080108-C
8.75
BSC SQ
TOP VIEW
Figure 66. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5757ACPZ
AD5757ACPZ-REEL7
1
Resolution (Bits)
16
16
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Z = RoHS Compliant Part.
Rev. A | Page 42 of 44
Package Option
CP-64-3
CP-64-3
AD5757
NOTES
Rev. A | Page 43 of 44
AD5757
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09225-0-5/11(A)
Rev. A | Page 44 of 44
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