ADS 124 ® ADS 2 124 ADS1242 ADS1243 ® 3 SBAS235H – DECEMBER 2001 – REVISED OCTOBER 2013 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 24 BITS NO MISSING CODES ● SIMULTANEOUS 50Hz AND 60Hz REJECTION (–90dB MINIMUM) ● 0.0015% INL ● 21 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) ● PGA GAINS FROM 1 TO 128 ● SINGLE-CYCLE SETTLING ● PROGRAMMABLE DATA OUTPUT RATES ● EXTERNAL DIFFERENTIAL REFERENCE OF 0.1V TO 5V ● ON-CHIP CALIBRATION ● SPI™ COMPATIBLE ● 2.7V TO 5.25V SUPPLY RANGE ● 600µW POWER CONSUMPTION ● UP TO EIGHT INPUT CHANNELS ● UP TO EIGHT DATA I/O The ADS1242 and ADS1243 are precision, wide dynamic range, delta-sigma, analog-to-digital (A/D) converters with 24-bit resolution operating from 2.7V to 5.25V supplies. These delta-sigma, A/D converters provide up to 24 bits of no missing code performance and effective resolution of 21 bits. The input channels are multiplexed. Internal buffering can be selected to provide a very high input impedance for direct connection to transducers or low-level voltage signals. Burnout current sources are provided that allow for the detection of an open or shorted sensor. An 8-bit digital-to-analog converter (DAC) provides an offset correction with a range of 50% of the FSR (Full-Scale Range). The Programmable Gain Amplifier (PGA) provides selectable gains of 1 to 128 with an effective resolution of 19 bits at a gain of 128. The A/D conversion is accomplished with a second-order delta-sigma modulator and programmable FIR filter that provides a simultaneous 50Hz and 60Hz notch. The reference input is differential and can be used for ratiometric conversion. The serial interface is SPI compatible. Up to eight bits of data I/O are also provided that can be used for input or output. The ADS1242 and ADS1243 are designed for high-resolution measurement applications in smart transmitters, industrial process control, weight scales, chromatography, and portable instrumentation. APPLICATIONS ● ● ● ● ● ● INDUSTRIAL PROCESS CONTROL LIQUID /GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTATION WEIGHT SCALES VREF+ VDD VREF– XIN XOUT VDD Clock Generator 2µA Offset DAC AIN0/D0 A = 1:128 AIN1/D1 IN+ AIN2/D2 AIN3/D3 AIN4/D4 MUX IN– BUF + 2nd-Order Modulator PGA Digital Filter Controller Registers AIN5/D5 AIN6/D6 AIN7/D7 ADS1243 Only Serial Interface 2µA GND SCLK DIN DOUT CS GND PDWN DRDY Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2001-2013, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) VDD to GND ........................................................................... –0.3V to +6V Input Current ............................................................... 100mA, Momentary Input Current ................................................................. 10mA, Continuous AIN .................................................................... GND – 0.5V to VDD + 0.5V Digital Input Voltage to GND ...................................... –0.3V to VDD + 0.3V Digital Output Voltage to GND ................................... –0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ......................................... –40°C to +85°C Storage Temperature Range .......................................... –60°C to +100°C NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DIGITAL CHARACTERISTICS: TMIN to TMAX, VDD 2.7V to 5.25V PARAMETER Digital Input/Output Logic Family Logic Level: VIH VIL(1) VOH VOL Input Leakage: IIH IIL Master Clock Rate: fOSC Master Clock Period: tOSC CONDITIONS MIN TYP MAX UNITS VDD 0.2 • VDD V V V V µA µA MHz ns CMOS 0.8 • VDD GND VDD – 0.4 GND IOH = 1mA IOL = 1mA VI = VDD VI = 0 –10 1 200 1/fOSC GND + 0.4 10 5 1000 NOTE: (1) VIL for XIN is GND to GND + 0.05V. 2 ADS1242, 1243 www.ti.com SBAS235H ELECTRICAL CHARACTERISTICS: VDD = 5V All specifications TMIN to TMAX, VDD = +5V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. ADS1242 ADS1243 PARAMETER ANALOG INPUT (AIN0 – AIN7) Analog Input Range Full-Scale Input Range Differential Input Impedance Bandwidth fDATA = 3.75Hz fDATA = 7.50Hz fDATA = 15.00Hz Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources CONDITIONS MIN Buffer OFF Buffer ON (In+) – (In–), See Block Diagram, RANGE = 0 RANGE = 1 Buffer OFF Buffer ON GND – 0.1 GND + 0.05 –3dB –3dB –3dB User-Selectable Gain Ranges Output Noise Power-Supply Rejection VOLTAGE REFERENCE INPUT Reference Input Range VREF Common-Mode Rejection Common-Mode Rejection Bias Current(3) POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Current Power Dissipation UNITS VDD + 0.1 VDD – 1.5 ±VREF /PGA ±VREF /(2 • PGA) 5/PGA 5 V V V V MΩ GΩ 1.65 3.44 14.6 Hz Hz Hz 1 128 Modulator OFF, T = 25°C pF pA µA RANGE = 0 RANGE = 1 ±VREF /(2 • PGA) ±VREF /(4 • PGA) V V ±10 1 Bits % ppm/°C Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift Normal-Mode Rejection MAX 9 5 2 OFFSET DAC Offset DAC Range SYSTEM PERFORMANCE Resolution Integral Nonlinearity Offset Error (1) Offset Drift(1) Gain Error (1) Gain Error Drift(1) Common-Mode Rejection TYP 8 No Missing Codes End Point Fit 24 ±0.0015 7.5 0.02 0.005 0.5 fCM = fCM = fSIG = fSIG = at DC 60Hz, fDATA = 50Hz, fDATA = 50Hz, fDATA = 60Hz, fDATA = 100 15Hz 15Hz 15Hz 15Hz at DC, dB = –20 log(∆VOUT /VDD)(2) 80 REF IN+, REF IN– VREF ≡ (REF IN+) – (REF IN–), RANGE = 0 RANGE = 1 at DC fVREFCM = 60Hz, fDATA = 15Hz VREF = 2.5V 0 0.1 0.1 VDD PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON SLEEP Mode Read Data Continuous Mode PDWN PGA = 1, Buffer OFF 4.75 TEMPERATURE RANGE Operating Storage 130 120 100 100 See Typical Characteristics 95 2.5 dB VDD 2.6 VDD V V V dB dB µA 5.25 375 800 425 1400 1.9 V µA µA µA µA µA µA nA mW +85 +100 °C °C 120 120 1.3 240 450 290 960 60 230 0.5 1.2 –40 –60 Bits % of FS ppm of FS ppm of FS/°C % ppm/°C dB dB dB dB dB NOTES: (1) Calibration can minimize these errors. (2) ∆VOUT is a change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency. ADS1242, 1243 SBAS235H www.ti.com 3 ELECTRICAL CHARACTERISTICS: VDD = 3V All specifications TMIN to TMAX, VDD = +3V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, unless otherwise specified. ADS1242 ADS1243 PARAMETER ANALOG INPUT (AIN0 – AIN7) Analog Input Range Full-Scale Input Voltage Range Input Impedance Bandwidth fDATA = 3.75Hz fDATA = 7.50Hz fDATA = 15.00Hz Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources CONDITIONS MIN Buffer OFF Buffer ON (In+) – (In–) See Block Diagram, RANGE = 0 RANGE = 1 Buffer OFF Buffer ON GND – 0.1 GND + 0.05 –3dB –3dB –3dB User-Selectable Gain Ranges Output Noise Power-Supply Rejection VOLTAGE REFERENCE INPUT Reference Input Range VREF Common-Mode Rejection Common-Mode Rejection Bias Current(3) POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Current Power Dissipation UNITS VDD + 0.1 VDD – 1.5 ±VREF /PGA ±VREF /(2 • PGA) 5/PGA 5 V V V V MΩ GΩ 1.65 3.44 14.6 Hz Hz Hz 1 128 Modulator OFF, T = 25°C pF pA µA RANGE = 0 RANGE = 1 ±VREF /(2 • PGA) ±VREF /(4 • PGA) V V ±10 2 Bits % ppm/°C Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift Normal-Mode Rejection MAX 9 5 2 OFFSET DAC Offset DAC Range SYSTEM PERFORMANCE Resolution Integral Nonlinearity Offset Error(1) Offset Drift(1) Gain Error(1) Gain Error Drift(1) Common-Mode Rejection TYP 8 No Missing Codes End Point Fit 24 ±0.0015 15 0.04 0.01 1.0 fCM = fCM = fSIG = fSIG = at DC 60Hz, fDATA = 50Hz, fDATA = 50Hz, fDATA = 60Hz, fDATA = 100 15Hz 15Hz 15Hz 15Hz at DC, dB = –20 log(∆VOUT /VDD)(2) 75 130 120 100 100 See Typical Characteristics 90 REF IN+, REF IN– VREF ≡ (REF IN+) – (REF IN–), RANGE = 0 RANGE = 1 0 0.1 0.1 1.25 2.5 at DC fVREFCM = 60Hz, fDATA = 15Hz VREF = 1.25 VDD PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON SLEEP Mode Read Data Continuous Mode PDWN = 0 PGA = 1, Buffer OFF TEMPERATURE RANGE Operating Storage dB VDD 1.30 2.6 120 120 0.65 2.7 190 460 240 870 75 113 0.5 0.6 –40 –60 Bits % of FS ppm of FS ppm of FS/°C % ppm/°C dB dB dB dB dB V V V dB dB µA 3.3 375 700 375 1325 1.2 V µA µA µA µA µA µA nA mW +85 +100 °C °C NOTES: (1) Calibration can minimize these errors. (2) ∆VOUT is a change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency. 4 ADS1242, 1243 www.ti.com SBAS235H PIN CONFIGURATION (ADS1242) PIN CONFIGURATION (ADS1243) Top View TSSOP Top View TSSOP VDD 1 20 DRDY VDD 1 16 DRDY XIN 2 19 SCLK XIN 2 15 SCLK XOUT 3 18 DOUT XOUT 3 14 DOUT PDWN 4 17 DIN PDWN 4 VREF+ 5 VREF– 6 15 GND 13 DIN 16 CS ADS1243 ADS1242 VREF+ 5 12 CS VREF– 6 11 GND AIN0/D0 7 14 AIN3/D3 AIN0/D0 7 10 AIN3/D3 AIN1/D1 8 13 AIN2/D2 AIN1/D1 8 9 AIN4/D4 9 12 AIN7/D7 AIN5/D5 10 11 AIN6/D6 AIN2/D2 PIN DESCRIPTIONS (ADS1243) PIN DESCRIPTIONS (ADS1242) PIN NUMBER NAME DESCRIPTION 1 VDD Power Supply 2 XIN Clock Input 3 XOUT 4 PDWN PIN NUMBER NAME 1 2 3 VDD XIN XOUT 4 PDWN 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VREF+ VREF– AIN0/D0 AIN1/D1 AIN4/D4 AIN5/D5 AIN6/D6 AIN7/D7 AIN2/D2 AIN3/D3 GND CS DIN DOUT SCLK DRDY Clock Output, used with crystal or ceramic resonator. Active LOW. Power Down. The power down function shuts down the analog and digital circuits. 5 VREF+ Positive Differential Reference Input 6 VREF– Negative Differential Reference Input 7 AIN0/D0 Analog Input 0/Data I/O 0 8 AIN1/D1 Analog Input 1/Data I/O 1 9 AIN2/D2 Analog Input 2/Data I/O 2 10 AIN3/D3 11 GND Analog Input 3/Data I/O 3 Ground 12 CS Active LOW, Chip Select 13 DIN Serial Data Input, Schmitt Trigger 14 DOUT Serial Data Output 15 SCLK Serial Clock, Schmitt Trigger 16 DRDY Active LOW, Data Ready ADS1242, 1243 SBAS235H www.ti.com DESCRIPTION Power Supply Clock Input Clock Output, used with crystal or ceramic resonator. Active LOW. Power Down. The power down function shuts down the analog and digital circuits. Positive Differential Reference Input Negative Differential Reference Input Analog Input 0/Data I/O 0 Analog Input 1/Data I/O 1 Analog Input 4/Data I/O 4 Analog Input 5/Data I/O 5 Analog Input 6/Data I/O 6 Analog Input 7/Data I/O 7 Analog Input 2/Data I/O 2 Analog Input 3/Data I/O 3 Ground Active LOW, Chip Select Serial Data Input, Schmitt Trigger Serial Data Output Serial Clock, Schmitt Trigger Active LOW, Data Ready 5 TIMING DIAGRAMS CS t3 t1 t2 t10 SCLK t4 DIN MSB t2 t6 t5 t11 LSB t7 (Command or Command and Data) t8 DOUT t9 MSB(1) LSB(1) NOTE: (1) Bit order = 0. ADS1242 or ADS1243 Resets On Falling Edge 300 • tOSC < t12 < 500 • tOSC SCLK Reset Waveform t13 t13 t13 : > 5 • tOSC 550 • tOSC < t14 < 750 • tOSC SCLK t12 t14 1050 • tOSC < t15 < 1250 • tOSC t15 DIAGRAM 1. t16 tDATA DRDY PDWN t17 t18 SCLK t19 DIAGRAM 2. TIMING CHARACTERISTICS TABLE SPEC t1 DESCRIPTION MIN SCLK Period MAX UNITS 3 tOSC Periods DRDY Periods 4 t2 SCLK Pulse Width, HIGH and LOW 200 ns t3 CS low to first SCLK Edge; Setup Time(2) 0 ns t4 DIN Valid to SCLK Edge; Setup Time 50 ns t5 Valid DIN to SCLK Edge; Hold Time 50 ns t6 Delay between last SCLK edge for DIN and first SCLK edge for DOUT: t 7(1) RDATA, RDATAC, RREG, WREG SCLK Edge to Valid New DOUT t 8(1) SCLK Edge to DOUT, Hold Time 0 Last SCLK Edge to DOUT Tri-State 6 t9 50 50 tOSC Periods ns 10 tOSC Periods ns NOTE: DOUT goes tri-state immediately when CS goes HIGH. t10 t11 t16 t17 t18 t19 CS LOW time after final SCLK edge. Read from the device Write to the device Final SCLK edge of one command until first edge SCLK of next command: RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL SELFCAL RESET (also SCLK Reset) Pulse Width Allowed analog input change for next valid conversion. DOR update, DOR data not valid. First SCLK after DRDY goes LOW: RDATAC Mode Any other mode 0 8 tOSC Periods tOSC Periods 4 2 4 16 4 4 tOSC Periods DRDY Periods DRDY Periods tOSC Periods tOSC Periods tOSC Periods tOSC Periods 10 0 tOSC Periods tOSC Periods 5000 NOTES: (1) Load = 20pF 10kΩ to GND. (2) CS may be tied LOW. 6 ADS1242, 1243 www.ti.com SBAS235H TYPICAL CHARACTERISTICS All specifications VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs PGA SETTING EFFECTIVE NUMBER OF BITS vs PGA SETTING 21.5 22 DR = 10 21.0 21 DR = 10 DR = 01 20 20.0 ENOB (rms) ENOB (rms) 20.5 19.5 19.0 DR = 00 18.5 19 DR = 01 18 DR = 00 17 18.0 Buffer ON Buffer OFF 16 17.5 15 17.0 1 2 4 8 16 32 64 1 128 2 16 32 64 128 NOISE vs INPUT SIGNAL EFFECTIVE NUMBER OF BITS vs PGA SETTING 2.0 20.5 1.8 20.0 DR = 10 19.0 Noise (rms, ppm of FS) 19.5 ENOB (rms) 8 PGA Setting PGA Setting DR = 01 18.5 18.0 DR = 00 17.5 17.0 Buffer OFF, VREF = 1.25V 16.5 1 2 4 8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 –2.5 16.0 16 32 64 128 –1.5 –0.5 0.5 1.5 PGA Setting VIN (V) COMMON-MODE REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY 140 140 120 120 100 100 PSRR (dB) CMRR (dB) 4 80 60 40 2.5 80 60 40 20 20 Buffer ON Buffer ON 0 0 1 10 100 1k 10k 100k ADS1242, 1243 SBAS235H 1 10 100 1k 10k 100k Frequency of Power Supply (Hz) Frequency of Power Supply (Hz) www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) All specification VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. GAIN vs TEMPERATURE (Cal at 25°C) OFFSET vs TEMPERATURE (Cal at 25°C) 1.00010 50 PGA16 PGA1 1.00006 Gain (Normalized) Offset (ppm of FS) 0 –50 PGA64 –100 PGA128 –150 1.00002 0.99998 0.99994 0.99990 0.99986 –200 –50 –30 –10 10 30 50 70 –50 90 –30 –10 10 30 50 Temperature (°C) Temperature (°C) INTEGRAL NONLINEARITY vs INPUT SIGNAL CURRENT vs TEMPERATURE (Buffer Off) 70 90 70 90 260 10 8 250 –40°C 240 4 +85°C Current (µA) INL (ppm of FS) 6 2 0 –2 –4 220 210 +25°C –6 230 200 –8 –10 –2.5 –2.0 –1.5 –1.0 –0.5 190 0 0.5 1.0 1.5 2.0 –50 2.5 –30 –10 CURRENT vs VOLTAGE 50 SUPPLY CURRENT vs SUPPLY Normal 4.91MHz 250 Normal 2.45MHz 250 IDIGITAL (µA) 300 Current (µA) 30 300 350 200 150 SLEEP 2.45MHz SLEEP 4.91MHz 100 200 SLEEP 4.91MHz Normal 2.45MHz Normal 4.91MHz 150 100 50 Power Down 50 0 SLEEP 2.45MHz Power Down 0 –50 3.0 3.25 3.5 3.75 4.0 4.25 4.5 4.75 5.0 3.0 VDD (V) 8 10 Temperature (°C) VIN (V) 3.5 4.0 4.5 5.0 VDD (V) ADS1242, 1243 www.ti.com SBAS235H TYPICAL CHARACTERISTICS (Cont.) All specification VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. OFFSET DAC OFFSET vs TEMPERATURE (Cal at 25°C) NOISE HISTOGRAM Number of Occurrences 3000 200 10k Readings VIN = 0V 170 140 Offset (ppm of FSR) 3500 2500 2000 1500 1000 110 80 50 20 –10 –40 500 –70 –100 0 –50 –3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 –10 10 30 50 Temperature (°C) OFFSET DAC GAIN vs TEMPERATURE (Cal at 25°C) OFFSET DAC NOISE vs SETTING 1.00020 70 90 0.8 1.00016 0.7 Noise (rms, ppm of FS) 1.00012 Gain (Normalized) –30 ppm of FS 1.00008 1.00004 1.00000 0.99996 0.99992 0.99988 0.99984 0.6 0.5 0.4 0.3 0.2 0.1 0.99980 0.99976 –50 –30 –10 10 30 50 70 90 Temperature (°C) –96 –64 –32 0 32 64 96 128 Offset DAC Setting ADS1242, 1243 SBAS235H 0 –128 www.ti.com 9 OVERVIEW INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 1. For example, if AIN0 is selected as the positive differential input channel, any other channel can be selected as the negative terminal for the differential input AIN0/D0 AIN1/D1 VDD channel. With this method, it is possible to have up to seven single-ended input channels or four independent differential input channels for the ADS1243, and three single-ended input channels or two independent differential input channels for the ADS1242. The ADS1242 and ADS1243 feature a single-cycle settling digital filter that provides valid data on the first conversion after a new channel selection. In order to minimize the settling error, synchronize MUX changes to the conversion beginning, which is indicated by the falling edge of DRDY. In other words, issuing a MUX change through the WREG command immediately after DRDY goes LOW minimizes the settling error. Increasing the time between the conversion beginning (DRDY goes LOW) and the MUX change command (tDELAY) results in a settling error in the conversion data, as shown in Figure 2. Burnout Current Source AIN2/D2 BURNOUT CURRENT SOURCES The Burnout Current Sources can be used to detect sensor short-circuit or open-circuit conditions. Setting the Burnout Current Sources (BOCS) bit in the SETUP register activates two 2µA current sources called burnout current sources. One of the current sources is connected to the converter’s negative input and the other is connected to the converter’s positive input. AIN3/D3 Input Buffer AIN4/D4 AIN5/D5 Burnout Current Source Figure 3 shows the situation for an open-circuit sensor. This is a potential failure mode for many kinds of remotely connected sensors. The current source on the positive input acts as a pull-up, causing the positive input to go to the positive analog supply, and the current source on the negative input acts as a pull-down, causing the negative input to go to ground. The ADS1242/43 therefore outputs full-scale (7FFFFF Hex). AIN6/D6 GND AIN7/D7 ADS1243 Only FIGURE 1. Input Multiplexer Configuration. Figure 4 shows a short-circuited sensor. Since the inputs are New Conversion Begins, Previous Conversion Data Complete Previous Conversion New Conversion Complete DRDY tDELAY SCLK DIN MSB LSB SETTLING ERROR vs DELAY TIME fCLK = 2.4576MHz 10 Settling Error (%) 1 0.1 0.01 0.001 0.0001 0.00001 0.000001 0 2 4 6 8 10 12 Delay Time, tDELAY (ms) 14 16 FIGURE 2. Input Multiplexer Configuration. 10 ADS1242, 1243 www.ti.com SBAS235H current required by the buffer depends on the PGA setting. When the PGA is set to 1, the buffer uses approximately 50µA; when the PGA is set to 128, the buffer uses approxi- VDD mately 500µA. 2µA VDD PGA ADC OPEN CIRCUIT CODE = 0x7FFFFFH 0V 2µA FIGURE 3. Burnout detection while sensor is open-circuited. shorted and at the same potential, the ADS1242/43 signal outputs are approximately zero. (Note that the code for shorted inputs is not exactly zero due to internal series resistance, low-level noise and other error sources.) INPUT BUFFER The Programmable Gain Amplifier (PGA) can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the effective resolution of the A/D converter. For instance, with a PGA of 1 on a 5V full-scale signal, the A/D converter can resolve down to 1µV. With a PGA of 128 and a full-scale signal of 39mV, the A/D converter can resolve down to 75nV. VDD current increases with PGA settings higher than 4. OFFSET DAC The input to the PGA can be shifted by half the full-scale input range of the PGA using the Offset DAC (ODAC) register. The ODAC register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Using the offset DAC does not reduce the performance of the A/D converter. For more details on the ODAC in the ADS1242/43, please refer to TI application report SBAA077 (available through the TI website). VDD MODULATOR The modulator is a single-loop second-order system. The modulator runs at a clock speed (fMOD) that is derived from the external clock (fOSC). The frequency division is determined by the SPEED bit in the SETUP register, as shown in Table I. 2µA VDD/2 SHORT CIRCUIT ADC CODE ≅ 0 VDD/2 2µA fOSC 2.4576MHz 4.9152MHz FIGURE 4. Burnout detection while sensor is short-circuited. SPEED BIT fMOD 00 0 1 0 1 19,200Hz 9,600Hz 38,400Hz 19,200Hz 15Hz 7.5Hz 30Hz 15Hz DR BITS 01 10 7.5Hz 3.75Hz 3.75Hz 1.875Hz 15Hz 7.5Hz 7.5Hz 3.75Hz 1st NOTCH FREQ. 50/60Hz 25/30Hz 100/120Hz 50/60Hz TABLE I. Output Configuration. The input impedance of the ADS1242/43 without the buffer enabled is approximately 5MΩ/PGA. For systems requiring very high input impedance, the ADS1242/43 provides a chopper-stabilized differential FET-input voltage buffer. When activated, the buffer raises the ADS1242/43 input impedance to approximately 5GΩ. The buffer’s input range is approximately 50mV to VDD – 1.5V. The buffer’s linearity will degrade beyond this range. Differential signals should be adjusted so that both signals are within the buffer’s input range. The buffer can be enabled using the BUFEN pin or the BUFEN bit in the ACR register. The buffer is on when the BUFEN pin is high and the BUFEN bit is set to one. If the BUFEN pin is low, the buffer is disabled. If the BUFEN bit is set to zero, the buffer is also disabled. CALIBRATION The offset and gain errors can be minimized with calibration. The ADS1242 and ADS1243 support both self and system calibration. Self-calibration of the ADS1242 and ADS1243 corrects internal offset and gain errors and is handled by three commands: SELFCAL, SELFGAL, and SELFOCAL. The SELFCAL command performs both an offset and gain calibration. SELFGCAL performs a gain calibration and SELFOCAL performs an offset calibration, each of which takes two tDATA periods to complete. During self-calibration, the ADC inputs are disconnected internally from the input pins. The PGA must be set to 1 prior to issuing a SELFCAL or SELFGCAL command. Any PGA is allowed when issuing a SELFOCAL command. For The buffer draws additional current when activated. The ADS1242, 1243 SBAS235H www.ti.com 11 example, if using PGA = 64, first set PGA = 1 and issue SELFGCAL. Afterwards, set PGA = 64 and issue SELFOCAL. For operation with a reference voltage greater than (VDD – 1.5) volts, the buffer must also be turned off during gain self-calibration to avoid exceeding the buffer input range. System calibration corrects both internal and external offset and gain errors. While performing system calibration, the appropriate signal must be applied to the inputs. The system offset calibration command (SYSOCAL) requires a zero input differential signal (see Table IV, page 18). It then computes the offset that nullifies the offset in the system. The system gain calibration command (SYSGCAL) requires a positive full-scale input signal. It then computes a value to nullify the gain error in the system. Each of these calibrations takes two tDATA periods to complete. System gain calibration is recommended for the best gain calibration at higher PGAs. Calibration should be performed after power on, a change in temperature, or a change of the PGA. The RANGE bit (ACR bit 2) must be zero during calibration. Calibration removes the effects of the ODAC; therefore, disable the ODAC during calibration, and enable again after calibration is complete. At the completion of calibration, the DRDY signal goes low, indicating the calibration is finished. The first data after calibration should be discarded since it may be corrupt from calibration data remaining in the filter. The second data is always valid. EXTERNAL VOLTAGE REFERENCE The ADS1242 and ADS1243 require an external voltage reference. The selection for the voltage reference value is made through the ACR register. XIN C1 Crystal XOUT C2 FIGURE 5. Crystal Connection. CLOCK SOURCE FREQUENCY C1 C2 PART NUMBER Crystal 2.4576 0-20pF 0-20pF ECS, ECSD 2.45 - 32 Crystal 4.9152 0-20pF 0-20pF ECS, ECSL 4.91 Crystal 4.9152 0-20pF 0-20pF ECS, ECSD 4.91 Crystal 4.9152 0-20pF 0-20pF CTS, MP 042 4M9182 TABLE II. Recommended Crystals. DIGITAL FILTER The ADS1242 and ADS1243 have a 1279 tap linear phase Finite Impulse Response (FIR) digital filter that a user can configure for various output data rates. When a 2.4576MHz crystal is used, the device can be programmed for an output data rate of 15Hz, 7.5Hz, or 3.75Hz. Under these conditions, the digital filter rejects both 50Hz and 60Hz interference. Figure 6 shows the digital filter frequency response for data output rates of 15Hz, 7.5Hz, and 3.75Hz. If a different data output rate is desired, a different crystal frequency can be used. However, the rejection frequencies shift accordingly. For example, a 3.6864MHz master clock with the default register condition has: (3.6864MHz/2.4576MHz) • 15Hz = 22.5Hz data output rate The external voltage reference is differential and is represented by the voltage difference between the pins: +VREF and –VREF. The absolute voltage on either pin, +VREF or –VREF, can range from GND to VDD. However, the following limitations apply: and the first and second notch is: For VDD = 5.0V and RANGE = 0 in the ACR, the differential VREF must not exceed 2.5V. The ADS1242 has four pins and the ADS1243 has eight pins that serve a dual purpose as both analog inputs and data I/O. These pins are configured through the IOCON, DIR, and DIO registers and can be individually configured as either analog inputs or data I/O. See Figure 7 (page 14) for the equivalent schematic of an Analog/Data I/O pin. For VDD = 5.0V and RANGE = 1 in the ACR, the differential VREF must not exceed 5V. For VDD = 3.0V and RANGE = 0 in the ACR, the differential VREF must not exceed 1.25V. For VDD = 3.0V and RANGE = 1 in the ACR, the differential VREF must not exceed 2.5V. CLOCK GENERATOR The clock source for the ADS1242 and ADS1243 can be provided from a crystal, oscillator, or external clock. When the clock source is a crystal, external capacitors must be provided to ensure start-up and stable clock frequency. This is shown in both Figure 5 and Table II. XOUT is only for use with external crystals and it should not be used as a clock driver for external 1.5 • (50Hz and 60Hz) = 75Hz and 90Hz DATA I/O INTERFACE The IOCON register defines the pin as either an analog input or data I/O. The power-up state is an analog input. If the pin is configured as an analog input in the IOCON register, the DIR and DIO registers have no effect on the state of the pin. If the pin is configured as data I/O in the IOCON register, then DIR and DIO are used to control the state of the pin. The DIR register controls the direction of the data pin, either as an input or output. If the pin is configured as an input in the DIR register, then the corresponding DIO register bit reflects the state of the pin. Make sure the pin is driven to a logic one or zero when configured as an input to prevent circuitry. 12 ADS1242, 1243 www.ti.com SBAS235H ADS1242 AND ADS1243 FILTER RESPONSE WHEN fDATA = 15Hz FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 15Hz 0 –40 –20 –50 –40 –60 Magnitude (dB) Gain (dB) –60 –80 –100 –120 –140 –90 –100 –110 –130 –180 –140 0 20 40 60 80 100 120 140 160 180 200 45 50 55 60 Frequency (Hz) Frequency (Hz) ADS1242 AND ADS1243 FILTER RESPONSE WHEN fDATA = 7.5Hz FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 7.5Hz 0 –40 –20 –50 –40 –60 Magnitude (dB) –60 Gain (dB) –80 –120 –160 –80 –100 –120 65 –70 –80 –90 –100 –110 –140 –120 –160 –130 –180 –140 0 20 Frequency (Hz) 55 Frequency (Hz) ADS1242 AND ADS1243 FILTER RESPONSE WHEN fDATA = 3.75Hz FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 3.75Hz 40 60 80 100 120 45 140 160 180 200 0 –40 –20 –50 –40 –60 –60 –70 Magnitude (dB) Gain (dB) –70 –80 –100 –120 –140 50 60 65 –80 –90 –100 –110 –120 –160 –130 –180 –140 0 20 40 60 80 100 120 140 160 180 200 45 50 Frequency (Hz) 55 60 65 Frequency (Hz) fOSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1 ATTENUATION DATA OUTPUT RATE –3dB BANDWIDTH fIN = 50 ± 0.3Hz fIN = 60 ± 0.3Hz fIN = 50 ± 1Hz 15Hz 14.6Hz –80.8dB –87.3dB –68.5dB –76.1dB 7.5Hz 3.44Hz –85.9dB –87.4dB –71.5dB –76.2dB 3.75Hz 1.65Hz –93.8dB –88.6dB –86.8dB –77.3dB fIN = 60 ± 1Hz FIGURE 6. Filter Frequency Responses. ADS1242, 1243 SBAS235H www.ti.com 13 excess current dissipation. If the pin is configured as an output in the DIR register, then the corresponding DIO register bit value determines the state of the output pin (0 = GND, 1 = VDD). It is still possible to perform A/D conversions on a pin configured as data I/O. This may be useful as a test mode, where the data I/O pin is driven and an A/D conversion is done on the pin. Data Input (DIN) and Data Output (DOUT) The data input (DIN) and data output (DOUT) receive and send data from the ADS1242 and ADS1243. DOUT is high impedance when not in use to allow DIN and DOUT to be connected together and driven by a bidirectional bus. Note: the Read Data Continuous Mode (RDATAC) command should not be issued when DIN and DOUT are connected. While in RDATAC mode, DIN looks for the STOPC or RESET command. If either of these 8-bit bytes appear on DOUT (which is connected to DIN), the RDATAC mode ends. IOCON DATA READY ( DRDY) PIN DIR The DRDY line is used as a status signal to indicate when data is ready to be read from the internal data register. DRDY goes LOW when a new data word is available in the DOR register. It is reset HIGH when a read operation from the data register is complete. It also goes HIGH prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. DIO WRITE AINx/Dx To Analog Mux DIO READ FIGURE 7. Analog/Data Interface Pin. SERIAL PERIPHERAL INTERFACE The Serial Peripheral Interface (SPI) allows a controller to communicate synchronously with the ADS1242 and ADS1243. The ADS1242 and ADS1243 operate in slave-only mode. The serial interface is a standard four-wire SPI (CS , SCLK, DIN and DOUT) interface. The status of DRDY can also be obtained by interrogating bit 7 of the ACR register (address 2H). The serial interface can operate in 3-wire mode by tying the CS input LOW. In this case, the SCLK, DIN, and DOUT lines are used to communicate with the ADS1242 and ADS1243. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port bit of the microcontroller. Chip Select (CS ) The chip select (CS ) input must be externally asserted before communicating with the ADS1242 or ADS1243. CS must stay LOW for the duration of the communication. Whenever CS goes HIGH, the serial interface is reset. CS may be hard-wired LOW. Serial Clock (SCLK) The serial clock (SCLK) features a Schmitt-triggered input and is used to clock DIN and DOUT data. Make sure to have a clean SCLK to prevent accidental double-shifting of the data. If SCLK is not toggled within three DRDY pulses, the serial interface resets on the next SCLK pulse and starts a new communication cycle. A special pattern on SCLK resets the entire chip; see the RESET section for additional information. 14 DSYNC OPERATION Synchronization can be achieved through the DSYNC command. When the DSYNC command is sent, the digital filter is reset on the edge of the last SCLK of the DSYNC command. The modulator is held in RESET until the next edge of SCLK is detected. Synchronization occurs on the next rising edge of the system clock after the first SCLK following the DSYNC command. POWER-UP—SUPPLY VOLTAGE RAMP RATE The power-on reset circuitry was designed to accommodate digital supply ramp rates as slow as 1V/10ms. To ensure proper operation, the power supply should ramp monotonically. ADS1242, 1243 www.ti.com SBAS235H ADS1242 AND ADS1243 REGISTERS The operation of the device is set up through individual registers. Collectively, the registers contain all the information needed to configure the part, such as data format, ADDRESS REGISTER BIT 7 BIT 6 BIT 5 multiplexer settings, calibration settings, data rate, etc. The 16 registers are shown in Table III. BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00H SETUP ID ID ID ID BOCS PGA2 PGA1 PGA0 01H 02H MUX ACR PSEL3 DRDY PSEL2 U/B PSEL1 SPEED PSEL0 BUFEN NSEL3 BIT ORDER NSEL2 RANGE NSEL1 DR1 NSEL0 DR0 03H 04H ODAC DIO SIGN DIO_7 OSET6 DIO_6 OSET5 DIO_5 OSET4 DIO_4 OSET3 DIO_3 OSET2 DIO_2 OSET1 DIO_1 OSET0 DIO_0 05H 06H DIR IOCON DIR_7 IO7 DIR_6 IO6 DIR_5 IO5 DIR_4 IO4 DIR_3 IO3 DIR_2 IO2 DIR_1 IO1 DIR_0 IO0 07H 08H OCR0 OCR1 OCR07 OCR15 OCR06 OCR14 OCR05 OCR13 OCR04 OCR12 OCR03 OCR11 OCR02 OCR10 OCR01 OCR09 OCR00 OCR08 09H 0AH OCR2 FSR0 OCR23 FSR07 OCR22 FSR06 OCR21 FSR05 OCR20 FSR04 OCR19 FSR03 OCR18 FSR02 OCR17 FSR01 OCR16 FSR00 0BH 0CH FSR1 FSR2 FSR15 FSR23 FSR14 FSR22 FSR13 FSR21 FSR12 FSR20 FSR11 FSR19 FSR10 FSR18 FSR09 FSR17 FSR08 FSR16 0DH 0EH DOR2 DOR1 DOR23 DOR15 DOR22 DOR14 DOR21 DOR13 DOR20 DOR12 DOR19 DOR11 DOR18 DOR10 DOR17 DOR09 DOR16 DOR08 0FH DOR0 DOR07 DOR16 FSR21 DOR04 DOR03 DOR02 DOR01 DOR00 TABLE III. Registers. DETAILED REGISTER DEFINITIONS MUX (Address 01H) Multiplexer Control Register Reset Value = 01H SETUP (Address 00H) Setup Register Reset Value = iiii0000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ID ID ID ID BOCS PGA2 PGA1 PGA0 bit 7-4 Factory Programmed Bits bit 3 BOCS: Burnout Current Source 0 = Disabled (default) 1 = Enabled bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier Gain Selection 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0 bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel Select 0000 = AIN0 (default) 0001 = AIN1 0010 = AIN2 0011 = AIN3 0100 = AIN4 0101 = AIN5 0110 = AIN6 0111 = AIN7 1111 = Reserved bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel Select 0000 = AIN0 0001 = AIN1 (default) 0010 = AIN2 0011 = AIN3 0100 = AIN4 0101 = AIN5 0110 = AIN6 0111 = AIN7 1111 = Reserved ADS1242, 1243 SBAS235H www.ti.com 15 ODAC (Address 03 ) Offset DAC Reset Value = 00H ACR (Address 02H) Analog Control Register Reset Value = X0H bit 7 bit 6 bit 5 bit 4 DRDY U/B SPEED BUFEN bit 3 bit 2 BIT ORDER RANGE bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DR1 DR0 SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0 bit 7 DRDY: Data Ready (Read Only) This bit duplicates the state of the DRDY pin. bit 6 U/B: Data Format 0 = Bipolar (default) 1 = Unipolar U/B 0 1 ANALOG INPUT DIGITAL OUTPUT (Hex) +FSR Zero –FSR +FSR Zero –FSR 0x7FFFFF 0x000000 0x800000 0xFFFFFF 0x000000 0x000000 bit 7 Sign 0 = Positive 1 = Negative Offset = VREF OSET [6 : 0] • 2 • PGA 127 RANGE = 0 Offset = VREF 4 • PGA OSET [6 : 0] • 127 RANGE = 1 NOTE: The offset DAC must be enabled after calibration or the calibration nullifies the effects. bit 5 SPEED: Modulator Clock Speed 0 = fMOD = fOSC/128 (default) 1 = fMOD = fOSC/256 bit 4 BUFEN: Buffer Enable 0 = Buffer Disabled (default) 1 = Buffer Enabled bit 3 bit 2 bit 1-0 DIO (Address 04H) Data I/O Reset Value = 00H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIO 7 DIO 6 DIO 5 DIO 4 DIO 3 DIO 2 DIO 1 DIO 0 0 = Most Significant Bit Transmitted First (default) 1 = Least Significant Bit Transmitted First If the IOCON register is configured for data, a value written to this register appears on the data I/O pins if the pin is configured as an output in the DIR register. Reading this register returns the value of the data I/O pins. Data is always shifted in or out MSB first. Bits 4 to 7 are not used in ADS1242. RANGE: Range Select 0 = Full-Scale Input Range equal to ±V REF (default). 1 = Full-Scale Input Range equal to ±1/2 VREF DIR (Address 05H) Direction Control for Data I/O Reset Value = FFH BIT ORDER: Data Output Bit Order NOTE: This allows reference voltages as high as VDD, but even with a 5V reference voltage the calibration must be performed with this bit set to 0. DR1: DR0: Data Rate (fOSC = 2.4576MHz, SPEED = 0) 00 = 15Hz (default) 01 = 7.5Hz 10 = 3.75Hz 11 = Reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 Each bit controls whether the corresponding data I/O pin is an output (= 0) or input (= 1). The default power-up state is as inputs. Bits 4 to 7 are not used in ADS1242. IOCON (Address 06H) I/O Configuration Register Reset Value = 00H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 bit 7-0 IO7: IO0: Data I/O Configuration 0 = Analog (default) 1 = Data Configuring the pin as a data I/O pin allows it to be controlled through the DIO and DIR registers. Bits 4 to 7 are not used in ADS1242. OCR0 (Address 07H) Offset Calibration Coefficient (Least Significant Byte) Reset Value = 00H 16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00 ADS1242, 1243 www.ti.com SBAS235H OCR1 (Address 08H) Offset Calibration Coefficient (Middle Byte) Reset Value = 00H FSR2 (Address 0CH) Full-Scale Register (Most Significant Byte) Reset Value = 55H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 OCR2 (Address 09H) Offset Calibration Coefficient (Most Significant Byte) Reset Value = 00H DOR2 (Address 0DH) Data Output Register (Most Significant Byte) (Read Only) Reset Value = 00H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16 FSR0 (Address 0AH) Full-Scale Register (Least Significant Byte) Reset Value = 59H DOR1 (Address 0EH) Data Output Register (Middle Byte) (Read Only) Reset Value = 00H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00 DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR09 DOR08 FSR1 (Address 0BH) Full-Scale Register (Middle Byte) Reset Value = 55H DOR0 (Address 0FH) Data Output Register (Least Significant Byte) (Read Only) Reset Value = 00H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08 DOR07 DOR06 DOR05 DOR04 DOR03 DOR02 DOR01 DOR00 ADS1242, 1243 SBAS235H www.ti.com 17 ADS1242 AND ADS1243 CONTROL COMMAND DEFINITIONS The commands listed in Table IV control the operations of the ADS1242 and ADS1243. Some of the commands are stand-alone commands (for example, RESET) while others require additional bytes (for example, WREG requires the count and data bytes). COMMANDS DESCRIPTION RDATA RDATAC STOPC RREG WREG SELFCAL SELFOCAL SELFGCAL SYSOCAL SYSGCAL WAKEUP DSYNC SLEEP RESET Read Data Read Data Continuously Stop Read Data Continuously Read from REG “rrrr” Write to REG “rrrr” Offset and Gain Self Cal Self Offset Cal Self Gain Cal Sys Offset Cal Sys GainCal Wakup from SLEEP Mode Sync DRDY Put in SLEEP Mode Reset to Power-Up Values Operands: n = count (0 to 127) r = register (0 to 15) x = don’t care OP CODE 0000 0000 0000 0001 0101 1111 1111 1111 1111 1111 1111 1111 1111 1111 2nd COMMAND BYTE 0001 (01H) 0011 (03H) 1111 (0FH) r r r r (1xH) r r r r (5xH) 0000 (F0H) 0001 (F1H) 0010 (F2H) 0011 (F3H) 0100 (F4H) 1011 (FB H) 1100 (FCH) 1101 (FDH) 1110 (FEH) — — — xxxx_nnnn (# of regs-1) xxxx_nnnn (# of regs-1) — — — — — — — — — NOTE: The received data format is always MSB first; the data out format is set by the BIT ORDER bit in the ACR register. TABLE IV. Command Summary. RDATA–Read Data RDATAC–Read Data Continuous Description: Read the most recent conversion result from the Data Output Register (DOR). This is a 24-bit value. Description: Read Data Continuous mode enables the continuous output of new data on each DRDY. This command eliminates the need to send the Read Data Command on each DRDY. This mode may be terminated by either the STOPC command or the RESET command. Wait at least 10 fOSC after Operands: None Bytes: 1 Encoding: 0000 0001 DRDY falls before reading. Data Transfer Sequence: DIN DOUT 0000 0001 • • •(1) xxxx xxxx MSB xxxx xxxx Mid-Byte xxxx xxxx LSB Operands: None Bytes: 1 Encoding: 0000 0011 Data Transfer Sequence: Command terminated when “uuuu uuuu” equals STOPC or RESET. NOTE: (1) For wait time, refer to timing specification. DRDY DIN 0000 0011 • • •(1) uuuu uuuu uuuu uuuu uuuu uuuu MSB Mid-Byte LSB Mid-Byte LSB ••• DOUT DRDY DOUT ••• MSB NOTE: (1) For wait time, refer to timing specification. 18 ADS1242, 1243 www.ti.com SBAS235H STOPC–Stop Continuous SELFCAL–Offset and Gain Self Calibration Description: Ends the continuous data output mode. Issue after DRDY goes LOW. Operands: None Description: Starts the process of self calibration. The Offset Calibration Register (OCR) and the Full-Scale Register (FSR) are updated with new values after this operation. Bytes: 1 Operands: None Encoding: 0000 1111 Bytes: 1 Encoding: 1111 0000 Data Transfer Sequence: Data Transfer Sequence: DRDY xxx DIN DIN 0000 1111 1111 0000 RREG–Read from Registers SELFOCAL–Offset Self Calibration Description: Output the data from up to 16 registers starting with the register address specified as part of the instruction. The number of registers read will be one plus the second byte count. If the count exceeds the remaining registers, the addresses wrap back to the beginning. Description: Starts the process of self-calibration for offset. The Offset Calibration Register (OCR) is updated after this operation. Operands: Operands: None Bytes: 1 r, n Encoding: 1111 0001 Bytes: 2 Data Transfer Sequence: Encoding: 0001 rrrr xxxx nnnn Data Transfer Sequence: Read Two Registers Starting from Register 01H (MUX) 0001 0001 DIN 0000 0001 • • •(1) DOUT xxxx xxxx xxxx xxxx MUX ACR DIN SELFGCAL–Gain Self Calibration Description: Starts the process of self-calibration for gain. The Full-Scale Register (FSR) is updated with new values after this operation. NOTE: (1) For wait time, refer to timing specification. Operands: None WREG–Write to Registers Bytes: 1 Encoding: 1111 0010 Description: Write to the registers starting with the register address specified as part of the instruction. The number of registers that will be written is one plus the value of the second byte. Data Transfer Sequence: Operands: r, n Bytes: 2 Encoding: 0101 rrrr xxxx nnnn 1111 0001 DIN 1111 0010 Data Transfer Sequence: Write Two Registers Starting from 04H (DIO) DIN 0101 0100 xxxx 0001 Data for DIO Data for DIR ADS1242, 1243 SBAS235H www.ti.com 19 SYSOCAL–System Offset Calibration DSYNC–Sync DRDY Description: Initiates a system offset calibration. The input should be set to 0V, and the ADS1242 and ADS1243 compute the OCR value that compensates for offset errors. The Offset Calibration Register (OCR) is updated after this operation. The user must apply a zero input signal to the appropriate analog inputs. The OCR register is automatically updated afterwards. Description: Synchronizes the ADS1242 and ADS1243 to an external event. Operands: None Bytes: 1 Encoding: 1111 1100 Data Transfer Sequence: Operands: None Bytes: 1 Encoding: 1111 0011 DIN 1111 1100 Data Transfer Sequence: SLEEP–Sleep Mode DIN 1111 0011 Description: Puts the ADS1242 and ADS1243 into a low power sleep mode. To exit sleep mode, issue the WAKEUP command. SYSGCAL–System Gain Calibration Description: Starts the system gain calibration process. For a system gain calibration, the input should be set to the reference voltage and the ADS1242 and ADS1243 compute the FSR value that will compensate for gain errors. The FSR is updated after this operation. To initiate a system gain calibration, the user must apply a full-scale input signal to the appropriate analog inputs. FCR register is updated automatically. Operands: None Bytes: 1 Encoding: 1111 0100 Operands: None Bytes: 1 Encoding: 1111 1101 Data Transfer Sequence: DIN 1111 1101 RESET–Reset to Default Values Description: Restore the registers to their power-up values. This command stops the Read Continuous mode. Data Transfer Sequence: DIN 1111 0100 Operands: None Bytes: 1 Encoding: 1111 1110 Data Transfer Sequence: WAKEUP Description: Wakes the ADS1242 and ADS1243 from SLEEP mode. Operands: None Bytes: 1 Encoding: 1111 1011 DIN 1111 1110 Data Transfer Sequence: DIN 20 1111 1011 ADS1242, 1243 www.ti.com SBAS235H APPLICATION EXAMPLES load cell output can be directly applied to the differential inputs of ADS1242. GENERAL-PURPOSE WEIGHT SCALE HIGH PRECISION WEIGHT SCALE Figure 8 shows a typical schematic of a general-purpose weight scale application using the ADS1242. In this example, the internal PGA is set to either 64 or 128 (depending on the maximum output voltage of the load cell) so that the Figure 9 shows the typical schematic of a high-precision weight scale application using the ADS1242. The front-end differential amplifier helps maximize the dynamic range. 2.7V ~ 5.25V EMI Filter VDD VREF+ VDD EMI Filter AIN0 DRDY Load Cell SCLK ADS1242 DOUT SPI DOUT MSP430x4xx or other Microprocessor CS EMI Filter AIN1 MCLK XIN XOUT VREF– GND GND EMI Filter FIGURE 8. Schematic of a General-Purpose Weight Scale. 2.7V ~ 5.25V 2.7V ~ 5.25V EMI Filter VREF+ VDD VDD EMI Filter RI OPA2335 AIN0 Load Cell RF DRDY SCLK ADS1242 ADS1243 CI RG RF DOUT DIN SPI MSP430x4xx or other Microprocessor CS RI EMI Filter OPA2335 AIN1 XIN MCLK XOUT VREF– GND GND EMI Filter G = 1 + 2 • RF/RG FIGURE 9. Block Diagram for a High-Precision Weight Scale. ADS1242, 1243 SBAS235H www.ti.com 21 DEFINITION OF TERMS fMOD = An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition of each term is given as follows: PGA SETTING Analog Input Voltage—the voltage at any one analog input relative to GND. Analog Input Differential Voltage—given by the following equation: (IN+) – (IN–). Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the differential is negative. For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 1, the positive full-scale output is produced when the analog input differential is 2.5V. The negative full-scale output is produced when the differential is –2.5V. In each case, the actual input voltages must remain within the GND to VDD range. Conversion Cycle—the term conversion cycle usually refers to a discrete A/D conversion operation, such as that performed by a successive approximation converter. As used here, a conversion cycle refers to the tDATA time period. Data Rate—The rate at which conversions are completed. See definition for fDATA. fDATA = fosc SPEED 128 • 2 • 1280 • 2 SPEED = 0, 1 DR = 0, 1, 2 fMOD—the frequency or speed at which the modulator of the ADS1242 and ADS1243 is running. This depends on the SPEED bit as given by the following equation: SPEED = 0 SPEED = 1 128 256 1, 2, 4, 8 f SAMP = fOSC mfactor 16 f SAMP = fOSC • 2 mfactor 32 f SAMP = fOSC • 4 mfactor 64, 128 f SAMP = fOSC • 8 mfactor fSAMP—the frequency, or switching speed, of the input sampling capacitor. The value is given by one of the following equations: fDATA—the frequency of the digital output data produced by the ADS1242 and ADS1243, fDATA is also referred to as the Data Rate. Full-Scale Range (FSR)—as with most A/D converters, the full-scale range of the ADS1242 and ADS1243 is defined as the input, that produces the positive full-scale digital output minus the input, that produces the negative full-scale digital output. Least Significant Bit (LSB) Weight—this is the theoretical amount of voltage that the differential voltage at the analog input has to change in order to observe a change in the output data of one least significant bit. It is computed as follows: LSB Weight = GAIN SETTING FULL-SCALE RANGE 1 2 4 8 16 32 64 128 5V 2.5V 1.25V 0.625V 312.5mV 156.25mV 78.125mV 39.0625mV ±2.5V ±1.25V ±0.625V ±312.5mV ±156.25mV ±78.125mV ±39.0625mV ±19.531mV Full − ScaleRange 2N – 1 where N is the number of bits in the digital output. tDATA—the inverse of fDATA, or the period between each data output. +5V SUPPLY ANALOG INPUT(1) DIFFERENTIAL INPUT VOLTAGES(2) SAMPLING FREQUENCY For example, when the converter is configured with a 2.5V reference and is placed in a gain setting of 2, the full-scale range is: [1.25V (positive full-scale) minus –1.25V (negative full-scale)] = 2.5V. DR fOSC—the frequency of the crystal oscillator or CMOS compatible input signal at the XIN input of the ADS1242 and ADS1243. mfactor fosc fosc = mfactor 128 • 2 SPEED GENERAL EQUATIONS PGA OFFSET RANGE ±1.25V ±0.625V ±312.5mV ±156.25mV ±78.125mV ±39.0625mV ±19.531mV ±9.766mV FULL-SCALE RANGE DIFFERENTIAL INPUT VOLTAGES(2) PGA SHIFT RANGE RANGE = 0 VREF PGA ± VREF 2 • PGA ± VREF 4 • PGA RANGE = 1 NOTES: (1) With a +2.5V reference. (2) Refer to electrical specification for analog input voltage range. TABLE VI. Full-Scale Range versus PGA Setting. 22 ADS1242, 1243 www.ti.com SBAS235H Revision History DATE REVISION 10/13 H 2/07 G 12/06 F PAGE SECTION DESCRIPTION 21 Application Examples 10 Overview Changed 1st paragraph of Input Multiplexer subsection. Changed Figure 9; switched plus and minus in upper op amp. 15 Registers Deleted 1xxx from Mux Register definition. 14 Overview Added DSYNC Operation subsection. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. ADS1242, 1243 SBAS235H www.ti.com 23 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) ADS1242IPWR ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS 1242 ADS1242IPWRG4 ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS 1242 ADS1242IPWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS 1242 ADS1242IPWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS 1242 ADS1243IPWR ACTIVE TSSOP PW 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1243 ADS1243IPWRG4 ACTIVE TSSOP PW 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1243 ADS1243IPWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1243 ADS1243IPWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1243 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 7-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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OTHER QUALIFIED VERSIONS OF ADS1243 : NOTE: Qualified Version Definitions: Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS1242IPWR TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 ADS1242IPWT TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS1243IPWR TSSOP PW 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 ADS1243IPWT TSSOP PW 20 250 180.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1242IPWR TSSOP PW 16 2500 367.0 367.0 35.0 ADS1242IPWT TSSOP PW 16 250 210.0 185.0 35.0 ADS1243IPWR TSSOP PW 20 2500 367.0 367.0 38.0 ADS1243IPWT TSSOP PW 20 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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