TI CY74FCT2646T 8-bit registered transceiver Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT2646T
8-Bit Registered Transceiver
SCCS043 - September 1994 - Revised March 2000
Features
Functional Description
• Function and pinout compatible with FCT and F logic
• FCT-C speed at 5.4 ns max.
FCT-A speed at 6.3 ns max.
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• 25Ω output series resistors to reduce transmission line
reflection noise
• Reduced VOH (typically=3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature permits live insertion
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and output logic levels
• Sink current
12 mA
Source current 15 mA
• Independent register for A and B buses
• Extended commercial temp. range of –40˚C to +85˚C
• Three-state output
The FCT2646T consists of a bus transceiver circuit with
three-state, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes to
a HIGH logic level. Enable Control G and direction pins are
provided to control the transceiver function. On-chip termination resistors have been added to the outputs to reduce system
noise caused by reflections so that the FCT2646T can be used
to replace the FCT646T in an existing design.
In the transceiver mode, data present at the high impedance
port may be stored in either the A or B register, or in both.
Select controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus will
receive data when the enable control G is Active LOW. In the
isolation mode (enable control G HIGH), A data may be stored
in the B register and/or B data may be stored in the A register.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Pin Configurations
Functional Block Diagram
G
QSOP
Top View
DIR
CPBA
SBA
CPAB
1
24
SAB
2
23
VCC
CPBA
CPAB
DIR
3
22
SBA
SAB
A1
4
21
G
A2
5
20
B1
A3
6
19
B2
A4
7
18
B3
A5
8
17
B4
A6
9
16
B5
A7
10
B6
A8
11
15
14
GND
12
13
B8
D
C
A1
B1
B7
FCT2646T–3
D
C
Logic Block Diagram
A1
CPAB
SAB
DIR
TO 7 OTHER CHANNELS
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
CPBA
FCT2646T–1
SBA
G
B1
FCT2646T–4
Copyright
© 2000, Texas Instruments Incorporated
CY74FCT2646T
Pin Description
Name
Description
A
Data Register A Inputs, Data Register B Outputs
B
Data Register B Inputs, Data Register A Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Output Data Source Select Inputs
DIR, G
Output Enable Inputs
BUS A
DIR
L
G
L
CPAB
X
CPBA
X
SAB
X
BUS B
BUS A
SBA
X
DIR
H
BUS B
G
L
Real-Time Transfer
Bus B to Bus A
G
L
L
H
CPAB
CPBA
X
X
CPBA
X
SAB
L
SBA
X
Real-Time Transfer
Bus A to Bus B
BUS A
DIR
H
L
X
CPAB
X
SAB
X
X
X
BUS B
BUS A
SBA
X
X
X
DIR [1]
L
H
Storage from
A and/or B
BUS A
G
L
L
CPAB
X
H or L
CPBA
H or L
X
Transfer Stored Data
to A and/or B
Note:
1. Cannot transfer data to A bus and B bus simultaneously.
2
SAB
X
H
SBA
H
X
CY74FCT2646T
Function Table[2]
Data I/O[3]
Inputs
Operation or Function
G
DIR
CPAB
CPBA
SAB
SBA
A1 thru A8
B1 thru B8
H
H
X
X
H or L
H or L
X
X
X
X
Input
Input
Isolation
Store A and B Data
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real Time B Data to A Bus
Stored B Data to A Bus
L
L
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real Time A Data to B Bus
Stored A Data to B Bus
Maximum Ratings[4, 5]
FCT2646T
DC Output Current (Maximum Sink Current/Pin) ...... 120 mA
Power Dissipation .......................................................... 0.5W
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied .............................................–65°C to +135°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
DC Input Voltage............................................ –0.5V to +7.0V
Commercial
Ambient
Temperature
VCC
–40°C to +85°C
5V ± 5%
DC Output Voltage ......................................... –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ[6]
2.4
3.3
VOH
Output HIGH Voltage
VCC=Min., IOH=–15 mA
VOL
Output LOW Voltage
VCC=Min., IOL=12 mA
ROUT
Output Resistance
VCC=Min., IOL=12 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[7]
All inputs
0.2
VIK
Input Clamp Diode Voltage
VCC=Min., IIN=–18 mA
–0.7
IIH
Input HIGH Current
IIH
Input HIGH Current
IIL
Input LOW Current
IOS
Output Short Circuit
IOFF
Power-Off Disable
20
Max.
V
0.3
0.55
V
25
40
Ω
2.0
V
0.8
Current[8]
Unit
V
V
–1.2
V
VCC=Max., VIN=VCC
5
µA
VCC=Max., VIN=2.7V
±1
µA
VCC=Max., VIN=0.5V
±1
µA
–225
mA
±1
µA
VCC=Max., VOUT=0.0V
VCC=0V, VOUT=4.5V
–60
–120
Notes:
2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.
3. The data output functions may be enabled or disabled by various signals at the G or DIR inputs. Data input functions are always enabled, i.e., data at the bus
pins will be stored on every LOW-to-HIGH transition of the clock inputs.
4. Unless otherwise noted, these limits are over the operating free-air temperature range.
5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
6. Typical values are at VCC=5.0V, TA=+25˚C ambient.
7. This parameter is specified but not tested.
8. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
3
CY74FCT2646T
Capacitance[7]
Parameter
Description
Typ.[6]
Max.
Unit
CIN
Input Capacitance
6
10
pF
COUT
Output Capacitance
8
12
pF
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.[6]
Max.
Unit
ICC
Quiescent Power Supply Current
VCC=Max., VIN≤0.2V,
VIN≥VCC–0.2V
0.1
0.2
mA
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
VCC=Max., VIN=3.4V,[9]
f1=0, Outputs Open
0.5
2.0
mA
ICCD
Dynamic Power Supply Current[10]
VCC=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
G=DIR=GND, GAB=GBA=GND,
VIN≤0.2V or VIN≥VCC–0.2V
0.06
0.12
mA/
MHz
IC
Total Power Supply Current[11]
VCC=Max., f0=10 MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=5 MHz,
G=DIR=GND, GAB=GBA=GND,
VIN≤0.2V or VIN≥VCC–0.2V
0.7
1.4
mA
VCC=Max., f0=10 MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=5 MHz,
G=DIR=GND, GAB=GBA=GND,
VIN=3.4V or VIN=GND
1.2
3.4
mA
VCC=Max., f0=10 MHz,
50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=5 MHz,
G=DIR=GND, GAB=GBA=GND,
VIN≤0.2V or VIN≥VCC–0.2V
2.8
5.6[12]
mA
VCC=Max., f0=10 MHz,
50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=5 MHz,
G=DIR=GND, GAB=GBA=GND,
VIN=3.4V or VIN=GND
5.1
14.6[12]
mA
Notes:
9. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
10. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= IQUIESCENT + IINPUTS + IDYNAMIC
11. IC
IC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
= Duty Cycle for TTL inputs HIGH
DH
= Number of TTL inputs at DH
NT
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Input signal frequency
f1
= Number of inputs changing at f1
N1
All currents are in milliamps and all frequencies are in megahertz.
12. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
4
CY74FCT2646T
Switching Characteristics Over the Operating Range[13]
CY74FCT2646AT
Parameter
Description
CY74FCT2646CT
Min.
Max.
Min.
Max.
Unit
Fig. No.[14]
tPLH
tPHL
Propagation Delay Bus to Bus
1.5
6.3
1.5
5.4
ns
1, 3
tPZH
tPZL
Output Enable Time Enable to
Bus and DIR to An or Bn
1.5
9.8
1.5
7.8
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
G to Bus and DIR to Bus
1.5
6.3
1.5
6.3
ns
1, 7, 8
tPLH
tPHL
Propagation Delay
Clock to Bus
1.5
6.3
1.5
5.7
ns
1, 5
tPLH
tPHL
Propagation Delay
SBA or SAB to A or B
1.5
7.7
1.5
6.2
ns
1, 5
tS
Set-Up Time HIGH or LOW, Bus
to Clock
2.0
2.0
ns
4
tH
Hold Time HIGH or LOW,
Bus to Clock
1.5
1.5
ns
4
tW
Pulse Width,[7]
HIGH or LOW
5.0
5.0
ns
5
Notes:
13. Minimum limits are specified but not tested on Propagation Delays.
14. See “Parameter Measurement Information” in the General Information section.
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
5.4
CY74FCT2646CTQCT
Q13
24-Lead (150-Mil) QSOP
Commercial
6.3
CY74FCT2646ATQCT
Q13
24-Lead (150-Mil) QSOP
Commercial
Document #: 38-00599
5
CY74FCT2646T
Package Diagrams
24-Lead Quarter Size Outline Q13
6
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