ree Lead-Fage P a c k ns Optio le! b Availa Features GAL16LV8 Low Voltage E2CMOS PLD Generic Array Logic™ Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology I/CLK CLK 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q I • 3.3V LOW VOLTAGE 16V8 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — 5V Compatible Inputs — I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C) PROGRAMMABLE AND-ARRAY (64 X 32) I • ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only) • E CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention I • EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity I • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability I 2 I • APPLICATIONS INCLUDE: — Glue Logic for 3.3V Systems — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade I I OE I/OE • ELECTRONIC SIGNATURE FOR IDENTIFICATION • LEAD-FREE PACKAGE OPTIONS Description Pin Configuration PLCC The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. I I I I/CLK Vcc 2 20 I/O/Q 18 4 I/O/Q I The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations. I I/O/Q GAL16LV8 6 16 I/O/Q Top View I/O/Q I Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. I 8 14 9 I GND 11 13 I/OE I/O/Q I/O/Q I/O/Q Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 16lv8_05 1 August 2004 Specifications GAL16LV8 GAL16LV8 Ordering Information Conventional Packaging Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package 3.5 3 2.5 70 GAL16LV8D-3LJ 20-Lead PLCC 5 4 3 70 GAL16LV8D-5LJ 20-Lead PLCC 7.5 6 5 65 GAL16LV8C-7LJ 20-Lead PLCC 10 7 7 65 GAL16LV8C-10LJ 20-Lead PLCC 15 12 10 65 GAL16LV8C-15LJ 20-Lead PLCC Lead-Free Packaging Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package 3.5 3 2.5 70 GAL16LV8D-3LJN 5 4 3 70 GAL16LV8D-5LJN Lead-Free 20-Lead PLCC 7.5 6 5 65 GAL16LV8C-7LJN Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC 10 7 7 65 GAL16LV8C-10LJN Lead-Free 20-Lead PLCC 15 12 10 65 GAL16LV8C-15LJN Lead-Free 20-Lead PLCC Part Number Description XXXXXXXX _ XX X XX X GAL16LV8D Device Name GAL16LV8C Grade Speed (ns) L = Low Power Power Blank = Commercial Package J = PLCC JN = Lead-free PLCC 2 Specifications GAL16LV8 Output Logic Macrocell (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL16LV8. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL16LV8 can emulate. It also shows the OLMC mode under which the GAL16LV8 emulates the PAL architecture. PAL Architectures Emulated by GAL16LV8 GAL16LV8 Global OLMC Mode 16R8 16R6 16R4 16RP8 16RP6 16RP4 Registered Registered Registered Registered Registered Registered 16L8 16H8 16P8 Complex Complex Complex 10L8 12L6 14L4 16L2 10H8 12H6 14H4 16H2 10P8 12P6 14P4 16P2 Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Compiler Support for OLMC as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. Software compilers support the three different global OLMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured ABEL CUPL LOG/iC OrCAD-PLD PLDesigner TANGO-PLD Registered Complex Simple Auto Mode Select P16V8R G16V8MS GAL16V8_R "Registered"1 P16V8R2 G16V8R P16V8C G16V8MA GAL16V8_C7 "Complex"1 P16V8C2 G16V8C P16V8AS G16V8AS GAL16V8_C8 "Simple"1 P16V8C2 G16V8AS3 P16V8 G16V8 GAL16V8 GAL16V8A P16V8A G16V8 1) Used with Configuration keyword. 2) Prior to Version 2.0 support. 3) Supported on Version 1.20 or later. 3 Specifications GAL16LV8 Registered Mode In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Dedicated input or output functions can be implemented as subsets of the I/O function. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register placement. Registered outputs have eight product terms per output. I/Os have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/Os are possible in this mode. CLK Registered Configuration for Registered Mode D XOR - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1 controls common CLK for the registered outputs. - Pin 11 controls common OE for the registered outputs. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. Q Q OE Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 4 Specifications GAL16LV8 Registered Mode Logic Diagram PLCC Package Pinout 1 0 4 8 12 16 20 24 28 2128 PTD 0000 OLMC 0224 19 XOR-2048 AC1-2120 2 0256 OLMC 0480 18 XOR-2049 AC1-2121 3 0512 OLMC 0736 17 XOR-2050 AC1-2122 4 0768 OLMC 0992 16 XOR-2051 AC1-2123 5 1024 OLMC 1248 15 XOR-2052 AC1-2124 6 1280 OLMC 1504 14 XOR-2053 AC1-2125 7 1536 OLMC 1760 13 XOR-2054 AC1-2126 8 1792 OLMC 2016 XOR-2055 AC1-2127 9 2191 SYN-2192 AC0-2193 5 12 OE 11 Specifications GAL16LV8 Complex Mode In the Complex mode, macrocells are configured as output only or I/O functions. signs requiring eight I/Os can be implemented in the Registered mode. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1 and 11 are always available as data inputs into the AND array. Up to six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 12 & 19) do not have input capability. De- The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 13 through Pin 18 are configured to this function. XOR Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 12 and Pin 19 are configured to this function. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 6 Specifications GAL16LV8 Complex Mode Logic Diagram PLCC Package Pinout 1 2128 0 4 8 12 16 20 24 28 PTD 0000 OLMC 19 XOR-2048 AC1-2120 0224 2 0256 OLMC 18 XOR-2049 AC1-2121 0480 3 0512 OLMC 17 XOR-2050 AC1-2122 0736 4 0768 OLMC 16 XOR-2051 AC1-2123 0992 5 1024 OLMC 15 XOR-2052 AC1-2124 1248 6 1280 OLMC 14 XOR-2053 AC1-2125 1504 7 1536 OLMC 13 XOR-2054 AC1-2126 1760 8 1792 OLMC 12 XOR-2055 AC1-2127 2016 9 11 2191 SYN-2192 AC0-2193 7 Specifications GAL16LV8 Simple Mode Pins 1 and 11 are always available as data inputs into the AND array. The center two macrocells (pins 15 & 16) cannot be used as input or I/O pins, and are only available as dedicated outputs. In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of generic output polarity or input choices. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has programmable polarity. Combinatorial Output with Feedback Configuration for Simple Mode Vcc - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. XOR Combinatorial Output Configuration for Simple Mode Vcc - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 15 & 16 are permanently configured to this function. XOR Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 8 Specifications GAL16LV8 Simple Mode Logic Diagram PLCC Package Pinout 1 2128 0 4 8 12 16 20 24 28 PTD 0000 OLMC XOR-2048 AC1-2120 0224 19 2 0256 OLMC XOR-2049 AC1-2121 0480 18 3 0512 OLMC XOR-2050 AC1-2122 0736 17 4 0768 OLMC XOR-2051 AC1-2123 0992 16 5 1024 OLMC XOR-2052 AC1-2124 1248 15 6 1280 OLMC XOR-2053 AC1-2125 1504 14 7 1536 OLMC XOR-2054 AC1-2126 1760 13 8 1792 OLMC XOR-2055 AC1-2127 2016 9 12 11 2191 SYN-2192 AC0-2193 9 Specifications GAL16LV8D Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC ................................... –0.5 to +4.6V Input voltage applied ................................ –0.5 to +5.6V I/O voltage applied ................................... –0.5 to +4.6V Off-state output voltage applied ............... –0.5 to +4.6V Storage Temperature ................................ –65 to 150°C Ambient Temperature with Power Applied ........................................ –55 to 125°C Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75°C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL1 IIH VOL VOH MIN. TYP.3 MAX. UNITS Input Low Voltage Vss – 0.3 — 0.8 V Input High Voltage 2.0 — 5.25 V I/O High Voltage 2.0 — Vcc+0.5 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA Input or I/O High Leakage Current (Vcc-0.2)V ≤ VIN ≤ VCC — — 10 µA Input High Leakage Current Vcc ≤ VIN ≤ 5.25V — — 10 µA I/O High Leakage Current Vcc ≤ VIN ≤ 4.6V — — 20 mA Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V IOL = 500µA Vin = VIL or VIH — — 0.2 V IOH = MAX. Vin = VIL or VIH 2.4 — — V Vcc-0.2V — — V Low Level Output Current — — 8 mA High Level Output Current — — –8 mA –15 — –80 mA — 45 70 mA Output High Voltage IOH = -100µA Vin = VIL or VIH IOL IOH IOS2 Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current VCC = 3.3V VOUT = 0.5V TA= 25°C VIL = 0V VIH = 3.0V Unused Inputs at VIL ftoggle = 1MHz Outputs Open 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and TA = 25 °C 10 Specifications GAL16LV8D AC Switching Characteristics Over Recommended Operating Conditions PARAMETER tpd2 tco2 tcf3 tsu th fmax4 twh4 twl4 ten tdis 1) 2) 3) 4) TEST COND1. COM COM -3 -5 DESCRIPTION UNITS MIN. MAX. MIN. MAX. A Input or I/O to Combinational Output 1 3.5 1 5 ns A Clock to Output Delay 1 2.5 1 3 ns — Clock to Feedback Delay — 2 — 2 ns — Setup Time, Input or Feedback before Clock↑ 3 — 4 — ns — Hold Time, Input or Feedback after Clock↑ 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 180 — 142.8 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 200 — 166 — MHz A Maximum Clock Frequency with No Feedback 250 — 166 — MHz — Clock Pulse Duration, High 2 — 3 — ns — Clock Pulse Duration, Low 2 — 3 — ns B Input or I/O to Output Enabled — 4.5 — 6 ns B OE to Output Enabled — 3.5 — 5 ns C Input or I/O to Output Disabled — 4.5 — 6 ns C OE to Output Disabled — 3.5 — 5 ns Refer to Switching Test Conditions section. Minimum values for tpd and tco are not 100% tested but established by characterization. Calculated from fmax with internal feedback. Refer to fmax Descriptions section. Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CI Input Capacitance 5 pF VCC = 3.3V, VI = 0V CI/O I/O Capacitance 5 pF VCC = 3.3V, VI/O = 0V 11 Specifications GAL16LV8C Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC ................................... –0.5 to +5.6V Input voltage applied ................................ –0.5 to +5.6V Off-state output voltage applied ............... –0.5 to +5.6V Storage Temperature ................................ –65 to 150°C Ambient Temperature with Power Applied ........................................ –55 to 125°C Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75°C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IOS1 MIN. TYP.2 MAX. UNITS Input Low Voltage Vss – 0.5 — 0.8 V Input High Voltage 2.0 — 5.25 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -10 µA Input or I/O High Leakage Current (VCC - 0.2)V ≤ VIN ≤ VCC — — 10 µA VCC ≤ VIN ≤ 5.25V — — 30 mA IOL = MAX. Vin = VIL or VIH — — 0.4 V IOL = 500 µA Vin = VIL or VIH — — 0.2 V IOH = MAX. Vin = VIL or VIH 2.4 — — V IOH = -500 µA Vin = VIL or VIH Vcc-0.45 — — V IOH = -100 µA Vin = VIL or VIH Vcc-0.2 — — V Low Level Output Current — — 8 mA High Level Output Current — — -4 mA -10 — -60 mA — 45 65 mA Output Low Voltage Output High Voltage Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current VIL = 0.0V VCC = 3.3V VIH = 3.0V VOUT = 0.5V TA = 25°C ftoggle = 1MHz Outputs Open 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and TA = 25 °C 12 Specifications GAL16LV8C AC Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) PARAMETER tpd2 tco2 tcf3 tsu th fmax4 twh twl ten tdis TEST COND1. COM COM COM -7 -10 -15 DESCRIPTION UNITS MIN. MAX. MIN. MAX. MIN. MAX. A Input or I/O to Combinational Output 1 7.5 1 10 1 15 ns A Clock to Output Delay 1 5 1 7 1 10 ns — Clock to Feedback Delay — 4 — 5 — 8 ns — Setup Time, Input or Feedback before Clock↑ 6 — 7 — 12 — ns — Hold Time, Input or Feedback after Clock↑ 0 — 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 90.9 — 71.4 — 45.5 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 100 — 83.3 — 50 — MHz A Maximum Clock Frequency with No Feedback 100 — 83.3 — 62.5 — MHz — Clock Pulse Duration, High 5 — 6 — 8 — ns — Clock Pulse Duration, Low 5 — 6 — 8 — ns B Input or I/O to Output Enabled — 9 — 10 — 15 ns B OE to Output Enabled — 6 — 8 — 15 ns C Input or I/O to Output Disabled — 9 — 10 — 15 ns C OE to Output Disabled — 6 — 8 — 15 ns 1) Refer to Switching Test Conditions section. 2) Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 3.3V, VI = 0V CI/O I/O Capacitance 8 pF VCC = 3.3V, VI/O = 0V 13 Specifications GAL16LV8 Switching Waveforms INPUT or I/O FEEDBACK VALID INPUT tsu th CLK INPUT or I/O FEEDBACK VALID INPUT tco REGISTERED OUTPUT tpd COMBINATIONAL OUTPUT 1/fmax (external fdbk) Combinatorial Output Registered Output INPUT or I/O FEEDBACK OE tdis ten tdis COMBINATIONAL OUTPUT ten REGISTERED OUTPUT Input or I/O to Output Enable/Disable twh OE to Output Enable/Disable twl CLK 1/ fmax (internal fdbk) CLK tcf 1/ fmax (w/o fb) REGISTERED FEEDBACK Clock Width fmax with Feedback 14 tsu Specifications GAL16LV8 fmax Descriptions CL K LOGIC ARR AY CLK R EG I S T E R LOGIC ARRAY ts u REGISTER tc o fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. t cf t pd CLK fmax with Internal Feedback 1/(tsu+tcf) LOGIC ARRAY Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. REGISTER tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 15 Specifications GAL16LV8 GAL16LV8D: Switching Test Conditions Input Pulse Levels GND to 3.0V Input Rise and Fall Times 1.5ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load +1.45V See Figure TEST POINT R1 GAL16LV8D Output Load Conditions (see figure) Test Condition A B C High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V R1 CL 50Ω 50Ω 50Ω 50Ω 50Ω 35pF 35pF 35pF 35pF 35pF FROM OUTPUT (O/Q) UNDER TEST Z0 = 50Ω, CL = 35pF* *CL INCLUDES TEST FIXTURE AND PROBE CAPACITANCE GAL16LV8C: Switching Test Conditions Input Pulse Levels +3.3V GND to 3.0V Input Rise and Fall Times 1.5ns 10% – 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels R1 1.5V Output Load See Figure FROM OUTPUT (O/Q) UNDER TEST 3-state levels are measured 0.5V from steady-state active level. GAL16LV8C Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low TEST POINT R2 R1 R2 CL 316Ω 316Ω 316Ω 316Ω 316Ω 348Ω 348Ω 348Ω 348Ω 348Ω 35pF 35pF 35pF 5pF 5pF C L* *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 16 Specifications GAL16LV8 Electronic Signature Output Register Preload An electronic signature is provided in every GAL16LV8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum. Security Cell GAL16LV8 devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. A security cell is provided in the GAL16LV8 devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Input Buffers GAL16LV8 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. Latch-Up Protection GAL16LV8 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. The GAL16LV8D input and I/O pins have built-in active pull-ups. As a result, unused inputs and I/O's will float to a TTL "high" (logical "1"). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, VCC, or Ground. Doing this will tend to improve noise immunity and reduce ICC for the device. Device Programming GAL devices are programmed using a Lattice Semiconductor-approved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. Typical Input Pull-up Characteristic (GAL16LV8D) 0 I nput Current (µA) -10 -20 -30 -40 -50 -60 -70 Input Voltage (V) 17 4 3.5 3 2.5 2 1.5 1 0.5 0 -80 Specifications GAL16LV8 Power-Up Reset Vcc Vcc (min.) t su t wl CLK t pr INTERNAL REGISTER Q - OUTPUT Internal Register Reset to Logic "0" FEEDBACK/EXTERNAL OUTPUT REGISTER Device Pin Reset to Logic "1" conditions must be met to provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Circuitry within the GAL16LV8 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1µs MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some Input/Output Equivalent Schematics PIN PIN Feedback Vcc Active Pull-up Circuit (GAL16LV8D Only) Active Pull-up Circuit (GAL16LV8D Only) Vcc Vref Tri-State Control Vcc ESD Protection Circuit Vcc Vref Data Output PIN PIN ESD Protection Circuit Feedback (To Input Buffer) Typ. Vref = Vcc Typ. Vref = Vcc Typical Input Typical Output 18 Specifications GAL16LV8 GAL16LV8D: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.05 1.05 PT L->H 1 0.95 0.9 3.00 3.15 3.30 3.45 RISE 1.025 FALL 1 0.975 0.95 3.00 3.60 Normalized Tsu PT H->L Normalized Tco 3.15 Supply Voltage (V) 3.30 3.45 Normalized Tpd vs Temp 1 0.9 0.8 0.7 -25 0 25 50 75 100 RISE 1.1 FALL 1 0.95 PT L->H 1.15 1.1 1.05 1 0.9 -55 -25 0 25 50 75 100 -55 125 -25 0 0 -0.1 -0.2 RISE -0.3 FALL -0.4 -0.05 -0.1 -0.15 -0.2 RISE -0.25 FALL -0.3 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 22 18 RISE 14 FALL Delta Tco (ns) 22 10 6 2 -2 18 RISE 14 FALL 10 6 2 -2 -6 -6 0 50 100 150 200 250 300 0 Output Loading (pF) 50 100 150 200 250 Output Loading (pF) 19 25 50 75 100 Temperature (deg. C) Delta Tco vs # of Outputs Switching 0 Delta Tpd (ns) PT H->L 1.2 Temperature (deg. C) 2 3.60 0.95 Delta Tpd vs # of Outputs Switching 1 3.45 1.25 1.05 125 3.30 1.3 1.15 Temperature (deg. C) Delta Tpd (ns) 3.15 Normalized Tsu vs Temp 0.9 -55 0.9 Supply Voltage (V) Normalized Tsu PT L->H Normalized Tco 1.1 1 0.8 3.00 3.60 1.2 PT H->L PT L->H Normalized Tco vs Temp 1.3 1.2 PT H->L 1.1 Supply Voltage (V) Delta Tco (ns) Normalized Tpd 1.1 Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 300 125 Specifications GAL16LV8 GAL16LV8D: Typical AC and DC Characteristic Diagrams Vol vs Iol Voh vs Ioh Voh vs Ioh 3 2.25 3 2 2.5 2.95 1.25 1 0.75 2 Voh (V) 1.5 Voh (V) Vol (V) 1.75 1.5 1 2.9 2.85 0.5 0.5 0.25 0 0.00 10.00 20.00 30.00 0 0.00 40.00 5.00 10.00 Iol (mA) 0.95 0.90 3.30 3.45 1.1 1 0.9 3.60 Supply Voltage (V) -25 0 25 50 75 100 125 Temperature (deg. C) 0 5 Iik (mA) 10 6 4 15 20 25 2 30 0.50 1.00 1.50 2.00 Vin (V) 2.50 3.00 3.50 1.03 1.00 0.98 35 -2.00 -1.50 -1.00 Vik (V) 20 -0.50 0 25 50 75 Frequency (MHz) Input Clamp (Vik) Delta Icc vs Vin (1 input) 8 4.00 0.95 -55 10 3.00 1.05 0.8 3.15 2.00 Normalized Icc vs Freq. Normalized Icc Normalized Icc 1.00 0.85 3.00 1.00 Ioh(mA) 1.2 1.05 0 0.00 2.8 0.00 25.00 Normalized Icc vs Temp 1.10 Normalized Icc 20.00 Ioh(mA) Normalized Icc vs Vcc Delta Icc (mA) 15.00 0.00 100 Specifications GAL16LV8 GAL16LV8C: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.1 1.1 PT L->H 1 0.9 0.8 3.00 3.15 3.30 3.45 RISE 1.05 FALL 1 0.95 0.9 3.00 3.60 3.15 Supply Voltage (V) Normalized Tpd vs Temp 3.30 3.45 PT H->L 1.1 PT L->H 1 0.9 0.8 0.7 0 25 50 75 100 RISE 1.1 FALL 1 0.9 0.8 -25 0 25 50 75 Delta Tpd (ns) PT L->H 1.1 1 0.9 100 125 -55 -25 0 0 0 -0.05 -0.1 -0.15 -0.2 RISE -0.25 FALL -0.3 -0.05 -0.1 -0.15 -0.2 RISE -0.25 FALL -0.3 4 5 6 7 8 1 2 3 4 5 6 7 8 Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 34 34 30 30 26 Delta Tco (ns) RISE FALL 22 18 14 10 6 2 -2 RISE 26 22 FALL 18 14 10 6 2 -2 -6 -6 0 50 100 150 200 250 300 0 Output Loading (pF) 50 100 150 200 250 Output Loading (pF) 21 25 50 75 100 Temperature (deg. C) Delta Tco vs # of Outputs Switching 0.05 3 3.60 PT H->L 1.2 Temperature (deg. C) 2 3.45 0.8 -55 Delta Tpd vs # of Outputs Switching 1 3.30 1.3 Temperature (deg. C) Delta Tpd (ns) 3.15 Normalized Tsu vs Temp 1.2 125 0.9 Normalized Tco vs Temp Delta Tco (ns) -25 1 Supply Voltage (V) 0.7 -55 PT L->H Supply Voltage (V) Normalized Tsu 1.2 PT H->L 1.1 0.8 3.00 3.60 1.3 Normalized Tco 1.3 Normalized Tsu PT H->L Normalized Tco Normalized Tpd 1.2 Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 300 125 Specifications GAL16LV8 GAL16LV8C: Typical AC and DC Characteristic Diagrams Vol vs Iol Voh vs Ioh Voh (V) Vol (V) 0.8 0.6 0.4 4 3 3 2.9 Voh (V) 1 2 1 0.2 0 5.00 10.00 15.00 20.00 25.00 30.00 35.00 2.6 0.00 2.00 4.00 Iol (mA) 6.00 8.00 10.00 12.00 14.00 1.00 0.90 0.80 1.2 1.1 1 0.9 0.8 3.30 3.45 Supply Voltage (V) -25 0 25 50 75 100 125 Temperature (deg. C) 0 20 8 Iik (mA) Delta Icc (mA) 10 10 6 4 30 40 50 60 70 2 80 0.50 1.00 1.50 2.00 Vin (V) 2.50 3.00 3.50 1.60 1.40 1.20 90 -3.00 -2.50 -2.00 -1.50 -1.00 Vik (V) 22 -0.50 0 25 50 75 Frequency (MHz) Input Clamp (Vik) Delta Icc vs Vin (1 input) 12 4.00 1.00 -55 3.60 3.00 1.80 Normalized Icc Normalized Icc 1.10 2.00 Normalized Icc vs Freq. 1.3 3.15 1.00 Ioh (mA) Normalized Icc vs Temp 1.20 0 0.00 0.00 Ioh (mA) Normalized Icc vs Vcc 3.00 2.8 2.7 0 0.00 Normalized Icc Voh vs Ioh 0.00 100