Cypress CY7C235A-25JC 1k x 8 registered prom Datasheet

1CY 7C23 5A
CY7C235A
1K x 8 Registered PROM
Features
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static discharge
• CMOS for optimum speed/power
• High speed
Functional Description
— 18 ns address set-up
The CY7C235A is a high-performance 1024 word by 8 bit electrically programmable read only memory packaged in a slim
300-mil plastic or hermetic DIP, 28-pin leadless chip carrier, or
28-pin plastic leaded chip carrier. The memory cells utilize
proven EPROM floating gate technology and byte-wide intelligent programming algorithms.
— 12 ns clock to output
• Low power
— 495 mW (commercial)
— 660 mW (military)
• Synchronous and asynchronous output enables
The CY7C235A replaces bipolar devices pin for pin and offers
the advantages of lower power, superior performance, and
high programming yield. The EPROM cell requires only 12.5V
for the supervoltage, and low current requirements allow for
gang programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that the
product will meet AC specification limits after customer programming.
• On-chip edge-triggered registers
• Programmable asynchronous registers (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP or 28-pin
LCC and PLCC
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
Logic Block Diagram
Pin Configuration
DIP
Top View
INIT
O7
A9
O6
A8
ROW
ADDRESS
A7
PROGRAMMABLE
ARRAY
MULTIPLEXER
O5
8-BIT
EDGETRIGGERED
REGISTER
A6
A5
ADDRESS
DECODER
A4
O4
O3
A3
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
E
INIT
ES
CP
O7
O6
O5
O4
O3
C235A-2
A2
O2
COLUMN
ADDRESS
A1
LCC/PLCC
Top View
O1
A0
O0
CP
CP
ES
C235A-1
E
A4
A3
A2
A1
A0
NC
O0
4 3 2 1 28 27 26
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12 1314151617 18
E
INIT
ES
CP
NC
O7
O6
C235A-3
Selection Guide
7C235A-18
18
12
90
Minimum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating
Commercial
Current (mA)
Military
Cypress Semiconductor Corporation
•
3901 North First Street
7C235A-25
25
12
90
120
•
7C235A-30
30
15
90
120
7C235A-40
40
20
90
120
San Jose •
CA 95134 •
408-943-2600
November 1992 – Revised March 1995
CY7C235A
Maximum Ratings
DC Program Voltage (Pins 7, 18, 20 for DIP) ............... 13.0V
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current ..................................................... >200 mA
Storage Temperature ..................................... −65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12 for DIP) .................................. − 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .................................................... − 0.5V to +7.0V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ±10%
−40°C to +85°C
5V ±10%
− 55°C to +125°C
5V ±10%
Industrial
[1]
Military[2]
DC Input Voltage .................................................−3.0V to +7.0V
Electrical Characteristics Over Operating Range[3]
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VIN = VIH or VIL
VOL
Output LOW Voltage
VCC = Min., IOL = 16 mA
VIN = VIH or VIL
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All
Inputs[4]
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All
Inputs[4]
IIX
Input Leakage Current
GND < VIN < VCC
VCD
Input Clamp Diode Voltage
Note 5
IOZ
Output Leakage Current
GND < VOUT < VCC Output Disabled[4]
IOS
Output Short Circuit Current
VCC = Max., VOUT =
ICC
Power Supply Current
IOUT = 0 mA,
VCC = Max.
VPP
Programming Supply Voltage
IPP
Programming Supply Current
VIHP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
Max.
Unit
2.4
V
0.4
V
2.0
V
0.8
V
−10
+10
µA
−10
+10
µA
−20
−90
mA
Commercial
90
mA
Military
120
0.0V[6]
12
13
V
50
mA
3.0
V
0.4
V
Capacitance[5]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC =5.0V
Max.
10
10
Unit
pF
pF
Notes:
1.
2.
3.
4.
5.
6.
Contact a Cypress representative for industrial temperature range specifications.
TA is the “instant on” case temperature.
See the last page of this specification for Group A subgroup testing information.
For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
See Introduction to CMOS PROMs in this Data Book for general information on testing.
For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
a
2
CY7C235A
AC Test Loads and Waveforms[5]
R1 250Ω
5V
R1 250Ω
5V
OUTPUT
50pF
R2
167Ω
(a) Normal Load
Equivalent to:
5 pF
INCLUDING
JIGAND
SCOPE
INCLUDING
JIGAND
SCOPE
ALL INPUT PULSES
3.0V
OUTPUT
R2
167Ω
90%
10%
GND
≤ 5 ns
C235A-4
90%
10%
≤ 5 ns
C235A-5
(b) High Z Load
THÉVENIN EQUIVALENT
100Ω
OUTPUT
2.0V
C235A-6
System timing is simplified in that the on-chip edge-triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
Operating Modes
The CY7C235A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined microprogrammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with synchronous (ES) and asynchronous (E) output
enables and asynchronous initialization (INIT).
The CY7C235A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophisticated functions such as a built-in “jump start” address. When
activated the initialize control input causes the contents of a
user programmed 1025th 8-bit word to be loaded into the
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the register. In the unprogrammed state, activating
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are programmed, activating INIT
performs a register PRESET (all outputs HIGH).
Upon power-up, the synchronous enable (ES) flip-flop will be
in the set condition causing the outputs (O0 − O7) to be in the
OFF or high-impedance state. Data is read by applying the
memory location to the address input (A0 − A9) and a logic
LOW to the enable (ES) input. The stored data is accessed and
loaded into the master flip-flops of the data register during the
address set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which
drive the output buffers, and the accessed data will appear at
the outputs (O0 − O 7), provided the asynchronous enable (E)
is also LOW.
Applying a LOW to the INIT input causes an immediate load of
the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs, including the clock (CP). The initialize data will appear at the device
outputs after the outputs are enabled by bringing the asynchronous enable (E) LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be returned to the active state by switching the enable to a logic
LOW.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge after the synchronous enable (ES) input is switched to a HIGH
level. If the synchronous enable pin is switched to a logic LOW,
the subsequent positive clock edge will return the output to the
active state if E is LOW. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature allows the CY7C235A decoders and sense amplifiers to access
the next location while previously addressed data remains stable on the outputs.
When power is applied the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in the
high-impedance state. In order to enable the outputs, a clock
must occur and the ES input pin must be LOW at least a set-up
time prior to the clock LOW-to-HIGH transition. The E input
may then be used to enable the outputs.
When the asynchronous initialize input, INIT, is LOW, the data
in the initialize byte will be asynchronously loaded into the output register. It will not, however, appear on the output pins until
they are enabled, as described in the preceding paragraph.
3
CY7C235A
Switching Characteristics Over Operating Range[3, 5]
Parameter
Description
7C235A-18
7C235A-25
7C235A-30
7C235A-40
Min.
Min.
Min.
Min.
Max.
Max.
25
Max.
30
Max.
tSA
Address Set-Up to Clock HIGH
18
tHA
Address Hold from Clock HIGH
0
tCO
Clock HIGH to Valid Output
tPWC
Clock Pulse Width
12
12
15
20
ns
tSES
ES Set-Up to Clock HIGH
10
10
10
15
ns
tHES
ES Hold from Clock HIGH
5
tDI
Delay from INIT to Valid Output
tRI
INIT Recovery to Clock HIGH
15
tPWI
INIT Pulse Width
15
tCOS
Inactive to Valid Output from Clock HIGH[7]
0
0
12
12
5
25
20
ns
20
5
25
20
20
ns
0
15
5
20
HIGH[7]
40
Unit
ns
35
20
20
ns
ns
ns
25
ns
15
20
20
25
ns
15
20
20
25
ns
tHZC
Inactive Output from Clock
tDOE
Valid Output from E LOW
15
20
20
25
ns
tHZE
Inactive Output from E HIGH
15
20
20
25
ns
Notes:
7. Applies only when the synchronous (ES) function is used.
Switching Waveforms[5]
tHA
tSA
tHA
tHES
tSES
tHES
A0 − A10
ES
tSES
CP
tPWC
O0 − O7
tCO
tHES
tPWC
tHZC
tSES
tPWC
tPWC
tPWC
tCOS
tPWC
tCO
tHZE
tDOE
E
tDI
tRI
INIT
C235A-7
tPWI
Programming Information
programming information, including a listing of software packages, please see the PROM Programming Information located
at the end of this section. Programming algorithms can be obtained from any Cypress representative.
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
4
CY7C235A
Table 1. Mode Selection.
Pin Function[8]
Read or Output Disable
A0, A3 − A9
A1
A2
CP
ES
E
INIT
O7 − O0
Other
A0, A3 − A9
A1
A2
PGM
VFY
E
VPP
D7 − D0
Read
A0, A3 − A9
A1
A2
X
VIL
VIL
VIH
O7 − O0
Output Disable
A0, A3 − A9
A1
A2
X
VIH
X
VIH
High Z
Output Disable
A0, A3 − A9
A1
A2
X
X
VIH
VIH
High Z
Initialize
A0, A3 − A9
A1
A2
X
X
VIL
VIL
Init Byte
Program
A0, A3 − A9
A1
A2
VILP
VIHP
VIHP
VPP
D7 − D0
Program Verify
A0, A3 − A9
A1
A2
VIHP
VILP
VIHP
VPP
O7 − O0
Program Inhibit
A0, A3 − A9
A1
A2
VIHP
VIHP
VIHP
VPP
High Z
Intelligent Program
A0, A3 − A9
A1
A2
VILP
VIHP
VIHP
VPP
D7 − D0
Program Initialize Byte
A0, A3 − A9
VPP
VILP
VILP
VIHP
VIHP
VPP
D7 − D0
Blank Check
A0, A3 − A9
A1
A2
VIHP
VILP
VIHP
VPP
Zeros
Mode
Notes:
8. X = “don’t care” but not to exceed VCC ±5%.
DIP
Top View
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LCC/PLCC
Top View
VCC
A8
A9
E
VPP
VFY
PGM
D7
D6
D5
D4
D3
A4
A3
A2
A1
A0
NC
D0
4 3 2 1 28 27 26
25
24
23
22
21
20
19
121314151617 18
5
6
7
8
9
10
11
E
VPP
VFY
PGM
NC
D7
D6
C235A-9
C235A-8
Figure 1. Programming Pinouts.
5
CY7C235A
Typical DC and AC Characteristics
1.6
CLOCK TO OUTPUT TIME
vs. VCC
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
1.4
1.4
1.1
1.2
1.2
1.0
1.0
1.0
0.9
TA =25°C
f = fMAX
0.8
0.6
4.0
4.5
5.0
5.5
0.8
TA =25°C
6.0
0.8
−55
25
125
0.6
4.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
NORMALIZED SET-UP TIME
vs. SUPPLY VOLTAGE
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.6
1.2
1.6
1.4
1.0
1.4
1.2
1.2
0.8
1.0
1.0
0.6
0.8
0.8
TA =25°C
0.6
−55
25
125
0.4
4.0
AMBIENT TEMPERATURE (°C)
5.0
5.5
6.0
VCC =5.5V
TA =25°C
0.98
125
25
AMBIENT TEMPERATURE (°C)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
175
30.0
1.00
0.6
−55
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
1.02
4.5
150
25.0
125
20.0
100
0.96
15.0
0.94
10.0
0.92
0
25
50
75
CLOCK PERIOD (ns)
100
0.0
VCC =5.0V
TA =25°C
50
TA =25°C
VCC =4.5V
5.0
0.90
0.88
75
0
200
400
600
800 1000
CAPACITANCE (pF)
25
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
C235A-10
6
CY7C235A
Ordering Information[9]
Speed
(ns)
tSA tCO
Ordering Code
18
12 CY7C235A-18DC
CY7C235A-18JC
CY7C235A-18PC
25
12 CY7C235A-25DC
CY7C235A-25JC
CY7C235A-25PC
CY7C235A-25DMB
CY7C235A-25LMB
30
15 CY7C235A-30DC
CY7C235A-30JC
CY7C235A-30PC
CY7C235A-30DMB
CY7C235A-30LMB
40
20 CY7C235A-40DC
CY7C235A-40JC
CY7C235A-40PC
CY7C235A-40DMB
CY7C235A-40LMB
Package
Name
D14
J64
P13
D14
J64
P13
D14
L64
D14
J64
P13
D14
L64
D14
J64
P13
D14
L64
Package Type
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
Notes:
9. Most of the above products are available in industrial temperature range. Contact a Cypress representative
for specifications and product availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
tSA
tHA
tCO
DC Characteristics
Parameter
VOH
VOL
VIH
VIL
IIX
IOZ
ICC
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Document #: 38-00229-C
7
CY7C235A
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835
28-Lead Plastic Leaded Chip Carrier J64
D-9 Config.A
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
8
CY7C235A
Package Diagrams (Continued)
24-Lead (300-Mil) Molded DIP P13/P13A
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.