AN1048 Application note ST7 software LCD driver Introduction This note describes a technique for driving Liquid Crystal Displays (LCD) with any standard ST7 Microcontroller (MCU) i.e without any specific on-chip LCD driver hardware. This technique offers a solution for applications which require a display at low cost together with the versatile capabilities of the standard ST7 MCUs. This note also provides a technique to control the LCD contrast through software. After an introduction on LCDs in Section 1, Section 2 & 3 of this note describes the typical waveforms required to drive an LCD with a multiplexing rate of 1 or 2 (duplex) and 4 (quadruplex). Section 3 presents a solution based on a standard ST7 MCU directly driving a quadruplex LCD. This solution can be implemented with any ST7 MCU as it only requires the standard I/O ports and one timer, both of which are standard features on all ST7 MCUs. Section 4 describes how to control the contrast through software. Finally, Section 5 gives a brief overview of the LCD demo board including the board schematics. The demo board, based on a ST72F321B microcontroller, allows the user to develop and test applications using an LCD device. The program size (~300 bytes), the CPU load required for controlling the LCD (0.2%), and the number of external components is kept to the minimum (two external resistors per COM line). The number of I/O’s is the same as a solution using an on-chip LCD hardware driver or an external hardware LCD driver. With software contrast control, it is a very flexible solution that can be adapted easily to a range of applications. May 2006 Rev 5 1/21 www.st.com Contents AN1048 Contents 1 LCD requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 LCD drive signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Single backplane LCD drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Duplexed LCD drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Quadruplex LCD drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.1 LCD mean voltage calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.2 Contrast calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Example of a quadruplex LCD with ST72F321B . . . . . . . . . . . . . . . . . . 11 4 Software contrast control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 5 6 2/21 Contrast calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LCD demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 Oscillation system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AN1048 1 LCD requirements LCD requirements 2 With a low Root Mean Square (RMS i.e.: Mean ( Signal ) ) voltage applied to it, an LCD is practically transparent. The LCD segment is inactive(OFF) if the RMS voltage is below the LCD threshold voltage and is active(ON) if the LCD RMS voltage is above the threshold voltage. The LCD threshold voltage depends on the quality of the liquid used in the LCD and the temperature. The optical contrast is defined by the difference in transparency of a LCD segment ON (dark) and a LCD segment OFF (transparent). The optical contrast depends on the difference between the RMS voltage on an ON segment (VON) and the RMS voltage on an OFF segment (VOFF). The higher the difference between VON(rms) and VOFF(rms), the higher the optical contrast. The optical contrast also depends on the level of VON versus the LCD threshold voltage. If VON is below or close to the threshold voltage, the LCD is completely or almost transparent. If VOFF is close or above the threshold voltage, the LCD is completely dark. In this document, contrast is defined as D = VON(rms) / VOFF(rms). The applied LCD voltage must alternate to give a zero DC value in order to ensure a long LCD life time. The higher the multiplexing rates, the lower the contrast. The signal period has also to be short enough to avoid visible flickering on the display. The LCD voltage for each segment is equal to the difference between the S and COM voltages (see Figure 1). Figure 1. Equivalent Electrical Schematic of an LCD Segment C S Rs COM Note: The DC Value should never be more than 100mV (refer to the LCD manufacturer’s datasheet). Otherwise the life time can be shortened. The frequency range is 30 - 200Hz typically. If it is less, it flickers; if it is more, the power consumption increases. 3/21 LCD drive signals AN1048 2 LCD drive signals 2.1 Single backplane LCD drive In a single backplane drive, each LCD segment is connected to a segment line(Sx) and to one backplane(common line) common to all the segments. A display using S segments is driven with S+1 MCU output lines. The backplane is driven with a “COM” signal controlled between 0 and VDD with a duty cycle of 50%. When switching a segment “ON”, a signal with opposite polarity to “COM” is sent to the corresponding “Segment” pin. When the non-inverted signal “COM” is sent to the “Segment” pin, the segment is “OFF”. Using an MCU, the I/O operates in output mode either at logic 0 or 1. Figure 2. LCD signals for direct drive COM +Vdd S +Vdd S1=COM-S +Vdd O F F S +Vdd S1=COM-S +Vdd O N -Vdd 2.2 Duplexed LCD drive In a duplexed drive, two backplanes are used instead of one. Each LCD segment line(Sx) is connected to two LCD segments, each one connected on the other side to one of the two backplanes or common lines(refer to Figure 3). Thus, only (S/2)+2 MCU pins are necessary to drive an LCD with S segments. Three different voltage levels have to be generated on the backplanes: 0, VDD/2 and VDD. The “Segment” voltage levels are 0 and VDD only. Figure 4 shows typical Backplane, Segment and LCD waveforms. The intermediate voltage VDD/2 is only required for the Backplane voltages. The ST7 I/O pins selected as “Backplanes” are set by software to output mode for 4/21 AN1048 LCD drive signals 0 or VDD levels and to high impedance input mode for VDD/2. When one backplane is active, the other one is neutralised by applying VDD/2 to it. This VDD/2 voltage is defined by two resistors of equal value, externally connected to the I/O pin. By using an MCU with flexible I/O pin configuration, a duplexed LCD drive can be implemented with only 2 external resistors bridge (each on two com lines). Figure 3. Basic LCD Segment Connection in duplexed mode S1 S11 S2 S3 S12 COM1 COM2 Figure 4. LCD signals for duplexed mode (used in the ST7 example) COM1 +Vdd +Vdd/2 COM2 +Vdd +Vdd/2 S1 +Vdd CASE1 CASE2 CASE3 CASE4 S11=COM1-S1 +Vdd +Vdd/2 -Vdd/2 -Vdd SEGMENT1 OFF ON OFF ON ON ON OFF OFF S12=COM2-S1 +Vdd +Vdd/2 -Vdd/2 -Vdd SEGMENT2 5/21 LCD drive signals 2.3 AN1048 Quadruplex LCD drive In a quadruplex LCD drive, four backplanes are used. Each LCD pin is connected to four LCD segments, with each segment connected on the other side to one of the four backplanes. Thus, only (S/4)+4 MCU pins are necessary to drive an LCD with S segments. For example: to drive an LCD with 128 segments (32 x4), only 36 I/O ports are required (32 I/O ports to drive the segments, 4 I/O ports to drive the backplanes). Three different voltage levels have to be generated on the common lines: 0, VDD/2, VDD. The Segment line voltage levels are 0 and VDD only. The LCD segment is inactive if the RMS voltage is below the LCD threshold voltage and is active if the LCD RMS voltage is above the threshold. Figure 6 shows typical Backplane, Segment and LCD waveforms. The intermediate voltage VDD/2 is only required for Backplane voltages. The MCU I/O pins selected as “Backplanes” are set by software to output mode for 0 or VDD levels and to the high impedence input mode for VDD/2. The VDD/2 voltage is defined by two resistors of equal value, externally connected to the I/O pins. When one backplane or COM is active, the other ones are neutralized by applying VDD/2 to them. Figure 5. Basic LCD Segment Connection in Quadruplexed Mode S1 S11 S12 S13 COM1 COM2 COM3 COM4 6/21 S14 S2 S3 AN1048 LCD drive signals Figure 6. LCD timing diagram for Quadruplex Mode Single Frame Period Vcom Control Period Vdd/2 COM1 T/8 T/4 T/2 3T/8 T COM2 COM3 COM4 Vsegx Seg x_1 ON Segx_2 Off Segx_3 ON Segx_4 Off Vseg-Vcom Vsegx-Vcom1 Vsegx-Vcom4 7/21 LCD drive signals AN1048 Figure 7. LCD Timing Diagram for a single segment Vsegx Segx Vsegx Segx_1 (ON) Vcom1 Segx_1(off) 2.3.1 LCD mean voltage calculation The LCD mean voltage must be very close to zero to guarantee long life to the LCD. The LCD mean voltage for ON and OFF periods can be calculated as: Vmean(ON) = 1/8 Vseg + 1/8 (-Vcom) + 3(Vseg - Vr/2) + 3(-Vr/2) ----(1) Vmean(Off) = 3(Vseg/2) + 3(-Vr/2) -----(2) Vmean(ON) and Vmean(Off) assume identical periods for each phase. From eqn (1) & (2), to get Vmean(ON) and Vmean(Off) = zero Vseg = Vcom = Vr = Vcc Where: Vcom = Max voltage on COM line Vr/2 = Voltage in the middle of the resistor bridge applied on the COM line Vseg = Max voltage on Segx line Vcc = Microcontroller power supply 8/21 AN1048 2.3.2 LCD drive signals Contrast calculation The performance of an LCD driving system is defined by the contrast: Contrast(D) = Vrms(ON) / Vrms(Off) For the quadruplex signal as described on the previous page: Vrms ( ON ) = T 2 1 --- ∫ f ( t ) dt T 0 2T ------8 T --8 Vrms ( ON ) = T 2 2 Vcc 2 1 --- ∫ ( Vcc ) dt + ∫ ( Vcc ) dt + ∫ ⎛ ----------⎞ dt ⎝ 2 ⎠ T 0 T 2T --------8 8 Vrms ( ON ) = Vrms ( ON ) = 2 ⎞ 1⎛ 2 2 Vcc ) - ⋅ ( 6T ) ⁄ 8⎟ --- ⎜ ( Vcc ) ⋅ T--- + ( Vcc ) ⋅ T--- + (-----------------4 8 8 T⎝ ⎠ 2 7 ------ ( Vcc ) 16 Vrms ( ON ) = 0.661Vcc T --8 Vrms ( OFF ) = Vrms ( OFF ) = 2T ------8 T Vcc 2 1 --- ∫ ( 0 ) dt + ∫ ( 0 ) dt + ∫ ⎛ ----------⎞ dt ⎝ 2 ⎠ T 0 T 2T --------8 8 2 3 ------ ( Vcc ) 16 Vrms ( OFF ) = 0.43Vcc Contrast(D) = Vrms(ON) / Vrms(OFF) = 0.661Vcc / 0.43Vcc = 1.52 9/21 LCD drive signals AN1048 For comparison, a hardware LCD drive uses 1/3 bias voltage. With 1/3 bias control, the contrast value (D) is 1.73. Therefore, 1/3 bias gives only a small advantage of contrast versus temperature. This advantage is reduced to zero when using software contrast control. 10/21 AN1048 3 Example of a quadruplex LCD with ST72F321B Example of a quadruplex LCD with ST72F321B The following example describes a drive for a quadruplex mode (4COM) LCD using the ST72F321B (TQFP64 pin package 10 x 10). Refer to Figure 8. The only external components needed for driving the LCD are eight resistors. The resistor value of 56K is used to reduce the DC voltage on the LCD(~7.5 mV). This value can be further decreased to get the better DC voltage on the LCD but this will result in an increase of the current consumption. One I/O port per segment and one I/O port for each COM line are needed to drive the LCD. For example: To drive a quadruplex LCD that has 128 segments (with 32 segment lines and 4 COM lines) requires only a total of 36 I/O ports. In the example program, the Port PA0-A5, PB0-B7, PD0-D7, PF7-F0, PE7-E6 pins are connected to the 32 segment lines and are used to generate the segment signals. Ports PC3...PC0 are connected to the 4 COM lines and used to generate the COM signals. The LCD driver consists of two initialization routines (port init, timer init) and a TimerA interrupt routine “timer_rt”. To activate the LCD, these two initialization routines have to be called. After these routines are called, the ST7 gets the timer Output Compare 1 & Output Compare 2 interrupts. 11/21 Example of a quadruplex LCD with ST72F321B Figure 8. AN1048 Hardware Connection Diagram Vcc Network Resistors 56K 56K Common Lines LCD GLASS Segment Lines PC0-C3 PA0-A5 6 PB0-B7 PD0-D7 PF0-F7 PE6-E7 8 8 8 2 ST72F321B The LCD Timing is generated by the TimerA output compare interrupt. Each cycle consists of four phases, one for each backplane. Each COM line generates its waveform during the corresponding phase e.g. COM1 line during phase1. During other phases it remains at level VDD/2. Each phase consists of two parts: 1. Active time 2. Dead time During the Active time, the segment lines and COM lines are used to drive the LCD. During dead time Segment and COM lines are used to tune the contrast. 12/21 AN1048 Example of a quadruplex LCD with ST72F321B Active time starts after the Output Compare 1 interrupt and dead time starts after the Output Compare 2 interrupt. A total of 16 interrupts are generated in each frame period with four interrupts per control period. There are 2 Output Compare 1 events (OC1_1 and OC1_2) and 2 Output Compare 2 events in each phase.These are explained as follows: During OC1_1, VDD is applied to the segments which have to be turned ON and 0 for the segments which have to be turned OFF. The COM line which corresponds to this phase is set to low level. Other COM lines are set to level VDD/2. During OC2, all segments and COM lines are inactive (set to low level) if we want to decrease the Vrms (see Figure 9) and COM lines are set low, segments are set high if we want to increase the Vrms (see Figure 10). During OC1_2, Segment Lines are supplied with voltage levels which are inverted to the one applied during OC1_1.COM line which corresponds to this phase is set to high level.Other COM lines are set to level VDD/2. Again during OC2, all segments and COM lines are inactive(set to low level) if we want to decrease the Vrms and COM lines are set high, segments are set low if we want to increase the Vrms (see Figure 10). 13/21 Example of a quadruplex LCD with ST72F321B Figure 9. AN1048 LCD timing diagram with Dead & Active Time (to decrease Vrms) dead time active time Vcom control period Vdd/2 COM1 T/4 Vcom Vdd/2 COM2 Vcom Vdd/2 COM3 Vcom Vdd/2 COM4 Vseg Segx (ON) Vseg Vdd/2 Segx_1 On Vcom Vdd/2 Segx_1 Off OC2 oc1_1 14/21 OC2 OC1_2 oc1_1 T/2 3T/4 T AN1048 Example of a quadruplex LCD with ST72F321B Figure 10. LCD timing diagram with Active and dead time (to increase Vrms) Dead time Control Period Active time COM1 T/ 4 T/2 3T/4 T COM2 COM3 COM4 Vseg Segx (ON) Vseg Vdd/2 Segx_1 (ON) Vseg Vdd/2 Segx_1 (Off) oc1_1 oc1_2 oc2 oc2 15/21 Software contrast control 4 AN1048 Software contrast control The software contrast control is under pending patent from STMicroelectronics. The use of this technique with a non-STMicroelectronics' Microcontroller has to be agreed by STMicroelectronics. The LCD contrast is controlled entirely by software without the use of any external components. LCD contrast can be adjusted to the optimal value depending on the operating voltage of the LCD used. The LCD contrast is controlled by varying the timing of dead phase as shown in the LCD timing diagram. Deadtime can be used to decrease as well as to increase the Vrms of the LCD. Deadtime is the voltage compensation time to regulate rms voltage up and down. Dead time can be implemented either after each control period or at the end of the frame. To avoid flickering, the duration of the dead time must be adjusted depending on the quality of LCD and the frequency of the frame. In the example in Figure 9, the Rms value of the LCD decreases if the duration of dead time is increased and Rms value increases if the duration of dead time decreases. In Figure 10, this works the opposite way. 4.1 Contrast calculations Let the frame period = T + xT where T - Active Time, xT- Dead Time x- Proportion of dead time, Vx - Voltage during the dead time Vrms ( ON ) = Vrms ( ON ) = Vrms ( ON ) = 16/21 1 - ( T + XT ) 2 ---------------f ( t ) dt T + xT ∫0 ⎛ T 2T ⎝ 8 xT ⎞ ------------T ⎟ 1 - ⎜ --88 8 2 2 2 2 ---------------⎜ ( Vcc ) dt + ∫ ( – Vcc ) dt + ∫ ( ( Vcc ) ⁄ 2 ) dt + ∫ ( Vx ) dt ⋅ 8⎟ T 2T T + xT ⎜ ∫0 ⎟ --------0 8 2 ⎞ 2 xT 2 T 2 T ( Vcc ) 2T 1 -⎛ ---------------⎜ ( Vcc ) ⋅ --- + ( Vcc ) ⋅ --- + ------------------- ⋅ ------- + ⎛⎝ Vx ⋅ -------⎞⎠ ⋅ 8⎟ 8 4 T + xT ⎝ 8 8 8 ⎠ ⎠ AN1048 Software contrast control Vrms ( ON ) = 2 2 ⎞ 1 - ⎛ ( 14Vcc ) ----------⎜ -------------------------- + ( Vx ) ⋅ x⎟ 1 + x⎝ 32 ⎠ Since Vx = 0 (incase of a decrease in Vrms) Vrms ( ON ) = 2 1 ( 14Vcc ) ------------ -------------------------1+x 32 Vrms ( ON ) = 1 ------------0.661Vcc 1+x Vrms ( OFF ) = Vrms ( OFF ) = T 2T xT ⎛ --⎞ ------------T 1 -⎜ 8 8 8 2 2 ---------------( 0 ) d t + ( 0 ) dt + ( ( Vcc ) ⁄ 2 ) dt + ( Vx ) dt ⋅ 8⎟ ∫T--∫2T ∫0 ⎟ T + xT ⎜ ∫0 ------⎝ ⎠ 8 8 2 2 ⎞ 1 - ⎛ ( 6Vcc ) ----------⎜ ---------------------- + Vx ⋅ x⎟ 1 + x ⎝ 32 ⎠ Since Vx = 0 (incase of a decrease in Vrms) Vrms ( OFF ) = 1 ------------0.18Vcc 1+x 1 ⎛ ------------0.661Vcc ⎞ ⎝ 1+x ⎠ Contrast ( Dx ) = ------------------------------------------------1 ⎛ ------------0.18Vcc ⎞ ⎝ 1+x ⎠ Where Dx = Contrast calculation with contrast control method 17/21 PE6 PE7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD0 PD1 PD2 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HEADER 2 +5 2 1 +5 PE 4 PE5 PE6 PE7 PB0/PWM3 PB1/PWM2 PB2/PWM1 PB3/PWM0 PB4/ARTCLK PB5/ARTIC1 PB6/ARTIC2 PB7 PD0/AINO PD1/AIN1 PD2/AIN2 PD3/AIN3 U1 10µF C6 C1 100nF OSC1 OSC2 +5 PA5 PA4 RESET VPP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ST72321B 100nF 10µF C3 +5 10µF C2 100nF C8 C7 PA3 PA2 PA1 PA0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 22pf OSC2 C12 22pf 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Y1 16Mhz C11 OSCIN VSS1 VDD1 PA3 PA2 PA1 PA0 PC7/SS/AIN15 PC6/SCK/I CCCLK PC5/MOSI/AIN14 PC4/M ISO/ICCDATA PC3/I CAP1-B PC2/I CAP2-B PC1/OCMP1-B/AIN13 PC0/OCMP2-B/AIN12 VSS0 VDD0 PE3 PE2 PE1/RDI PE0/TDO VDD2 OSC1 OSC2 VSS2 TLI EVD RESET VPP PA7/SCLI PA6/SDA PA5 PA4 18/21 PD4 PD5 PD6 PD7 C10 10µF C9 10µF C5 100nF +5 C4 100nF +5 RESET +5 R2 4.7K GND C13 100nF R5 4.7k +5 10K R1 SW-PB S1 PC0 PC1 PC2 PC3 R6 10k +5 PD6 PD4 PD2 PD0 PB6 PB4 PB2 PB0 PF6 PF4 PF2 PF0 PE6 PA4 PA2 PA0 PC3 PC2 R12 56K R8 56K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 R13 56K R9 56K U2 VIM878-DP6.35-RH-W-HV R14 56K R10 56K R15 56K R11 56K 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 PD7 PD5 PD3 PD1 PB7 PB5 PB3 PB1 PF7 PF5 PF3 PF1 PE7 PA5 PA3 PA1 PC0 PC1 PORTC 56K R3 4.7K VPP RESET PC6 PC4 R7 10K 9 7 5 3 1 OSC1 MISO MOSI PC5 SCK SS R4 4.7K ICC 10 8 6 4 2 JP2 OSCIN J2 SPI 1 2 3 4 J1 +5 Schematic PD4/AIN4 PD5/AIN5 PD6/AIN6 PD7/AIN7 VAREF VSSA VDD3 VSS3 PF0/AIN8/MCO PF1/BEEP PF2 PF3/AIN9/OCMP2-A PF4/AIN10/OCMP1-A PF5/AIN11/ICAP2-A PF6/ICAP1-A PF7/EXTCLK-A 5.1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LCD demo board PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 5 1 2 3 JP1 LCD demo board AN1048 The contrast D, between VON and VOFF is constant (quality of contrast). We only change the optical contrast by tuning VON close to the threshold value of the LCD. AN1048 5.2 LCD demo board Power supply The LCD demo board should be supplied by a maximum DC voltage of 5V. The board is provided with the connector JP1 for this board supply. Note: For the demo software loaded inside the micro, the board should be supplied with 5V. The software attached to this application note displays the word “EMBEDDED” and tunes automatically its contrast from transparent to dark with the ST software pattented method. The Vrms increase is performed by putting the segment voltage once at Vdd, once at -Vdd during the dead times, the Vrms decrease is performed by putting at 0 the segment voltage during the same dead times. The voltage average is then kept. Refer to the software attached to this application note for more details. 5.3 Programming The demo board uses the ST72F321B microcontroller and can be programmed using the ICC protocol. The board is provided with the ICC connnector JP2. By default, OSC_TYP is programmed as a resonator oscillator in the option bytes. You can disable the option bytes when you want to use the ICC clock to program the micro. 5.4 Reset The device can be reset by pressing the switch s1 on the demo board. 5.5 Oscillation system The demo board is mounted with a 16 MHz crystal with 8 MHz fcpu. You can change this clock value but need to modify the timer setting inside the software accordingly. 19/21 Revision history 6 AN1048 Revision history Table 1. Document revision history Date 09-May-2006 20/21 Revision Changes 5 Document reformatted References to ST72F321 changed to ST72F321B Formulae for VRMS(ON) and VRMS(OFF) corrected, Section 4.1 on page 16 Note updated, Section 5.2 on page 19 AN1048 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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