Samsung M391T2953BG0-CC Ddr2 unbuffered sdram module Datasheet

256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
DDR2 Unbuffered SDRAM MODULE
240pin Unbuffered Module based on 512Mb B-die
64/72-bit Non-ECC/ECC
Revision 1.2
January 2005
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
DDR2 Unbuffered DIMM Ordering Information
Part Number
Density
Organization
M378T3354BG(Z)0-CD5/CC
256MB
32Mx64
M378T6553BG(Z)0-CD5/CC
512MB
64Mx64
M378T2953BG(Z)0-CD5/CC
1GB
128Mx64
Number of
Rank
Height
32Mx16(K4T51163QB)*4
1
30mm
64Mx8(K4T51083QB)*8
1
30mm
64Mx8(K4T51083QB)*16
2
30mm
Component Composition
x64 Non ECC
x72 ECC
M391T6553BG(Z)0-CD5/CC
512MB
64Mx72
64Mx8(K4T51083QB)*9
1
30mm
M391T2953BG(Z)0-CD5/CC
1GB
128Mx72
64Mx8(K4T51083QB)*18
2
30mm
Note: “Z” of Part number stand for Lead-free products.
Features
• Performance range
D5(DDR2-533)
CC(DDR2-400)
Unit
Speed@CL3
400
400
Mbps
Speed@CL4
533
400
Mbps
Speed@CL5
-
-
Mbps
CL-tRCD-tRP
4-4-4
3-3-3
CK
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin
• 4 Bank
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refesh Period 7.8us at lower then TCASE 85×C, 3.9us at 85×C < TCASE < 95 ×C
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 64Mx8, 84ball FBGA - 32Mx16
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
64Mx8(512Mb) based Module
32Mx16(512Mb) based Module
A0-A13
A0-A12
A0-A9
A0-A9
BA0-BA1
BA0-BA1
A10
A10
x64 DIMM Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREF
121
VSS
31
DQ19
151
VSS
61
A4
181
VDDQ
91
VSS
211
DM5
2
VSS
122
DQ4
32
VSS
152
DQ28
62
VDDQ
182
A3
92
DQS5
212
NC
3
DQ0
123
DQ5
33
DQ24
153
DQ29
63
A2
183
A1
93
DQS5
213
VSS
64
VDD
184
VDD
4
DQ1
124
VSS
34
DQ25
154
VSS
5
VSS
125
DM0
35
VSS
155
DM3
6
DQS0
126
NC
36
DQS3
156
NC
65
VSS
185
7
DQS0
127
VSS
37
DQS3
157
VSS
66
VSS
186
94
VSS
214
DQ46
95
DQ42
215
DQ47
CK0
96
DQ43
216
VSS
CK0
97
VSS
217
DQ52
DQ53
KEY
8
VSS
128
DQ6
38
VSS
158
DQ30
67
VDD
187
VDD
98
DQ48
218
9
DQ2
129
DQ7
39
DQ26
159
DQ31
68
NC
188
A0
99
DQ49
219
VSS
10
DQ3
130
VSS
40
DQ27
160
VSS
69
VDD
189
VDD
100
VSS
220
CK2
CK2
11
VSS
131
DQ12
41
VSS
161
NC
70
A10/AP
190
BA1
101
SA2
221
12
DQ8
132
DQ13
42
NC
162
NC
71
BA0
191
VDDQ
102
222
VSS
13
DQ9
133
VSS
43
NC
163
VSS
72
VDDQ
192
RAS
103
NC, TEST2
VSS
223
DM6
14
VSS
134
DM1
44
VSS
164
NC
73
WE
193
S0
104
DQS6
224
NC
15
DQS1
135
NC
45
NC
165
NC
74
CAS
194
VDDQ
105
DQS6
225
VSS
16
DQS1
136
VSS
46
NC
166
VSS
75
VDDQ
195
ODT0
106
VSS
226
DQ54
17
VSS
137
CK1
47
VSS
167
NC
76
S1
196
107
DQ50
227
DQ55
18
NC
138
CK1
48
NC
168
NC
77
ODT1
197
A131
VDD
108
DQ51
228
VSS
19
NC
139
VSS
49
NC
169
VSS
78
VDDQ
198
VSS
109
VSS
229
DQ60
DQ61
20
VSS
140
DQ14
50
VSS
170
VDDQ
79
VSS
199
DQ36
110
DQ56
230
21
DQ10
141
DQ15
51
VDDQ
171
CKE1
80
DQ32
200
DQ37
111
DQ57
231
VSS
22
DQ11
142
VSS
52
CKE0
172
VDD
81
DQ33
201
VSS
112
VSS
232
DM7
23
VSS
143
DQ20
53
VDD
173
NC
82
VSS
202
DM4
113
DQS7
233
NC
24
DQ16
144
DQ21
54
NC
174
NC
83
DQS4
203
NC
114
DQS7
234
VSS
25
DQ17
145
VSS
55
NC
175
VDDQ
84
DQS4
204
VSS
115
VSS
235
DQ62
26
VSS
146
DM2
56
VDDQ
176
A12
85
VSS
205
DQ38
116
DQ58
236
DQ63
27
DQS2
147
NC
57
A11
177
A9
86
DQ34
206
DQ39
117
DQ59
237
VSS
28
DQS2
148
VSS
58
A7
178
VDD
87
DQ35
207
VSS
118
VSS
238
VDDSPD
29
VSS
149
DQ22
59
VDD
179
A8
88
VSS
208
DQ44
119
SDA
239
SA0
30
DQ18
150
DQ23
60
A5
180
A6
89
DQ40
209
120
SCL
240
SA1
90
DQ41
210
DQ45
VSS
NC = No Connect, RFU = Reserved for Future Use
1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
x72 DIMM Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREF
121
VSS
31
DQ19
151
VSS
61
A4
181
VDDQ
91
VSS
211
DM5
2
VSS
122
DQ4
32
VSS
152
DQ28
62
VDDQ
182
A3
92
DQS5
212
NC
3
DQ0
123
DQ5
33
DQ24
153
DQ29
63
A2
183
A1
93
DQS5
213
VSS
64
VDD
184
VDD
4
DQ1
124
VSS
34
DQ25
154
VSS
5
VSS
125
DM0
35
VSS
155
DM3
94
VSS
214
DQ46
95
DQ42
215
DQ47
6
DQS0
126
NC
36
DQS3
156
NC
65
VSS
185
7
DQS0
127
VSS
37
DQS3
157
VSS
66
VSS
186
CK0
96
DQ43
216
VSS
CK0
97
VSS
217
DQ52
8
VSS
128
DQ6
38
VSS
158
DQ30
67
VDD
187
VDD
98
9
DQ2
129
DQ7
39
DQ26
159
DQ31
68
NC
188
A0
99
DQ48
218
DQ53
DQ49
219
10
DQ3
130
VSS
40
DQ27
160
VSS
69
VDD
189
VDD
100
VSS
VSS
220
CK2
CK2
KEY
11
VSS
131
DQ12
41
VSS
161
CB4
70
A10/AP
190
BA1
101
SA2
221
12
DQ8
132
DQ13
42
CB0
162
CB5
71
BA0
191
VDDQ
102
NC, TEST2
222
VSS
13
DQ9
133
VSS
43
CB1
163
VSS
72
VDDQ
192
RAS
103
VSS
223
DM6
14
VSS
134
DM1
44
VSS
164
DM8
73
WE
193
S0
104
DQS6
224
NC
15
DQS1
135
NC
45
DQS8
165
NC
74
CAS
194
VDDQ
105
DQS6
225
VSS
16
DQS1
136
VSS
46
DQS8
166
VSS
75
VDDQ
195
ODT0
106
VSS
226
DQ54
17
VSS
137
CK1
47
VSS
167
CB6
76
S1
196
A13
107
DQ50
227
DQ55
18
NC
138
CK1
48
CB2
168
CB7
77
ODT1
197
VDD
108
DQ51
228
VSS
19
NC
139
VSS
49
CB3
169
VSS
78
VDDQ
198
VSS
109
VSS
229
DQ60
DQ61
20
VSS
140
DQ14
50
VSS
170
VDDQ
79
VSS
199
DQ36
110
DQ56
230
21
DQ10
141
DQ15
51
VDDQ
171
CKE1
80
DQ32
200
DQ37
111
DQ57
231
VSS
22
DQ11
142
VSS
52
CKE0
172
VDD
81
DQ33
201
VSS
112
VSS
232
DM7
23
VSS
143
DQ20
53
VDD
173
NC
82
VSS
202
DM4
113
DQS7
233
NC
24
DQ16
144
DQ21
54
NC
174
NC
83
DQS4
203
NC
114
DQS7
234
VSS
25
DQ17
145
VSS
55
NC
175
VDDQ
84
DQS4
204
VSS
115
VSS
235
DQ62
26
VSS
146
DM2
56
VDDQ
176
A12
85
VSS
205
DQ38
116
DQ58
236
DQ63
27
DQS2
147
NC
57
A11
177
A9
86
DQ34
206
DQ39
117
DQ59
237
VSS
28
DQS2
148
VSS
58
A7
178
VDD
87
DQ35
207
VSS
118
VSS
238
VDDSPD
29
VSS
149
DQ22
59
VDD
179
A8
88
VSS
208
DQ44
119
SDA
239
SA0
30
DQ18
150
DQ23
60
A5
180
A6
89
DQ40
209
DQ45
120
SCL
240
SA1
90
DQ41
210
VSS
NC = No Connect, RFU = Reserved for Future Use
1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin Description
Pin Name
A0-A13
BA0, BA1
Description
Pin Name
Description
DDR2 SDRAM address bus
CK0, CK1, CK2
DDR2 SDRAM clocks (positive line of differential pair)
DDR2 SDRAM bank select
CK0, CK1, CK2
DDR2 SDRAM clocks (negative line of differential pair)
RAS
DDR2 SDRAM row address strobe
SCL
I2C serial bus clock for EEPROM
CAS
DDR2 SDRAM column address strobe
SDA
I2C serial bus data line for EEPROM
WE
DDR2 SDRAM wirte enable
S0, S1
DIMM Rank Select Lines
SA0-SA2
VDD*
I2C serial address select for EEPROM
DDR2 SDRAM core power supply
CKE0,CKE1
DDR2 SDRAM clock enable lines
VDDQ*
DDR2 SDRAM I/O Driver power supply
ODT0, ODT1
On-die termination control lines
VREF
DDR2 SDRAM I/O reference supply
DQ0 - DQ63
DIMM memory data bus
VSS
CB0 - CB7
DIMM ECC check bits
VDDSPD
DQS0 - DQS8
DDR2 SDRAM data strobes
NC
DM(0-8)
DDR2 SDRAM data masks
RESET
DQS0-DQS8
DDR2 SDRAM differential data strobes
TEST
Power supply return (ground)
Serial EEPROM positive power supply
Spare Pins(no connect)
Not used on UDIMM
Used by memory bus analysis tools (unused on memory
DIMMs)
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Input/Output Functional Description
Symbol
Type
Function
CK0-CK2
CK0-CK2
Input
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing
of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of
CK and CK (Both directions of crossing)
CKE0-CKE1
Input
Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode
S0-S1
Input
Enables the associated SDRAM command decoder when low and disables the command decoder
when high. When the command decoder is disbled, new command are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks
RAS, CAS, WE
Input
RAS, CAS, and WE (ALONG WITH CS) define the command being entered.
ODT0-ODT1
Input
When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is
enabled in the Extended Mode Register Set (EMRS).
VREF
Supply
Reference voltage for SSTL 18 inputs.
VDDQ
Supply
Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0-BA1
Input
Selects which SDRAM BANK of four is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the colum address, In addition to the
column address, AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If
AP is low, autoprecharge is disbled. During a precharge command cycle, AP is used in conjunction
with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to precharge.
A0-A13
Input
DQ0-DQ63
CB0-CB7
In/Out
DM0-DM8
Input
VDD,VSS
Supply
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to
VDD/VDDQ planes on these modules.
DQS0-DQS8
DQS0-DQS8
In/Out
Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to
the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM
SA0-SA2
Input
These signals and tied at the system planar to either VSS or VDD to configure the serial SPD EERPOM address range.
SDA
In/Out
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to VDD to act as a pullup on the system board.
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to VDD to act as a pullup onthe system board.
VDD SPD
Supply
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident
with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins
are input only, the DM loading matches the DQ and DQS loading.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 512MB, 64Mx64 Module(Populated as 1 rank of x8 DDR2 SDRAMs)
M378T6553BG(Z)0
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DQS1
DM1
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D4
DQS5
DQS5
DM5
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQS2
DQS2
DM2
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D5
DQS6
DQS6
DM6
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DQS3
DM3
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D6
DQS7
DQS7
DM7
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
NU/ CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D3
Serial PD
SCL
SDA
WP
BA0 - BA1
A0 - A13
RAS
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
A0
A1
A2
SA0
SA1
SA2
VDDSPD
Serial PD
VDD/VDDQ
D0 - D7
VREF
D0 - D7
VSS
D0 - D7
BA0-BA1 : DDR2 SDRAMs D0 - D7
A0-A13 : DDR2 SDRAMs D0 - D7
CAS : DDR2 SDRAMs D0 - D7
CKE0
CKE : DDR2 SDRAMs D0 - D7
ODT0
DQS DQS
D7
* Clock Wiring
Clock
Input
DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 DDR2 SDRAMs
3 DDR2 SDRAMs
3 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
RAS : DDR2 SDRAMs D0 - D7
CAS
WE
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
WE : DDR2 SDRAMs D0 - D7
Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.
ODT : DDR2 SDRAMs D0 - D7
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 512MB, 64Mx72 ECC Module(Populated as 1 rank of x8 DDR2 SDRAMs)
M391T6553BG(Z)0
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DQS1
DM1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQS2
DQS2
DM2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQS DQS
D5
D2
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D6
DQS7
DQS7
DM7
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
DQS8
DQS8
DM8
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D7
Serial PD
DM
CS
SCL
DQS DQS
SDA
WP
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
VDDSPD
VDD/VDDQ
BA0-BA1 : DDR2 SDRAMs D0 - D8
A0-A13 : DDR2 SDRAMs D0 - D8
RAS
RAS : DDR2 SDRAMs D0 - D8
CAS
CAS : DDR2 SDRAMs D0 - D8
CKE0
CKE : DDR2 SDRAMs D0 - D8
ODT0
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS3
DQS3
DM3
WE
D4
DQS6
DQS6
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
A0 - A13
DQS DQS
DQS5
DQS5
DM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
BA0 - BA1
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
WE : DDR2 SDRAMs D0 - D8
A0
A1
A2
SA0
SA1
SA2
* Clock Wiring
Serial PD
D0 - D8
VREF
D0 - D8
VSS
D0 - D8
Clock
Input
DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 DDR2 SDRAMs
3 DDR2 SDRAMs
3 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.
ODT : DDR2 SDRAMs D0 - D8
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs)
M378T2953BG(Z)0
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
DQS DQS
DM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D8
DQS1
DQS1
DM1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D12
DQS5
DQS5
DM5
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS DQS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D9
DQS2
DQS2
DM2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
D13
DQS6
DQS6
DM6
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DQS DQS
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D10
DQS3
DQS3
DM3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
D14
DQS7
DQS7
DM7
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A0 - A13
D3
DQS DQS
DM
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Serial PD
VDD/VDDQ
D0 - D15
VREF
D0 - D15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
D15
Serial PD
SCL
SDA
WP
A0
A1
A2
SA0
SA1
SA2
* Clock Wiring
D0 - D15
BA0-BA1 : DDR2 SDRAMs D0 - D15
A0-A13 : DDR2 SDRAMs D0 - D15
CKE0
CKE : DDR2 SDRAMs D0 - D7
CKE1
CKE : DDR2 SDRAMs D8 - D15
RAS
RAS : DDR2 SDRAMs D0 - D15
CAS
CAS : DDR2 SDRAMs D0 - D15
WE
WE : DDR2 SDRAMs D0 - D15
ODT0
ODT1
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D11
VDDSPD
VSS
BA0 - BA1
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ODT : DDR2 SDRAMs D0 - D7
ODT : DDR2 SDRAMs D8 - D15
Clock
Input
DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
4 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx72 ECC Module(Populated as 2 ranks of x8 DDR2 SDRAMs)
M391T2953BG(Z)0
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
CS
DQS DQS
DM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D9
DQS1
DQS1
DM1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
CS
DQS DQS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D10
DQS2
DQS2
DM2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
DQS3
DQS3
DM3
DM
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D13
CS
DQS DQS
DM
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
D14
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
D15
DQS7
DQS7
DM7
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
CS DQS DQS
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D12
DQS8
DQS8
DM8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DM
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
D16
Serial PD
DM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE1
CKE : DDR2 SDRAMs D9 - D17
RAS
RAS : DDR2 SDRAMs D0 - D17
CAS
CAS : DDR2 SDRAMs D0 - D17
WE
WE : DDR2 SDRAMs D0 - D17
ODT : DDR2 SDRAMs D0 - D8
ODT : DDR2 SDRAMs D9 - D17
SDA
WP
D17
A0-A13 : DDR2 SDRAMs D0 - D17
CKE : DDR2 SDRAMs D0 - D8
SCL
CS DQS DQS
BA0-BA1 : DDR2 SDRAMs D0 - D17
CKE0
ODT0
ODT1
DQS DQS
DQS6
DQS6
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
A0 - A13
CS
DQS5
DQS5
DM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
BA0 - BA1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0
A1
A2
SA0
SA1
SA2
* Clock Wiring
VDDSPD
Serial PD
VDD/VDDQ
D0 - D17
VREF
D0 - D17
VSS
D0 - D17
Clock
Input
DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 256MB, 32Mx64 Module(Populated as 1 rank of x16 DDR2 SDRAMs)
M378T3354BG(Z)0
S0
CS
DQS1
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDOS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDOS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
DQS5
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D0
DQS4
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
LDQS
LDOS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDOS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D2
CS
DQS3
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS2
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
LDQS
LDOS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDOS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
VDD/VDDQ
Serial PD
A0 - A12
A0
A1
A2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
SA0
SA1
SA2
LDQS
LDOS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDOS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D3
* Clock Wiring
Serial PD
D0 - D3
VREF
D0 - D3
VSS
D0 - D3
Clock
Input
DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
NC
2 DDR2 SDRAMs
2 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
BA0-BA1 : DDR2 SDRAMs D0 - D3
A0-A12 : DDR2 SDRAMs D0 - D3
CKE0
CKE : DDR2 SDRAMs D0 - D3
RAS
RAS : DDR2 SDRAMs D0 - D3
CAS
CAS : DDR2 SDRAMs D0 - D3
WE
WE : DDR2 SDRAMs D0 - D3
ODT0
DQS6
DQS6
DM6
SDA
WP
BA0 - BA1
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D1
VDDSPD
SCL
CS
DQS7
DQS7
DM7
Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
4. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.
ODT : DDR2 SDRAMs D0 - D3
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Absolute Maximum DC Ratings
Symbol
Rating
Units
Voltage on VDD pin relative to Vss
- 1.0 V ~ 2.3 V
V
1
VDDQ
Voltage on VDDQ pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
VDDL
Voltage on VDDL pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
Voltage on any pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
-55 to +100
°C
1, 2
VDD
VIN, VOUT
TSTG
1.
Parameter
Storage Temperature
Notes
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please
refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Min.
Typ.
Max.
Notes
VDD
Supply Voltage
1.7
1.8
1.9
V
VDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
VDDQ
Supply Voltage for Output
1.7
1.8
1.9
V
4
VREF
Input Reference Voltage
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ
mV
1,2
Termination Voltage
VREF-0.04
VREF
VREF+0.04
V
3
VTT
4
There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must
be less than or equal to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JESD51.2 standard.
2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.
3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to
enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
VIH(DC)
DC input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL(DC)
DC input logic low
- 0.3
VREF - 0.125
V
Notes
Input AC Logic Level
Parameter
Min.
Max.
Units
VIH(AC)
Symbol
AC input logic high
VREF + 0.250
-
V
VIL(AC)
AC input logic low
-
VREF - 0.250
V
Notes
AC Input Test Conditions
Symbol
VREF
Condition
Value
Units
Notes
Input reference voltage
0.5 * VDDQ
V
1
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF
to VIL(AC) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on
the negative transitions.
VDDQ
VIH(AC) min
VIH(DC) min
VSWING(MAX)
VREF
VIL(DC) max
VIL(AC) max
delta TF
Falling Slew =
delta TR
VREF - VIL(AC) max
Rising Slew =
delta TF
VSS
VIH(AC) min - VREF
delta TR
< AC Input Test Signal Waveform >
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol
Proposed Conditions
IDD0
Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD
= tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING;
Data pattern is same as IDD4W
mA
Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE; Data bus inputs are FLOATING
mA
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
mA
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Units
Fast PDN Exit MRS(12) = 0mA
mA
Slow PDN Exit MRS(12) = 1mA
mA
Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS
= tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Notes
mA
mA
mA
Normal
mA
Low Power
mA
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =
tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R;
Refer to the following page for detailed timing conditions
mA
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)
M378T6553BG(Z)0 : 512MB(64Mx8 *8) Module
Symbol
D5
CC
Unit
(DDR2-533@CL=4) (DDR2-400@CL=3)
IDD0
800
760
mA
IDD1
880
800
mA
IDD2P
64
64
mA
IDD2Q
200
200
mA
IDD2N
240
240
mA
IDD3P-F
240
240
mA
IDD3P-S
120
120
mA
IDD3N
560
520
mA
IDD4W
1,600
1,160
mA
IDD4R
1,440
1,160
mA
IDD5B
1,560
1,480
mA
44
44
mA
2,200
2,160
mA
IDD6
Normal
IDD7
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M378T2953BG(Z)0 : 1GB(64Mx8 *16) Module
Symbol
IDD6
D5
CC
(DDR2-533@CL=4) (DDR2-400@CL=3) Unit
IDD0
1,360
1,280
mA
IDD1
1,440
1,320
mA
IDD2P
128
128
mA
IDD2Q
400
400
mA
IDD2N
480
480
mA
IDD3P-F
480
480
mA
IDD3P-S
240
240
mA
IDD3N
1,120
1,040
mA
IDD4W
2,160
1,680
mA
IDD4R
2,000
1,680
mA
IDD5B
2,120
2,000
mA
88
88
mA
2,760
2,680
mA
Normal
IDD7
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)
M378T3354BG(Z)0 : 256MB(32Mx16 *4) Module
Symbol
IDD6
D5
CC
Unit
(DDR2-533@CL=4) (DDR2-400@CL=3)
IDD0
480
460
IDD1
580
500
mA
IDD2P
32
32
mA
IDD2Q
100
100
mA
IDD2N
120
120
mA
IDD3P-F
120
120
mA
IDD3P-S
60
60
mA
IDD3N
280
260
mA
IDD4W
920
740
mA
IDD4R
820
680
mA
IDD5B
780
740
mA
22
22
mA
1,560
1,500
mA
Normal
IDD7
Notes
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M391T6553BG(Z)0 : 512MB(64Mx8 *9) ECC Module
Symbol
IDD6
D5
CC
Unit
(DDR2-533@CL=4) (DDR2-400@CL=3)
IDD0
900
855
mA
IDD1
990
900
mA
IDD2P
72
72
mA
IDD2Q
225
225
mA
IDD2N
270
270
mA
IDD3P-F
270
270
mA
IDD3P-S
135
135
mA
IDD3N
630
585
mA
IDD4W
1,800
1,305
mA
IDD4R
1,620
1,305
mA
IDD5B
1,755
1,665
mA
50
50
mA
2,475
2,430
mA
Normal
IDD7
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Operating Current Table(1-3) (TA=0oC, VDD= 1.9V)
M391T2953BG(Z)0 : 1GB(64Mx8 *18) ECC Module
D5
CC
Unit
(DDR2-533@CL=4) (DDR2-400@CL=3)
Symbol
IDD6
IDD0
1,530
1,440
mA
IDD1
1,620
1,485
mA
IDD2P
144
144
mA
IDD2Q
450
450
mA
IDD2N
540
540
mA
IDD3P-F
540
540
mA
IDD3P-S
270
270
mA
mA
IDD3N
1,260
1,170
IDD4W
2,430
1,890
mA
IDD4R
2,250
1,890
mA
IDD5B
2,385
2,250
mA
99
99
mA
3,105
3,015
mA
Normal
IDD7
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Parameter
Symbol
Non-ECC
Input capacitance, CK and CK
Min
Max
M378T6553BG(Z)0
Min
Max
M378T2953BG(Z)0
Min
Max
M378T3354BG(Z)0
CCK0
-
24
-
26
-
22
CCK1
-
25
-
28
-
24
CCK2
-
25
Input capacitance, CKE and CS
CI1
-
42
-
42
-
34
Input capacitance, Addr, RAS, CAS, WE
CI2
-
42
-
42
-
34
Input/output capacitance, DQ, DM, DQS, DQS
CIO
-
6
-
10
-
6
ECC
Input capacitance, CK and CK
M391T6553BG(Z)0
28
24
pF
M391T2953BG(Z)0
CCK0
-
25
-
28
CCK1
-
25
-
28
CCK2
Units
25
28
Input capacitance, CKE and CS
CI1
-
44
-
44
Input capacitance, Addr, RAS, CAS, WE
CI2
-
44
-
44
Input/output capacitance, DQ, DM, DQS, DQS
CIO
-
6
-
10
pF
Note: DM is internally loaded to match DQ and DQS identically.
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(0 °C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
Refresh Parameters by Device Density
Parameter
Symbol
Refresh to active/Refresh command time
tRFC
Average periodic refresh interval
tREFI
256Mb
512Mb
1Gb
2Gb
4Gb
Units
75
105
127.5
195
tbd
ns
0 °C ≤ TCASE ≤ 85°C
7.8
7.8
7.8
7.8
7.8
µs
85 °C < TCASE ≤ 95°C
3.9
3.9
3.9
3.9
3.9
µs
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR2-533(D5)
DDR2-400(CC)
Bin (CL - tRCD - tRP)
4-4-4
3-3-3
Units
Parameter
min
max
min
max
tCK, CL=3
5
8
5
8
ns
tCK, CL=4
3.75
8
5
8
ns
tCK, CL=5
-
-
-
-
ns
tRCD
15
15
ns
tRP
15
15
ns
tRC
55
55
ns
tRAS
40
70000
70000
40
ns
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
Symbol
DDR2-533
Units
DDR2-400
min
max
min
max
Notes
DQ output access time from
CK/CK
tAC
-500
+500
-600
+600
ps
DQS output access time
from CK/CK
tDQSCK
-450
+450
-500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL,
tCH)
x
min(tCL,
tCH)
x
ps
20,21
Clock cycle time, CL=x
tCK
3750
8000
5000
8000
ps
24
DQ and DM input hold time
tDH
225
x
275
x
ps
15,16,
17
DQ and DM input setup
time
tDS
100
x
150
x
ps
15,16,
17
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
Parameter
Symbol
DDR2-533
DDR2 SDRAM
Units
DDR2-400
min
max
min
max
Control & Address input
pulse width for each input
tIPW
0.6
x
0.6
x
tCK
DQ and DM input pulse
width for each input
tDIPW
0.35
x
0.35
x
tCK
Data-out high-impedance
time from CK/CK
tHZ
x
tAC max
x
tAC max
ps
DQS low-impedance time
from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time
from CK/CK
tLZ(DQ)
2* tACmin
tAC max
2* tACmin
tAC max
ps
DQS-DQ skew for DQS and
associated DQ signals
tDQSQ
x
300
x
350
ps
DQ hold skew factor
tQHS
x
400
x
450
ps
DQ/DQS output hold time
from DQS
tQH
tHP - tQHS
x
tHP - tQHS
x
ps
Write command to first DQS
latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
DQS input high pulse width
tDQSH
0.35
x
0.35
x
tCK
DQS input low pulse width
tDQSL
0.35
x
0.35
x
tCK
DQS falling edge to CK
setup time
tDSS
0.2
x
0.2
x
tCK
DQS falling edge hold time from
CK
tDSH
0.2
x
0.2
x
tCK
Mode register set command
cycle time
tMRD
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
x
0.35
x
tCK
Address and control input
hold time
tIH
375
x
475
x
ps
Address and control input
setup time
tIS
250
x
350
x
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to active command
period for 1KB page size
products
tRRD
7.5
x
7.5
x
ns
Active to active command
period for 2KB page size
products
tRRD
10
x
10
x
ns
Four Activate Window for
1KB page size products
tFAW
37.5
37.5
ns
Four Activate Window for
2KB page size products
tFAW
50
50
ns
CAS to CAS command
delay
tCCD
2
2
tCK
Notes
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
Parameter
Symbol
DDR2-533
DDR2 SDRAM
Units
DDR2-400
min
max
min
max
Write recovery time
tWR
15
x
15
x
ns
Auto precharge write
recovery + precharge time
tDAL
tWR+tRP
x
tWR+tRP
x
tCK
Internal write to read
command delay
tWTR
7.5
x
10
x
ns
Internal read to precharge
command delay
tRTP
7.5
7.5
ns
Exit self refresh to a nonread command
tXSNR
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read
command
tXSRD
200
200
tCK
Exit precharge power down
to any non-read command
tXP
2
x
2
x
tCK
Exit active power down to
read command
tXARD
2
x
2
x
tCK
Exit active power down to
read command
(Slow exit, Lower power)
tXARDS
CKE minimum pulse width
(high and low pulse width)
6 - AL
6 - AL
t
CKE
3
3
ODT turn-on delay
t
2
2
2
2
tCK
ODT turn-on
t
tAC(min)
tAC(max)
+1
tAC(min)
tAC(max)+
1
ns
ODT turn-on(Power-Down
mode)
t
tAC(min)+
2
2tCK+tAC
(max)+1
tAC(min)+
2
2tCK+tAC
(max)+1
ns
ODT turn-off delay
t
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+
0.6
ns
ODT turn-off (Power-Down
mode)
t
tAC(min)+
2
2.5tCK+
tAC(max)
+1
tAC(min)+
2
2.5tCK+
tAC(max)+
1
ns
ODT to power down entry
latency
tANPD
3
3
tCK
ODT power down exit
latency
tAXPD
8
8
tCK
OCD drive mode output
delay
tOIT
0
Minimum time clocks
remains ON after CKE
asynchronously drops LOW
tDelay
AOND
AON
AONPD
AOFD
AOFPD
tIS+tCK
+tIH
12
0
tIS+tCK
+tIH
Notes
tCK
tCK
12
ns
ns
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Physical Dimensions: 64Mbx8 based 64Mx64/x72 Module(1 Rank)
M378/91T6553BG(Z)0
Units : Millimeters
133.35
(2X)4.00
131.35
128.95
N/A
10.00
(for x64)
ECC
SPD
30.00
(2)
2.50
A
17.80
2.30
(for x72)
B
63.00
2.7
55.00
1.270 ± 0.10
4.00
4.00
3.00
2.50±0.20
5.00
0.80±0.05
3.80
2.50
1.50±0.10
Detail A
0.20
1.00
4.00
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QB
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Physical Dimensions: 64Mbx8 based 128Mx64/x72 Module(2 Ranks)
M378/91T2953BG(Z)0
Units : Millimeters
133.35
(2X)4.00
131.35
128.95
10.00
N/A
(for x64)
SPD
30.00
ECC
(2)
2.50
A
17.80
2.30
(for x72)
B
63.00
4.00
55.00
N/A
(for x64)
ECC
(for x72)
1.270 ± 0.10
4.00
4.00
3.00
2.50±0.20
5.00
0.80±0.05
3.80
2.50
1.50±0.10
Detail A
0.20
1.00
4.00
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QB
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Physical Dimensions: 32Mbx16 based 32Mx64/x72 Module(1 Rank)
M378T3354BG(Z)0
Units : Millimeters
133.35
(2X)4.00
131.35
10.00
128.95
SPD
(2)
2.50
A
17.80
2.30
30.00
B
63.00
2.7
55.00
1.270 ± 0.10
4.00
4.00
3.00
2.50±0.20
5.00
0.80±0.05
3.80
2.50
1.50±0.10
Detail A
0.20
1.00
4.00
Detail B
The used device is 32M x16 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51163QB
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Revision History
Revision 1.0 (Jan. 2004)
- Initial Release
Revision 1.1 (Jun. 2004)
- Added lead-free part number in the ordering information
- Changed IDD2P
Revision 1.2 (Jan. 2005)
- Removed DDR2-667 UDIMM
Rev. 1.2 Jan. 2005
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