TI1 MSP430G2230IDR Mixed signal microcontroller Datasheet

MSP430G22x0
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SLAS753D – JANUARY 2012 – REVISED AUGUST 2012
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
23
•
•
•
•
•
•
Low Supply Voltage Range: 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode: 220 µA at 1 MHz, 2.2 V
– Standby Mode: 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
– Internal Very-Low-Power Low-Frequency
Oscillator
16-Bit Timer_A With Two Capture/Compare
Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope Analog-to-Digital
•
•
•
•
•
•
•
•
(A/D) Conversion (MSP430G2210 Only)
10-Bit 200-ksps Analog-to-Digital (A/D)
Converter With Internal Reference, Sampleand-Hold, and Autoscan (MSP430G2230 Only)
Universal Serial Interface (USI) Supports SPI
and I2C (MSP430G2230 Only)
Brownout Detector
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
Family Members:
– MSP430G22x0
– 2KB + 256B Flash Memory
– 128B RAM
Available in 8-Pin Plastic Packages (D)
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide (SLAU144)
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G22x0 series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer and four
I/O pins. In addition, the MSP430G2230 has a built-in communication capability using synchronous protocols
(SPI or I2C) and a 10-bit A/D converter. The MSP430G2210 has a versatile analog comparator.
Table 1. Available Options (1)
TA
-40°C to 85°C
(1)
(2)
PACKAGED DEVICES (2)
PLASTIC 8-PIN (D)
MSP430G2230ID
MSP430G2210ID
For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Device Pinout and Functional Block Diagram, MSP430G2210
See Application Information for detailed I/O information.
D PACKAGE
(TOP VIEW)
DVSS
DVCC
1
P1.2/TA0.1/CA2
2
8
7
P1.5/TA0.0/CA5
P1.6/TA0.1/CA6
3
6
TEST/SBWTCK
RST/NMI/SBWTDIO
4
5
P1.7/CAOUT/CA7
Figure 1. Device Pinout, MSP430G2210
VCC
P1.2, P1.5,
P1.6, P1.7
4
VSS
XOUT
XIN
Basic Clock
System+
Port P1
ACLK
SMCLK
Flash
RAM
COMP_A+
2kB
128B
4 Channel
input MUX
MCLK
16MHz
CPU
incl. 16
Registers
4 I/O
Interrupt
capability,
pull−up/down
resistors
MAB
MDB
Emulation
(2BP)
JTAG
Interface
Brownout
Protection
Watchdog
WDT+
15/16−Bit
Timer_A2
2 CC
Registers
Spy−Bi Wire
RST/NMI
Figure 2. Functional Block Diagram, MSP430G2210
2
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Device Pinout and Functional Block Diagram, MSP430G2230
See Application Information for detailed I/O information.
D PACKAGE
(TOP VIEW)
DVSS
DVCC
1
P1.2/TA0.1/A2
2
8
7
P1.5/TA0.0/A5/SCLK
P1.6/TA0.1/A6/SDO/SCL
3
6
TEST/SBWTCK
RST/NMI/SBWTDIO
4
5
P1.7/A7/SDI/SDA
Figure 3. Device Pinout, MSP430G2230
VCC
P1.2, P1.5,
P1.6, P1.7
4
VSS
XOUT
XIN
Basic Clock
System+
ACLK
SMCLK
Flash
RAM
2kB
128B
MCLK
16MHz
CPU
incl. 16
Registers
ADC
Port P1
10-Bit
4 Channel
Autoscan
1 ch DMA
4 I/O
Interrupt
capability,
pull−up/down
resistors
MAB
MDB
Emulation
(2BP)
JTAG
Interface
USI
Brownout
Protection
Watchdog
WDT+
15/16−Bit
Spy−Bi Wire
Timer_A2
2 CC
Registers
Universal
Serial
Interface
SPI, I2C
RST/NMI
Figure 4. Functional Block Diagram, MSP430G2230
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Table 2. Terminal Functions, MSP430G2210 (1)
TERMINAL
NAME
NO.
D
DESCRIPTION
I/O
P1.2/
TA0.1/
CA2
2
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare Out1 output
Comparator_A+, CA2 input
P1.5/
TA0.0/
CA5
3
I/O
General-purpose digital I/O pin
Timer_A, compare Out0 output
Comparator_A+, CA5 input
P1.6/
TA0.1/
CA6
4
I/O
General-purpose digital I/O pin
Timer_A, compare: Out1 output
Comparator_A+, CA6 input
5
I/O
P1.7/
CAOUT/
CA7
General-purpose digital I/O pin
Comparator_A+, output
Comparator_A+, CA7 input
RST/
NMI/
SBWTDIO
6
I
Reset input
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/
SBWTCK
7
I
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC
1
Digital supply voltage
DVSS
8
Digital ground reference
(1)
4
The GPIOs P1.0, P1.1, P1.3, P1.4, P2.6, and P2.7 are implemented but not available on the device pinout. To avoid floating inputs,
these digital I/Os should be properly configured. The pullup or pulldown resistors of the unbounded P1.x GPIOs should be enabled, and
the VLO should be selected as the ACLK source (see the MSP430x2xx Family User's Guide (SLAU144)).
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Table 3. Terminal Functions, MSP430G2230 (1)
TERMINAL
NAME
P1.2/
TA0.1/
A2
P1.5/
TA0.0/
A5/
SCLK
P1.6/
TA0.1/
A6/
SDO/
SCL
NO.
D
2
3
4
DESCRIPTION
I/O
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare Out1 output
ADC10 analog input A2
I/O
General-purpose digital I/O pin
Timer_A, compare Out0 output
ADC10 analog input A5
USI: clock input in I2C mode; clock input/output in SPI mode
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1B input, compare: Out1 output
ADC10 analog input A6
USI: Data output in SPI mode
USI: I2C clock in I2C mode
General-purpose digital I/O pin
ADC10 analog input A7
USI: Data input in SPI mode
USI: Data input in I2C mode
P1.7/
A7/
SDI/
SDA
5
I/O
RST/
NMI/
SBWTDIO
6
I
Reset input
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/
SBWTCK
7
I
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC
1
Digital supply voltage
DVSS
8
Digital ground reference
(1)
The GPIOs P1.0, P1.1, P1.3, P1.4, P2.6, and P2.7 are implemented but not available on the device pinout. To avoid floating inputs,
these digital I/Os should be properly configured. The pullup or pulldown resistors of the unbounded P1.x GPIOs should be enabled, and
the VLO should be selected as the ACLK source (see the MSP430x2xx Family User's Guide (SLAU144)).
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SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
Instruction Set
General-Purpose Register
R11
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 4 shows examples of the three types of
instruction formats; Table 5 shows the address
modes.
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
Table 4. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 ---> R5
Single operands, destination only
CALL R8
PC -->(TOS), R8--> PC
Relative jump, un/conditional
JNE
Jump-on-equal bit = 0
Table 5. Address Mode Descriptions
ADDRESS MODE
6
D
(1)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 --> R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)--> M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) --> M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) --> M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) --> M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) --> R11
R10 + 2--> R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 --> M(TONI)
(1)
S
(1)
OPERATION
S = source, D = destination
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Operating Modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake the device from any of the five low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active. MCLK is disabled
– DCO's dc-generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0x0FFFF to
0x0FFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0x0FFFE) contains 0x0FFFF (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 6. Interrupt Sources
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog Timer+
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
Reset
0xFFFE
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
(non)-maskable,
(non)-maskable,
(non)-maskable
0xFFFC
30
0xFFFA
29
0xFFF8
28
0xFFF6
27
maskable
0xFFF4
26
maskable
0xFFF2
25
maskable
0xFFF0
24
0xFFEE
23
Comparator_A+
(MSP430G2210 Only)
CAIFG
Watchdog Timer+
WDTIFG
Timer_A2
Timer_A2
TACCR0 CCIFG
(4)
TACCR1 CCIFG, TAIFG (2) (4)
0xFFEC
22
ADC10 (MSP430G2230 Only)
ADC10IFG (4)
maskable
0xFFEA
21
USI (MSP430G2230 Only)
USIIFG, USISTTIFG (2) (4)
maskable
0xFFE8
20
0xFFE6
19
I/O Port P1(four flags)
P1IFG.2, P1IFG.5, P1IFG.6, and
P1IFG.7 (2) (4) (5)
0xFFE4
18
0xFFE2
17
See
(1)
(2)
(3)
(4)
(5)
(6)
8
(4)
(6)
maskable
0xFFE0
16
0xFFDE to 0xFFC0
15 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
All eight interrupt flags P1IFG.0 to P1IFG.7 are implemented while four are connected to pins.
The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 7. Interrupt Enable Register 1 and 2
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval
timer mode.
Oscillator fault interrupt enable. Set to 0.
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
2
1
0
01h
Table 8. Interrupt Flag Register 1 and 2
Address
7
6
5
02h
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault. The XIN/XOUT pins are not available as device terminals.
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set by RST/NMI pin
7
6
5
4
3
2
1
0
03h
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Memory Organization
Table 9. Memory Organization
MSP430G22x0
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
2KB Flash
0xFFFF-0xFFC0
0xFFFF-0xF800
Information memory
Size
Flash
256 Byte
0x10FF - 0x1000
RAM
Size
128 Byte
0x027F - 0x0200
Peripherals
16-bit
8-bit
8-bit SFR
0x01FF - 0x0100
0x00FF - 0x0010
0x000F - 0x0000
Flash Memory
The flash memory can be programmed by the Spy-Bi-Wire or JTAG port, or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
10
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally-controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF (VLOCLK) oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
NOTE
The LFXT1 oscillator is not available. LFXT1Sx bits of the BCSCTL3 register should be
configured to use VLOCLK (see the MSP430x2xx Family User's Guide (SLAU144)).
Table 10. DCO Calibration Data (Provided From
Factory in Flash Information Memory Segment A)
DCO
FREQUENCY
1 MHz
8 MHz
12 MHz
16 MHz
CALIBRATION
REGISTER
SIZE
ADDRESS
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
CALBC1_8MHZ
byte
010FDh
CALDCO_8MHZ
byte
010FCh
CALBC1_12MHZ
byte
010FBh
CALDCO_12MHZ
byte
010FAh
CALBC1_16MHZ
byte
010F9h
CALDCO_16MHZ
byte
010F8h
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are four pins of one 8-bit I/O port implemented—port P1:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all the four bits of port P1.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
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Watchdog Timer (WDT+)
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 11. Timer_A2 Signal Connections - MSP430G2210
INPUT PIN
NUMBER
OUTPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
TACLK
TACLK
Timer
NA
ACLK
ACLK
SMCLK
SMCLK
-
TACLK
INCLK
-
TA0
CCI0A
CCR0
TA0
3 - P1.5
ACLK (internal)
CCI0B
VSS
GND
CCR1
TA1
2 - P1.2
D
-
2 - P1.2
VCC
VCC
TA1
CCI1A
CAOUT
(internal)
CCI1B
VSS
GND
VCC
VCC
D
4 - P1.6
Table 12. Timer_A2 Signal Connections - MSP430G2230
INPUT PIN
NUMBER
D
-
-
12
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
TACLK
TACLK
Timer
NA
CCR0
TA0
CCR1
TA1
ACLK
ACLK
SMCLK
SMCLK
TACLK
INCLK
TA0
CCI0A
ACLK (internal)
CCI0B
VSS
GND
VCC
VCC
2 - P1.2
TA1
CCI1A
4 - P1.6
TA1
CCI1B
VSS
GND
VCC
VCC
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OUTPUT PIN
NUMBER
D
2 - P1.2
4 - P1.6
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USI (MSP430G2230 Only)
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
ADC10 (MSP430G2230 Only)
The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
Comparator_A+ (MSP430G2210 Only)
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals
Peripheral File Map
Table 13. Peripherals With Word Access
ADC10
(MSP430G2230 Only)
ADC control 0
ADC10 control 1
ADC memory
Timer_A
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
Flash Memory
Flash control 3
Flash control 2
Flash control 1
Watchdog Timer+
Watchdog/timer control
ADC10CTL0
ADC10CTL1
ADC10MEM
01B0h
01B2h
01B4h
TACCR1
TACCR0
TAR
TACCTL1
TACCTL0
TACTL
TAIV
0174h
0172h
0170h
0164h
0162h
0160h
012Eh
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
WDTCTL
0120h
Table 14. Peripherals With Byte Access
ADC10
(MSP430G2230 Only)
Analog Enable
ADC10AE
04Ah
USI
(MSP430G2230 Only)
USI
USI
USI
USI
USI
USICTL0
USICTL1
USICKCTL
USICNT
USISR
078h
079h
07Ah
07Bh
07Ch
Comparator_A+
(MSP430G2210 Only)
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock System+
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P1
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
Copyright © 2012, Texas Instruments Incorporated
control 0
control 1
clock control
bit counter
shift register
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Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
-0.3 V to 4.1 V
Voltage applied to any pin (2)
-0.3 V to VCC + 0.3 V
Diode current at any device terminal
Storage temperature (3)
Tstg
(1)
±2 mA
Unprogrammed device
-55°C to 150°C
Programmed device
-40°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
(3)
Recommended Operating Conditions
MIN
VCC
Supply voltage
VSS
Supply voltage
TA
Operating free-air temperature
(1)
(2)
MAX
During program execution
1.8
3.6
During flash program/erase
2.2
3.6
0
Processor frequency (maximum MCLK frequency) (1) (2)
fSYSTEM
NOM
UNIT
V
V
-40
85
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
6
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC ≥ 3.3 V,
Duty cycle = 50% ± 10%
dc
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency −MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage −V
Note:
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 5. Safe Operating Area
14
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
Active mode (AM)
current (1 MHz)
IAM,1MHz
(1)
TEST CONDITIONS
TA
VCC
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 0 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
MIN
TYP
2.2 V
220
3V
300
MAX
UNIT
µA
370
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Typical Characteristics – Active Mode Supply Current (Into VCC)
ACTIVE MODE CURRENT
vs
VCC
(TA = 25°C)
ACTIVE MODE CURRENT
vs
DCO FREQUENCY
4.0
5.0
Active Mode Current − mA
Active Mode Current − mA
f DCO = 16 MHz
4.0
3.0
f DCO = 12 MHz
2.0
1.0
f DCO = 8 MHz
TA = 25°C
2.0
TA = 85°C
1.0
2.0
2.5
VCC = 3 V
TA = 25°C
VCC = 2.2 V
f DCO = 1 MHz
0.0
1.5
TA = 85°C
3.0
3.0
VCC − Supply Voltage − V
Figure 6.
Copyright © 2012, Texas Instruments Incorporated
3.5
4.0
0.0
0.0
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 7.
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TA
VCC
Low-power mode 0
(LPM0) current (2)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
25°C
2.2 V
65
ILPM2
Low-power mode 2
(LPM2) current (3)
fMCLK = fSMCLK = 0 MHz, fDCO = 1
MHz,
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
25°C
2.2 V
22
29
µA
ILPM3,VLO
Low-power mode 3
(LPM3) current (3)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator
(VLO),
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
25°C
2.2 V
0.5
0.7
µA
0.5
ILPM4
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
0.1
Low-power mode 4
(LPM4) current (4)
0.8
1.5
ILPM0,1MHz
(1)
(2)
(3)
(4)
16
TEST CONDITIONS
25°C
85°C
2.2 V
MIN
TYP
MAX
UNIT
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
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Schmitt-Trigger Inputs (Port P1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Input voltage hysteresis
(VIT+ - VIT-)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
TYP
MAX
0.45 VCC
0.75 VCC
1.35
2.25
3V
UNIT
V
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1.0
V
50
kΩ
20
35
V
5
pF
Leakage Current (Port P1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
VCC
(1) (2)
High-impedance leakage current
MIN
/3 V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs (Port P1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
VOL
(1)
TEST CONDITIONS
I(OHmax) = -6 mA (1)
High-level output voltage
Low-level output voltage
I(OLmax) = 6 mA
(1)
VCC
MIN
MAX
UNIT
3V
VCC - 0.6
TYP
VCC
V
3V
VSS
VSS + 0.6
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Port P1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency
(with load)
CL = 20 pF, RL = 1 kΩ
fPort°CLK
Clock output frequency
CL = 20 pF (2)
(1)
(2)
(1) (2)
VCC
MIN
TYP
MAX
UNIT
3V
12
MHz
3V
16
MHz
A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC = 2.2 V
P1.7
TA = 25°C
25.0
TA = 85°C
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
30.0
VCC = 3 V
P1.7
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
VOL − Low-Level Output Voltage − V
1.5
2.0
2.5
Figure 9.
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
3.0
3.5
0.0
VCC = 2.2 V
P1.7
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
1.0
Figure 8.
−5.0
−10.0
−15.0
TA = 85°C
−20.0
TA = 25°C
0.5
1.0
1.5
2.0
VOH − High-Level Output Voltage − V
Figure 10.
18
0.5
VOL − Low-Level Output Voltage − V
0.0
−25.0
0.0
TA = 25°C
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2.5
VCC = 3 V
P1.7
−10.0
−20.0
−30.0
TA = 85°C
−40.0
TA = 25°C
−50.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 11.
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SLAS753D – JANUARY 2012 – REVISED AUGUST 2012
POR/Brownout Reset (BOR) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VCC(start)
See Figure 12
dVCC/dt ≤ 3 V/s
0.7 ×
V(B_IT–)
V(B_IT–)
See Figure 12 through Figure 14
dVCC/dt ≤ 3 V/s
1.35
Vhys(B_IT–)
See Figure 12
dVCC/dt ≤ 3 V/s
140
td(BOR)
See Figure 12
t(reset)
Pulse duration needed at RST/NMI pin to
accept reset internally
(1)
MAX
V
1
V
mV
2000
3V
UNIT
2
µs
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT–)is ≤ 1.8 V.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 12. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics – POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
20
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Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Supply voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3.0
3.6
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3V
0.12
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3V
0.15
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3V
0.21
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3V
0.30
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3V
0.41
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3V
0.58
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3V
0.80
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3V
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3V
1.6
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3V
2.3
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3V
3.4
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3V
4.25
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3V
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3V
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3V
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
15.25
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
21
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
ratio
SDCO
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
ratio
3V
50
Copyright © 2012, Texas Instruments Incorporated
0.14
V
fDCO(0,0)
Duty cycle
0.06
UNIT
0.80
MHz
1.50
4.3
7.30
7.8
8.6
MHz
MHz
MHz
MHz
13.9
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%
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Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over temperature
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
3
%
8-MHz tolerance over temperature
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±1.0
3
%
12-MHz tolerance over temperature
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±1.0
3
%
16-MHz tolerance over temperature
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±2.0
3
%
MIN
TYP
MAX
Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TA
VCC
1-MHz tolerance over VCC
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
TEST CONDITIONS
UNIT
25°C
1.8 V to 3.6 V
-3
±2
+3
%
8-MHz tolerance over VCC
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
25°C
1.8 V to 3.6 V
-3
±2
+3
%
12-MHz tolerance over VCC
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
25°C
2.2 V to 3.6 V
-3
±2
+3
%
16-MHz tolerance over VCC
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
25°C
3 V to 3.6 V
-6
±2
+3
%
MIN
TYP
MAX
Calibrated DCO Frequencies - Overall Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TA
VCC
1-MHz tolerance overall
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
I: -40°C to 85°C
1.8 V to 3.6 V
-5
±2
+5
%
8-MHz tolerance overall
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
I: -40°C to 85°C
1.8 V to 3.6 V
-5
±2
+5
%
12-MHz tolerance overall
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
I: -40°C to 85°C
2.2 V to 3.6 V
-5
±2
+5
%
16-MHz tolerance overall
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
I: -40°C to 85°C
3 V to 3.6 V
-6
±3
+6
%
22
TEST CONDITIONS
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Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
tDCO,LPM3/4
BCSCTL1 = CALBC1_8MHZ,
DCO clock wake-up time DCOCTL = CALDCO_8MHZ
from LPM3/4 (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
(1)
(2)
UNIT
2
2.2 V, 3 V
1.5
µs
1
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
tCPU,LPM3/4
MAX
3V
CPU wake-up time from
LPM3/4 (2)
1
1 / fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4
DCO WAKE-UP TIME FROM LPM3
vs
DCO FREQUENCY
DCO Wake Time − us
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 15.
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MSP430G22x0
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Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TA
VCC
MIN
4
fVLO
VLO frequency
-40°C to 85°C
3V
dfVLO/dT
VLO frequency temperature drift (1)
-40°C to 85°C
3V
dfVLO/dVCC
VLO frequency supply voltage drift (2)
25°C
1.8 V to 3.6 V
(1)
(2)
TYP
MAX
12
20
UNIT
kHz
0.5
%/°C
4
%/V
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
Internal: SMCLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TAx
VCC
MIN
3V
TYP
MAX UNIT
fSYSTEM
MHz
20
ns
USI, Universal Serial Interface (MSP430G2230 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fUSI
USI clock frequency
VOL,I2
Low-level output voltage on SDA
and SCL
C
VCC
External: SCLK,
Duty cycle = 50% ±10%,
SPI slave mode USI module in I2C mode,
I(OLmax) = 1.5 mA
MIN
TYP
MAX
fSYSTEM
3V
VSS
UNIT
MHz
VSS + 0.4
V
Typical Characteristics, USI Low-Level Output Voltage on SDA and SCL (MSP430G2230 Only)
USI LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
USI LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.0
5.0
TA = 25°C
4.0
3.0
TA = 85°C
2.0
1.0
0.0
0.0
0.2
0.4
0.6
0.8
VOL − Low-Level Output Voltage − V
Figure 16.
24
TA = 25°C
VCC = 3 V
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1.0
I OL − Low-Level Output Current − mA
I OL − Low-Level Output Current − mA
VCC = 2.2 V
4.0
TA = 85°C
3.0
2.0
1.0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
VOL − Low-Level Output V oltage − V
Figure 17.
Copyright © 2012, Texas Instruments Incorporated
MSP430G22x0
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SLAS753D – JANUARY 2012 – REVISED AUGUST 2012
Comparator_A+ (MSP430G2210 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
(1)
I(DD)
I(Refladder/
RefDiode)
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
CAON = 1, CARSEL = 0, CAREF = 0
3V
45
µA
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
No load at CA0 and CA1
3V
45
µA
V(IC)
Common–mode input voltage
CAON = 1
3V
V(Ref025)
(Voltage at 0.25 VCC node) / VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at CA0 and CA1
3V
0.24
V(Ref050)
(Voltage at 0.5 VCC node) / VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at CA0 and CA1
3V
0.48
V(RefVT)
See Figure 18 and Figure 19
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at CA0 and CA1, TA = 85°C
3V
490
mV
V(offset)
Offset voltage (2)
3V
±10
mV
Vhys
Input hysteresis
3V
0.7
mV
120
ns
1.5
µs
t(response)
(1)
(2)
Response time
(low-to-high and high-to-low)
CAON = 1
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1
0
VCC-1
V
3V
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
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Typical Characteristics – Comparator_A+ (MSP430G2210 Only)
650
650
VCC = 2.2 V
600
V(REFVT) − Reference Volts −mV
V(REFVT) − Reference Volts −mV
VCC = 3 V
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
95
600
Typical
550
500
450
400
−45
115
−25
TA − Free-Air Temperature − °C
−5
15
35
55
75
95
115
TA − Free-Air Temperature − °C
Figure 18. V(RefVT) vs Temperature, VCC = 3 V
Figure 19. V(RefVT) vs Temperature, VCC = 2.2 V
Short Resistance − kOhms
100.00
VCC = 1.8V
VCC = 2.2V
10.00
VCC = 3.0V
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC − Normalized Input Voltage − V/V
Figure 20. Short Resistance vs VIN/VCC
26
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10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2230 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
TEST CONDITIONS
Analog supply voltage
VAx
Analog input voltage
IADC10
IREF+
VCC
VSS = 0 V
(2)
ADC10 supply current
TA
(3)
Reference supply current,
reference buffer disabled (4)
All Ax terminals, Analog inputs
selected in ADC10AE register
fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
3V
25°C
3V
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
0.6
mA
0.25
25°C
3V
mA
0.25
IREFB,0
fADC10CLK = 5.0 MHz,
Reference buffer supply
ADC10ON = 0, REFON = 1,
current with ADC10SR = 0 (4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
25°C
3V
1.1
mA
IREFB,1
fADC10CLK = 5.0 MHz,
Reference buffer supply
ADC10ON = 0, REFON = 1,
current with ADC10SR = 1 (4) REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
25°C
3V
0.5
mA
CI
Input capacitance
Only one terminal Ax can be selected
at one time
25°C
3V
RI
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
25°C
3V
(1)
(2)
(3)
(4)
27
1000
pF
Ω
The leakage current is defined in the leakage current table with Px.y/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied by terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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MSP430G22x0
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10-Bit ADC, Built-In Voltage Reference (MSP430G2230 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC,REF+
IVREF+ ≤ 1 mA, REF2_5V = 0
Positive built-in reference
analog supply voltage range IVREF+ ≤ 1 mA, REF2_5V = 1
VREF+
Positive built-in reference
voltage
ILD,VREF+
Maximum VREF+ load
current
VREF+ load regulation
IVREF+ ≤ IVREF+max, REF2_5V = 0
IVREF+ ≤ IVREF+max, REF2_5V = 1
VCC
MIN
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
MAX
2.2
3V
UNIT
V
2.9
1.41
1.5
1.59
2.35
2.5
2.65
3V
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
TYP
±1
V
mA
±2
3V
LSB
±2
VREF+ load regulation
response time
IVREF+ = 100 µA→900 µA,
VAx ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
ADC10SR = 0
3V
400
ns
CVREF+
Maximum capacitance at
pin VREF+
IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
3V
100
pF
TCREF+
Temperature coefficient (1)
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA
3V
±100
ppm/
°C
tREFON
Settling time of internal
reference voltage to 99.9%
VREF
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
3.6 V
30
µs
tREFBURST
Settling time of reference
buffer to 99.9% VREF
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
3V
2
µs
(1)
28
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
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10-Bit ADC, External Reference (MSP430G2230 Only) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VEREF+
TEST CONDITIONS
Positive external reference input
voltage range (2)
1.4
3
0
1.2
V
1.4
VCC
V
Differential external reference
input voltage range,
ΔVEREF = VEREF+ – VEREF–
VEREF+ > VEREF–
(1)
(2)
(3)
(4)
(5)
UNIT
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
ΔVEREF
Static input current into VEREF–
MAX
VCC
VEREF+ > VEREF–
IVEREF–
TYP
1.4
Negative external reference input
voltage range (4)
Static input current into VEREF+
MIN
VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
VEREF–
IVEREF+
VCC
V
(5)
0 V ≤ VEREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
3V
±1
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
3V
0
0 V ≤ VEREF– ≤ VCC
3V
±1
µA
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters (MSP430G2230 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in oscillator
frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn-on settling time of
the ADC
(1)
ADC10SR = 1
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
3V
3.7
6.3
3V
2.06
3.51
3V
UNIT
MHz
MHz
µs
13 ×
ADC10DIV ×
1/fADC10CLK
fADC10CLK from ACLK, MCLK, or SMCLK:
ADC10SSELx ≠ 0
(1)
100
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
10-Bit ADC, Linearity Parameters (MSP430G2230 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
EI
Integral linearity error
PARAMETER
3V
±1
LSB
ED
Differential linearity error
3V
±1
LSB
EO
Offset error
3V
±1
LSB
EG
Gain error
3V
±1.1
±2
LSB
ET
Total unadjusted error
3V
±2
±5
LSB
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TEST CONDITIONS
Source impedance RS < 100 Ω
VCC
MIN
TYP
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MSP430G22x0
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10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2230 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISENSOR
Temperature sensor supply
current (1)
TCSENSOR
TEST CONDITIONS
VCC
REFON = 0, INCHx = 0Ah,
TA = 25°C
ADC10ON = 1, INCHx = 0Ah
(2)
60
3V
3.55
tSensor(sample)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3V
IVMID
Current into divider at channel 11
ADC10ON = 1, INCHx = 0Bh
3V
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≈ 0.5 × VCC
3V
tVMID(sample)
Sample time required if channel
11 is selected (5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
3V
(2)
(3)
(4)
(5)
30
TYP
3V
Sample time required if channel
10 is selected (3)
(1)
MIN
MAX
µA
mV/°C
30
µs
(4)
1.5
1220
UNIT
µA
V
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V, 3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V, 3.6 V
1
7
mA
tCPT
Cumulative program time (1)
2.2 V, 3.6 V
10
ms
tCMErase
Cumulative mass erase time
2.2 V, 3.6 V
20
ms
4
Program and erase endurance
5
10
10
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
(2)
30
tFTG
tBlock,
Block program time for first byte or word
(2)
25
tFTG
tBlock, 1-63
Block program time for each additional byte or
word
(2)
18
tFTG
tBlock,
Block program end-sequence wait time
(2)
6
tFTG
tMass Erase
Mass erase time
(2)
10593
tFTG
tSeg Erase
Segment erase time
(2)
4819
tFTG
(1)
(2)
0
End
100
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
(1)
TEST CONDITIONS
MIN
CPU halted
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V, 3 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V, 3 V
15
RInternal
Internal pulldown resistance on TEST
2.2 V, 3 V
25
(1)
VCC
MIN
TYP
60
100
µs
90
kΩ
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
After the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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MSP430G22x0
SLAS753D – JANUARY 2012 – REVISED AUGUST 2012
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APPLICATION INFORMATION
Port (P1.2 and P1.5) Pin Schematics - MSP430G2210
To Comparator
from Comparator
CAPD.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
PxSEL.y
PxOUT.y
From Module
0
1
1
0
1
Bus
Keeper
EN
P1.2/TA0.1/CA2
P1.5/TA0.0/CA5
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Figure 21.
Table 15. Port P1 (P1.2 to P1.5) Pin Functions - MSP430G2210
PIN NAME (P1.x)
x
P1.2/
2
CA2
P1.5/
5
CA5
32
P1DIR.x
P1SEL.x
CAPD.y
0
0
TA0.1
1
1
0
TA0.CCI1A
0
1
0
CA2
X
X
1 (y = 2)
0
P1.x (I/O)
TA0.0/
CONTROL BITS AND SIGNALS (1)
I: 0; O: 1
P1.x (I/O)
TA0.1/
(1)
FUNCTION
I: 0; O: 1
0
TA0.0
1
1
0
CA5
X
Xx
1 (y = 5)
X = don't care
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Port P1 (P1.6 and 1.7) Pin Schematic - MSP430G2210
To Comparator
From Comparator
CAPD.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
From Module
DVSS
0
DV CC
1
1
0
1
P1.6/TA0.1/CA6
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Figure 22.
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To Comparator
From Comparator
CAPD.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
DVSS
0
DV CC
1
1
0
1
From Module
P1.7/CAOUT/CA7
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Figure 23.
Table 16. Port P1 (P1.6 and P1.7) Pin Functions - MSP430G2210
PIN NAME (P1.x)
x
P1.6/
FUNCTION
P1.x (I/O)
TA0.1/
6
TA0.1
CA6
CA6
P1.7/
P1.x (I/O)
CA7/
7
CAOUT
(1)
34
CONTROL BITS AND SIGNALS (1)
P1DIR.x
P1SEL.x
CAPD.y
I: 0; O: 1
0
0
1
1
0
1 (y = 6)
X
X
I: 0; O: 1
0
0
CA7
X
X
1 (y = 7)
CAOUT
1
1
0
X = don't care
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SLAS753D – JANUARY 2012 – REVISED AUGUST 2012
Port P1 (P1.2 ) Pin Schematics - MSP430G2230
To ADC10
INCHx = y
ADC10AE.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxREN.y
DVSS
DVCC
PxSEL.y
PxOUT.y
0
1
1
0
1
From Module
Bus
Keeper
EN
P1.2/TA0.1/A2
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Figure 24.
Table 17. Port P1 (P1.2) Pin Functions - MSP430G2230
CONTROL BITS AND SIGNALS (1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
ADC10AE.x
(INCH.y = 1)
P1.2/
P1.x (I/O)
I: 0; O: 1
0
0
TA0.1/
TA0.1
1
1
0
TA0.CCI1A
0
1
0
A2
X
X
1 (y = 2)
A2
(1)
2
X = don't care
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MSP430G22x0
SLAS753D – JANUARY 2012 – REVISED AUGUST 2012
www.ti.com
Port P1 (P1.5 ) Pin Schematics - MSP430G2230
To ADC10
INCHx = y
ADC10AE.y
PxDIR.y
USI Module Direction
0
1
Direction
0: Input
1: Output
USIPE5
PxREN.y
PxSEL.y
DVSS
DVCC
PxOUT.y
From Module
0
1
1
0
1
Bus
Keeper
EN
P1.5/TA0.0/SCLK/A5
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Figure 25.
Table 18. Port P1 (P1.5) Pin Functions - MSP430G2230
PIN NAME
(P1.x)
CONTROL BITS AND SIGNALS (1)
x
FUNCTION
P1DIR.x
P1SEL.x
USIP.x
ADC10AE.x
(INCH.y = 1)
INCHx
P1.5/
P1.x (I/O)
I: 0; O: 1
0
0
0
X
TA0.0/
TA0.0
1
1
0
0
X
SCLK
X
X
1
X
X
A5
X
X
X
1 (y = 5)
5
5
SCLK/
A5
(1)
36
X = don't care
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MSP430G22x0
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SLAS753D – JANUARY 2012 – REVISED AUGUST 2012
Port P1 (P1.6 and 1.7) Pin Schematic - MSP430G2230
To ADC10
INCHx
ADC10AE0.y
PxDIR.y
from USI
USIPE6
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y or
USIP E6
PxOUT.y
From USI
DVSS
0
DV CC
1
1
0
1
Bus
Keeper
EN
P1.6/TA0.1/SDO/SCL/A6
PxSEL.y
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
USI in I2C mode: Output driver drives low level only.
Figure 26.
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To ADC10
INCHx
ADC10AE0.y
USIPE7
PxDIR.y
1
Direction
0: Input
1: Output
0
from USI
PxSEL.y
PxREN.y
PxSEL.y or
USIPE7
PxOUT.y
0
From USI
1
DVSS
0
DVCC
1
1
Bus
Keeper
EN
P1.7/SDI/SDA/A7
PxSEL.y
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
USI in I2C mode: Output driver drives low level only.
Figure 27.
Table 19. Port P1 (P1.6 and P1.7) Pin Functions - MSP430G2230
PIN NAME
(P1.x)
CONTROL BITS AND SIGNALS (1)
x
FUNCTION
P1DIR.x
P1SEL.x
USIP.x
ADC10AE.x
(INCH.y = 1)
P1.6/
P1.x (I/O)
I: 0; O: 1
0
0
0
TA0.1/
TA0.CCI1A
0
1
0
0
TA0.1
1
1
0
0
0
6
SDO/
SPI Mode
from USI
1
1
SCL/
I2C Mode
from USI
1
1
0
A6
A6
X
X
0
1 (y = 6)
P1.7/
P1.x (I/O)
I: 0; O: 1
0
0
0
SDI/
SDI
X
1
1
0
SDA
X
1
1
0
A7
X
X
0
1 (y = 7)
7
SDA/
A7
(1)
38
X = don't care
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MSP430G22x0
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SLAS753D – JANUARY 2012 – REVISED AUGUST 2012
REVISION HISTORY
Literature
Number
Comments
SLAS753
Production Data release
SLAS753A
Changed Table 11.
Added Table 12.
SLAS753B
Corrected "Basic Clock Module Configurations" list in Features.
Added note to TCREF+ in 10-Bit ADC, Built-In Voltage Reference (MSP430G2230 Only).
SLAS753C
Added Flash Memory.
SLAS753D
Table 15, Removed ADC10AE.x column and removed A2 and A5 rows (no ADC on this device).
Table 18, Added USIP.x column.
Table 19, Added "(INCH.y = 1)" to ADC10AE.x column header.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430G2210ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430G2210IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430G2230ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430G2230IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430G2230 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
• Enhanced Product: MSP430G2230-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
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