TI1 LM5100A High-voltage, high-side and low-side gate driver Datasheet

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LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015
LM5100A/B/C, LM5101A/B/C 3-A, 2-A, and 1-A High-Voltage, High-Side
and Low-Side Gate Drivers
1 Features
•
1
•
•
•
•
•
•
•
•
Drives Both a High-Side and Low-Side N-Channel
MOSFETs
Independent High- and Low-Driver Logic Inputs
Bootstrap Supply Voltage up to 118 V DC
Fast Propagation Times (25-ns Typical)
Drives 1000-pF Load With 8-ns Rise and Fall
Times
Excellent Propagation Delay Matching (3-ns
Typical)
Supply Rail Undervoltage Lockout
Low Power Consumption
Pin Compatible With HIP2100/HIP2101
An integrated high-voltage diode is provided to
charge the high-side gate drive bootstrap capacitor. A
robust level shifter operates at high speed while
consuming low power and providing clean level
transitions from the control logic to the high-side gate
driver. Undervoltage lockout is provided on both the
low-side and the high-side power rails. These devices
are available in the standard SOIC-8 pin, SO
PowerPAD-8 pin, and the WSON-10 pin packages.
The LM5100C and LM5101C are also available in
MSOP-PowerPAD-8 package. The LM5101A is also
available in WSON-8 pin package.
Device Information(1)
PART NUMBER
INPUT THRESHOLD
PEAK OUTPUT
CURRENT
LM5100A
CMOS
3A
2 Applications
LM5101A
TTL
3A
•
•
•
•
•
LM5100B
CMOS
2A
LM5101B
TTL
2A
LM5100C
CMOS
1A
LM5101C
TTL
1A
Current-Fed Push-Pull Converters
Half and Full Bridge Power Converters
Synchronous Buck Converters
Two Switch Forward Power Converters
Forward with Active Clamp Converters
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
The LM5100A/B/C and LM5101A/B/C high-voltage
gate drivers are designed to drive both the high-side
and the low-side N-Channel MOSFETs in a
synchronous buck or a half-bridge configuration. The
floating high-side driver is capable of operating with
supply voltages up to 100 V. The A versions provide
a full 3-A of gate drive, while the B and C versions
provide 2 A and 1 A, respectively. The outputs are
independently controlled with CMOS input thresholds
(LM5100A/B/C) or TTL input thresholds
(LM5101A/B/C).
Simplified Block Diagram
HB
UVLO
LEVEL
SHIFT
DRIVER
HO
HS
HI
VDD
UVLO
LI
DRIVER
LO
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics ......................................... 6
Switching Characteristics......................................... 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (March 2013) to Revision Q
•
Page
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
Changes from Revision O (March 2013) to Revision P
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 19
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SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015
5 Device Comparison Table
PART NUMBER
PACKAGE
LM5100A, LM5100C
LM5100B, LM5101B
LM5101A
LM5101C
BODY SIZE (NOM)
WSON (10)
4.00 mm × 4.00 mm
SO PowerPAD™ (8)
3.90 mm × 4.89 mm
SOIC (8)
3.91 mm × 4.90 mm
WSON (10)
4.00 mm × 4.00 mm
SOIC (8)
3.91 mm × 4.90 mm
WSON (8)
4.00 mm × 4.00 mm
WSON (10)
4 .00mm × 4.00 mm
SO PowerPAD (8)
3.90 mm × 4.89 mm
SOIC (8)
3.91 mm × 4.90 mm
MSOP PowerPAD (8)
3.00 mm × 3.00 mm
WSON (10)
4.00 mm × 4.00 mm
SOIC (8)
3.91 mm × 4.90 mm
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
VDD
1
HB
2
DPR Package
10-Pin WSON With Exposed Thermal Pad
Top View
8
LO
7
LO
VDD
1
10
VSS
HB
2
9
VSS
HO
3
8
LI
HS
4
7
HI
NC
5
6
NC
SOIC-8
HO
3
6
LI
HS
4
5
HI
NGT Package
8-Pin WSON With Exposed Thermal Pad
Top View
VDD
1
8
LO
HB
2
7
VSS
HO
3
6
LI
WSON-10
DDA Package
8-Pin SO PowerPAD
Top View
VDD
1
HB
2
8
LO
7
VSS
WSON-8
SO
PowerPad-8
HS
4
5
HI
HO
3
6
LI
HS
4
5
HI
Exposed Pad
Connect to VSS
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3
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015
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DGN Package
8-Pin MSOP-PowerPAD
Top View
VDD
1
HB
2
HO
HS
8
LO
7
VSS
3
6
LI
4
5
HI
MSOPPowerPad-8
Pin Functions
PIN
I/O
DESCRIPTION
2
I
High-side gate driver bootstrap supply. Connect the positive terminal of the bootstrap
capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be
placed as close to the IC as possible.
5
7
I
High-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
HO
3
3
O
High-side gate driver output. Connect to the gate of high-side MOSFET with a short,
low inductance path.
HS
4
4
—
High-side MOSFET source connection. Connect to the bootstrap capacitor negative
terminal and the source of the high-side MOSFET.
LI
6
8
I
Low-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
LO
8
10
O
Low-side gate driver output. Connect to the gate of the low-side MOSFET with a
short, low inductance path.
VDD
1
1
I
Positive gate drive supply . Locally decouple to VSS using low ESR/ESL capacitor
located as close to the IC as possible.
VSS
7
9
—
Ground return. All signals are referenced to this ground.
—
TI recommends that the exposed pad on the bottom of the package is soldered to
ground plane on the PC board, and that ground plane should extend out from
beneath the IC to help dissipate heat.
8 PINS
10 PINS (1)
HB
2
HI
NAME
EP (2)
(1)
(2)
4
For WSON-10 package, pins 5 and 6 have no connection.
Exposed pad is not available on the 8-pin SOIC package.
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SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
See
(1) (2)
MIN
MAX
UNIT
VDD to VSS
−0.3
18
V
HB to HS
−0.3
18
V
LI or HI input
−0.3
VDD + 0.3
V
LO output
−0.3
VDD + 0.3
V
VHS − 0.3
VHB + 0.3
V
−5
100
V
118
V
150
°C
150
°C
HO output
HS to VSS
(3)
HB to VSS
Junction temperature
−55
Storage temperature
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military or Aerospace specified devices are required, contact the Texas Instruments Sales Office or Distributors for availability and
specifications.
In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not
exceed –1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage
transiently. If negative transients occur, the HS voltage must never be more negative than VDD – 15 V. For example if VDD = 10 V, the
negative transients at HS must not exceed –5 V.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
Electrostatic
discharge
Machine Model (MM)
(2)
UNIT
±2000
Option A
50
Option B and C
100
V
The Human Body Model (HBM) is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2 kV for all pins except Pin 2,
Pin 3 and Pin 4 which are rated at 1000 V for HBM.
Machine Model (MM) ratings are: 100 V(MM) for Options B and C; 50 V(MM) for Option A.
7.3 Recommended Operating Conditions
MIN
VDD
NOM
MAX
UNIT
9
14
V
HS
–1
100
V
HB
VHS + 8
VHS + 14
HS slew rate
−40
Junction temperature
Copyright © 2006–2015, Texas Instruments Incorporated
V/ns
125
°C
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V
< 50
5
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015
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7.4 Thermal Information
LM5100A,
LM5100C,
LM5101A
LM5101C
LM5101A
SO PowerPAD
MSOPPowerPAD (2)
WSON (2)
WSON (2)
SOIC
THERMAL METRIC (1)
LM5100x,
LM5101x
UNIT
8 PINS
8 PINS
8 PINS
10 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance (3)
40
80
37.8
40
170
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
—
—
36.7
—
—
°C/W
RθJB
Junction-to-board thermal resistance
—
—
14.9
—
—
°C/W
ψJT
Junction-to-top characterization parameter
—
—
0.3
—
—
°C/W
ψJB
Junction-to-board characterization parameter
—
—
15.2
—
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
4.4
—
—
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4-layer board with Cu finished thickness 1.5, 1, 1, 1.5 oz. Maximum die size used. 5× body length of Cu trace on PCB top.
50-mm × 50-mm ground and power planes embedded in PCB. See Application Note AN-1187 (SNOA401).
The RθJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
7.5
Electrical Characteristics
unless otherwise specified, limits are for TJ = 25°C, VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO
PARAMETER
TEST CONDITIONS
MIN
(1)
TYP
.
MAX
UNIT
SUPPLY CURRENTS
TJ = 25°C
0.1
VDD quiescent current,
LM5100A/B/C
LI = HI = 0 V
VDD quiescent current,
LM5101A/B/C
LI = HI = 0 V
IDDO
VDD operating current
f = 500 kHz
IHB
Total HB quiescent current
LI = HI = 0 V
IHBO
Total HB operating current
f = 500 kHz
IHBS
HB to VSS current, quiescent
HS = HB = 100 V
IHBSO
HB to VSS current, operating
f = 500 kHz
VIL
Input voltage threshold
LM5100A/B/C
Rising Edge
VIL
Input voltage threshold
LM5101A/B/C
Rising Edge
VIHYS
Input voltage hysteresis
LM5100A/B/C
500
mV
VIHYS
Input voltage hysteresis
LM5101A/B/C
50
mV
RI
Input pulldown resistance
IDD
TJ = –40°C to 125°C
0.2
TJ = 25°C
0.25
TJ = –40°C to 125°C
0.4
TJ = 25°C
2
TJ = –40°C to 125°C
3
TJ = 25°C
0.06
TJ = –40°C to 125°C
0.2
TJ = 25°C
1.6
TJ = –40°C to 125°C
3
TJ = 25°C
0.1
TJ = –40°C to 125°C
10
0.4
mA
mA
mA
mA
mA
µA
mA
INPUT PINS
(1)
6
TJ = 25°C
5.4
TJ = –40°C to 125°C
4.5
TJ = 25°C
1.8
TJ = –40°C to 125°C
1.3
TJ = 25°C
TJ = –40°C to 125°C
6.3
2.3
200
100
400
V
V
kΩ
Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015
Electrical Characteristics (continued)
unless otherwise specified, limits are for TJ = 25°C, VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UNDER VOLTAGE PROTECTION
VDDR
VDD rising threshold
VDDH
VDD threshold hysteresis
VHBR
HB rising threshold
VHBH
HB threshold hysteresis
TJ = 25°C
6.9
TJ = –40°C to 125°C
6
7.4
0.5
TJ = 25°C
V
6.6
TJ = –40°C to 125°C
5.7
V
7.1
0.4
V
V
BOOT STRAP DIODE
VDL
Low-current forward voltage
IVDD-HB = 100 µA
VDH
High-current forward voltage
IVDD-HB = 100 mA
RD
Dynamic resistance
LM5100A/B/C, LM5101A/B/C
IVDD-HB = 100 mA
TJ = 25°C
0.52
TJ = –40°C to 125°C
TJ = 25°C
0.85
0.8
TJ = –40°C to 125°C
TJ = 25°C
1
1.0
TJ = –40°C to 125°C
1.65
V
V
Ω
LO AND HO GATE DRIVER
TJ = 25°C
Low-level output voltage
LM5100A/LM5101A
VOL
VOH
Low-level output voltage
LM5100B/LM5101B
IHO = ILO = 100 mA
TJ = 25°C
TJ = 25°C
0.16
High-level output voltage
LM5100A/LM5101A
TJ = 25°C
0.28
0.65
0.24
TJ = –40°C to 125°C
IHO = ILO = 100 mA
VOH = VDD– LO or
VOH = HB - HO
TJ = 25°C
0.45
0.28
TJ = –40°C to 125°C
TJ = 25°C
0.60
0.6
TJ = –40°C to 125°C
Peak pullup current
LM5100A/LM5101A
IOLL
0.4
TJ = –40°C to 125°C
High-level output voltage
LM5100C/LM5101C
IOHL
0.25
TJ = –40°C to 125°C
Low-level output voltage
LM5100C/LM5101C
High-level output voltage
LM5100B/LM5101B
0.12
TJ = –40°C to 125°C
1.10
V
V
V
V
V
V
3
A
2
A
Peak pullup current
LM5100C/LM5101C
1
A
Peak pulldown current
LM5100A/LM5101A
3
A
2
A
1
A
Peak pullup current
LM5100B/LM5101B
Peak pulldown current
LM5100B/LM5101B
HO, LO = 0 V
HO, LO = 12 V
TJ = 25°C
TJ = 25°C
Peak pulldown current
LM5100C/LM5101C
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7.6
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Switching Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO (1).
PARAMETER
tLPHL
tLPLH
tHPHL
tHPLH
tMON
tMOFF
tRC, tFC
TYP
MAX
20
45
ns
22
56
ns
20
45
ns
26
56
ns
20
45
ns
22
56
ns
20
45
ns
26
56
ns
Delay matching: LO on and HO off
LM5100A/B/C
1
10
ns
Delay matching: LO on and HO off
LM5101A/B/C
4
10
ns
Delay matching: LO off and HO on
LM5100A/B/C
1
10
ns
Delay matching: LO on and HO off
LM5101A/B/C
4
10
ns
LO turnoff propagation delay LM5100A/B/C
LO turnoff propagation delay LM5101A/B/C
LO turnon propagation delay LM5100A/B/C
LO turnon propagation delay LM5101A/B/C
HO turnoff propagation delay
LM5100A/B/C
HO turnoff propagation delay
LM5101A/B/C
LO turnon propagation delay LM5100A/B/C
LO turnon propagation delay LM5101A/B/C
Either output rise and fall time
TEST CONDITIONS
LI Falling to LO Falling
LI Rising to LO Rising
tF
HI Rising to HO Rising
CL = 1000 pF
8
ns
430
ns
570
ns
Output rise time (3 V to 9 V)
LM5100C/LM5101C
990
ns
Output fall time (3 V to 9 V)
LM5100A/LM5101A
260
ns
430
ns
715
ns
50
ns
37
ns
Output rise time (3 V to 9 V)
LM5100B/LM5101B
Output fall time (3 V to 9 V)
LM5100B/LM5101B
CL = 0.1 µF
CL = 0.1 µF
Output fall time (3 V to 9 V)
LM5100C/LM5101C
tPW
Minimum input pulse width that changes
the output
tBS
Bootstrap diode reverse recovery time
(1)
8
UNIT
HI Falling to HO Falling
Output rise time (3 V to 9 V)
LM5100A/LM5101A
tR
MIN
IF = 100 mA,
IR = 100 mA
Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015
LI
LI
HI
HI
tHPLH
tLPLH
tHPHL
tLPHL
LO
LO
HO
HO
tMON
tMOFF
Figure 1. Timing Diagram
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7.7 Typical Characteristics
5.0
5.0
4.5
4.5
4.0
4.0
LM5100A/LM5101A
3.5
CURRENT (A)
CURRENT (A)
3.5
3.0
2.5
2.0
LM5100B/LM5101B
1.5
1.0
2.5
2.0
LM5100B/LM5101B
1.5
1.0
LM5100C/LM5101C
0.5
0.0
LM5100A/LM5101A
3.0
0.0
7
8
9
10
11
12
13
14
LM5100C/LM5101C
0.5
15
7
8
9
10
11
VDD (V)
13
14
15
Figure 3. Peak Sinking Current vs VDD
Figure 2. Peak Sourcing Current vs VDD
3.5
3.5
VDD = 12 V
VDD = 12 V
3.0
3.0
LM5100A/LM5101A
LM5100A/LM5101A
2.5
CURRENT (A)
2.5
CURRENT (A)
12
VDD (V)
2.0
LM5100B/LM5101B
1.5
2.0
LM5100B/LM5101B
1.5
1.0
1.0
LM5100C/LM5101C
0.0
LM5100C/LM5101C
0.5
0.5
0
2
4
8
6
10
0.0
12
0
OUTPUT VOLTAGE (V)
Figure 4. Sink Current vs Output Voltage
100000
2
4
8
10
6
OUTPUT VOLTAGE (V)
Figure 5. Source Current vs Output Voltage
100000
VDD = 12 V
VDD = 12 V
CL = 4400 pF
CL = 4400 pF
CURRENT (μA)
CURRENT (μA)
10000
CL = 1000 pF
1000
100
10
0.1
10000
CL = 1000 pF
1000
CL = 0 pF
1
10
100
CL = 0 pF
1000
FREQUENCY (kHz)
Figure 6. LM5100A/B/C IDD vs Frequency
10
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0.1
1
10
100
1000
FREQUENCY (kHz)
Figure 7. LM5101A/B/C IDD vs Frequency
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Typical Characteristics (continued)
100000
2.3
2.1
HB = 12 V,
HS = 0 V
IDDO (LM5101A/B/C)
1.9
IDDO (LM5100A/B/C)
1.7
CURRENT (PA)
CURRENT (mA)
CL = 4400 pF
10000
IHBO
1.5
1.3
CL = 1000 pF
1000
CL = 0 pF
100
1.1
0.9
0.7
-50 -25
0
25
50
75
10
0.1
100 125 150
1
TEMPERATURE ( oC)
Figure 8. Operating Current vs Temperature
1000
350
350
300
IDD (LM5101A/B/C)
300
IDD (LM5101A/B/C)
250
CURRENT (μA)
CURRENT (μA)
100
Figure 9. IHB vs Frequency
400
250
200
IDD (LM5100A/B/C)
150
200
150
100
100
IHB
50
0
10
FREQUENCY (kHz)
IDD (LM5100A/B/C)
50
IHB
8
9
10
11
12
13
14
15
0
-50 -25
16
VDD, VHB (V)
0
25
50
75
100 125 150
TEMPERATURE (°C)
Figure 10. Quiescent Current vs Supply Voltage
Figure 11. Quiescent Current vs Temperature
7.30
0.60
7.20
0.55
7.00
HYSTERESIS (V)
THRESHOLD (V)
7.10
VDDR
6.90
6.80
6.70
6.60
VDDH
0.50
0.45
VHBH
0.40
VHBR
6.50
0.35
6.40
6.30
-50 -25
0
25
50
75 100 125 150
TEMPERATURE (°C)
Figure 12. Undervoltage Rising Thresholds vs Temperature
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0.30
-50
0
25
TEMPERATURE ( oC)
Figure 13. Undervoltage Threshold Hysteresis vs
Temperature
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Typical Characteristics (continued)
50
1.00E-01
THRESHOLD VOLTAGE (%VDD)
T = 150°C
1.00E-02
ID (A)
1.00E-03
T = 25°C
1.00E-04
T = -40°C
1.00E-05
1.00E-06
0.2
0.3
0.4
0.5
0.6
0.7
0.8
VD (V)
Rising
47
46
45
44
Falling
43
42
41
0
25
50
75 100 125 150
TEMPERATURE (°C)
Figure 15. LM5100A/B/C Input Threshold vs Temperature
1.92
50
1.90
THRESHOLD VOLTAGE (%VDD)
1.91
THRESHOLD VOLTAGE (V)
48
40
-50 -25
0.9
Figure 14. Bootstrap Diode Forward Voltage
49
Rising
1.89
1.88
1.87
1.86
Falling
1.85
1.84
1.83
1.82
1.81
1.80
-50 -25
0
25
50
49
48
46
45
44
43
TEMPERATURE (°C)
Falling
42
41
40
75 100 125 150
Rising
47
8
9
10
11
12
13
14
15
16
VDD (V)
Figure 17. LM5100A/B/C Input Threshold vs VDD
Figure 16. LM5101A/B/C Input Threshold vs Temperature
35
1.92
1.90
Rising
1.89
30
1.88
DELAY (ns)
THRESHOLD VOLTAGE (V)
1.91
1.87
1.86
1.85
Falling
1.84
25
T_PLH
20
1.83
1.82
T_PHL
1.81
1.80
8
9
10
11
12
13
14
15
16
VDD (V)
Figure 18. LM5101A/B/C Input Threshold vs VDD
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15
-50
-25
0
25
50
75 100 125 150
TEMPERATURE (°C)
Figure 19. LM5100A/B/C Propagation Delay vs Temperature
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Typical Characteristics (continued)
1.0
40
VDD = 12 V
0.9
0.8
35
LM5100C/LM5101C
30
VOH (V)
DELAY (ns)
0.7
T_PLH
25
T_PHL
0.6
0.5
LM5100B/LM5101B
0.4
0.3
0.2
20
LM5100A/LM5101A
0.1
15
-50
-25
0
25
50
0.0
-50 -25
75 100 125 150
25
50
75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. LO and HO Gate Drive - High Level Output
Voltage vs Temperature
Figure 20. LM5101A/B/C Propagation Delay vs Temperature
0.50
0
0.8
VDD = 12 V
IOUT = -100 mA
0.45
0.7
0.40
0.6
LM5100C/LM5101C
0.30
0.25
VOH (V)
VOL (V)
0.35
LM5100B/LM5101B
0.20
0.15
LM5100C/LM5101C
0.5
0.4
0.3
0.10
LM5100B/LM5101B
LM5100A/LM5101A
0.05
0.2
0.00
-50 -25
0.1
LM5100A/LM5101A
0
25
50
75 100 125 150
7
8
TEMPERATURE (°C)
9
10
11
12
13
14
15
VDD (V)
Figure 22. LO and HO Gate Drive - Low Level Output
Voltage vs Temperature
Figure 23. LO and HO Gate Drive - Output High Voltage vs
VDD
0.35
IOUT = 100 mA
VOL (V)
0.30
LM5100C/LM5101C
0.25
0.20
LM5100B/LM5101B
0.15
LM5100A/LM5101A
0.10
7
8
9
10
11
12
13
14
15
VDD (V)
Figure 24. LO and HO Gate Drive - Output Low Voltage vs VDD
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8 Detailed Description
8.1 Overview
The LM5100A/B/C and LM5101A/B/C are designed to drive both the high-side and the low-side N-channel FETs
in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with CMOS input
thresholds(LM5101A/B/C) or TTL input thresholds(LM5101A/B/C). The floating high-side driver is capable of
working with supply voltages up to 100 V. An integrated high voltage diode is provided to charge high side gate
drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing
clean level transitions from the control logic to the high side gate driver. Under-voltage lockout is provided on
both the low side and the high side power rails.
8.2 Functional Block Diagram
HB
UVLO
LEVEL
SHIFT
DRIVER
HO
HS
HI
VDD
UVLO
LI
DRIVER
LO
GND
8.3 Feature Description
8.3.1 Start-up and UVLO
Both high and low-side drivers include under voltage lockout (UVLO) protection circuitry which monitors the
supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each
driver until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO
hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD
pin of the LM5100A/B/C and LM5101A/B/C, the outputs of the low-side and high-side are held low until VDD
exceeds the UVLO threshold, typically about 6.6 V. Any UVLO condition on the bootstrap capacitor will disable
only the high-side output (HO).
8.3.2 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
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Feature Description (continued)
8.3.3 Bootstrap Diode
The bootstrap diode necessary to generate the high-side bias is included in the LM5100/1 family. The diode
anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS
pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode
provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable
operation.
8.3.4 Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,
and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The
low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.
8.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO
operation mode. In normal mode, the output stage is dependent on the states of the HI and LI pins.
Table 1. Input/Output Logic Table
LI
HO (1)
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
x (3)
x
L
L
HI
(1)
(2)
(3)
LO (2)
HO is measured with respect to the HS.
LO is measured with the respect to the VSS.
x is floating condition
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
The LM5100A/B/C and LM5101A/B/C are the high voltage gate drivers that are designed to drive both the highside and low-side N-Channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit.
The floating high side driver is capable of operating with supply voltages up to 100 V. This allows for N-Channel
MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies. The
outputs are independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing
full and independent flexibility to control on and off state of the output.
9.2 Typical Application
Optional external
fast recovery diode
VIN
VCC
RBOOT DBOOT
HB
RGATE
HO
VDD
VDD
CBOOT
PWM
Controller
0.1 µF
HI
OUT1
HS
T1
LM5101A
LI
OUT2
LO
RGATE
1.0 µF
VSS
Figure 25. LM5101A Driving MOSFETs in Half-Bridge Configuration
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Typical Application (continued)
9.2.1 Design Requirements
See Table 2 for the parameter and values.
Table 2. Operating Parameters
PARAMETER
VALUE
Gate Driver
LM5101A
MOSFET
CSD18531Q5A
VDD
10 V
Qgmax
43 nC
Fsw
100 kHz
Dmax
95%
IHBS
10 µA
VDH
1.0 V
VHBR
7.1 V
VHBH
0.4 V
9.2.2 Detailed Design Procedure
9.2.2.1 Select Bootstrap and VDD capacitor
The bootstrap capacitor must maintain the HB pin voltage above the UVLO voltage for the HB circuit in any
circumstances during normal operation. Calculate the maximum allowable drop across the bootstrap capacitor
with Equation 1.
ΔVHB = VDD – VDH – VHBL= 10 V – 1.0 V – 6.7 V = 2.3 V
where
•
•
•
VDD = Supply voltage of the gate drive IC
VDH = Bootstrap diode forward voltage drop
VHBL = VHBR – VHBH = 6.7 V, HB falling threshold
(1)
The quiescent current of the bootstrap circuit is 10 µA, which is negligible compared to the Qgs of the MOSFET
(see Equation 2 and Equation 3).
D
0.95
QTOTAL = Qgmax + IHBS MAX = 43 nC + 10 µA
= 43.01nC
FSW
100 kHz
(2)
CBOOT =
QTOTAL 43.01nC
=
=18.7 nF
DVHB
2.3 V
(3)
In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where
the power stage may skip pulse due to load transients. It is recommended to place the bootstrap capacitor as
close to the HB and HS pins as possible.
CBOOT = 100 nF
(4)
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.
CVDD = 10 × CBOOT = 1 µF
(5)
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be
twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across
them and to ensure long-term reliability of the devices.
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9.2.2.2 Select External Bootstrap Diode and Resistor
The bootstrap capacitor is charged by the VDD through the internal bootstrap diode every cycle when low side
MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power
dissipation in the internal bootstrap diode may be significant and dependent on its forward voltage drop. Both the
diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver and need to
be considered in the gate driver IC power dissipation.
For high frequency and high capacitive loads, it may be necessary to consider using an external bootstrap diode
placed in parallel with internal bootstrap diode to reduce power dissipation of the driver. For the selection of
external bootstrap diodes for LM510x device, please refer to the application note SNVA083.
Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of HB-HS. It is recommended that RBOOT is between 2 Ω and 10 Ω. For this design, a current limiting
resistor of 2.2 Ω is selected to limit inrush current of bootstrap diode.
V - VDBOOT 10 V - 0.6 V
IDBOOT(pk ) = DD
=
= 4.27 A
RBOOT
2.2 W
(6)
9.2.2.3 Select Gate driver Resistor
Resistor RGATE is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the
current coming out of the gate driver. For this design 4.7-Ω resistors were selected for this design. Maximum HO
and LO drive current are calculated by Equation 7 through Equation 10.
V - VDH - VOH 10 V - 1.0 V - 0.45 V
IHOH = DD
=
= 1.819 A
RGATE
4.7 W
(7)
ILOH =
IHOL =
ILOL
VDD - VOH 10 V - 0.45 V
=
= 2.032 A
RGATE
4.7 W
(8)
VDD - VDH - VOL 10 V - 1.0 V - 0.25 V
=
= 1.862 A
RGATE
4.7 W
(9)
V - VOH 10 V - 0.25 V
= DD
=
= 2.074 A
RGATE
4.7 W
where
•
•
•
•
•
•
IHOH = Maximum HO source current
ILOH = Maximum LO source current
IHOL = Maximum HO sink current
ILOH = Maximum HO sink current
VOH = High-Level output voltage drop across HB to HO or VDD to LO
VOL = Low-Level output voltage drop across HO to HS or LO to GND
(10)
9.2.2.4 Estimate the Driver Power Losses
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (fsw), output load capacitance on LO and HO (CL), and supply
voltage (VDD). The gate charge losses can be calculated by Equation 11.
2
PDGATES = 2 ´ VDD
´ CL ´ fsw
There are some additional losses in the gate drivers due to
HO outputs. The following plot shows the measured gate
capacitance. At higher frequencies and load capacitance
power losses driving the output loads and agrees well with
the power losses due to the gate drivers.
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the internal CMOS stages used to buffer the LO and
driver power dissipation versus frequency and load
values, the power dissipation is dominated by the
Equation 11. Figure 26 can be used to approximate
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1.000
POWER (W)
CL = 4400 pF
0.100
CL = 1000 pF
0.010
CL = 0 pF
0.001
0.1
1.0
10.0
100.0
1000.0
SWITCHING FREQUENCY (kHz)
Figure 26. Gate Driver Power Dissipation (LO + HO)
VDD = 12 V, Neglecting Diode Losses
The internal bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculation
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the internal diode power dissipation. If the diode losses can be significant, an external
diode placed in parallel with the internal bootstrap diode can be helpful to reduce power dissipation within the IC.
0.100
POWER (W)
CL = 4400 pF
CL = 0 pF
0.010
0.001
1
10
100
1000
SWITCHING FREQUENCY (kHz)
Figure 27. Diode Power Dissipation VIN = 50 V
The total IC power dissipation can be estimated from the plots shown in Figure 26 and Figure 27 by summing the
gate drive losses with the internal bootstrap diode losses for the intended application. For a given ambient
temperature, the maximum allowable power loss of the IC can be defined as equation Equation 12.
T - TA
Ploss = J
RqJA
where
•
•
•
•
Ploss = The total power dissipation of the driver
TJ = Junction temperature
TA = Ambient temperature
RθJA = Junction-to-ambient thermal resistance
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The thermal metrics for the driver package is summarized in the Thermal Information table. For detailed
information regarding the thermal information table, refer to the Application Note from Texas Instruments entitled
Semiconductor and IC Package Thermal Metrics SPRA953.
9.2.3 Application Curves
Figure 28. HI/LI to HO/LO Turnon Propagation Delay
Figure 29. HI/LI to HO/LO Turnoff Propagation Delay
10 Power Supply Recommendations
The bias supply voltage range for which the device is rated to operate is from 9 V to 14 V. The lower end of this
range is governed by the internal under voltage-lockout (UVLO) protection feature on the VDD pin supply circuit
blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VDDR supply start
threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is
driven by the 18-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating).
Keeping a 4-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin
is 14 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDDH.
Therefore, ensuring that, while operating at or near the 9-V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown.
During system shutdown, the device operation continues until the VDD pin voltage has dropped below the
threshold (VDDR – VDDH), which must be accounted for while evaluating system shutdown timing design
requirements. Likewise, at system start up, the device does not begin operation until the VDD pin voltage has
exceeded above the VDDR threshold. The quiescent current consumed by the internal circuit blocks of the device
is supplied through the VDD pin. Keep in mind that the charge for source current pulses delivered by the LO pin
is also supplied through the same VDD pin. As a result, every time a current is sourced out of the LO pin a
corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that a local bypass
capacitor is provided between the VDD and GND pins and located as close as possible to the device for the
purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is necessary. TI recommends
using two capacitors between VDD and GND: a 100-nF ceramic surface-mount capacitor that can be nudged
very close to the pins of the device and another surface-mount capacitor in the range 0.22 µF to 10 µF added in
parallel. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore,
a 0.022-µF to 1-µF local decoupling capacitor is recommended between the HB and HS pins.
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11 Layout
11.1 Layout Guidelines
The optimum performance of high and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. Low-ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak currents being drawn from VDD during turnon of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
– The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
A recommended layout pattern for the driver is shown in Figure 30. If possible a single layer placement is
preferred.
11.2 Layout Example
Recommended Layout for Driver IC and
Passives
VDD
LO
HB
VSS
SO
PowerPAD-8
LI
HS
HI
D
LO
N
To Hi-Side FET
Multi Layer
Option
G
HO
HS
HO
Single Layer
Option
HO
To Low-Side FET
Figure 30. PCB Layout Recommendation
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
21
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
• AN-1317 Selection of External Bootstrap Diode for LM510X Devices (SNVA083)
• Semiconductor and IC Package Thermal Metrics (SPRA953)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM5100A
Click here
Click here
Click here
Click here
Click here
LM5100B
Click here
Click here
Click here
Click here
Click here
LM5100C
Click here
Click here
Click here
Click here
Click here
LM5101A
Click here
Click here
Click here
Click here
Click here
LM5101B
Click here
Click here
Click here
Click here
Click here
LM5101C
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM5100AM/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
L5100
AM
LM5100AMR/NOPB
ACTIVE SO PowerPAD
DDA
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
L5100
AMR
LM5100AMRX/NOPB
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
L5100
AMR
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5100
AM
LM5100AMX/NOPB
ACTIVE
SOIC
D
8
2500
LM5100ASD
NRND
WSON
DPR
10
1000
TBD
Call TI
Call TI
-40 to 125
5100ASD
LM5100ASD/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5100ASD
LM5100BMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5100
BMA
LM5100BMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5100
BMA
LM5100BSD/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5100BSD
LM5100CMA/NOPB
LIFEBUY
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5100
CMA
LM5100CMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5100
CMA
LM5100CMY/NOPB
LIFEBUY
MSOPPowerPAD
DGN
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
SXCB
LM5100CMYE/NOPB
LIFEBUY
MSOPPowerPAD
DGN
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
SXCB
LM5100CMYX/NOPB
LIFEBUY
MSOPPowerPAD
DGN
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
SXCB
LM5100CSD/NOPB
LIFEBUY
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5100CSD
LM5101AM/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5101
AM
DDA
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
LM5101AMR/NOPB
ACTIVE SO PowerPAD
Addendum-Page 1
L5101
AMR
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2015
Orderable Device
Status
(1)
LM5101AMRX/NOPB
(1)
Package Type Package Pins Package
Drawing
Qty
ACTIVE SO PowerPAD
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
L5101
AMR
LM5101AMX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5101
AM
LM5101ASD
NRND
WSON
DPR
10
1000
TBD
Call TI
Call TI
-40 to 125
5101ASD
LM5101ASD-1/NOPB
ACTIVE
WSON
NGT
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
LM5101ASD/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
5101ASD
-40 to 125
5101ASD
5101A-1
LM5101ASDX
NRND
WSON
DPR
10
4500
TBD
Call TI
Call TI
LM5101ASDX-1/NOPB
ACTIVE
WSON
NGT
8
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5101ASDX/NOPB
ACTIVE
WSON
DPR
10
4500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
5101ASD
LM5101BMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5101
BMA
LM5101BMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5101
BMA
LM5101BSD/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(5101ASD ~
5101BSD)
LM5101BSDX/NOPB
ACTIVE
WSON
DPR
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5101BSD
LM5101CMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5101
CMA
LM5101CMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5101
CMA
LM5101CMY/NOPB
ACTIVE
MSOPPowerPAD
DGN
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
SXDB
LM5101CMYE/NOPB
ACTIVE
MSOPPowerPAD
DGN
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
SXDB
LM5101CMYX/NOPB
ACTIVE
MSOPPowerPAD
DGN
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
SXDB
LM5101CSD/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
The marketing status values are defined as follows:
Addendum-Page 2
5101A-1
-40 to 125
5101CSD
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2015
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM5100AMRX/NOPB
Package Package Pins
Type Drawing
SO
Power
PAD
DDA
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5100AMX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5100ASD
WSON
DPR
10
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5100ASD/NOPB
WSON
DPR
10
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5100BMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5100BSD/NOPB
WSON
DPR
10
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5100CMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5100CMY/NOPB
MSOPPower
PAD
DGN
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5100CMYE/NOPB
MSOPPower
PAD
DGN
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5100CMYX/NOPB
MSOPPower
PAD
DGN
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5100CSD/NOPB
WSON
DPR
10
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5101AMRX/NOPB
SO
Power
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PAD
LM5101AMX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5101ASD
WSON
DPR
10
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5101ASD-1/NOPB
WSON
NGT
8
1000
180.0
12.4
4.3
4.3
1.1
8.0
12.0
Q1
LM5101ASD/NOPB
WSON
DPR
10
1000
180.0
12.4
4.3
4.3
1.1
8.0
12.0
Q1
LM5101ASDX
WSON
DPR
10
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5101ASDX-1/NOPB
WSON
NGT
8
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5101ASDX/NOPB
WSON
DPR
10
4500
330.0
12.4
4.3
4.3
1.1
8.0
12.0
Q1
LM5101BMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5101BSD/NOPB
WSON
DPR
10
1000
180.0
12.4
4.3
4.3
1.1
8.0
12.0
Q1
LM5101BSDX/NOPB
WSON
DPR
10
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5101CMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5101CMY/NOPB
MSOPPower
PAD
DGN
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5101CMYE/NOPB
MSOPPower
PAD
DGN
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5101CMYX/NOPB
MSOPPower
PAD
DGN
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5101CSD/NOPB
WSON
DPR
10
1000
180.0
12.4
4.3
4.3
1.1
8.0
12.0
Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5100AMRX/NOPB
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
LM5100AMX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM5100ASD
WSON
DPR
10
1000
210.0
185.0
35.0
LM5100ASD/NOPB
WSON
DPR
10
1000
210.0
185.0
35.0
LM5100BMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM5100BSD/NOPB
WSON
DPR
10
1000
210.0
185.0
35.0
LM5100CMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM5100CMY/NOPB
MSOP-PowerPAD
DGN
8
1000
210.0
185.0
35.0
LM5100CMYE/NOPB
MSOP-PowerPAD
DGN
8
250
210.0
185.0
35.0
LM5100CMYX/NOPB
MSOP-PowerPAD
DGN
8
3500
367.0
367.0
35.0
LM5100CSD/NOPB
WSON
DPR
10
1000
210.0
185.0
35.0
LM5101AMRX/NOPB
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
LM5101AMX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM5101ASD
WSON
DPR
10
1000
210.0
185.0
35.0
LM5101ASD-1/NOPB
WSON
NGT
8
1000
203.0
203.0
35.0
LM5101ASD/NOPB
WSON
DPR
10
1000
203.0
203.0
35.0
LM5101ASDX
WSON
DPR
10
4500
367.0
367.0
35.0
LM5101ASDX-1/NOPB
WSON
NGT
8
4500
367.0
367.0
35.0
LM5101ASDX/NOPB
WSON
DPR
10
4500
346.0
346.0
35.0
LM5101BMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5101BSD/NOPB
WSON
DPR
10
1000
203.0
203.0
35.0
LM5101BSDX/NOPB
WSON
DPR
10
4500
367.0
367.0
35.0
LM5101CMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM5101CMY/NOPB
MSOP-PowerPAD
DGN
8
1000
210.0
185.0
35.0
LM5101CMYE/NOPB
MSOP-PowerPAD
DGN
8
250
210.0
185.0
35.0
LM5101CMYX/NOPB
MSOP-PowerPAD
DGN
8
3500
367.0
367.0
35.0
LM5101CSD/NOPB
WSON
DPR
10
1000
203.0
203.0
35.0
Pack Materials-Page 4
MECHANICAL DATA
DGN0008A
MUY08A (Rev A)
BOTTOM VIEW
www.ti.com
MECHANICAL DATA
DDA0008B
MRA08B (Rev B)
www.ti.com
MECHANICAL DATA
NGT0008A
SDC08A (Rev A)
www.ti.com
MECHANICAL DATA
DPR0010A
SDC10A (Rev A)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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