TI1 LM3429-Q1 N-channel controller for constant current led driver Datasheet

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LM3429, LM3429-Q1
SNVS616H – APRIL 2009 – REVISED JULY 2015
LM3429/-Q1 N-Channel Controller for Constant Current LED Drivers
1 Features
3 Description
•
The LM3429 is a versatile high voltage N-channel
MosFET controller for LED drivers. It can be easily
configured in buck, boost, buck-boost and SEPIC
topologies. This flexibility, along with an input voltage
rating of 75V, makes the LM3429 ideal for
illuminating LEDs in a very diverse, large family of
applications.
1
•
•
•
•
•
•
•
•
•
•
•
•
LM3429-Q1 is AEC-Q100 Grade 1 Qualified for
Automotive Applications
VIN Range From 4.5 V to 75 V
Adjustable Current Sense Voltage
High-Side Current Sensing
2-Ω, 1-A Peak MosFET Gate Driver
Input Undervoltage Protection
Overvoltage Protection
PWM Dimming
Analog Dimming
Cycle-by-Cycle Current Limit
Programmable Switching Frequency
Low Profile 14-lead HTSSOP Package
Thermal Shutdown
Adjustable high-side current sense voltage allows for
tight regulation of the LED current with the highest
efficiency possible. The LM3429 uses Predictive Offtime (PRO) control, which is a combination of peak
current-mode control and a predictive off-timer. This
method of control eases the design of loop
compensation while providing inherent input voltage
feed-forward compensation.
The LM3429 includes a high-voltage startup regulator
that operates over a wide input range of 4.5 V to 75
V. The internal PWM controller is designed for
adjustable switching frequencies of up to 2 MHz, thus
enabling compact solutions. Additional features
include analog dimming, PWM dimming, overvoltage
protection, undervoltage lock-out, cycle-by-cycle
current limit, and thermal shutdown.
2 Applications
•
•
•
•
•
LED Drivers - Buck, Boost, Buck-Boost, SEPIC
Indoor and Outdoor SSL
Automotive
General Illumination
Constant-Current Regulators
Device Information(1)
PART NUMBER
LM3429
LM3429-Q1
PACKAGE
BODY SIZE (NOM)
HTSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Boost Application Circuit
VIN
1
2
3
4
5
6
VIN
LM3429
HSN
COMP
HSP
CSH
IS
RCT
VCC
AGND
GATE
OVP
PGND
14
13
12
11
ILED
10
9
DAP
PWM
7
nDIM
NC
8
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3429, LM3429-Q1
SNVS616H – APRIL 2009 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Typical Characteristics .............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 21
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Applications ................................................ 24
9
Power Supply Recommendations...................... 53
9.1 Input Supply Current Limit ...................................... 53
10 Layout................................................................... 53
10.1 Layout Guidelines ................................................. 53
10.2 Layout Example .................................................... 54
11 Device and Documentation Support ................. 55
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
55
56
56
12 Mechanical, Packaging, and Orderable
Information ........................................................... 56
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 2013) to Revision H
•
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision F (May 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 51
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 52
2
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SNVS616H – APRIL 2009 – REVISED JULY 2015
5 Pin Configuration and Functions
PWP Package
14- Pin HTSSOP
Top View
VIN
1
14 HSN
COMP
2
13 HSP
CSH 3
RCT
12 IS
DAP
15
4
AGND 5
11 VCC
10 GATE
OVP 6
9
PGND
nDIM 7
8
NC
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
APPLICATION INFORMATION
1
VIN
I
Input Voltage
Bypass with 100 nF capacitor to AGND as close to the device as
possible in the circuit board layout.
2
COMP
I
Compensation
Connect a capacitor to AGND to set compensation.
3
CSH
I
Current Sense High
4
RCT
I
Resistor Capacitor Timing
5
AGND
GND
Analog Ground
6
OVP
I
Overvoltage Protection
7
nDIM
I
Not DIM input
Connect a PWM signal for dimming as detailed in the PWM Dimming
section and/or a resistor divider from VIN to program input
undervoltage lockout (UVLO). Turn-on threshold is 1.24 V and
hysteresis for turn-off is provided by 20 µA current source.
8
NC
No Connection
Leave open.
9
PGND
GND
Power Ground
Connect to AGND through DAP copper pad to provide ground return
for GATE.
10
GATE
O
Gate Drive Output
11
VCC
I
Internal Regulator Output
12
IS
I
Main Switch Current Sense
Connect to the drain of the main N-channel MosFET switch for RDSON sensing or to a sense resistor installed in the source of the same
device.
13
HSP
I
LED Current Sense Positive
Connect through a series resistor to LED current sense resistor
(positive).
14
HSN
I
LED Current Sense Negative
Connect through a series resistor to LED current sense resistor
(negative).
DAP
(15)
DAP
GND
Thermal pad on bottom of IC
Connect to AGND and PGND.
Connect a resistor to AGND to set signal current. For analog
dimming, connect current source or potentiometer to AGND (see
Analog Dimming section).
Connect a resistor from the switch node and a capacitor to AGND to
set the switching frequency.
Connect to PGND through the DAP copper circuit board pad to
provide proper ground return for CSH, COMP, and RCT.
Connect to a resistor divider from the output (VO) or the input to
program output overvoltage lockout (OVLO). Turn-off threshold is
1.24 V and hysteresis for turn-on is provided by 20 µA current
source.
Connect to the gate of the external NFET.
Bypass with a 2.2 µF–3.3 µF, ceramic capacitor to PGND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VIN, nDIM
–0.3
76
OVP, HSP, HSN
–0.3
76
RCT
–0.3
3
–0.3
76
IS
Voltage
–2 for 100 ns
VCC
–0.3
8
COMP, CSH
–0.3
6
GATE
–0.3
VCC
VCC+2.5 for 100 ns
–0.3
0.3
–2.5
2.5 for 100 ns
VIN, nDIM
OVP, HSP, HSN
RCT
–1
µA
mA
–200
200
µA
–1
1
mA
260
°C
150
°C
Maximum Junction Temperature
Internally Limited
Maximum Lead Temperature (Reflow and Solder)
(3)
Continuous Power Dissipation
Internally Limited
Storage Temperature, Tstg
(3)
mA
–1
GATE
(2)
–1
–100
5
IS
COMP, CSH
(1)
V
–2.5 for 100 ns
PGND
Continuous Current
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Refer to http://www.ti.com/packaging for more detailed information and mounting techniques.
6.2 ESD Ratings
VALUE
UNIT
LM3429 IN PWP PACKAGE
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
Human body model (HBM), per AEC Q100-002 (3)
±2000
Charged device model (CDM), per AEC Q100-011
±1000
V
LM3429-Q1 IN PWP PACKAGE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
Operating Junction Temperature Range
–40
125
°C
Input Voltage VIN
4.5
75
V
4
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6.4 Thermal Information
THERMAL METRIC (1)
LM3429-Q1
LM3429
PWP (HTSSOP)
PWP (HTSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
47.8
47.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.5
26.5
°C/W
RθJB
Junction-to-board thermal resistance
22.3
22.3
°C/W
ψJT
Junction-to-top characterization parameter
0.7
0.7
°C/W
ψJB
Junction-to-board characterization parameter
22.1
22.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.3
3.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
MIN and MAX limits apply TJ = (−40°C to 125°C) unless specified otherwise. Unless otherwise stated the following condition
applies: VIN = 14 V.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
6.9
7.35
UNIT
STARTUP REGULATOR (VCC)
VCC-REG
VCC Regulation
ICC = 0 mA
6.3
ICC-LIM
VCC Current Limit
VCC = 0V
20
IQ
Quiescent Current
Static
VCC-UVLO
VCC UVLO Threshold
VCC Increasing
VCC-HYS
VCC UVLO Hysteresis
VCC Decreasing
3.7
V
27
1.6
3
4.17
4.5
mA
4.08
V
0.1
OVERVOLTAGE PROTECTION (OVP)
VTH-OVP
OVP OVLO Threshold
OVP Increasing
IHYS-OVP
OVP Hysteresis Source Current
OVP Active (high)
1.18
1.24
1.28
V
10
20
30
µA
1.235
1.26
V
ERROR AMPLIFIER
VCSH
CSH Reference Voltage
With Respect to AGND
1.21
Error Amplifier Input Bias Current
MIN, MAX: TJ = 25°C
–0.6
0
0.6
10
26
40
COMP Sink / Source Current
Transconductance
(3)
Linear Input Range
Transconductance Bandwidth
-6dB Unloaded
Response (3), MIN: TJ =
25°C
0.5
µA
100
µA/V
±125
mV
1
MHz
OFF TIMER (RCT)
tOFF-MIN
Minimum Off-time
RRCT
RCT Reset Pulldown Resistance
RCT = 1V through 1 kΩ
VRCT
VIN/25 Reference Voltage
VIN = 14V
35
75
ns
36
120
Ω
540
565
585
mV
700
800
900
mV
215
245
275
mV
35
75
250
450
PWM COMPARATOR
COMP to PWM Offset
CURRENT LIMIT (IS)
VLIM
Current Limit Threshold
VLIM Delay to Output
tON-MIN
(1)
(2)
(3)
Leading Edge Blanking Time
75
ns
All limits specified at room temperature (TYP) and at temperature extremes (MIN/MAX). All room temperature limits are 100%
production tested. All limits at temperature extremes are specified through correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely norm.
These electrical parameters are specified by design, and are not verified by test.
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Electrical Characteristics (continued)
MIN and MAX limits apply TJ = (−40°C to 125°C) unless specified otherwise. Unless otherwise stated the following condition
applies: VIN = 14 V.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
10
µA
20
119
mA/V
–1.5
0
1.5
µA
–7
0
7
mV
250
500
UNIT
HIGH SIDE TRANSCONDUCTANCE AMPLIFIER
Input Bias Current
Transconductance
Input Offset Current
Input Offset Voltage
Transconductance Bandwidth
ICSH = 100 µA (3), MIN: TJ
= 25°C
kHz
GATE DRIVER (GATE)
RSRC(GATE)
GATE Sourcing Resistance
GATE = High
2
6
RSNK(GATE)
GATE Sinking Resistance
GATE = Low
1.3
4.5
Ω
UNDERVOLTAGE LOCKOUT and DIM INPUT (nDIM)
VTH-nDIM
nDIM / UVLO Threshold
1.18
1.24
1.28
V
IHYS-nDIM
nDIM Hysteresis Current
10
20
30
µA
THERMAL SHUTDOWN
TSD
Thermal Shutdown Threshold
(3)
165
THYS
Thermal Shutdown Hysteresis
(3)
25
6
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6.6 Typical Characteristics
TA= 25°C and VIN = 14 V unless otherwise specified. The measurements for Figure 1 and Figure 3 were made using the
standard boost evaluation board from AN-1986 (SNVA404). The measurements for Figure 2, Figure 4, and Figure 5, Figure 6
were made using the standard buck-boost evaluation board from AN-1985 (SNVA403).
100
100
95
EFFICIENCY (%)
EFFICIENCY (%)
95
90
90
85
80
85
75
70
80
VIN (V)
32
48
VIN (V)
Figure 1. Boost Efficiency vs Input Voltage
VO = 32 V (9 LEDs)
Figure 2. Buck-Boost Efficiency vs Input Voltage
VO = 20 V (6 LEDs)
15
20
25
0
30
1.00
1.05
0.99
1.03
ILED (A)
ILED (A)
10
0.98
16
64
80
1.01
0.99
0.97
0.97
0.96
5
10
15
20
25
0
30
16
32
48
64
80
VIN (V)
Figure 3. Boost LED Current vs Input Voltage
VO = 32 V (9 LEDs)
Figure 4. Buck-boost LED Current vs Input Voltage
VO = 20 V (6 LEDs)
1.0
1.0
0.8
0.8
0.6
0.6
ILED (A)
ILED (A)
VIN (V)
0.4
0.2
500 Hz
0.4
100 Hz
0.2
0.0
0
20
40
60
80
100
0.0
0
ICSH (éA)
20
40
60
80
100
DUTY CYCLE (%)
Figure 5. Analog Dimming
VO = 20 V (6 LEDs)
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Figure 6. PWM Dimming
VO = 20V (6 LEDs)
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Typical Characteristics (continued)
1.250
7.10
1.245
7.05
1.240
7.00
VCC (V)
VCSH (V)
TA= 25°C and VIN = 14 V unless otherwise specified. The measurements for Figure 1 and Figure 3 were made using the
standard boost evaluation board from AN-1986 (SNVA404). The measurements for Figure 2, Figure 4, and Figure 5, Figure 6
were made using the standard buck-boost evaluation board from AN-1985 (SNVA403).
1.235
6.95
1.230
6.90
1.225
6.85
1.220
6.80
-50
-14
22
58
94
130
-50
-14
TEMPERATURE (°C)
Figure 7. VCSH vs. Junction Temperature
58
94
130
Figure 8. VCC vs. Junction Temperature
246
569
568
244
VLIM (mV)
VRCT (mV)
22
TEMPERATURE (°C)
567
566
242
240
565
564
-50
238
-14
22
58
94
-50
130
-14
22
58
94
130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. VLIM vs. Junction Temperature
Figure 9. VRCT vs. Junction Temperature
280
tON-MIN (ns)
275
270
265
260
255
250
-50
-14
22
58
94
130
TEMPERATURE (°C)
Figure 11. tON-MIN vs. Junction Temperature
8
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7 Detailed Description
7.1 Overview
The LM3429 is an N-channel MosFET (NFET) controller for buck, boost and buck-boost current regulators which
are ideal for driving LED loads. The controller has wide input voltage range allowing for regulation of a variety of
LED loads. The high-side differential current sense, with low adjustable threshold voltage, provides an excellent
method for regulating output current while maintaining high system efficiency. The LM3429 uses a Predictive Offtime (PRO) control architecture that allows the regulator to be operated using minimal external control loop
compensation, while providing an inherent cycle-by-cycle current limit. The adjustable current sense threshold
provides the capability to amplitude (analog) dim the LED current and the output enable/disable function allows
for PWM dimming using no external components. When designing, the maximum attainable LED current is not
internally limited because the LM3429 is a controller. Instead it is a function of the system operating point,
component choices, and switching frequency allowing the LM3429 to easily provide constant currents up to 5A.
This simple controller contains all the features necessary to implement a high-efficiency versatile LED driver.
7.2 Functional Block Diagram
VIN
6.9V LDO
Regulator
UVLO
UVLO
HYSTERESIS
VccUVLO
Standby
REFERENCE
1.24V
TLIM Thermal
Limit
Dimming
20 PA
nDIM
VCC
1.24V
VIN/25
Start new on time
Reset
Dominant
Q
GATE
R QB
PGND
S
RCT
VCC
COMP
OVP
HYSTERESIS
PWM
1.24V
CSH
20 PA
OVP
1.24V
800 mV
HSP
LOGIC
HSN
CURRENT
LIMIT
AGND
IS
245 mV
LEB
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7.3 Feature Description
7.3.1 Current Regulators
Current regulators can be designed to accomplish three basic functions: buck, boost, and buck-boost. All three
topologies in their most basic form contain a main switching MosFET, a recirculating diode, an inductor and
capacitors. The LM3429 is designed to drive a ground referenced NFET which is perfect for a standard boost
regulator. Buck and buck-boost regulators, on the other hand, usually have a high-side switch. When driving an
LED load, a ground referenced load is often not necessary, therefore a ground referenced switch can be used to
drive a floating load instead. The LM3429 can then be used to drive all three basic topologies as shown in the
Typical Applications section.
Looking at the buck-boost design, the basic operation of a current regulator can be analyzed. During the time
that the NFET (Q1) is turned on (tON), the input voltage source stores energy in the inductor (L1) while the output
capacitor (CO) provides energy to the LED load. When Q1 is turned off (tOFF), the re-circulating diode (D1)
becomes forward biased and L1 provides energy to both CO and the LED load. Figure 12 shows the inductor
current (iL(t)) waveform for a regulator operating in CCM.
iL (t)
IL-MAX
ÂiL-PP
IL
IL-MIN
tON = DTS
tOFF = (1-D)TS
t
0
TS
Figure 12. Ideal CCM Regulator Inductor Current iL(t)
The average output LED current (ILED) is proportional to the average inductor current (IL) , therefore if IL is tightly
controlled, ILED will be well regulated. As the system changes input voltage or output voltage, the ideal duty cycle
(D) is varied to regulate IL and ultimately ILED. For any current regulator, D is a function of the conversion ratio:
Buck
D=
VO
VIN
(1)
VO - VIN
VO
(2)
Boost
D=
Buck-Boost
D=
VO
VO + VIN
(3)
7.3.2 Predictive Off-Time (PRO) Control
PRO control is used by the LM3429 to control ILED. It is a combination of average peak current control and a oneshot off-timer that varies with input voltage. The LM3429 uses peak current control to regulate the average LED
current through an array of HBLEDs. This method of control uses a series resistor in the LED path to sense LED
current and can use either a series resistor in the MosFET path or the MosFET RDS-ON for both cycle-by-cycle
current limit and input voltage feed forward. D is indirectly controlled by changes in both tOFF and tON, which vary
depending on the operating point.
10
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Feature Description (continued)
Even though the off-time control is quasi-hysteretic, the input voltage proportionality in the off-timer creates an
essentially constant switching frequency over the entire operating range for boost and buck-boost topologies.
The buck topology can be designed to give constant ripple over either input voltage or output voltage, however
switching frequency is only constant at a specific operating point .
This type of control minimizes the control loop compensation necessary in many switching regulators, simplifying
the design process. The averaging mechanism in the peak detection control loop provides extremely accurate
LED current regulation over the entire operating range.
PRO control was designed to mitigate “current mode instability” (also called “sub-harmonic oscillation”) found in
standard peak current mode control when operating near or above 50% duty cycles. When using standard peak
current mode control with a fixed switching frequency, this condition is present, regardless of the topology.
However, using a constant off-time approach, current mode instability cannot occur, enabling easier design and
control.
Predictive off-time advantages:
• There is no current mode instability at any duty cycle.
• Higher duty cycles / voltage transformation ratios are possible, especially in the boost regulator.
The only disadvantage is that synchronization to an external reference frequency is generally not available.
7.3.3 Switching Frequency
An external resistor (RT) connected between the RCT pin and the switch node (where D1, Q1, and L1 connect),
in combination with a capacitor (CT) between the RCT and AGND pins, sets the off-time (tOFF) as shown in
Figure 13. For boost and buck-boost topologies, the VIN proportionality ensures a virtually constant switching
frequency (fSW).
VSW
LM3429
RT
VIN/25
Start tON
RCT
CT
Reset timer
Figure 13. Off-timer Circuitry for Boost and Buck-boost Regulators
For a buck topology, RT and CT are also used to set tOFF, however the VIN proportionality will not ensure a
constant switching frequency. Instead, constant ripple operation can be achieved. Changing the connection of RT
in Figure 13 from VSW to VIN will provide a constant ripple over varying VIN. Adding a PNP transistor as shown in
Figure 14 will provide constant ripple over varying VO.
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Feature Description (continued)
VIN
RSNS
RT
LM3429
VIN/25
LED-
Start tON
RCT
CT
Reset timer
Figure 14. Off-timer Circuitry for Buck Regulators
The switching frequency is defined:
Buck (Constant Ripple vs. VIN)
fSW =
25 x ( VIN - VO )
RT x CT X VIN
(4)
Buck (Constant Ripple vs. VO)
25 x (VIN x VO - VO )
2
fSW =
2
RT x C T x VIN
(5)
Boost and Buck-Boost
fSW =
25
R T x CT
(6)
For all topologies, the CT capacitor is recommended to be 1 nF and should be located very close to the LM3429.
7.3.4 Average LED Current
The LM3429 uses an external current sense resistor (RSNS) placed in series with the LED load to convert the
LED current (ILED) into a voltage (VSNS) as shown in Figure 15. The HSP and HSN pins are the inputs to the
high-side sense amplifier which are forced to be equal potential (VHSP=VHSN) through negative feedback.
Because of this, the VSNS voltage is forced across RHSP to generate the signal current (ICSH) which flows out of
the CSH pin and through the RCSH resistor. The error amplifier will regulate the CSH pin to 1.24 V, therefore ICSH
can be calculated:
ICSH =
VSNS
RHSP
(7)
This means VSNS will be regulated as follows:
RHSP
VSNS = 1.24V x
RCSH
(8)
ILED can then be calculated:
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Feature Description (continued)
ILED =
VSNS
1.24V RHSP
x
=
RSNS
RSNS
RCSH
(9)
The selection of the three resistors (RSNS, RCSH, and RHSP) is not arbitrary. For matching and noise performance,
the suggested signal current ICSH is approximately 100 µA. This current does not flow in the LEDs and will not
affect either the off state LED current or the regulated LED current. ICSH can be above or below this value, but
the high-side amplifier offset characteristics may be affected slightly. In addition, to minimize the effect of the
high-side amplifier voltage offset on LED current accuracy, the minimum VSNS is suggested to be 50 mV. Finally,
a resistor (RHSN = RHSP) should be placed in series with the HSN pin to cancel out the effects of the input bias
current (~10 µA) of both inputs of the high-side sense amplifier. The CSH pin can also be used as a low-side
current sense input regulated to 1.24 V. The high-side sense amplifier is disabled if HSP and HSN are tied to
GND.
LM3429
ILED
RHSP
HSP
High-Side
Sense Amplifier
ICSH
VSNS
RSNS
RHSN
HSN
RCSH
CSH
Error Amplifier
1.24V
CCMP
To PWM
Comparator
COMP
Figure 15. LED Current Sense Circuitry
7.3.5 Analog Dimming
The CSH pin can be used to analog dim the LED current by adjusting the current sense voltage (VSNS). There
are several different methods to adjust VSNS using the CSH pin:
1. External variable resistance : Adjust a potentiometer placed in series with RCSH to vary VSNS.
2. External variable current source: Source current (0 µA to ICSH) into the CSH pin to adjust VSNS.
In general, analog dimming applications require a lower switching frequency to minimize the effect of the leading
edge blanking circuit. As the LED current is reduced, the output voltage and the duty cycle decreases.
Eventually, the minimum on-time is reached. The lower the switching frequency, the wider the linear dimming
range. Figure 16 shows how both methods are physically implemented.
Method 1 uses an external potentiometer in the CSH path which is a simple addition to the existing circuitry.
However, the LEDs cannot dim completely because there is always some resistance causing signal current to
flow. This method is also susceptible to noise coupling at the CSH pin because the potentiometer increases the
size of the signal current loop.
Method 2 provides a complete dimming range and better noise performance, though it is more complex. It
consists of a PNP current mirror and a bias network consisting of an NPN, 2 resistors and a potentiometer
(RADJ), where RADJ controls the amount of current sourced into the CSH pin. A higher resistance value will source
more current into the CSH pin causing less regulated signal current through RHSP, effectively dimming the LEDs.
VREF should be a precise external voltage reference, while Q7 and Q8 should be a dual pair PNP for best
matching and performance. The additional current (IADD) sourced into the CSH pin can be calculated:
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Feature Description (continued)
IADD =
§ RADJ x VREF ·
¨R + R ¸ - VBE-Q6
© ADJ MAX ¹
RBIAS
(10)
The corresponding ILED for a specific IADD is:
§RHSP·
ILED = ICSH - IADD x ¨
¸
RSNS
(
)
©
¹
(11)
Variable Current Source
VCC
LM3429
VREF
Q8
Q7
RMAX
Q6
RADJ
RBIAS
CSH
RCSH
RADJ
Variable
Resistance
Figure 16. Analog Dimming Circuitry
7.3.6 Current Sense and Current Limit
The LM3429 achieves peak current mode control using a comparator that monitors the MosFET transistor
current, comparing it with the COMP pin voltage as shown in Figure 17. Further, it incorporates a cycle-by-cycle
overcurrent protection function. Current limit is accomplished by a redundant internal current sense comparator.
If the voltage at the current sense comparator input (IS) exceeds 245 mV (typical), the on cycle is immediately
terminated. The IS input pin has an internal N-channel MosFET which pulls it down at the conclusion of every
cycle. The discharge device remains on an additional 250 ns (typical) after the beginning of a new cycle to blank
the leading edge spike on the current sense signal. The leading edge blanking (LEB) determines the minimum
achievable on-time (tON-MIN).
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Feature Description (continued)
LM3429
COMP
Q1
GATE
PWM
800 mV
IS
245 mV
IT
RLIM
LEB
PGND
Figure 17. Current Sense / Current Limit Circuitry
There are two possible methods to sense the transistor current. The RDS-ON of the main power MosFET can be
used as the current sense resistance because the IS pin was designed to withstand the high voltages present on
the drain when the MosFET is in the off state. Alternatively, a sense resistor located in the source of the MosFET
may be used for current sensing, however a low inductance (ESL) type is suggested. The cycle-by-cycle current
limit (ILIM) can be calulated using either method as the limiting resistance (RLIM):
ILIM =
245 mV
RLIM
(12)
In general, the external series resistor allows for more design flexibility, however it is important to ensure all of
the noise sensitive low power ground connections are connected together local to the controller and a single
connection is made to the high current PGND (sense resistor ground point).
7.3.7 Control Loop Compensation
The LM3429 control loop is modeled like any current mode controller. Using a first order approximation, the
uncompensated loop can be modeled as a single pole created by the output capacitor and, in the boost and
buck-boost topologies, a right half plane zero created by the inductor, where both have a dependence on the
LED string dynamic resistance. There is also a high frequency pole in the model, however it is above the
switching frequency and plays no part in the compensation design process therefore it will be neglected.
Because ceramic capacitance is recommended for use with LED drivers due to long lifetimes and high ripple
current rating, the ESR of the output capacitor can also be neglected in the loop analysis. Finally, there is a DC
gain of the uncompensated loop which is dependent on internal controller gains and the external sensing
network.
A buck-boost regulator will be used as an example case. See the Typical Applications section for compensation
of all topologies.
The uncompensated loop gain for a buck-boost regulator is given by the following equation:
§
s ·
¸
¨1 ¨ ZZ1 ¸
¹
©
TU = TU0 x
§
s ·
¨1+
¸
¨ ZP1 ¸
©
¹
(13)
Where the uncompensated DC loop gain of the system is described as:
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Feature Description (continued)
TU0 =
Dc x 500V x RCSH x RSNS
(1+ D) x RHSP x R LIM
=
Dc x 620V
(1+ D) x ILED x R LIM
(14)
3
And the output pole (ωP1) is approximated:
1+ D
ZP1 =
rD x CO
(15)
And the right half plane zero (ωZ1) is:
rD x Dc2
ZZ1 =
D x L1
(16)
100
öZ1
80
135
öP1
90
GAIN
GAIN (dB)
0
40
PHASE
-45
20
0° Phase Margin
-90
0
-20
-135
-40
-180
-60
1e-1
PHASE (°)
45
60
1e1
1e3
1e5
-225
1e7
FREQUENCY (Hz)
Figure 18. Uncompensated Loop Gain Frequency Response
Figure 18 shows the uncompensated loop gain in a worst-case scenario when the RHP zero is below the output
pole. This occurs at high duty cycles when the regulator is trying to boost the output voltage significantly. The
RHP zero adds 20dB/decade of gain while loosing 45°/decade of phase which places the crossover frequency
(when the gain is zero dB) extremely high because the gain only starts falling again due to the high frequency
pole (not modeled or shown in figure). The phase will be below -180° at the crossover frequency which means
there is no phase margin (180° + phase at crossover frequency) causing system instability. Even if the output
pole is below the RHP zero, the phase will still reach -180° before the crossover frequency in most cases yielding
instability.
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Feature Description (continued)
LM3429
ILED
RHSP
HSP
High-Side
Sense Amplifier
CFS
VSNS
RSNS
RHSN
HSN
RFS
sets öP3
RCSH
Error Amplifier
CSH
1.24V
sets öP2
CCMP
RO
To PWM
Comparator
COMP
Figure 19. Compensation Circuitry
To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the
crossover frequency. A simple compensator using a single capacitor at the COMP pin (CCMP) will add a dominant
pole to the system, which will ensure adequate phase margin if placed low enough. At high duty cycles (as
shown in Figure 18), the RHP zero places extreme limits on the achievable bandwidth with this type of
compensation. However, because an LED driver is essentially free of output transients (except catastrophic
failures open or short), the dominant pole approach, even with reduced bandwidth, is usually the best approach.
The dominant compensation pole (ωP2) is determined by CCMP and the output resistance (RO) of the error
amplifier (typically 5 MΩ):
1
ZP2
6
5x10 : x CCMP
(17)
It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate
switching noise and, in some cases, provide better gain margin. This pole can be placed across RSNS to filter the
ESL of the sense resistor at the same time. Figure 19 shows how the compensation is physically implemented in
the system.
The high frequency pole (ωP3) can be calculated:
1
ZP3 =
RFS x CFS
(18)
The total system transfer function becomes:
§ s ·
¨1 ¸
¨ ZZ1¸
©
¹
T = TU0 x
§
s · §
s · §
s ·
¸ ¨
¸ ¨
¨1+
¸
¨ ZP1¸ x ¨1+ ZP2¸ x ¨1+ ZP3¸
¹ ©
¹ ©
©
¹
(19)
The resulting compensated loop gain frequency response shown in Figure 20 indicates that the system has
adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability:
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Feature Description (continued)
90
80
öP2
45
60
0
GAIN
20
0
öZ1
-90
PHASE
öP3
-20
-40
-45
öP1
-135
60° Phase Margin
-180
-225
-60
-80
1e-1
PHASE (°)
GAIN (dB)
40
1e1
1e3
1e5
-270
1e7
FREQUENCY (Hz)
Figure 20. Compensated Loop Gain Frequency Response
7.3.8 Output Overvoltage Lockout (OVLO)
The LM3429 can be configured to detect an output (or input) overvoltage condition through the OVP pin. The pin
features a precision 1.24-V threshold with 20 µA (typical) of hysteresis current as shown in Figure 21. When the
OVLO threshold is exceeded, the GATE pin is immediately pulled low and a 20 µA current source provides
hysteresis to the lower threshold of the OVLO hysteretic band.
LM3429
VO
20 PA
ROV2
OVP
1.24V
OVLO
ROV1
Figure 21. Overvoltage Protection Circuitry
If the LEDs are referenced to a potential other than ground (floating), as in the buck-boost and buck
configuration, the output voltage (VO) should be sensed and translated to ground by using a single PNP as
shown in Figure 22.
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Feature Description (continued)
LED+
ROV2
LM3429
LEDOVP
ROV1
Figure 22. Floating Output OVP Circuitry
The overvoltage turnoff threshold (VTURN-OFF) is defined as follows:
Ground Referenced
§R + ROV 2·
¸
VTURN - OFF = 1.24V x ¨¨ OV1
¸
© R OV1 ¹
(20)
Floating
§0.5 x R OV1+ R OV2·
¸
VTURN - OFF = 1.24V x ¨¨
¸
R OV1
¹
©
(21)
In the ground referenced configuration, the voltage across ROV2 is VO - 1.24 V whereas in the floating
configuration it is VO - 620 mV where 620 mV approximates the VBE of the PNP transistor.
The overvoltage hysteresis (VHYSO) is defined as follows:
VHYSO = 20 PA x ROV2
(22)
7.3.9 Input Undervoltage Lockout (UVLO)
The nDIM pin is a dual-function input that features an accurate 1.24 V threshold with programmable hysteresis
as shown in Figure 23. This pin functions as both the PWM dimming input for the LEDs and as a VIN UVLO.
When the pin voltage rises and exceeds the 1.24 V threshold, 20 µA (typical) of current is driven out of the nDIM
pin into the resistor divider providing programmable hysteresis.
LM3429
VIN
20 PA
RUV2
RUV1
nDIM
1.24V
RUVH
UVLO
(optional)
Figure 23. UVLO Circuit
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Feature Description (continued)
When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra series
resistor to set the hysteresis. This allows the standard resistor divider to have smaller resistor values minimizing
PWM delays due to a pulldown MosFET at the nDIM pin (see PWM Dimming section). In general, at least 3V of
hysteresis is necessary when PWM dimming if operating near the UVLO threshold.
The turn-on threshold (VTURN-ON) is defined as follows:
§R UV1 + RUV2·
¸
¨
VTURN ON
- = 1. 24V x ¨
¸
© RUV1 ¹
(23)
The hysteresis (VHYS) is defined as follows:
UVLO Only
VHYS = 20 PA x RUV2
(24)
PWM Dimming and UVLO
§
R x (RUV1 + RUV2) ·
¸
VHYS = 20 PA x ¨¨RUV2 + UVH
¸
RUV1
¹
©
(25)
7.3.10 PWM Dimming
The active low nDIM pin can be driven with a PWM signal which controls the main NFET (Q1). The brightness of
the LEDs can be varied by modulating the duty cycle of this signal. LED brightness is approximately proportional
to the PWM signal duty cycle, so 30% duty cycle equals approximately 30% LED brightness. This function can
be ignored if PWM dimming is not required by using nDIM solely as a VIN UVLO input as described in the Input
Undervoltage Lockout (UVLO) section or by tying it directly to VCC or VIN (if less than 76VDC).
Inverted
PWM
VIN
LM3429
DDIM
RUV2
nDIM
RUVH
RUV1
QDIM
Standard
PWM
Figure 24. PWM Dimming Circuit
Figure 24 shows two ways the PWM signal can be applied to the nDIM pin:
1. Connect the dimming MosFET (QDIM) with the drain to the nDIM pin and the source to GND. Apply an
external logic-level PWM signal to the gate of QDIM. A pull down resistor may be necessary to properly turn
off QDIM if no signal is present.
2. Connect the anode of a Schottky diode (DDIM) to the nDIM pin. Apply an external inverted logic-level PWM
signal to the cathode of the same diode.
A minimum on-time must be maintained in order for PWM dimming to operate in the linear region of its transfer
function. Because the controller is disabled during dimming, the PWM pulse must be long enough such that the
energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and
buck-boost regulators, the following condition must be maintained:
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Feature Description (continued)
2 x ILED x VO X L1
tPULSE =
VIN2
(26)
In the previous equation, tPULSE is the length of the PWM pulse in seconds.
7.3.11 Startup Regulator (VCC LDO)
The LM3429 includes a high voltage, low dropout (LDO) bias regulator. When power is applied, the regulator is
enabled and sources current into an external capacitor connected to the VCC pin. The VCC output voltage is 6.9V
nominally and the supply is internally current limited to 20 mA (minimum). The recommended bypass
capacitance range for the VCC regulator is 2.2 µF to 3.3 µF. The output of the VCC regulator is monitored by an
internal UVLO circuit that protects the device during startup, normal operation, and shutdown from attempting to
operate with insufficient supply voltage.
7.3.12 Thermal Shutdown
The LM3429 includes thermal shutdown. If the die temperature reaches approximately 165°C the device will shut
down (GATE pin low), until it reaches approximately 140°C where it turns on again.
7.4 Device Functional Modes
This device has no functional modes.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Inductor
The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy
is stored in the inductor and transfered to the load in different ways (as an example, buck-boost operation is
detailed in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the
switching subinterval (tON or tOFF) determines the inductor current ripple (ΔiL-PP). In the design process, L1 is
chosen to provide a desired ΔiL-PP. For a buck regulator the inductor has a direct connection to the load, which is
good for a current regulator. This requires little to no output capacitance therefore ΔiL-PP is basically equal to the
LED ripple current ΔiLED-PP. However, for boost and buck-boost regulators, there is always an output capacitor
which reduces ΔiLED-PP, therefore the inductor ripple can be larger than in the buck regulator case where output
capacitance is minimal or completely absent.
In general, ΔiLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED).
Therefore, for the buck regulator with no output capacitance, ΔiL-PP should also be less than 40% of ILED. For the
boost and buck-boost topologies, ΔiL-PP can be much higher depending on the output capacitance value.
However, ΔiL-PP is suggested to be less than 100% of the average inductor current (IL) to limit the RMS inductor
current.
L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable
RMS inductor current (IL-RMS).
8.1.2 LED Dynamic Resistance (rD)
When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus RSNS.
LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the
forward voltage of a single LED (VLED) by the forward current (ILED) leads to an incorrect calculation of the
dynamic resistance of a single LED (rLED). The result can be 5 to 10 times higher than the true rLED value.
Figure 25. Dynamic Resistance
Obtaining rLED is accomplished by referring to the manufacturer's LED I-V characteristic. It can be calculated as
the slope at the nominal operating point as shown in Figure 25. For any application with more than 2 series
LEDs, RSNS can be neglected allowing rD to be approximated as the number of LEDs multiplied by rLED.
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Application Information (continued)
8.1.3 Output Capacitor
For boost and buck-boost regulators, the output capacitor (CO) provides energy to the load when the recirculating
diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a buck topology will
simply reduce the LED current ripple (ΔiLED-PP) below the inductor current ripple (ΔiL-PP). In all cases, CO is sized
to provide a desired ΔiLED-PP. As mentioned in the Inductor section, ΔiLED-PP is recommended by manufacturers to
be less than 40% of the average LED current (ILED).
CO should be carefully chosen to account for derating due to temperature and operating voltage. It must also
have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current
rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested.
8.1.4 Input Capacitors
The input capacitance (CIN) provides energy during the discontinuous portions of the switching period. For buck
and buck-boost regulators, CIN provides energy during tON and during tOFF, the input voltage source charges up
CIN with the average input current (IIN). For boost regulators, CIN only needs to provide the ripple current due to
the direct connection to the inductor. CIN is selected given the maximum input voltage ripple (ΔvIN-PP) which can
be tolerated. ΔvIN-PP is suggested to be less than 10% of the input voltage (VIN).
An input capacitance at least 100% greater than the calculated CIN value is recommended to account for derating
due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to
minimize the large current draw from the input voltage source during the rising transition of the LED current
waveform.
The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the
best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R
dieletric rating is suggested.
For most applications, TI recommends bypassing the VIN pin with an 0.1-µF ceramic capacitor placed as close as
possible to the pin. In situations where the bulk input capacitance may be far from the LM3429 device, a 10-Ω
series resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150 kHz
filter to eliminate undesired high frequency noise coupling.
8.1.5 N-Channel MosFET (NFET)
The LM3429 requires an external NFET (Q1) as the main power MosFET for the switching regulator. Q1 is
recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe
operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the
switch node due to the diode parasitic capacitance and the lead inductance. The current rating is recommended
to be at least 10% higher than the average transistor current. The power rating is then verified by calculating the
power loss given the RMS transistor current and the NFET on-resistance (RDS-ON).
In general, the NFET should be chosen to minimize total gate charge (Qg) whenever switching frequencies are
high and minimize RDS-ON otherwise. This will minimize the dominant power losses in the system. Frequently,
higher current NFETs in larger packages are chosen for better thermal performance.
8.1.6 Re-Circulating Diode
A re-circulating diode (D1) is required to carry the inductor current during tOFF. The most efficient choice for D1 is
a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 is
recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe
operation during the ringing of the switch node and a current rating at least 10% higher than the average diode
current. The power rating is verified by calculating the power loss through the diode. This is accomplished by
checking the typical diode forward voltage from the I-V curve on the product data sheet and multiplying by the
average diode current. In general, higher current diodes have a lower forward voltage and come in better
performing packages minimizing both power losses and temperature rise.
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8.2 Typical Applications
8.2.1 Basic Topology Schematics
L1
D1
VIN
CIN
RT
1
CCMP
2
LM3429
VIN
HSN
HSP
COMP
14
13
RHSN
CFS
RHSP
RSNS
CO
RFS
RCSH
3
CT
4
CSH
IS
RCT
VCC
ILED
12
11
CBYP
5
6
RUV2
PWM
GATE
OVP
PGND
10
Q1
9
RLIM
ROV2
DAP
RUVH
RUV1
AGND
7
nDIM
NC
8
COV
Q3
ROV1
Figure 26. Boost Regulator (VIN < VO)
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Typical Applications (continued)
VIN
CIN
1
LM3429
VIN
HSN
14
RT
2
HSP
COMP
13
RHSN
CFS
RHSP
RSNS
CO
CCMP
RFS
3
CSH
IS
12
D1
ILED
L1
RCSH
4
RCT
VCC
11
CT
CBYP
5
AGND
GATE
10
Q1
ROV2
6
RUV2
OVP
PGND
7
PWM
RLIM
Q2
DAP
RUVH
RUV1
9
nDIM
NC
8
COV
Q3
ROV1
Figure 27. Buck Regulator (VIN > VO)
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Typical Applications (continued)
L1
D1
VIN
CIN
ILED
RT
1
CCMP
2
VIN
LM3429
HSN
HSP
COMP
14
13
RHSN
CO
CFS
RHSP
RSNS
VIN
RFS
RCSH
3
CT
4
CSH
IS
RCT
VCC
12
11
CBYP
5
AGND
GATE
10
Q1
ROV2
6
RUV2
OVP
PGND
7
PWM
RLIM
VIN
DAP
RUVH
RUV1
9
nDIM
NC
Q2
8
COV
Q3
ROV1
Figure 28. Buck-Boost Regulator
8.2.1.1 Design Requirements
Number of series LEDs: N
Single LED forward voltage: VLED
Single LED dynamic resistance: rLED
Nominal input voltage: VIN
Input voltage range: VIN-MAX, VIN-MIN
Switching frequency: fSW
Current sense voltage: VSNS
Average LED current: ILED
Inductor current ripple: ΔiL-PP
LED current ripple: ΔiLED-PP
Peak current limit: ILIM
Input voltage ripple: ΔvIN-PP
Output OVLO characteristics: VTURN-OFF, VHYSO
Input UVLO characteristics: VTURN-ON, VHYS
26
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Operating Point
Given the number of series LEDs (N), the forward voltage (VLED) and dynamic resistance (rLED) for a single LED,
solve for the nominal output voltage (VO) and the nominal LED string dynamic resistance (rD):
VO = N x VLED
(27)
rD = N x rLED
(28)
Solve for the ideal nominal duty cycle (D):
Buck
D=
VO
VIN
(29)
VO - VIN
VO
(30)
Boost
D=
Buck-boost
D=
VO
VO + VIN
(31)
Using the same equations, find the minimum duty cycle (DMIN) using maximum input voltage (VIN-MAX) and the
maximum duty cycle (DMAX) using the minimum input voltage (VIN-MIN). Also, remember that D' = 1 - D.
8.2.1.2.2 Switching Frequency
Set the switching frequency (fSW) by assuming a CT value of 1 nF and solving for RT:
Buck (Constant Ripple vs. VIN)
RT =
25 x ( VIN - VO )
fSW x CT X VIN
(32)
Buck (Constant Ripple vs. VO)
2
RT =
25 x (VIN x VO - VO
fSW x C T x
)
2
VIN
(33)
Boost and Buck-Boost
25
RT =
fSW x C T
(34)
8.2.1.2.3 Average LED Current
For all topologies, set the average LED current (ILED) knowing the desired current sense voltage (VSNS) and
solving for RSNS:
VSNS
RSNS =
ILED
(35)
If the calculated RSNS is too far from a desired standard value, then VSNS must be adjusted to obtain a standard
value.
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Typical Applications (continued)
Setup the suggested signal current of 100 µA by assuming RCSH = 12.4 kΩ and solving for RHSP:
ILED x RCSH x RSNS
RHSP =
1.24V
(36)
If the calculated RHSP is too far from a desired standard value, then RCSH can be adjusted to obtain a standard
value.
8.2.1.2.4 Inductor Ripple Current
Set the nominal inductor ripple current (ΔiL-PP) by solving for the appropriate inductor (L1):
Buck
L1
(VIN VO ) x D
'iL PP x fSW
(37)
Boost and Buck-Boost
VIN x D
L1
'iL PP x fSW
(38)
To set the worst case inductor ripple current, use VIN-MAX and DMIN when solving for L1.
The minimum allowable inductor RMS current rating (IL-RMS) can be calculated as:
Buck
IL-RMS = ILED x
1 § 'IL-PP·
x
1+
¸
12 ¨ ILED
©
2
¹
(39)
Boost and Buck-Boost
1 §'IL-PP x D' ·
x
x 1+
IL-RMS =
¸
12 ¨ ILED
D'
ILED
©
2
¹
(40)
8.2.1.2.5 LED Ripple Current
Set the nominal LED ripple current (ΔiLED-PP), by solving for the output capacitance (CO):
Buck
CO =
'iL - PP
8 x fSW x rD x 'iLED - PP
(41)
Boost and Buck-Boost
ILED x D
Co
rD x 'iLED PP
(42)
To set the worst case LED ripple current, use DMAX when solving for CO.
The minimum allowable RMS output capacitor current rating (ICO-RMS) can be approximated:
Buck
ICO - RMS =
28
üiLED - PP
12
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Typical Applications (continued)
Boost and Buck-boost
ICO-RMS = ILED x
DMAX
1-DMAX
(44)
8.2.1.2.6 Peak Current Limit
Set the peak current limit (ILIM) by solving for the transistor path sense resistor (RLIM):
R LIM =
245 mV
ILIM
(45)
8.2.1.2.7 Loop Compensation
Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the
necessary loop compensation can be determined.
First, the uncompensated loop gain (TU) of the regulator can be approximated:
Buck
TU = TU0 x
1
§
s ·
¨1+
¸
¨ ZP1 ¸
©
¹
(46)
Boost and Buck-Boost
§
s ·
¸
¨1 ¨ ZZ1 ¸
¹
©
TU = TU0 x
§
s ·
¨1+
¸
¨ ZP1 ¸
©
¹
(47)
Where the pole (ωP1) is approximated:
3
Buck
1
rD x CO
ZP1 =
(48)
3
Boost
2
rD x CO
ZP1 =
(49)
3
Buck-Boost
ZP1 =
1+ D
rD x CO
(50)
And the RHP zero (ωZ1) is approximated:
Boost
ZZ1 =
rD x Dc2
L1
(51)
Buck-Boost
ZZ1 =
rD x Dc2
D x L1
(52)
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Typical Applications (continued)
And the uncompensated DC loop gain (TU0) is approximated:
Buck
500V x RCSH x RSNS
620V
=
RHSP x R LIM
ILED x RLIM
(53)
Dc x 500V x RCSH x RSNS
Dc x 310V
=
2 x RHSP x R LIM
ILED x R LIM
(54)
TU0 =
Boost
TU0 =
Buck-Boost
Dc x 500V x RCSH x RSNS
Dc x 620V
TU0 =
=
(1+ D) x RHSP x R LIM (1+ D) x ILED x R LIM
(55)
For all topologies, the primary method of compensation is to place a low-frequency dominant pole (ωP2) which
will ensure that there is ample phase margin at the crossover frequency. This is accomplished by placing a
capacitor (CCMP) from the COMP pin to GND, which is calculated according to the lower value of the pole and the
RHP zero of the system (shown as a minimizing function):
ZP2 =
min(Z P1, ZZ1)
5 x TU0
(56)
1
C CMP =
ѠP2 ×5×106
(57)
If analog dimming is used, CCMP should be approximately 4x larger to maintain stability as the LEDs are dimmed
to zero.
A high frequency compensation pole (ωP3) can be used to attenuate switching noise and provide better gain
margin. Assuming RFS = 10 Ω, CFS is calculated according to the higher value of the pole and the RHP zero of
the system (shown as a maximizing function):
ZP3 = max (ZP1, ZZ1) x 10
CFS =
(58)
1
10 x ZP3
(59)
The total system loop gain (T) can then be written as:
Buck
T = TU0 x
1
§
s · §
s ·
¸
¨1+
¸ ¨
¨ ZP2¸ x ¨1+ ZP3¸
¹
©
¹ ©
(60)
§ s ·
¨1 ¸
¨ ZZ1¸
©
¹
T = TU0 x
§
s · §
s · §
s ·
¸ ¨
¸ ¨
¨1+
¸
¨ ZP1¸ x ¨1+ ZP2¸ x ¨1+ ZP3¸
¹ ©
¹ ©
©
¹
(61)
§
s ·
¨1+
¸
¨ ZP1¸ x
©
¹
Boost and Buck-boost
8.2.1.2.8 Input Capacitance
Set the nominal input voltage ripple (ΔvIN-PP) by solving for the required capacitance (CIN):
Buck
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Typical Applications (continued)
CIN =
ILED x (1 - D) x D
'VIN-PP x fSW
(62)
Boost
CIN =
'iL-PP
8 x 'VIN-PP x fSW
(63)
Buck-Boost
CIN =
ILED x D
'VIN-PP x fSW
(64)
Use DMAX to set the worst case input voltage ripple, when solving for CIN in a buck-boost regulator and DMID = 0.5
when solving for CIN in a buck regulator.
The minimum allowable RMS input current rating (ICIN-RMS) can be approximated:
Buck
ICIN - RMS = ILED x DMID x (1-DMID)
(65)
Boost
ICIN-RMS =
'iL-PP
12
(66)
Buck-Boost
ICIN-RMS = ILED x
DMAX
1-DMAX
(67)
8.2.1.2.9 NFET
The NFET voltage rating should be at least 15% higher than the maximum NFET drain-to-source voltage (VTMAX):
Buck
VT - MAX = VIN - MAX
(68)
VT - MAX = VO
(69)
Boost
Buck-Boost
VT - MAX = VIN - MAX + VO
(70)
The current rating should be at least 10% higher than the maximum average NFET current (IT-MAX):
Buck
IT-MAX = DMAX x ILED
(71)
Boost and Buck-Boost
DMAX
IT-MAX =
xI
1 - DMAX LED
(72)
Approximate the nominal RMS transistor current (IT-RMS) :
Buck
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Typical Applications (continued)
IT- RMS = ILED x D
(73)
Boost and Buck-Boost
ILED
x D
IT - RMS =
Dc
(74)
Given an NFET with on-resistance (RDS-ON), solve for the nominal power dissipation (PT):
2
PT = IT - RMS x R DSON
(75)
8.2.1.2.10 Diode
The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (VRD-MAX):
Buck
VRD-MAX = VIN-MAX
(76)
Boost
VRD-MAX = VO
(77)
Buck-Boost
VRD-MAX = VIN-MAX + VO
(78)
The current rating should be at least 10% higher than the maximum average diode current (ID-MAX):
Buck
ID-MAX = (1 - DMIN) x ILED
(79)
Boost and Buck-Boost
ID-MAX = ILED
(80)
Replace DMAX with D in the ID-MAX equation to solve for the average diode current (ID). Given a diode with forward
voltage (VFD), solve for the nominal power dissipation (PD):
PD = ID x VFD
(81)
8.2.1.2.11 Output OVLO
For boost and buck-boost regulators, output OVLO is programmed with the turn-off threshold voltage (VTURN-OFF)
and the desired hysteresis (VHYSO). To set VHYSO, solve for ROV2:
VHYSO
ROV2 =
20 PA
(82)
To set VTURN-OFF, solve for ROV1:
Boost
ROV1 =
1.24V x ROV2
VTURN - OFF - 1.24V
(83)
Buck-Boost
R OV1 =
32
1.24V x R OV2
VTURN - OFF - 620 mV
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Typical Applications (continued)
A small filter capacitor (COVP = 47 pF) should be added from the OVP pin to ground to reduce coupled switching
noise.
8.2.1.2.12 Input UVLO
For all topologies, input UVLO is programmed with the turn-on threshold voltage (VTURN-ON) and the desired
hysteresis (VHYS).
Method #1: If no PWM dimming is required, a two resistor network can be used. To set VHYS, solve for RUV2:
VHYS
RUV2 =
20 PA
(85)
To set VTURN-ON, solve for RUV1:
RUV1 =
1.24V x RUV2
VTURN - ON - 1.24V
(86)
Method #2: If PWM dimming is required, a three resistor network is suggested. To set VTURN-ON, assume RUV2 =
10 kΩ and solve for RUV1 as in Method #1. To set VHYS, solve for RUVH:
RUVH =
R UV1 x (VHYS - 20 PA x RUV2)
20 PA x (RUV1 + R UV2)
(87)
8.2.1.2.13 PWM Dimming Method
PWM dimming can be performed several ways:
Method #1: Connect the dimming MosFET (Q3) with the drain to the nDIM pin and the source to GND. Apply an
external PWM signal to the gate of QDIM. A pull down resistor may be necessary to properly turn off Q3.
Method #2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to
the cathode of the same diode.
8.2.1.2.14 Analog Dimming Method
Analog dimming can be performed several ways:
Method #1: Place a potentiometer in series with the RCSH resistor to dim the LED current from the nominal ILED
to near zero.
Method #2: Connect a controlled current source as detailed in the Analog Dimming section to the CSH pin.
Increasing the current sourced into the CSH node will decrease the LEDs from the nominal ILED to zero current.
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Typical Applications (continued)
8.2.2 Buck-Boost Application - 6 LEDs at 1 A
10V ± 70V
VIN
L1
CIN
D1
RT
1
CCMP
RCSH
CT
2
3
4
VIN
LM3429
HSN
HSP
COMP
CSH
IS
RCT
VCC
14
RHSN
13
RHSP
1A
ILED
CO
12
CFS
11
VIN
CBYP
5
AGND
GATE
RSNS
RFS
10
Q1
ROV2
6
RUV2
OVP
PGND
9
RLIM
VIN
DAP
7
nDIM
NC
Q2
8
COV
RUV1
ROV1
Figure 29. Buck-Boost Application - 6 LEDs at 1 A Schematic
8.2.2.1 Design Requirements
N=6
VLED = 3.5 V
rLED = 325 mΩ
VIN = 24 V
VIN-MIN = 10 V
VIN-MAX = 70 V
fSW = 700 kHz
VSNS = 100 mV
ILED = 1A
ΔiL-PP = 500 mA
ΔiLED-PP = 50 mA
ΔvIN-PP = 100 mV
ILIM = 6A
VTURN-ON = 10 V
VHYS = 3 V
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Typical Applications (continued)
VTURN-OFF = 40 V
VHYSO = 10 V
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Operating Point
Solve for VO and rD:
VO = N x VLED = 6 x 3.5V = 21V
(88)
rD = N x rLED = 6 x 325 m: = 1. 95:
(89)
Solve for D, D', DMAX, and DMIN:
D=
VO
21V
=
= 0.467
VO + VIN 21V + 24V
(90)
D' = 1 - D = 1 - 0. 467 = 0. 533
DMIN =
DMAX =
(91)
VO
21V
=
= 0.231
VO + VIN-MAX 21V + 70V
(92)
VO
21V
=
= 0.677
VO + VIN-MIN 21V + 10V
(93)
8.2.2.2.2 Switching Frequency
Assume CT = 1 nF and solve for RT:
RT =
25
25
=
= 35.7 k:
fSW x CT 700 kHz x 1 nF
(94)
The closest standard resistor is actually 35.7 kΩ therefore the fSW is:
fSW =
25
25
=
= 700 kHz
RT x CT 35.7 k: x 1 nF
(95)
The chosen components from step 2 are:
CT = 1 nF
RT = 35.7 k:
(96)
8.2.2.2.3 Average LED Current
Solve for RSNS:
V
100 mV
RSNS = SNS =
= 0.1:
ILED
1A
(97)
Assume RCSH = 12.4 kΩ and solve for RHSP:
ILED x RCSH x RSNS 1A x 12.4 k : x 0.1:
RHSP =
=
= 1.0 k:
1.24V
1.24V
(98)
The closest standard resistor for RSNS is actually 0.1Ω and for RHSP is actually 1 kΩ therefore ILED is:
1.24V x RHSP 1.24V x 1.0 k:
ILED =
=
= 1.0A
R SNS x R CSH 0.1: x 12.4 k:
(99)
The chosen components from step 3 are:
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RS NS = 0.1:
R CSH = 12.4 k :
RHSP = RHSN = 1 k:
(100)
8.2.2.2.4 Inductor Ripple Current
Solve for L1:
L1 =
VIN x D
24V x 0. 467
=
= 32 PH
'iL- PP x fSW 500 mA x 700 kHz
(101)
The closest standard inductor is 33 µH therefore the actual ΔiL-PP is:
'iL- PP =
VIN x D
24V x 0. 467
= 485 mA
=
L1 x fSW 33 PH x 700 kHz
(102)
Determine minimum allowable RMS current rating:
2
I
1 x §¨ 'iL - PP x Dc·¸
IL - RMS = LED x 1+
12 ¨© ILED ¸¹
Dc
2
1 x §485 mA x 0.533·
1A
x 1+
¸¸
12 ¨¨©
1A
0. 533
¹
IL - RMS = 1.88A
IL - RMS =
(103)
The chosen component from step 4 is:
L1 = 33 PH
(104)
8.2.2.2.5 Output Capacitance
Solve for CO:
CO =
CO =
ILED x D
rD x 'iLED- PP x fSW
1A x 0. 467
= 6.84 PF
1.95: x 50 mA x 7 00 kHz
(105)
The closest standard capacitor is 6.8 µF therefore the actual ΔiLED-PP is:
I xD
'iLED- PP = LED
rD x CO x fSW
'iLED- PP =
1A x 0. 467
= 50 mA
1.95 : x 6.8 PF x 7 00 kHz
(106)
Determine minimum allowable RMS current rating:
ICO- RMS = ILED x
DMAX
0.677
= 1.45A
= 1A x
1- DMAX
1- 0.677
(107)
The chosen components from step 5 are:
CO = 6.8 PF
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Typical Applications (continued)
8.2.2.2.6 Peak Current Limit
Solve for RLIM:
RLIM =
245 mV 245 mV
=
= 0.041:
ILIM
6A
(109)
The closest standard resistor is 0.04 Ω therefore ILIM is:
ILIM =
245 mV 245 mV
=
= 6.13A
RLIM
0.04 :
(110)
The chosen component from step 6 is:
RLIM = 0.04:
(111)
8.2.2.2.7 Loop Compensation
ωP1 is approximated:
ZP1 =
1.467
1+D
rad
=
= 110k
sec
rD x CO 1.95: x 6.8 PF
(112)
ωZ1 is approximated:
rD x Dc2 1.95: x 0.5332
rad
ZZ1 =
=
= 37k
D x L1 0.467 x 33 PH
sec
(113)
TU0 is approximated:
0.533 x 620V
Dc x 620V
TU0 =
=
= 5630
1
.
467
x 1A x 0.04:
(1+ D) x ILED x R LIM
(114)
To ensure stability, calculate ωP2:
rad
37k
min(ZP1, ZZ1)
ZZ1
sec
rad
ZP2 =
=
=
= 1.173
5 x 5630 5 x 5630
5 x TU0
sec
(115)
Solve for CCMP:
CCMP =
1
1
=
= 0.17 µF
Ѡ P2× 5×106 Ω 1.173 rad × 5×10 6 Ω
sec
(116)
To attenuate switching noise, calculate ωP3:
ZP3 = max ZP1, ZZ1 x 10 = ZP1 x 10
ZP3 = 110 k
rad
rad
x 10 = 1.1M
sec
sec
(117)
Assume RFS = 10 Ω and solve for CFS:
CFS =
1
=
10: x ZP3
1
10: x 1.1M
rad
sec
= 0.091 PF
(118)
The chosen components from step 7 are:
CCOMP = 0.22 PF
RFS = 10:
CFS = 0.1 PF
(119)
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Typical Applications (continued)
8.2.2.2.8 Input Capacitance
Solve for the minimum CIN:
CIN =
ILED x D
1A x 0. 467
=
= 6.66 PF
'vIN- PP x fSW 100 mV x 700 kHz
(120)
To minimize power supply interaction a 200% larger capacitance of approximately 14 µF is used, therefore the
actual ΔvIN-PP is much lower. Because high voltage ceramic capacitor selection is limited, three 4.7 µF X7R
capacitors are chosen.
Determine minimum allowable RMS current rating:
IIN- RMS = ILED x
DMAX
0.677
= 1.45A
= 1A x
1- DMAX
1- 0.677
(121)
The chosen components from step 8 are:
CIN = 3 x 4.7 PF
(122)
8.2.2.2.9 NFET
Determine minimum Q1 voltage rating and current rating:
VT - MAX = VIN - MAX + VO = 70V + 21V = 91V
IT- MAX =
(123)
0. 677
x 1A = 2.1A
1- 0.677
(124)
A 100-V NFET is chosen with a current rating of 32A due to the low RDS-ON = 50 mΩ. Determine IT-RMS and PT:
IT - RMS =
PT =
ILED
1A
x D=
x 0.467 = 1. 28A
0. 533
Dc
2
IT- RMS
(125)
2
x RDSON = 1. 28A x 50 m: = 82 mW
(126)
The chosen component from step 9 is:
Q1 o 32A, 100V, DPAK
(127)
8.2.2.2.10 Diode
Determine minimum D1 voltage rating and current rating:
VRD - MAX = VIN - MAX + VO = 70V + 21V = 91V
(128)
ID - MAX = ILED = 1A
(129)
A 100-V diode is chosen with a current rating of 12 A and VDF = 600 mV. Determine PD:
PD = ID x VFD = 1A x 600 mV = 600 mW
(130)
The chosen component from step 10 is:
D1 o 12A, 100V, DPAK
(131)
8.2.2.2.11 Input UVLO
Solve for RUV2:
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Typical Applications (continued)
R UV2 =
VHYS
3V
=
= 150 k:
20 P A 20 PA
(132)
The closest standard resistor is 150 kΩ therefore VHYS is:
VHYS = RUV2 x 20 P A = 150 k: x 20 P A = 3V
(133)
Solve for RUV1:
1.24V x R UV2
1.24V x 150 k:
R UV1 =
=
= 21.2 k:
VTURN - ON - 1.24V
10V -1.24V
(134)
The closest standard resistor is 21 kΩ making VTURN-ON:
VTURN - ON =
1.24V x (R UV1 + R UV2)
R UV1
VTURN- ON =
1.24V x (21 k: + 150 k:)
= 10.1V
21 k:
(135)
The chosen components from step 11 are:
RUV1 = 21 k:
RUV2 = 150 k:
(136)
8.2.2.2.12 Output OVLO
Solve for ROV2:
ROV2 =
VHYSO
10V
=
= 500 k:
20 P A 20 P A
(137)
The closest standard resistor is 499 kΩ therefore VHYSO is:
VHYSO = ROV2 x 20 PA = 499 k: x 20 PA = 9.98V
(138)
Solve for ROV1:
1.24V x ROV2
1.24V x 499 k:
R OV1 =
=
= 15.7 k:
VTURN - OFF - 0.62V
40V - 0.62V
(139)
The closest standard resistor is 15.8 kΩ making VTURN-OFF:
VTURN-OFF =
VTURN-OFF =
1.24V x (0.5 x ROV1 + ROV2)
ROV1
1.24V x (0.5 x 15.8 k: + 499 k:)
= 39.8V
15.8 k:
(140)
The chosen components from step 12 are:
ROV1 = 15.8 k:
ROV2 = 499 k:
(141)
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Typical Applications (continued)
Table 1. Design 1 Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3429
Boost controller
TI
LM3429MH
1
CCMP
0.22 µF X7R 10% 25 V
MURATA
GRM21BR71E224KA01L
1
CF
2.2 µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CFS
0.1 µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
3
CIN
4.7 µF X7R 10% 100 V
TDK
C5750X7R2A475K
1
CO
6.8 µF X7R 10% 50 V
TDK
C4532X7R1H685K
1
COV
47 pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000 pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 100 V 12 A
VISHAY
12CWQ10FNPBF
1
L1
33 µH 20% 6.3 A
COILCRAFT
MSS1278-333MLB
1
Q1
NMOS 100 V 32 A
FAIRCHILD
FDD3682
1
Q2
PNP 150 V 600 m A
FAIRCHILD
MMBT5401
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.04 Ω 1% 1W
VISHAY
WSL2512R0400FEA
1
ROV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RSNS
0.1 Ω 1% 1W
VISHAY
WSL2512R1000FEA
1
RT
35.7 kΩ 1%
VISHAY
CRCW080535K7FKEA
1
RUV1
21 kΩ 1%
VISHAY
CRCW080521K0FKEA
1
RUV2
150 kΩ 1%
VISHAY
CRCW0805150KFKEA
8.2.2.3 Application Curve
100
EFFICIENCY (%)
95
90
85
80
75
70
0
16
32
48
VIN (V)
64
80
Figure 30. Buck-Boost Efficiency vs Input Voltage, VO= 6 LEDs
40
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8.2.3 Boost PWM Dimming Application - 9 LEDs at 1 A
8V - 28V
VIN
L1
CIN
D1
RT
1
CCMP
2
LM3429
VIN
HSN
HSP
COMP
14
RHSN
13
RHSP
CFS
RSNS
RFS
RCSH
3
CT
4
CSH
IS
RCT
VCC
11
1A
ILED
CBYP
5
6
RUV2
PWM
GATE
OVP
PGND
10
Q1
9
RLIM
ROV2
DAP
RUVH
RUV1
AGND
CO
12
7
nDIM
NC
8
COV
Q2
ROV1
Figure 31. Boost PWM Dimming Application - 9 LEDs at 1 A Schematic
8.2.3.1 Detailed Design Procedure
Table 2. Design 2 Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3429
Boost controller
TI
LM3429MH
2
CCMP, CFS
0.1 µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
1
CF
2.2 µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
2, 1
CIN, CO
6.8 µF X7R 10% 50 V
TDK
C4532X7R1H685K
1
COV
47 pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000 pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 60 V 5 A
COMCHIP
CDBC560-G
1
L1
33 µH 20% 6.3 A
COILCRAFT
MSS1278-333MLB
1
Q1
NMOS 60 V 8 A
VISHAY
SI4436DY
1
Q2
NMOS 60 V 115 mA
ON SEMI
2N7002ET1G
2
RCSH, ROV1
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.06 Ω 1% 1 W
VISHAY
WSL2512R0600FEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RSNS
0.1 Ω 1% 1 W
VISHAY
WSL2512R1000FEA
1
RT
35.7 kΩ 1%
VISHAY
CRCW080535K7FKEA
1
RUV1
1.82 kΩ 1%
VISHAY
CRCW08051K82FKEA
1
RUV2
10 kΩ 1%
VISHAY
CRCW080510KFKEA
1
RUVH
17.8 kΩ 1%
VISHAY
CRCW080517K8FKEA
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8.2.4 Buck-Boost Analog Dimming Application - 4 LEDs at 2A
10V ± 30V
VIN
L1
D1
CIN
RT
1
LM3429
VIN
HSN
14
RHSN
13
RHSP
2A
ILED
CO
CCMP
RCSH
2
HSP
COMP
CFS
3
CSH
IS
RSNS
12
VIN
RADJ
RFS
CT
4
RCT
VCC
11
CBYP
5
AGND
GATE
10
Q1
ROV2
RUV2
6
OVP
PGND
9
RLIM
VIN
DAP
7
nDIM
NC
Q2
8
COV
RUV1
ROV1
Figure 32. Buck-Boost Analog Dimming Application - 4 LEDs at 2 A Schematic
8.2.4.1 Detailed Design Procedure
Table 3. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3429
Boost controller
TI
LM3429MH
1
CCMP
1 µF X7R 10% 10 V
MURATA
GRM21BR71A105KA01L
1
CF
2.2 µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CFS
0.1 µF X7R 10% 50 V
MURATA
GRM21BR71E104KA01L
2, 1
CIN, CO
6.8 µF X7R 10% 50 V
TDK
C4532X7R1H685K
1
COV
47 pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000 pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 60 V 5 A
VISHAY
CDBC560-G
1
L1
22 µH 20% 7.2 A
COILCRAFT
MSS1278-223MLB
1
Q1
NMOS 60 V 8 A
VISHAY
SI4436DY
1
Q2
PNP 150 V 600 mA
FAIRCHILD
MMBT5401
1
RADJ
1-MΩ potentiometer
BOURNS
3352P-1-105
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.04 Ω 1% 1 W
VISHAY
WSL2512R0400FEA
1
ROV1
18.2 kΩ 1%
VISHAY
CRCW080518K2FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RSNS
0.05 Ω 1% 1 W
VISHAY
WSL2512R0500FEA
1
RT
41.2 kΩ 1%
VISHAY
CRCW080541K2FKEA
42
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Table 3. Bill of Materials (continued)
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
RUV1
21 kΩ 1%
VISHAY
CRCW080521K0FKEA
1
RUV2
150 kΩ 1%
VISHAY
CRCW0805150KFKEA
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8.2.5 Boost Analog Dimming Application - 12 LEDs at 700 mA
L1
18V - 38V
VIN
D1
CIN
RT
1
CCMP
2
VREF
VIN
LM3429
HSN
HSP
COMP
14
RHSN
13
RHSP
CFS
RFS
Q4
Q3
3
RMAX
RBIAS
CSH
IS
RCT
VCC
12
CO
CT
Q2
RADJ
RSNS
4
11
700 mA
ILED
CBYP
RCSH
5
VIN
6
RUV2
AGND
GATE
OVP
PGND
10
Q1
9
RLIM
ROV2
DAP
7
nDIM
NC
8
COV
RUV1
ROV1
Figure 33. Boost Analog Dimming Application - 12 LEDs at 700 mA Schematic
8.2.5.1 Detailed Design Procedure
Table 4. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3429
Boost controller
TI
LM3429MH
1
CCMP
1 µF X7R 10% 10 V
MURATA
GRM21BR71A105KA01L
1
CF
2.2 µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CFS
0.1 µF X7R 10% 50 V
MURATA
GRM21BR71E104KA01L
2, 1
CIN, CO
6.8 µF X7R 10% 50 V
TDK
C4532X7R1H685K
1
COV
47 pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000 pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 100 V 12 A
VISHAY
12CWQ10FNPBF
1
L1
47 µH 20% 5.3 A
COILCRAFT
MSS1278-473MLB
1
Q1
NMOS 100 V 32 A
FAIRCHILD
FDD3682
1
Q2
NPN 40 V 200 mA
FAIRCHILD
MMBT3904
1
Q3, Q4 (dual pack)
Dual PNP 40 V 200 mA
FAIRCHILD
FFB3906
1
RADJ
100 kΩ potentiometer
BOURNS
3352P-1-104
1
RBIAS
40.2 kΩ 1%
VISHAY
CRCW080540K2FKEA
1
RCSH, ROV1, RUV1
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RHSP, RHSN
1.05 kΩ 1%
VISHAY
CRCW08051K05FKEA
1
RLIM
0.06 Ω 1% 1 W
VISHAY
WSL2512R0600FEA
1
RMAX
4.99 kΩ 1%
VISHAY
CRCW08054K99FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RSNS
0.15 Ω 1% 1 W
VISHAY
WSL2512R1500FEA
44
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SNVS616H – APRIL 2009 – REVISED JULY 2015
Table 4. Bill of Materials (continued)
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
RT
35.7 kΩ 1%
VISHAY
CRCW080535K7FKEA
1
RUV2
100 kΩ 1%
VISHAY
CRCW0805100KFKEA
1
VREF
5 V precision reference
TI
LM4040
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8.2.6 Buck-Boost PWM Dimming Application - 6 LEDs at 500 mA
10V ± 70V
VIN
L1
CIN
D1
RT
1
CCMP
2
RCSH
3
CT
4
LM3429
VIN
HSN
HSP
COMP
CSH
IS
RCT
VCC
14
RHSN
13
RHSP
500 mA
ILED
12
CFS
11
AGND
GATE
10
RSNS
VIN
CBYP
5
CO
RFS
Q1
ROV2
6
RUV2
OVP
PGND
9
VIN
DAP
RUVH
7
nDIM
NC
Q2
8
D2
COV
RUV1
ROV1
PWM
Figure 34. Buck-Boost PWM Dimming Application - 6 LEDs at 500 mA
8.2.6.1 Detailed Design Procedure
Table 5. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3429
Boost controller
TI
LM3429MH
1
CCMP
0.68 µF X7R 10% 25 V
MURATA
GRM21BR71E684KA88L
1
CF
2.2 µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CFS
0.1 µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
3
CIN
4.7 µF X7R 10% 100 V
TDK
C5750X7R2A475K
1
CO
6.8 µF X7R 10% 50 V
TDK
C4532X7R1H685K
1
COV
47 pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000 pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 100 V 12 A
VISHAY
12CWQ10FNPBF
1
D2
Schottky 30 V 500 mA
ON SEMI
BAT54T1G
1
L1
68 µH 20% 4.3 A
COILCRAFT
MSS1278-683MLB
1
Q1
NMOS 100 V 32 A
VISHAY
FDD3682
1
Q2
PNP 150 V 600 mA
FAIRCHILD
MMBT5401
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
ROV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RSNS
0.2 Ω 1% 1 W
VISHAY
WSL2512R2000FEA
1
RT
35.7 kΩ 1%
VISHAY
CRCW080535K7FKEA
1
RUV1
1.43 kΩ 1%
VISHAY
CRCW08051K43FKEA
1
RUV2
10 kΩ 1%
VISHAY
CRCW080510K0FKEA
46
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Table 5. Bill of Materials (continued)
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
RUVH
17.4 kΩ 1%
VISHAY
CRCW080517K4FKEA
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8.2.7 Buck Application - 3 LEDS at 1.25 A
15V ± 50V
VIN
CIN
1
LM3429
VIN
HSN
14
RHSN
RT
2
HSP
COMP
CFS
RHSP
13
RSNS
CO
CCMP
RFS
3
CSH
IS
RCT
VCC
D1
12
1.25A
ILED
RCSH
4
11
CT
L1
CBYP
5
AGND
GATE
10
Q1
ROV2
6
RUV2
OVP
PGND
9
RLIM
Q2
DAP
7
nDIM
NC
8
COV
RUV1
ROV1
Figure 35. Buck Application - 3 LEDS at 1.25 A Schematic
8.2.7.1 Detailed Design Procedure
Table 6. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3429
Boost controller
TI
LM3429MH
1
CCMP
0.015 µF X7R 10% 50 V
MURATA
GRM21BR71H153KA01L
1
CF
2.2 µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CFS
0.01 µF X7R 10% 50 V
MURATA
GRM21BR71H103KA01L
2
CIN
6.8 µF X7R 10% 50 V
TDK
C4532X7R1H685K
1
CO
1 µF X7R 10% 50 V
TDK
C4532X7R1H105K
1
COV
47 pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000 pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 60V 5 A
COMCHIP
CDBC560-G
1
L1
22 µH 20% 7.3 A
COILCRAFT
MSS1278-223MLB
1
Q1
NMOS 60 V 8 A
VISHAY
SI4436DY
1
Q2
PNP 150 V 600 mA
FAIRCHILD
MMBT5401
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RT
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.04 Ω 1% 1 W
VISHAY
WSL2512R0400FEA
1
ROV1
21.5 kΩ 1%
VISHAY
CRCW080521K5FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RSNS
0.08 Ω 1% 1 W
VISHAY
WSL2512R0800FEA
48
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SNVS616H – APRIL 2009 – REVISED JULY 2015
Table 6. Bill of Materials (continued)
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
RUV1
11.5 kΩ 1%
VISHAY
CRCW080511K5FKEA
1
RUV2
100 kΩ 1%
VISHAY
CRCW0805100KFKEA
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8.2.8 Buck-Boost Thermal Foldback Application - 8 LEDs at 2.5 A
L1
15V ± 60V
VIN
VREF
D1
CIN
RT
1
RGAIN
CCMP
RNTC
2
VIN
LM3429
HSN
HSP
COMP
14
RHSN
13
RHSP
2.5A
ILED
CO
D2
RBIAS
3
RCSH
CT
4
CSH
IS
RCT
VCC
12
11
CBYP
5
VIN
AGND
GATE
CFS
10
RSNS
Q1
VIN
RFS
6
RUV2
OVP
PGND
9
ROV2
RLIM
VIN
DAP
7
nDIM
NC
Q2
8
COV
RUV1
ROV1
Figure 36. Buck-Boost Thermal Foldback Application - 8 LEDs at 2.5 A Schematic
8.2.8.1 Detailed Design Procedure
Table 7. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3429
Boost controller
TI
LM3429MH
1
CCMP
0.1 µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
1
CF
2.2 µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CFS
0.1 µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
3
CIN
4.7 µF X7R 10% 100 V
TDK
C5750X7R2A475K
1
CO
6.8 µF X7R 10% 50 V
TDK
C4532X7R1H685K
1
COV
47 pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000 pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 100 V 12 A
VISHAY
12CWQ10FNPBF
1
L1
22 µH 20% 7.2 A
COILCRAFT
MSS1278-223MLB
1
Q1
NMOS 100 V 32 A
FAIRCHILD
FDD3682
1
Q2
PNP 150 V 600 mA
FAIRCHILD
MMBT5401
2
RCSH, ROV1
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
2
RLIM, RSNS
0.04 Ω 1% 1 W
VISHAY
WSL2512R0400FEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RT
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RUV1
13.7 kΩ 1%
VISHAY
CRCW080513K7FKEA
1
RUV2
150 kΩ 1%
VISHAY
CRCW0805150KFKEA
50
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8.2.9 SEPIC Application - 5 LEDs at 750 mA
9V - 36V
VIN
L1
CSEP
D1
L2
CIN
RT
1
CCMP
2
LM3429
VIN
HSN
HSP
COMP
14
RHSN
13
RHSP
CFS
RSNS
RFS
RCSH
CT
3
4
CSH
IS
RCT
VCC
11
750 mA
ILED
CBYP
5
6
RUV2
AGND
GATE
OVP
PGND
CO
12
10
Q1
9
ROV2
DAP
7
nDIM
NC
8
COV
RUV1
ROV1
Figure 37. 5 LEDs at 750 mA
8.2.9.1 Detailed Design Procedure
Table 8. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3429
Boost controller
TI
LM3429MH
1
CCMP
0.47 µF X7R 10% 25 V
MURATA
GRM21BR71E474KA01L
1
CF
2.2 µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CFS
0.1 µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
2, 1
CIN, CO
6.8 µF X7R 10% 50 V
TDK
C4532X7R1H685K
1
COV
47 pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CSEP
1 µF X7R 10% 100 V
TDK
C4532X7R2A105K
1
CT
1000 pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 60 V 5 A
COMCHIP
CDBC560-G
1
L1, L2
68 µH 20% 4.3 A
COILCRAFT
DO3340P-683
1
Q1
NMOS 60 V 8 A
VISHAY
SI4436DY
1
Q2
NMOS 60 V 115 mA
ON SEMI
2N7002ET1G
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RHSP, RHSN
750 Ω 1%
VISHAY
CRCW0805750RFKEA
1
RLIM
0.04 Ω 1% 1 W
VISHAY
WSL2512R0400FEA
2
ROV1, RUV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RSNS
0.1 Ω 1% 1 W
VISHAY
WSL2512R1000FEA
1
RT
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
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Table 8. Bill of Materials (continued)
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
RUV2
100 kΩ 1%
VISHAY
CRCW0805100KFKEA
52
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SNVS616H – APRIL 2009 – REVISED JULY 2015
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 4.5 V to 75 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the EVM or PCB, additional
bulk capacitance may be required in addition to the ceramic bypass capacitors.
9.1 Input Supply Current Limit
It is important to set the output current limit of your input supply to an appropriate value to avoid delays in your
converter analysis and optimization. If not set high enough, current limit can be tripped during start-up or when
your converter output power is increased, causing a foldback or shut-down condition. It is a common oversight
when powering up a converter for the first time.
10 Layout
10.1 Layout Guidelines
The performance of any switching regulator depends as much upon the layout of the PCB as the component
selection. Following a few simple guidelines will maximimize noise rejection and minimize the generation of EMI
within the circuit.
Discontinuous currents are the most likely to generate EMI; therefore, take care when routing these paths. The
main path for discontinuous current in the LM3429 buck regulator contains the input capacitor (CIN), the
recirculating diode (D1), the N-channel MosFET (Q1), and the switch sense resistor (RLIM). In the LM3429 boost
and buck-boost regulators, the discontinuous current flows through the output capacitor (CO), D1, Q1, and RLIM.
In either case, this loop should be kept as small as possible and the connections between all the components
should be short and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and Q1
connect) should be just large enough to connect the components. To minimize excessive heating, large copper
pours can be placed adjacent to the short current path of the switch node.
The RCT, COMP, CSH, IS, HSP and HSN pins are all high-impedance inputs which couple external noise easily,
therefore the loops containing these nodes should be minimized whenever possible.
In some applications the LED or LED array can be far away (several inches or more) from the LM3429, or on a
separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or
separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce the
effects of parasitic inductance on the AC impedance of the capacitor.
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10.2 Layout Example
Note critical paths and component placement:
Minimize power loop containing discontinuous currents
Minimize signal current loops (components close to IC)
x
Ground plane under IC for signal routing helps minimize noise coupling
discontinuous switching
frequency currents
L1
D1
VIN
Input
Power
CIN
RT
1
GND
VIN
LM3429
HSN
14
RHSN
13
RHSP
CCMP
2
HSP
COMP
CFS
RSNS
CO
RFS
RCSH
3
CSH
IS
RCT
VCC
12
ILED
CT
4
11
CBYP
5
RUV2
6
AGND
GATE
OVP
PGND
7
PWM
Q1
STAR GROUND
RLIM
9
ROV2
DAP
RUVH
RUV1
10
nDIM
NC
8
COV
Q3
ROV1
Power Ground
Figure 38. LM3429 Layout Guideline
54
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LM3429, LM3429-Q1
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SNVS616H – APRIL 2009 – REVISED JULY 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• AN-1986 LM3429 Boost Evaluation Board, SNVA404
• AN-1985 LM3429 Buck-Boost Evaluation Board, SNVA403
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM3429
Click here
Click here
Click here
Click here
Click here
LM3429-Q1
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: LM3429 LM3429-Q1
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11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
56
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM3429MH/NOPB
ACTIVE
HTSSOP
PWP
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM3429
MH
LM3429MHX/NOPB
ACTIVE
HTSSOP
PWP
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM3429
MH
LM3429Q1MH/NOPB
ACTIVE
HTSSOP
PWP
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM3429
Q1MH
LM3429Q1MHX/NOPB
ACTIVE
HTSSOP
PWP
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM3429
Q1MH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM3429, LM3429-Q1 :
• Catalog: LM3429
• Automotive: LM3429-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM3429MHX/NOPB
HTSSOP
PWP
14
2500
330.0
12.4
LM3429Q1MHX/NOPB
HTSSOP
PWP
14
2500
330.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.95
5.6
1.6
8.0
12.0
Q1
6.95
5.6
1.6
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3429MHX/NOPB
HTSSOP
PWP
14
2500
367.0
367.0
35.0
LM3429Q1MHX/NOPB
HTSSOP
PWP
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
PWP0014A
MXA14A (Rev A)
www.ti.com
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