STMicroelectronics L6228Q Dmos driver for bipolar stepper motor Datasheet

L6228Q
DMOS driver for bipolar stepper motor
Features
■
Operating supply voltage from 8 to 52 V
■
2.8A output peak current (1.4 A RMS)
■
RDS(ON) 0.73 Ω typ. value @ TJ = 25 °C
■
Operating frequency up to 100 kHz
■
Non dissipative overcurrent protection
■
Dual independent constant tOFF PWM
current controllers
■
Fast/slow decay mode selection
■
Fast decay quasi-synchronous rectification
■
Decoding logic for stepper motor full and half
step drive
■
Cross conduction protection
■
Thermal shutdown
■
Under voltage lockout
■
Integrated fast free wheeling diodes
VFQFPN 5x5 32L
Description
The L6228Q is a DMOS fully integrated stepper
motor driver with non-dissipative overcurrent
protection, realized in multipower-BCD
technology, which combines isolated DMOS
power transistors with CMOS and bipolar circuits
on the same chip. The device includes all the
circuitry needed to drive a two-phase bipolar
stepper motor including: a dual DMOS full bridge,
the constant off time PWM current controller that
performs the chopping regulation and the phase
sequence generator, that generates the stepping
sequence. Available in VFQFPN-32 5x5 package,
the L6228Q features a non-dissipative
overcurrent protection on the high side Power
MOSFETs and thermal shutdown.
Applications
■
Bipolar stepper motor
Figure 1.
Block diagram
VBOOT
VCP
VBOOT
VBOOT
VBOOT
10V
10V
OCDA
OCDB
OVER
CURRENT
DETECTION
OUT1A
THERMAL
PROTECTION
SENSEA
PWM
HALF/FULL
RESET
OUT2A
GATE
LOGIC
EN
CONTROL
CLOCK
VSA
CHARGE
PUMP
STEPPING
SEQUENCE
GENERATION
ONE SHOT
MONOSTABLE
CW/CCW
MASKING
TIME
+
SENSE
COMPARATOR
VREFA
RCA
BRIDGE A
VOLTAGE
REGULATOR
10V
5V
VSB
OVER
CURRENT
DETECTION
OUT1B
OUT2B
SENSEB
GATE
LOGIC
VREFB
BRIDGE B
RCB
D01IN1225
January 2008
Rev 1
1/32
www.st.com
32
Contents
L6228Q
Contents
1
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5
Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6
Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7
Normal drive mode (Full-step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 18
4.8
Wave drive mode (Full-step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . 18
4.9
Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Output current capability and IC power dissipation . . . . . . . . . . . . . . 25
7
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
L6228Q
Electrical data
1
Electrical data
1.1
Absolute maximum ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
VS
VOD
VBOOT
Parameter
Value
Unit
Supply voltage
VSA = VSB = VS
60
V
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS = 60 V;
VSENSEA = VSENSEB =
GND
60
V
Bootstrap peak voltage
VSA = VSB = VS
VS + 10
V
VIN,VEN
Input and enable voltage range
-0.3 to +7
V
VREFA, VREFB
Voltage range at pins VREFA and
VREFB
-0.3 to +7
V
VRCA, VRCB
Voltage range at pins RCA and RCB
-0.3 to +7
V
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
-1 to +4
V
IS(peak)
Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection
VSA = VSB = VS;
tPULSE < 1 ms
3.55
A
RMS supply current (for each VS pin) VSA = VSB = VS
1.4
A
-40 to 150
°C
IS
Storage and operating temperature
range
Tstg, TOP
1.2
Recommended operating conditions
Table 2.
Recommended operating conditions
Symbol
VS
VOD
VREFA, VREFB
VSENSEA,
VSENSEB
IOUT
Parameter
Parameter
Supply voltage
VSA = VSB = VS
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
Voltage range at pins VREFA and
VREFB
Voltage range at pins SENSEA and
SENSEB
(pulsed tW < trr)
(DC)
Min
Max
Unit
8
52
V
52
V
-0.1
5
V
-6
-1
6
1
V
V
1.4
A
+125
°C
100
kHz
RMS output current
Tj
Operating junction temperature
fsw
Switching frequency
-25
3/32
Electrical data
1.3
Thermal data
Table 3.
Symbol
Rth(JA)
4/32
L6228Q
Thermal data
Parameter
Thermal resistance junction-ambient max.
Value
Unit
32
°C/W
L6228Q
Pin connection
2
Pin connection
Figure 2.
Note:
Pin connection (top view)
1
The pins 2 to 8 are connected to die PAD.
2
The die PAD must be connected to GND pin.
5/32
Pin connection
Table 4.
L6228Q
Pin description
N°
Pin
Type
Function
1, 21
GND
GND
9
OUT1B
11
RCB
RC Pin
RC Network Pin. A parallel RC network connected between this pin and
ground sets the Current Controller OFF-Time of the Bridge B.
12
SENSEB
Power
Supply
Bridge B Source Pin. This pin must be connected to Power Ground through a
sensing power resistor.
13
VREFB
Analog Input
14
HALF/FULL
Logic Input
Step Mode Selector. HIGH logic level sets HALF STEP Mode, LOW logic
level sets FULL STEP Mode.
If not used, it has to be connected to GND or +5 V.
15
CONTROL
Logic Input
Decay Mode Selector. HIGH logic level sets SLOW DECAY Mode. LOW logic
level sets FAST DECAY Mode.
If not used, it has to be connected to GND or +5 V.
Ground terminals.
Power Output Bridge B Output 1.
Logic Input
Bridge B Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
Chip Enable. LOW logic level switches OFF all Power MOSFETs of both
Bridge A and Bridge B. This pin is also connected to the collector of the
Overcurrent and Thermal Protection to implement over current protection.
If not used, it has to be connected to +5 V through a resistor.
16
EN
17
VBOOT
19
OUT2B
20
VSB
Power
Supply
Bridge B Power Supply Voltage. It must be connected to the Supply Voltage
together with pin VSA
22
VSA
Power
Supply
Bridge A Power Supply Voltage. It must be connected to the Supply Voltage
together with pin VSB
23
OUT2A
24
VCP
Output
25
RESET
Logic Input
26
VREFA
Analog Input
27
CLOCK
Logic Input
Step Clock input. The state machine makes one step on each rising edge.
28
CW/CCW
Logic Input
Selects the direction of the rotation. HIGH logic level sets clockwise direction,
whereas LOW logic level sets counterclockwise direction.
If not used, it has to be connected to GND or +5 V.
29
SENSEA
Power
Supply
Bridge A Source Pin. This pin must be connected to Power Ground through a
sensing power resistor.
30
RCA
RC Pin
RC Network Pin. A parallel RC network connected between this pin and
ground sets the Current Controller OFF-Time of the Bridge A.
31
OUT1A
(1)
Supply
Voltage
Bootstrap Voltage needed for driving the upper Power MOSFETs of both
Bridge A and Bridge B.
Power Output Bridge B Output 2.
Power Output Bridge A Output 2.
Charge Pump Oscillator Output.
Reset Pin. LOW logic level restores the Home State (State 1) on the Phase
Sequence Generator State Machine.
If not used, it has to be connected to +5 V.
Bridge A Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
Power Output Bridge A Output 1.
1. Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven
putting in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100kΩ
6/32
L6228Q
Electrical characteristics
3
Electrical characteristics
Table 5.
Electrical characteristcs (TA = 25 °C, Vs = 48 V, unless otherwise specified)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
VSth(ON)
Turn-on threshold
5.8
6.3
6.8
V
VSth(OFF)
Turn-off threshold
5
5.5
6
V
5
10
mA
IS
Tj(OFF)
All bridges OFF;
Tj = -25 °C to 125 °C(1)
Quiescent supply current
Thermal shutdown temperature
°C
165
Output DMOS transistors
RDS(ON)
IDSS
High-Side + Low-Side Switch ON
resistance
Tj = 25 °C
Tj =125 °C
(1)
1.47
1.69
Ω
2.35
2.70
Ω
2
mA
EN = Low; OUT = VS
Leakage current
EN = Low; OUT = GND
-0.3
mA
Source drain diodes
VSD
Forward ON Voltage
ISD = 1.4 A, EN = LOW
1.15
1.3
V
trr
Reverse Recovery Time
If = 1.4 A
300
ns
tfr
Forward Recovery Time
200
ns
Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
VIL
Low level logic input voltage
-0.3
0.8
V
VIH
High level logic input voltage
2
7
V
IIL
Low level logic input current
GND logic input voltage
IIH
High level logic input current
7V logic input voltage
-10
µA
1.8
10
µA
2.0
V
Vth(ON)
Turn-on input threshold
Vth(OFF)
Turn-off input threshold
0.8
1.3
V
Vth(HYS)
Input threshold hysteresis
0.25
0.5
V
Switching characteristics
tD(ON)EN
Enable to output turn-on delay
time (2)
ILOAD =1.4 A, Resistive load
500
650
800
ns
tD(OFF)EN
Enable to output turn-off delay time (2)
ILOAD =1.4 A, Resistive load
500
800
1000
ns
ILOAD =1.4 A, Resistive load
40
250
ns
ILOAD =1.4 A, Resistive load
40
250
ns
(2)
tRISE
Output rise time
tFALL
Output fall time (2)
tDCLK
tCLK(min)L
tCLK(min)H
Clock to output delay time
ILOAD =1.4 A, Resistive load
2
µs
(4)
1
µs
time (4)
1
µs
Minimum clock time
Minimum clock
(3)
7/32
Electrical characteristics
Table 5.
Electrical characteristcs (continued) (TA = 25 °C, Vs = 48 V, unless otherwise specified)
Symbol
fCLK
tS(MIN)
tH(MIN)
tR(MIN)
tRCLK(MIN)
tDT
fCP
L6228Q
Parameter
Test condition
Min
Typ
Clock frequency
Minimum set-up time(5)
Minimum hold time
(5)
Minimum reset time
(5)
Minimum reset to clock delay time
(5)
Dead time protection
0.5
Charge pump frequency
Tj = -25 °C to 125 °C
(1)
Max
Unit
100
kHz
1
µs
1
µs
1
µs
1
µs
1
0.6
µs
1
MHz
PWM comparator and monostable
IRCA, IRCB
Source current at pins RCA and RCB
VRCA = VRCB = 2.5 V
Voffset
Offset voltage on sense comparator
VREFA, VREFB = 0.5 V
3.5
(6)
tPROP
Turn OFF propagation delay
tBLANK
Internal blanking time on SENSE pins
tON(MIN)
Minimum on time
5.5
mA
±5
mV
500
ns
1
µs
2.5
tOFF
PWM recirculation time
IBIAS
Input bias current at pins VREFA and
VREFB
3
µs
ROFF = 20 kΩ; COFF = 1 nF
13
µs
ROFF = 100 kΩ; COFF = 1 nF
61
µs
10
µA
Over current protection
ISOVER
Input supply overcurrent protection
threshold
Tj = -25 °C to 125 °C (1)
2.8
ROPDR
Open drain ON resistance
I = 4 mA
40
tOCD(ON)
OCD turn-on delay time (7)
I = 4 mA; CEN < 100 pF
200
ns
tOCD(OFF)
(7)
I = 4 mA; CEN < 100 pF
100
ns
OCD turn-off delay time
1. Tested at 25 °C in a restricted range and guaranteed by characterization
2. See Figure 3.
3. See Figure 4.
4. See Figure 5.
5. See Figure 6.
6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
7. See Figure 7.
8/32
A
60
W
L6228Q
Electrical characteristics
Figure 3.
Switching characteristic definition
EN
Vth(ON)
Vth(OFF)
t
IOUT
90%
10%
t
D01IN1316
tD(OFF)EN
Figure 4.
tRISE
tFALL
tD(ON)EN
Clock to output delay time
CLOCK
Vth(ON)
t
IOUT
D01IN1317
t
tDCLK
9/32
Electrical characteristics
Figure 5.
L6228Q
Minimum timing definition; clock input
CLOCK
Vth(ON)
Vth(OFF)
tCLK(MIN)L
Figure 6.
Vth(OFF)
tCLK(MIN)H
D01IN1318
Minimum timing definition; logic inputs
CLOCK
Vth(ON)
LOGIC INPUTS
tS(MIN)
RESET
Vth(OFF)
Vth(ON)
tR(MIN)
Figure 7.
tH(MIN)
tRCLK(MIN)
D01IN1319
Overcurrent detection timing definition
IOUT
ISOVER
ON
BRIDGE
OFF
VEN
90%
10%
tOCD(ON)
10/32
tOCD(OFF)
D02IN1399
L6228Q
Circuit description
4
Circuit description
4.1
Power stages and charge pump
The L6228Q integrates two independent Power MOS Full Bridges. Each Power MOS has an
RDS(ON) = 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Switching
patterns are generated by the PWM Current Controller and the Phase Sequence Generator
(see below). Cross conduction protection is achieved using a dead time (tDT = 1 µs typical
value) between the switch off and switch on of two Power MOSFETs in one leg of a bridge.
Pins VSA and VSB must be connected together to the supply voltage VS. The device
operates with a supply voltage in the range from 8 V to 52 V. It has to be noticed that the
RDS(ON) increases of some percents when the supply voltage is in the range from 8 V to 12 V.
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply voltage VBOOT is obtained
through an internal Oscillator and few external components to realize a charge pump circuit
as shown in Figure 8. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10V amplitude. Recommended values/part numbers for the charge pump circuit are shown
in Table 6.
Table 6.
Figure 8.
Charge pump external components values
CBOOT
220 nF
CP
10 nF
RP
100 Ω
D1
1N4148
D2
1N4148
Charge pump circuit
VS
D1
CBOOT
D2
RP
CP
VCP
VBOOT
VSA VSB
D01IN1328
11/32
Circuit description
4.2
L6228Q
Logic inputs
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and uC
compatible logic inputs. The internal structure is shown in Figure 9. Typical value for turn-on
and turn-off thresholds are respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V.
Pin EN (Enable) has identical input structure with the exception that the drain of the
Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection some care needs to be taken in driving this pin. The EN input may be driven in
one of two configurations as shown in Figure 10 or Figure 11. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in
Figure 10. If the driver is a standard Push-Pull structure the resistor REN and the capacitor
CEN are connected as shown in Figure 11. The resistor REN should be chosen in the range
from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and
5.6nF. More information on selecting the values is found in the Overcurrent Protection
section.
Figure 9.
Logic inputs internal structure
5V
ESD
PROTECTION
D01IN1329
Figure 10. EN pin open collector driving
5V
5V
REN
OPEN
COLLECTOR
OUTPUT
EN
CEN
ESD
PROTECTION
D01IN1330
Figure 11. EN pin push-pull driving
5V
PUSH-PULL
OUTPUT
REN
EN
CEN
ESD
PROTECTION
D01IN1331
12/32
L6228Q
4.3
Circuit description
PWM current control
The L6228Q includes a constant off time PWM current controller for each of the two bridges.
The current control circuit senses the bridge current by sensing the voltage drop across an
external sense resistor connected between the source of the two lower power MOS
transistors and ground, as shown in Figure 12. As the current in the motor builds up the
voltage across the sense resistor increases proportionally. When the voltage drop across
the sense resistor becomes greater than the voltage at the reference input (VREFA or
VREFB) the sense comparator triggers the monostable switching the bridge off. The power
MOS remain off for the time set by the monostable and the motor current recirculates as
defined by the selected decay mode, described in the next section. When the monostable
times out the bridge will again turn on. Since the internal dead time, used to prevent cross
conduction in the bridge, delays the turn on of the power MOS, the effective off time is the
sum of the monostable time plus the dead time.
Figure 12. PWM current controller simplified schematic
VSA (or B)
BLANKING TIME
MONOSTABLE
TO GATE LOGIC
1µs
FROM THE
LOW-SIDE
GATE DRIVERS
5mA
2H
S
Q
(0)
(1)
MONOSTABLE
SET
1H
IOUT
BLANKER
R
OUT2A(or B)
DRIVERS
+
DEAD TIME
-
DRIVERS
+
DEAD TIME
+
5V
2 PHASE
STEPPER MOTOR
OUT1A(or B)
2.5V
SENSE
COMPARATOR
2L
1L
+
COMPARATOR
OUTPUT
RCA(or B)
COFF
ROFF
-
VREFA(or B)
SENSEA(or B)
RSENSE
D01IN1332
Figure 13 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the RC pin voltage and the status of the bridge. More details
regarding the Synchronous Rectification and the output stage configuration are included in
the next section.
Immediately after the Power MOS turns on, a high peak current flows through the sensing
resistor due to the reverse recovery of the freewheeling diodes. The L6228Q provides a 1µs
Blanking Time tBLANK that inhibits the comparator output so that this current spike cannot
prematurely re-trigger the monostable.
13/32
Circuit description
L6228Q
Figure 13. Output current regulation waveforms
IOUT
VREF
RSENSE
tOFF
tON
tOFF
1µs tBLANK
1µs tBLANK
VSENSE
VREF
Slow Decay
0
Slow Decay
ay
ay
c
Fast De
c
Fast De
tRCRISE
VRC
tRCRISE
5V
2.5V
tRCFALL
tRCFALL
1µs tDT
1µs tDT
ON
OFF
SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION
D01IN1334
B
C
D
A
B
C
D
Figure 14 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be
approximately calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated
Dead Time with:
20 kΩ ≤ ROFF ≤ 100 kΩ
0.47 nF ≤ COFF ≤ 100 nF
tDT = 1 µs (typical value)
Therefore:
tOFF(MIN) = 6.6 µs
tOFF(MAX) = 6 ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the
pin RCOFF. The Rise Time tRCRISE will only be an issue if the capacitor is not completely
charged before the next time the monostable is triggered. Therefore, the on time tON, which
depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a
good current regulation by the PWM stage. Furthermore, the on time tON can not be smaller
than the minimum on time tON(MIN).
14/32
L6228Q
Circuit description
⎧ t ON > t ON ( MIN ) = 2.5µs ⎫
⎨
⎬
⎩ t ON > t RCRISE – t DT
⎭
(typ. value)
tRCRISE = 600 · COFF
Figure 15 shows the lower limit for the on time tON for having a good PWM current regulation
capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes
this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues
to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and,
therefore, higher switching frequency), but, the smaller is the value for COFF, the more
influential will be the noises on the circuit performance.
Figure 14. tOFF versus COFF and ROFF
4
1 .10
R off = 100kΩ
3
1 .10
R off = 47kΩ
toff [µs]
R off = 20kΩ
100
10
1
0.1
1
10
100
Coff [nF]
15/32
Circuit description
L6228Q
Figure 15. Area where tON can vary maintaining the PWM regulation.
ton(min) [us]
100
10
2.5µs (typ. value)
1
0.1
1
10
100
Coff [nF]
4.4
Decay modes
The CONTROL input is used to select the behavior of the bridge during the off time. When
the CONTROL pin is low, the Fast Decay mode is selected and both transistors in the bridge
are switched off during the off time. When the CONTROL pin is high, the Slow Decay mode
is selected and only the low side transistor of the bridge is switched off during the off time.
Figure 16 shows the operation of the bridge in the Fast Decay mode. At the start of the off
time, both of the power MOS are switched off and the current recirculates through the two
opposite free wheeling diodes. The current decays with a high dI/dt since the voltage across
the coil is essentially the power supply voltage. After the dead time, the lower power MOS in
parallel with the conducting diode is turned on in synchronous rectification mode. In
applications where the motor current is low it is possible that the current can decay
completely to zero during the off time. At this point if both of the power MOS were operating
in the synchronous rectification mode it would then be possible for the current to build in the
opposite direction. To prevent this only the lower power MOS is operated in synchronous
rectification mode. This operation is called Quasi-Synchronous Rectification Mode. When
the monostable times out, the power MOS are turned on again after some delay set by the
dead time to prevent cross conduction.
Figure 17 shows the operation of the bridge in the Slow Decay mode. At the start of the off
time, the lower power MOS is switched off and the current recirculates around the upper half
of the bridge. Since the voltage across the coil is low, the current decays slowly. After the
dead time the upper power MOS is operated in the synchronous rectification mode. When
the monostable times out, the lower power MOS is turned on again after some delay set by
the dead time to prevent cross conduction.
16/32
L6228Q
Circuit description
Figure 16. Fast decay mode output stage configurations
A) ON TIME
B) 1µs DEAD TIME
D01IN1335
C) QUASI-SYNCHRONOUS
RECTIFICATION
D) 1µs SLOW DECAY
Figure 17. Slow decay mode output stage configurations
A) ON TIME
B) 1µs DEAD TIME
D01IN1336
4.5
C) SYNCHRONOUS
RECTIFICATION
D) 1µs DEAD TIME
Stepping sequence generation
The phase sequence generator is a state machine that provides the phase and enable
inputs for the two bridges to drive a stepper motor in either full step or half step. Two full step
modes are possible, the Normal Drive Mode where both phases are energized each step
and the Wave Drive Mode where only one phase is energized at a time. The drive mode is
selected by the HALF/FULL input and the current state of the sequence generator as
described below. A rising edge of the CLOCK input advances the state machine to the next
state. The direction of rotation is set by the CW/CCW input. The RESET input resets the
state machine to state 1.
4.6
Half step mode
A HIGH logic level on the HALF/FULL input selects Half Step Mode. Figure 18 shows the
motor current waveforms and the state diagram for the Phase Sequencer Generator. At
Start-Up or after a RESET the Phase Sequencer is at state 1. After each clock pulse the
state changes following the sequence 1,2,3,4,5,6,7,8,… if CW/CCW is high (Clockwise
movement) or 1,8,7,6,5,4,3,2,… if CW/CCW is low (Counterclockwise movement).
17/32
Circuit description
4.7
L6228Q
Normal drive mode (Full-step two-phase-on)
A LOW level on the HALF/FULL input selects the Full Step mode. When the low level is
applied when the state machine is at an ODD numbered state the Normal Drive Mode is
selected. Figure 19 shows the motor current waveform state diagram for the state machine
of the Phase Sequencer Generator. The Normal Drive Mode can easily be selected by
holding the HALF/FULL input low and applying a RESET. At start -up or after a RESET the
State Machine is in state 1. While the HALF/FULL input is kept low, state changes following
the sequence 1,3,5,7,… if CW/CCW is high (Clockwise movement) or 1,7,5,3,… if CW/CCW
is low (Counterclockwise movement).
4.8
Wave drive mode (Full-step one-phase-on)
A LOW level on the pin HALF/FULL input selects the Full Step mode. When the low level is
applied when the state machine is at an EVEN numbered state the Wave Drive Mode is
selected. Figure 20 shows the motor current waveform and the state diagram for the state
machine of the Phase Sequence Generator. To enter the Wave Drive Mode the state
machine must be in an EVEN numbered state. The most direct method to select the Wave
Drive Mode is to first apply a RESET, then while keeping the HALF/FULL input high apply
one pulse to the clock input then take the HALF/FULL input low. This sequence first forces
the state machine to state 1. The clock pulse, with the HALF/FULL input high advances the
state machine from state 1 to either state 2 or 8 depending on the CW/CCW input. Starting
from this point, after each clock pulse (rising edge) will advance the state machine following
the sequence 2,4,6,8,… if CW/CCW is high (Clockwise movement) or 8,6,4,2,… if CW/CCW
is low (Counterclockwise movement).
Figure 18. Half step mode
IOUTA
3
4
5
2
6
1
8
IOUTB
7
Start Up or Reset
CLOCK
1
2
3
4
3
5
7
5
6
7
8
D01IN1320
Figure 19. Normal drive mode
IOUTA
3
4
2
1
5
IOUTB
6
8
7
CLOCK
Start Up or Reset
D01IN1322
18/32
1
1
3
5
7
L6228Q
Circuit description
Figure 20. Wave drive mode
IOUTA
3
4
IOUTB
6
2
1
5
8
7
CLOCK
Start Up or Reset
2
4
6
8
2
4
6
8
D01IN1321
4.9
Non-dissipative overcurrent protection
The L6228Q integrates an Overcurrent Detection Circuit (OCD) for full protection. This
circuit provides protection against a short circuit to ground or between two phases of the
bridge. With this internal over current detection, the external current sense resistor normally
used and its associated power dissipation are eliminated. Figure 21 shows a simplified
schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current IREF. When the
output current reaches the detection threshold (typically 2.8 A) the OCD comparator signals
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off
threshold (1.3 V typical) by an internal open drain MOS with a pull down capability of 4 mA.
By using an external R-C on the EN pin, the off time before recovering normal operation can
be easily programmed by means of the accurate thresholds of the logic inputs.
19/32
Circuit description
L6228Q
Figure 21. Overcurrent protection simplified schematic
OUT1A
VSA
OUT2A
POWER SENSE
1 cell
HIGH SIDE DMOSs OF
THE BRIDGE A
I1A
POWER DMOS
n cells
TO GATE
LOGIC
µC or LOGIC
POWER DMOS
n cells
POWER SENSE
1 cell
+
OCD
COMPARATOR
VDD
I2A
I1A / n
I2A / n
(I1A+I2A) / n
REN.
CEN.
EN
IREF
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
OVER TEMPERATURE
OCD
COMPARATOR
FROM THE
BRIDGE B
D01IN1337
Figure 22 shows the Overcurrent Detection operation. The Disable Time tDISABLE before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by CEN and REN values and its
magnitude is reported in Figure 23. The Delay Time tDELAY before turning off the bridge
when an overcurrent has been detected depends only by CEN value. Its magnitude is
reported in Figure 24.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore
the value of CEN should be chosen as big as possible according to the maximum tolerable
Delay Time and the REN value should be chosen according to the desired Disable Time.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 µs
Disable Time.
20/32
L6228Q
Circuit description
Figure 22. Overcurrent protection waveforms
IOUT
ISOVER
VEN
VDD
Vth(ON)
Vth(OFF)
VEN(LOW)
ON
OCD
OFF
ON
tDELAY
BRIDGE
tDISABLE
OFF
tOCD(ON)
tEN(FALL)
tOCD(OFF)
tD(OFF)EN
tEN(RISE)
tD(ON)EN
D02IN1400
21/32
Circuit description
L6228Q
Figure 23. tDISABLE versus CEN and REN (VDD = 5 V).
R EN = 220 kΩ
3
1 .1 0
R EN = 100 kΩ
R EN = 47 kΩ
R EN = 33 kΩ
tDISABLE [µs]
R EN = 10 kΩ
100
10
1
1
10
100
C E N [n F ]
Figure 24. tDELAY versus CEN (VDD = 5V).
tdelay [µs]
10
1
0.1
4.10
1
10
Cen [nF]
100
Thermal protection
In addition to the Ovecurrent Protection, the L6228Q integrates a Thermal Protection for
preventing the device destruction in case of junction over temperature. It works sensing the
die temperature by means of a sensible element integrated in the die. The device switch-off
when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis
(typ. value).
22/32
L6228Q
5
Application information
Application information
A typical Bipolar Stepper Motor Driver application using L6228Q is shown in Figure 25.
Typical component values for the application are shown in Table 7. A high quality ceramic
capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and
VSB) and ground near the L6228Q to improve the high frequency filtering on the power
supply and reduce high frequency transients generated by the switching. The capacitor
connected from the EN input to ground sets the shut down time when an over current is
detected (see Overcurrent Protection). The two current sensing inputs (SENSEA and
SENSEB) should be connected to the sensing resistors with a trace length as short as
possible in the layout. The sense resistors should be non-inductive resistors to minimize the
dI/dt transients across the resistor. To increase noise immunity, unused logic pins (except
EN) are best connected to 5 V (High Logic Level) or GND (Low Logic Level) (see pin
description). It is recommended to keep Power Ground and Signal Ground separated on
PCB.
Table 7.
Component values for typical application
Component
Value
C1
100µF
C2
100nF
CA
1nF
CB
1nF
CBOOT
220nF
CP
10nF
CEN
5.6nF
CREF
68nF
D1
1N4148
D2
1N4148
RA
39kΩ
RB
39kΩ
REN
100kΩ
RP
100Ω
RSENSEA
0.6Ω
RSENSEB
0.6Ω
23/32
Application information
L6228Q
Figure 25. Typical application
Note:
24/32
To reduce the IC thermal resistance, therefore improve the dissipation path, the NC pins can
be connected to GND.
L6228Q
6
Output current capability and IC power dissipation
Output current capability and IC power dissipation
In Figure 26, Figure 27, Figure 28 and Figure 29 are shown the approximate relation
between the output current and the IC power dissipation using PWM current control driving
a two-phase stepper motor, for different driving sequences:
●
HALF STEP mode (Figure 26) in which alternately one phase / two phases are
energized.
●
NORMAL DRIVE (FULL-STEP TWO PHASE ON) mode (Figure 27) in which two
phases are energized during each step.
●
WAVE DRIVE (FULL-STEP ONE PHASE ON) mode (Figure 27) in which only one
phase is energized at each step.
●
MICROSTEPPING mode (Figure 29), in which the current follows a sine-wave profile,
provided through the Vref pins.
For a given output current and driving sequence the power dissipated by the IC can be
easily evaluated, in order to establish which package should be used and how large must be
the on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
Figure 26. IC power dissipation versus output current in HALF STEP mode
HALF STEP
10
IA
I OUT
8
IB
6
PD [W]
I OUT
4
2
0
0 0.25 0.5 0.75 1 1.25 1.5
I OUT [A]
Test Conditions:
Supply Voltage = 24V
No PWM
f SW = 30 kHz (slow decay)
25/32
Output current capability and IC power dissipation
L6228Q
Figure 27. IC power dissipation versus output current in NORMAL mode
(full step two phase on)
NORM AL DRIVE
IA
10
8
I OUT
IB
6
I OUT
PD [W ]
4
Test Conditions:
Supply Volt age =24 V
2
0
0
0.25 0.5 0.75 1
No PWM
f SW = 30 kHz (slow decay)
1.25 1.5
I OUT [A ]
Figure 28. IC power dissipation versus output current in WAVE mode
(full step one phase on)
WAVE DRIVE
10
IA
I OUT
8
IB
6
PD [W]
I OUT
4
Test Conditions:
Supply Voltage = 24V
2
0
0
0.25 0.5 0.75 1
No PW M
fSW = 3 0 kHz (slow decay)
1.25 1.5
I OUT [A]
Figure 29. IC power dissipation versus output current in MICROSTEPPING mode
MICROSTEPPING
10
IA
I OUT
8
I OUT
6
IB
PD [W]
4
2
0
0
0.25 0.5 0.75 1
I OUT [A]
26/32
1.25 1.5
Test Conditions:
Supply Voltage = 24V
f SW = 30 kHz (slow decay)
f SW = 50 kHz (slow decay)
L6228Q
7
Thermal management
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness.
For instance, using a VFQFPN32L 5x5 package the typical Rth(j-amb) is about 32 °C/W.
27/32
Package mechanical data
8
L6228Q
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Table 8.
VFQFPN 5x5x1.0 32L pitch 0.50
Databook (mm)
Dim.
Min
Typ
Max
A
0.80
0.85
0.95
b
0.18
0.25
0.30
b1
0.165
0.175
0.185
D
4.85
5.00
5.15
D2
3.00
3.10
3.20
D3
1.10
1.20
1.30
E
4.85
5.00
5.15
E2
4.20
4.30
4.40
E3
0.60
0.70
0.80
e
L
ddd
Note:
0.50
0.30
0.40
0.50
0.08
VFQFPN stands for Thermally Enhanced Very thin profile Fine pitch Quad Flat Package No
lead. Very thin profile: 0.80 < A < 1.00mm.
Details of terminal 1 are optional but must be located on the top surface of the package by
using either a mold or marked features.
28/32
L6228Q
Package mechanical data
Figure 30. Package dimensions
29/32
Order codes
9
Order codes
Table 9.
30/32
L6228Q
Order codes
Part number
Package
Packaging
L6228Q
VFQFPN 5x5x1.0 32L
Tube
L6228Q
10
Revision history
Revision history
Table 10.
Document revision history
Date
Revision
14-Jan-2008
1
Changes
First release
31/32
L6228Q
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