IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM SEPTEMBER 2007 FEATURES DESCRIPTION • 100 percent bus utilization The 4 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K words by 18 bits, fabricated with ISSI's advanced CMOS technology. • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119ball PBGA packages • Power supply: NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) • Industrial temperature available • Lead-free available Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence.When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency -250 2.6 4 250 -200 3.1 5 200 Units ns ns MHz Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 1 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A BLOCK DIAGRAM x 32/x 36: A [0:16] or x 18: A [0:17] ADDRESS REGISTER MODE A0-A1 CLK CONTROL LOGIC K CKE 128Kx32; 128Kx36; 256Kx18 MEMORY ARRAY A2-A16 or A2-A17 WRITE ADDRESS REGISTER BURST ADDRESS COUNTER A'0-A'1 WRITE ADDRESS REGISTER K DATA-IN REGISTER K DATA-IN REGISTER CE CE2 CE2 ADV WE BWŸX } CONTROL REGISTER K CONTROL LOGIC (X=a,b,c,d or a,b) OUTPUT REGISTER BUFFER OE ZZ 32, 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A Bottom View 165-Ball, 13 mm x 15mm BGA 1 mm Ball Pitch, 11 x 15 Ball Array Bottom View 119-Ball, 14 mm x 22 mm BGA 1 mm Ball Pitch, 7 x 17 Ball Array Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 3 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A Pin Configuration — 128K x 36, 165-Ball PBGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd CE CE2 Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq BWc BWd VSS Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS CKE WE VSS VSS VSS VSS VSS VSS VSS VSS VSS ADV OE VSS Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd NC NC Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq A A NC DQb DQb DQb DQb NC DQa DQa DQa NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa N P R DQPd NC MODE NC NC NC Vddq A A Vdd VSS A A VSS NC NC NC VSS NC A1* A0* VSS NC NC NC Vdd VSS A A Vddq Vddq A A DQa NC A A DQa DQPa NC A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a-d) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode 4 MODE VDD NC DQx DQPx VDDQ Vss Burst Sequence Selection 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 119-PIN PBGA PACKAGE CONFIGURATION 128K x 36 (TOP VIEW) 1 2 3 4 5 6 A VDDQ A A NC A A VDDQ B NC CE2 A ADV A CE2 NC C NC A A VDD A A NC D DQc DQPc VSS NC Vss DQPb DQb E DQc DQc VSS CE Vss DQb DQb F VDDQ DQc VSS OE Vss DQb VDDQ G DQc DQc BWc NC BWb DQb DQb H DQc DQc VSS WE Vss DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS CLK Vss DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd VSS CKE Vss DQa VDDQ N DQd DQd VSS A 1* Vss DQa DQa P DQd DQPd VSS A0* Vss DQPa DQa R NC A MODE VDD NC A NC T NC NC A A A NC ZZ U VDDQ NC NC NC NC VDDQ NC 7 Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a-d) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 OE ZZ MODE Vdd Vss NC DQa-DQd DQPa-Pd Vddq Output Enable Power Sleep Mode Burst Sequence Selection Power Supply Ground No Connect Data Inputs/Outputs Parity Data I/O Output Power Supply 5 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 165-PIN PBGA PACKAGE CONFIGURATION 256K x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A BWb NC CE2 CKE ADV B NC A CE CE2 NC NC A A C NC NC VDDQ NC Vss BWa Vss CLK Vss WE Vss D NC DQb VDDQ VDD Vss Vss Vss OE Vss VDD A VDDQ NC NC DQPa VDDQ NC DQa E NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa F NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa G NC DQb VDDQ Vss H NC NC NC VDD VDD Vss Vss Vss Vss VDD VDD VDDQ NC DQa J DQb NC VDDQ VDD Vss Vss NC NC ZZ Vss Vss VDD VDDQ DQa NC K DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa VDD Vss Vss VDD VDDQ DQa VDDQ VDD Vss Vss Vss NC NC L DQb NC VDDQ M DQb NC Vss VDD VDDQ DQa NC N DQPb NC Vss A NC NC NC NC Vss NC NC NC VDDQ A P NC A NC R MODE NC A A NC A A A1* A0* NC A VDDQ A NC A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a,b) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode 6 MODE VDD NC DQx DQPx VDDQ Vss Burst Sequence Selection 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 119-PIN PBGA PACKAGE CONFIGURATION 256K x 18 (TOP VIEW) 1 2 3 4 5 6 7 A VDDQ A A NC A A VDDQ B NC CE2 A ADV A CE2 NC C NC A A VDD A A NC D DQb NC VSS NC Vss DQPa NC E DQb VSS CE Vss NC DQa F NC VDDQ NC VSS OE Vss DQa VDDQ G NC DQb BWb NC NC NC DQa H DQb NC WE Vss DQa NC J VDDQ VDD VSS NC VDD NC VDD VDDQ K NC DQb VSS CLK Vss NC DQa L DQb NC NC NC BWa DQa NC M VDDQ DQb VSS CKE Vss NC VDDQ N DQb NC VSS A 1* Vss DQa NC P NC DQPb VSS A0* Vss NC DQa R NC A MODE VDD NC A NC T NC A A NC A A ZZ U VDDQ NC NC NC NC NC VDDQ Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a,b) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 OE ZZ MODE Vdd Vss NC DQa-DQb DQPa-Pb Vddq Output Enable Power Sleep Mode Burst Sequence Selection Power Supply Ground No Connect Data Inputs/Outputs Parity Data I/O Output Power Supply 7 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIGURATION DQb DQc DQb Vss NC VDD ZZ DQc NC VDD DQa DQd DQa DQd VDDQ VDDQ Vss NC Vss DQa Vss DQd DQa DQd DQa DQa Vss DQd DQd Vss VDDQ VDDQ DQa DQa DQPa DQd DQd NC NC OE ADV NC CKE CLK WE CE2 VDD Vss BWa BWc BWb BWd CE2 CE A A NC DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa NC A A VDDQ VDDQ A Vss Vss A DQc A DQb A DQb DQc NC A DQc DQc NC DQb DQb VDD Vss Vss Vss NC NC VDDQ A A NC OE ADV NC CKE CLK WE CE2 VDD Vss BWa BWc BWb BWd CE2 CE A A VDDQ A1 A0 MODE DQd DQd DQPd DQc A VDDQ DQb A DQd DQd Vss DQc A DQd DQb 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A Vss DQd NC MODE VDDQ DQPb A A DQd A DQd A NC Vss A DQc NC VDD A DQc NC A VDDQ NC Vss VDD DQc Vss DQc NC NC DQc DQc A1 A0 Vss A VDDQ A DQc A DQc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQPc A A 100-Pin TQFP 128K x 32 128K x 36 PIN DESCRIPTIONS A0, A1 A CLK ADV BWa-BWd WE CKE Vss NC 8 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected CE, CE2, CE2 OE DQa-DQd DQPa-DQPd MODE Vdd Vss Vddq ZZ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIGURATION VDDQ Vss DQb DQb DQPb NC Vss VDDQ MODE NC NC NC NC ADV NC OE CKE CLK WE CE2 VDD Vss BWa NC BWb NC CE2 CE A A A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC A A DQb A DQb A NC Vss A DQb NC VDD A DQb NC A VDDQ NC Vss VDD DQb Vss DQb NC NC NC NC A1 A0 Vss A VDDQ A NC A NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC A A 100-Pin TQFP 256K x 18 PIN DESCRIPTIONS A0, A1 A CLK ADV BWa-BWd WE CKE Vss NC Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 CE, CE2, CE2 OE DQa-DQd DQPa-DQPd MODE Vdd Vss Vddq ZZ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable 9 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A STATE DIAGRAM READ READ READ BURST WRITE BEGIN READ DS DS READ WRITE DESELECT BURST BURST READ BEGIN WRITE BURST DS BURST DS DS WRITE READ BURST WRITE WRITE WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Notes: Address Used N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address CE H X X X L X L X L X L X X CE2 X L X X H X H X H X H X X CE2 X X H X L X L X L X L X X ADV L L L H L H L H L H L H X WE X X X X H X H X L X L X X BWx X X X X X X X X L L H H X OE X X X X L L H H X X X X X CKE L L L L L L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1. 2. 3. 4. "X" means don't care. The rising edge of clock is symbolized by ↑ A continue deselect cycle can only be entered if a deselect cycle is executed first. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ASYNCHRONOUS TRUTH TABLE(1) Operation Sleep Mode Read Write Deselected Notes: ZZ H L L L L I/O STATUS High-Z DQ High-Z Din, High-Z High-Z OE X L H X X 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L BWa X L H L H BWb X H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 11 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A WRITE TRUTH TABLE (x32/x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L L L BWa X L H H H L H BWb X H L H H L H BWc X H H L H L H BWd X H H H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC) External Address A1 A0 00 01 10 11 12 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol Tstg Pd Iout Vin, Vout Vin Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs Value –65 to +150 1.6 100 –0.5 to Vddq + 0.5 –0.5 to 4.6 Unit °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61NLPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C Vdd 3.3V ± 5% 3.3V ± 5% Vddq 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% Vdd 2.5V ± 5% 2.5V ± 5% Vddq 2.5V ± 5% 2.5V ± 5% OPERATING RANGE (IS61NVPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 13 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V Symbol Parameter Voh Output HIGH Voltage Vol Output LOW Voltage Vih(1) Input HIGH Voltage (1) Vil Input LOW Voltage Ili Input Leakage Current Ilo Output Leakage Current Test Conditions Min. Ioh = –4.0 mA (3.3V) 2.4 Ioh = –1.0 mA (2.5V) Iol = 8.0 mA (3.3V) — Iol = 1.0 mA (2.5V) 2.0 –0.3 (1) Vss ≤ Vin ≤ Vdd –5 Vss ≤ Vout ≤ Vddq, OE = Vih –5 2.5V Max. — Min. 2.0 Max. — Unit V 0.4 — 0.4 V Vdd + 0.3 0.8 5 5 1.7 –0.3 –5 –5 Vdd + 0.3 0.7 5 5 V V µA µA Note: 1. Overshoot: Vih (AC) < Vdd + 2.0V (Pulse width less than tkc/2). Undershoot: Vil (AC) > -2V (Pulse width less than tkc/2). POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc AC Operating Supply Current -250 MAX x18x32/x36 225 225 250 250 Test Conditions Temp. range Device Selected, Com. OE = Vih, ZZ ≤ Vil, Ind. All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Cycle Time ≥ tkc min. Isb Standby Current Device Deselected, Com. 90 90 TTL Input Vdd = Max., Ind. 100 100 All Inputs ≤ Vil or ≥ Vih, ZZ ≤ Vil, f = Max. Isbi Standby Current Device Deselected, Com. 70 70 CMOS Input Vdd = Max., Ind. 75 75 Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V typ.(2) 40 f=0 Isb2 Sleep Mode ZZ>Vih Com. 30 30 Ind. 35 35 typ.(2) 20 -200 MAX x18x32/x36 200 200 210 210 Unit mA 90 90 100 100 mA 70 70 75 75 mA 30 30 35 35 mA Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. 2. Typical values are measured at Vdd = 3.3V, Ta = 25oC and not 100% tested. 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω +3.3V Zo= 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 351 Ω 1.5V Figure 1 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 Figure 2 15 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 16 Figure 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z -250 Min. — 4.0 1.7 1.7 — 0.8 0.8 — — 0 Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down — 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 — — Symbol fmax tkc tkh tkl tkq tkqx(2) tkqlz(2,3) tkqhz(2,3) toeq toelz(2,3) toehz(2,3) tas tws tces tse tadvs tds tah the twh tceh tadvh tdh tpds tpus Notes: Max. 250 — — — 2.6 — — 2.6 2.8 — 2.6 — — — — — — — — — — — — 2 2 -200 Min. Max. — 200 5 — 2 — 2 — — 3.1 1.5 — 1 — — 3.0 — 3.1 0 — Unit MHz ns ns ns ns ns ns ns ns ns — 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 — — ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc 3.0 — — — — — — — — — — — — 2 2 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 17 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Isb2 tpds tpus tzzi trzzi Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current Conditions ZZ ≥ Vih Min. Max. 35 2 2 2 0 Unit mA cycle cycle cycle ns SLEEP MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care 18 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A READ CYCLE TIMING tKH tKL CLK tKC tADVS tADVH ADV tAS tAH Address A1 A3 A2 tWS tWH WRITE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ Data Out Q1-1 tOEHZ tKQX Q2-1 tKQ Q2-2 tKQHZ Q2-3 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don't Care Undefined 19 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A WRITE CYCLE TIMING tKH tKL CLK tKC ADV Address A1 A3 A2 WRITE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tOEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 20 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A SINGLE READ/WRITE CYCLE TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 Q1 Q3 A5 A6 A7 A8 A9 WRITE CE ADV OE tOEQ Data Out tOELZ Q4 Q6 Q7 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 D5 Don't Care Undefined 21 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CKE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CE ADV OE tKQ Data Out tKQLZ tKQHZ Q1 Q3 Q4 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 22 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 WRITE CE ADV OE tOEQ Data Out tOELZ tKQHZ Q1 tKQ tKQLZ Q2 Q4 tDS tDH D3 Data In NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 D5 Don't Care Undefined 23 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V/3.3V) Commercial Range: 0°C to +70°C Access Time 250 200 250 200 250 200 24 Order Part Number 128Kx32 IS61NLP12832B-250TQ IS61NLP12832B-250B3 IS61NLP12832B-250B2 IS61NLP12832B-200TQ IS61NLP12832B-200B3 IS61NLP12832B-200B2 128Kx36 IS61NLP12836B-250TQ IS61NLP12836B-250B3 IS61NLP12836B-250B2 IS61NLP12836B-200TQ IS61NLP12836B-200B3 IS61NLP12836B-200B2 256Kx18 IS61NLP25618A-250TQ IS61NLP25618A-250B3 IS61NLP25618A-250B2 IS61NLP25618A-200TQ IS61NLP25618A-200B3 IS61NLP25618A-200B2 Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V/3.3V) Industrial Range: -40°C to +85°C Access Time 250 200 250 200 250 200 Order Part Number 128Kx32 IS61NLP12832B-250TQI IS61NLP12832B-250B3I IS61NLP12832B-250B2I IS61NLP12832B-200TQI IS61NLP12832B-200TQLI IS61NLP12832B-200B3I IS61NLP12832B-200B2I 128Kx36 IS61NLP12836B-250TQI IS61NLP12836B-250B3I IS61NLP12836B-250B2I IS61NLP12836B-200TQI IS61NLP12836B-200TQLI IS61NLP12836B-200B3I IS61NLP12836B-200B2I IS61NLP12836B-200B2LI 256Kx18 IS61NLP25618A-250TQI IS61NLP25618A-250B3I IS61NLP25618A-250B2I IS61NLP25618A-200TQI IS61NLP25618A-200TQLI IS61NLP25618A-200B3I IS61NLP25618A-200B3LI IS61NLP25618A-200B2I Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA 119 PBGA, Lead-free 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 165 PBGA, Lead-free 119 PBGA 25 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERING INFORMATION (Vdd = 2.5V/Vddq = 2.5V) Commercial Range: 0°C to +70°C Access Time 250 200 250 200 Order Part Number 128Kx36 IS61NVP12836B-250TQ IS61NVP12836B-250B3 IS61NVP12836B-250B2 IS61NVP12836B-200TQ IS61NVP12836B-200B3 IS61NVP12836B-200B2 256Kx18 IS61NVP25618A-250TQ IS61NVP25618A-250B3 IS61NVP25618A-250B2 IS61NVP25618A-200TQ IS61NVP25618A-200B3 IS61NVP25618A-200B2 Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA Industrial Range: -40°C to +85°C Access Time 250 200 250 200 26 Order Part Number 128Kx36 IS61NVP12836B-250TQI IS61NVP12836B-250B3I IS61NVP12836B-250B2I IS61NVP12836B-200TQI IS61NVP12836B-200B3I IS61NVP12836B-200B2I 256Kx18 IS61NVP25618A-250TQI IS61NVP25618A-250B3I IS61NVP25618A-250B2I IS61NVP25618A-200TQI IS61NVP25618A-200B3I IS61NVP25618A-200B2I Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 PACKAGING INFORMATION Plastic Ball Grid Array Package Code: B (119-pin) φ b (119X) E A 7 6 5 4 D2 D1 e A2 A3 E2 Sym. Min. N0. Leads Max. SEATING PLANE INCHES Min. Max. Notes: 119 A — 2.41 — 0.095 A1 0.50 0.70 0.020 0.028 A2 0.80 1.00 0.032 0.039 A3 1.30 1.70 0.051 0.067 A4 0.56 BSC 0.60 0.90 0.024 0.035 D 21.80 22.20 0.858 0.874 20.32 BSC 0.800 BSC D2 19.40 19.60 0.764 0.772 E 13.80 14.20 0.543 0.559 E1 E2 e 7.62 BSC 11.90 12.10 1.27 BSC 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 0.022 BSC b D1 E1 A1 A4 MILLIMETERS 1 A B C D E F G H J K L M N P R T U 30ϒ D 3 2 0.300 BSC 0.469 0.476 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 02/12/03 PACKAGING INFORMATION Ball Grid Array Package Code: B (165-pin) BOTTOM VIEW TOP VIEW A1 CORNER 1 2 3 4 A1 CORNER φ b (165X) 5 6 7 8 9 10 11 10 11 9 8 7 6 5 4 3 2 1 A A B B C C D D E E e F F G G D D1 H H J J K K L L M M N N P P R R E1 E A2 e A A1 BGA - 13mm x 15mm MILLIMETERS Sym. Min. N0. Leads Nom. Max. Notes: 1. Controlling dimensions are in millimeters. INCHES Min. 165 Nom. Max. 165 A — — 1.20 — A1 0.25 0.33 0.40 0.010 — 0.047 0.013 0.016 A2 — 0.79 — — 0.031 — D 14.90 15.00 15.10 0.587 0.591 0.594 D1 13.90 14.00 14.10 0.547 0.551 0.555 E 12.90 13.00 13.10 0.508 0.512 0.516 E1 9.90 10.00 10.10 0.390 0.394 0.398 e — 1.00 — — 0.039 — b 0.40 0.45 0.50 0.016 0.018 0.020 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 06/11/03 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ D D1 E E1 N L1 L C 1 e SEATING PLANE A2 A b A1 Millimeters Min Max Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max Symbol Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. o o C 0 7 0o 7o 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03 Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters.