Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters AD9776/AD9778/AD9779 FEATURES GENERAL DESCRIPTION Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions SFDR = 78 dBc to fOUT = 100 MHz Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP package The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high dynamic range, digital-to-analog converters (DACs) that provide a sample rate of 1 GSPS, permitting multicarrier generation up to the Nyquist frequency. They include features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators such as the AD8349. A serial peripheral interface (SPI®) provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 10 mA to 30 mA. The devices are manufactured on an advanced 0.18 μm CMOS process and operate on 1.8 V and 3.3 V supplies for a total power consumption of 1.0 W. They are enclosed in 100-lead TQFP packages. APPLICATIONS Wireless infrastructure WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM Digital high or low IF synthesis Internal digital upconversion capability Transmit diversity Wideband communications: LMDS/MMDS, point-to-point PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. CMOS data input interface with adjustable set up and hold. Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth. TYPICAL SIGNAL CHAIN QUADRATURE MODULATOR/ MIXER/ AMPLIFIER COMPLEX I AND Q DC LO DC DIGITAL INTERPOLATION FILTERS I DAC POST DAC ANALOG FILTER FPGA/ASIC/DSP AD9779 A 05361-114 Q DAC Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. AD9776/AD9778/AD9779 TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Map ............................................................................ 27 Applications....................................................................................... 1 Interpolation Filter Architecture .................................................. 31 General Description ......................................................................... 1 Interpolation Filter Minimum and Maximum Bandwidth Specifications .............................................................................. 35 Product Highlights ........................................................................... 1 Typical Signal Chain......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 Digital Specifications ................................................................... 6 Digital Input Data Timing Specifications ................................. 7 AC Specifications.......................................................................... 7 Absolute Maximum Ratings............................................................ 8 Driving the REFCLK Input....................................................... 35 Internal PLL Clock Multiplier/Clock Distribution................ 36 Full-Scale Current Generation ................................................. 38 Power Dissipation....................................................................... 39 Power-Down and Sleep Modes................................................. 41 Interleaved Data Mode .............................................................. 41 Timing Information ................................................................... 41 Synchronization of Input Data to DATACLK Output (Pin 37)........................................................................... 43 Thermal Resistance ...................................................................... 8 Synchronization of Input Data to the REFCLK Input (Pin 5 and Pin 6) with PLL Enabled or Disabled............................... 43 ESD Caution.................................................................................. 8 Evaluation Board Operation ......................................................... 46 Pin Configurations and Function Descriptions ........................... 9 Modifying the Evaluation Board to Use the AD8349 OnBoard Quadrature Modulator................................................... 48 Typical Performance Characteristics ........................................... 15 Terminology .................................................................................... 24 Theory of Operation ...................................................................... 25 Evaluation Board Schematics ................................................... 49 Outline Dimensions ....................................................................... 56 Ordering Guide .......................................................................... 56 Serial Peripheral Interface ......................................................... 25 MSB/LSB Transfers..................................................................... 26 REVISION HISTORY 3/07—Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Applications .................................................................. 1 Changes to General Product Highlights........................................ 1 Added Figure 1, Renumbered Figures Sequentially..................... 1 Changes to Table 1............................................................................ 4 Changes to Table 2............................................................................ 5 Changes to Table 3............................................................................ 5 Changes to Figure 53 and Figure 54............................................. 26 Changes to Table 12........................................................................ 29 Changes to Power Dissipation Section ........................................ 39 Added Table 19, Renumbered Tables Sequentially .................... 41 Changes to Figure 92 and Figure 93............................................. 42 Changes to Figure 94...................................................................... 42 Added New Figure 95, Renumbered Figures Sequentially ....... 42 Changes to Synchronization of Input Data to the REFCLK Input (Pin 5 and Pin 6) with PLL Enabled or Disabled Section ......... 43 Added New Figure 96, Renumbered Figures Sequentially ....... 43 Changes to Figure 106 ................................................................... 51 7/05—Revision 0: Initial Version Rev. A | Page 2 of 56 AD9776/AD9778/AD9779 FUNCTIONAL BLOCK DIAGRAM DELAY LINE CLOCK GENERATION/DISTRIBUTION SYNC_I DATACLK_OUT CLOCK MULTIPLIER 2×/4×/8× DELAY LINE DATA ASSEMBLER SYNC1 2× 2× 2× n × fDAC /8 n = 0, 1, 2 ... 7 2× 2× 2× SYNC1 DIGITAL CONTROLLER 10 10 SERIAL PERIPHERAL INTERFACE 16-BIT IDAC GAIN 16-BIT QDAC IOUT1_P IOUT1_N IOUT2_P IOUT2_N VREF I120 GAIN POWER-ON RESET 10 10 GAIN AUX1_P AUX1_N GAIN AUX2_P AUX2_N 05361-001 Q LATCH SDO SDIO SCLK CSB P2D(15:0) CLK– COMPLEX MODULATOR P1D(15:0) I LATCH CLK+ REFERENCE AND BIAS SYNC_O Figure 2. Functional Block Diagram Rev. A | Page 3 of 56 AD9776/AD9778/AD9779 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. AD9776, AD9778, and AD9779 DC Specifications Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Output Resistance Gain DAC Monotonicity MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage AUX DAC OUTPUTS Resolution Full-Scale Output Current1 Output Compliance Range (Source) Output Compliance Range (Sink) Output Resistance Aux DAC Monotonicity Guaranteed REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD33 DVDD18 POWER CONSUMPTION 1× Mode, fDAC = 100 MSPS, IF = 1 MHz 2× Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL Off 2× Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL On 4× Mode, fDAC/4 Modulation, fDAC = 500 MSPS, IF = 137.5 MHz, Q DAC Off Min AD9776 Typ Max 12 AD9778 Typ Max 14 Min ±0.1 ±0.6 Min ±0.65 ±1 AD9779 Typ Max 16 ±2.1 ±3.7 Unit Bits LSB LSB −0.001 0 ±2 +0.001 −0.001 0 ±2 +0.001 −0.001 0 ±2 +0.001 % FSR % FSR 8.66 −1.0 20.2 31.66 +1.0 8.66 −1.0 20.2 31.66 +1.0 8.66 −1.0 20.2 31.66 +1.0 mA V MΩ 10 Guaranteed 10 Guaranteed 0.04 100 30 10 Guaranteed 0.04 100 30 10 0.04 100 30 10 ppm/°C ppm/°C ppm/°C −1.998 0 +1.998 1.6 −1.998 0 +1.998 1.6 −1.998 0 10 +1.998 1.6 Bits mA V 0.8 1.6 0.8 1.6 0.8 1.6 V 1 1 1 MΩ 1.2 5 1.2 5 1.2 5 V kΩ 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 V V 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 V V 250 300 250 300 250 300 mW 498 498 498 mW 588 588 588 mW 572 572 572 mW Rev. A | Page 4 of 56 AD9776/AD9778/AD9779 Parameter 8× Mode, fDAC/4 Modulation, fDAC = 1 GSPS, IF = 262.5 MHz Power-Down Mode Power Supply Rejection Ratio, AVDD33 OPERATING RANGE 1 Min AD9776 Typ Max 980 2 −0.3 −40 +25 Min 3.7 +0.3 −0.3 +85 −40 AD9778 Typ Max 980 2 Based on a 10 kΩ external resistor. Rev. A | Page 5 of 56 +25 Min 3.7 +0.3 −0.3 +85 −40 AD9779 Typ Max 980 Unit mW 2 3.7 +0.3 mW % FSR/V +25 +85 °C AD9776/AD9778/AD9779 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. AD9776, AD9778, and AD9779 Digital Specifications Parameter CMOS INPUT LOGIC LEVEL Input VIN Logic High Input VIN Logic Low Maximum Input Data Rate at Interpolation 1× 2× 4× 8× CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37) 1 Output VOUT Logic High Output VOUT Logic Low LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH − VIDTHL Receiver Differential Input Impedance, RIN 2 LVDS Input Rate Set-Up Time, SYNC_I to DAC Clock Hold Time, SYNC_I to DAC Clock LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage, |VOD| Output Offset Voltage, VOS Output Impedance, RO Maximum Clock Rate DAC CLOCK INPUT (CLK+, CLK−) Differential Peak-to-Peak Voltage (CLK+, CLK−) 3 Common-Mode Voltage Maximum Clock Rate 4 SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High Minimum Pulse Width Low Conditions Min Typ Max Unit 0.8 V V 2.0 300 250 200 125 MSPS MSPS MSPS MSPS 2.4 0.4 V V SYNC_I+ = VIA, SYNC_I− = VIB 825 −100 1575 +100 20 80 120 125 −0.2 1 mV mV mV Ω MSPS ns ns SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination Single-ended 825 1025 150 1150 80 1 400 300 1 1575 200 100 250 1250 120 800 400 2000 500 40 12.5 12.5 1 mV mV mV mV Ω GHz mV mV GSPS MHz ns ns Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests using an external buffer for this signal. Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C. 3 When using the PLL, a differential swing of 2 V p-p is recommended. 4 Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V. 2 Rev. A | Page 6 of 56 AD9776/AD9778/AD9779 DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. AD9776, AD9778, and AD9779 Digital Input Data Timing Specifications Parameter INPUT DATA (ALL MODES, −40°C to +85°C) 1 Set-Up Time, Input Data to DATACLK Hold Time, Input Data to DATACLK Set-Up Time, Input Data to REFCLK Hold Time, Input Data to REFCLK 1 Min Typ Max +2.5 −0.4 −0.8 +2.9 Unit ns ns ns ns Timing vs. temperature and data valid keep out windows are delineated in Table 19. AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4. AD9776, AD9778, and AD9779 AC Specifications Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 100 MSPS, fOUT = 20 MHz fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 70 MHz fDAC = 800 MSPS, fOUT = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 60 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 100 MHz NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING fDAC = 200 MSPS, fOUT = 80 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 80 MHz WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 100 MHz fDAC = 491.52 MSPS, fOUT = 200 MHz WCDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 100 MHz fDAC = 491.52 MSPS, fOUT = 200 MHz Min AD9776 Typ Max Min AD9778 Typ Max Min AD9779 Typ Max Unit 82 81 80 85 82 81 80 85 82 82 80 87 dBc dBc dBc dBc 87 80 75 75 87 85 81 80 91 85 81 81 dBc dBc dBc dBc −152 −155 −157.5 −155 −159 −160 −158 −160 −161 dBm/Hz dBm/Hz dBm/Hz 76 69 78 73 79 74 dBc dBc 77.5 76 80 78 81 78 dBc dBc Rev. A | Page 7 of 56 AD9776/AD9778/AD9779 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD33, DVDD33 DVDD18, CVDD18 AGND DGND CGND I120, VREF, IPTAT IOUT1-P, IOUT1-N, IOUT2-P, IOUT2-N, Aux1-P, Aux1-N, Aux2-P, Aux2-N P1D15 to P1D0, P2D15 to P2D0 DATACLK, TXENABLE CLK+, CLK− RESET, IRQ, PLL_LOCK, SYNC_O+, SYNC_O−, SYNC_I+, SYNC_I−, CSB, SCLK, SDIO, SDO Junction Temperature Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. With Respect To AGND, DGND, CGND AGND, DGND, CGND DGND, CGND AGND, CGND AGND, DGND AGND AGND −0.3 V to AVDD33 + 0.3 V −1.0 V to AVDD33 + 0.3 V DGND −0.3 V to DVDD33 + 0.3 V DGND CGND DGND −0.3 V to DVDD33 + 0.3 V −0.3 V to CVDD18 + 0.3 V −0.3 V to DVDD33 + 0.3 V Rating −0.3 V to +3.6 V −0.3 V to +1.98 V THERMAL RESISTANCE −0.3 V to +0.3 V 100-lead, thermally enhanced TQFP_EP package, θJA = 19.1°C/W with the bottom EPAD soldered to the PCB. With the bottom EPAD not soldered to the PCB, θJA = 27.4°C/W. These specifications are valid with no airflow movement. −0.3 V to +0.3 V −0.3 V to +0.3 V ESD CAUTION +125°C −65°C to +150°C Rev. A | Page 8 of 56 AD9776/AD9778/AD9779 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 PIN 1 2 CGND 3 ANALOG DOMAIN 75 I120 74 VREF 73 IPTAT CGND 4 72 AGND CLK+ 5 71 IRQ CLK– 6 70 RESET CGND 7 69 CSB CGND 8 68 SCLK DIGITAL DOMAIN CVDD18 9 AD9776 67 SDIO CVDD18 10 TOP VIEW (Not to Scale) 66 SDO 65 PLL_LOCK AGND 12 64 DGND SYNC_I+ 13 63 SYNC_O+ SYNC_I– 14 62 SYNC_O– DGND 15 61 DVDD33 DVDD18 16 60 DVDD18 P1D<11> 17 59 NC P1D<10> 18 58 NC P1D<9> 19 57 NC P1D<8> 20 56 NC P1D<7> 21 55 P2D<0> DGND 22 54 DGND DVDD18 23 53 DVDD18 P1D<6> 24 52 P2D<1> P1D<5> 25 51 P2D<2> CGND 11 P2D<3> P2D<4> P2D<5> P2D<6> P2D<7> P2D<8> DGND DVDD18 P2D<9> P2D<10> P2D<11> TXENABLE DVDD33 DATACLK NC NC NC DVDD18 DGND NC P1D<0> P1D<1> P1D<2> P1D<3> 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P1D<4> NC = NO CONNECT 05361-002 CVDD18 Figure 3. AD9776 Pin Configuration Table 6. AD9776 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Mnemonic CVDD18 CVDD18 CGND CGND CLK+ 1 CLK−1 CGND CGND CVDD18 CVDD18 CGND AGND SYNC_I+ SYNC_I− DGND DVDD18 P1D<11> P1D<10> P1D<9> Description 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Common. Clock Common. Differential Clock Input. Differential Clock Input. Clock Common. Clock Common. 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Common. Analog Common. Differential Synchronization Input. Differential Synchronization Input. Digital Common. 1.8 V Digital Supply. Port 1, Data Input D11 (MSB). Port 1, Data Input D10. Port 1, Data Input D9. Pin No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Rev. A | Page 9 of 56 Mnemonic P1D<8> P1D<7> DGND DVDD18 P1D<6> P1D<5> P1D<4> P1D<3> P1D<2> P1D<1> P1D<0> NC DGND DVDD18 NC NC NC DATACLK DVDD33 Description Port 1, Data Input D8. Port 1, Data Input D7. Digital Common. 1.8 V Digital Supply. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Port 1, Data Input D2. Port 1, Data Input D1. Port 1, Data Input D0 (LSB). No Connect. Digital Common. 1.8 V Digital Supply. No Connect. No Connect. No Connect. Data Clock Output. 3.3 V Digital Supply. AD9776/AD9778/AD9779 Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Mnemonic TXENABLE P2D<11> P2D<10> P2D<9> DVDD18 DGND P2D<8> P2D<7> P2D<6> P2D<5> P2D<4> P2D<3> P2D<2> P2D<1> DVDD18 DGND P2D<0> NC NC NC NC DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET IRQ AGND Description Transmit Enable. Port 2, Data Input D11 (MSB). Port 2, Data Input D10. Port 2, Data Input D9. 1.8 V Digital Supply. Digital Common. Port 2, Data Input D8. Port 2, Data Input D7. Port 2, Data Input D6. Port 2, Data Input D5. Port 2, Data Input D4. Port 2, Data Input D3. Port 2, Data Input D2. Port 2, Data Input D1. 1.8 V Digital Supply. Digital Common. Port 2, Data Input D0 (LSB). No Connect. No Connect. No Connect. No Connect. 1.8 V Digital Supply. 3.3 V Digital Supply. Differential Synchronization Output. Differential Synchronization Output Digital Common PLL Lock Indicator SPI Port Data Output SPI Port Data Input/Output SPI Port Clock SPI Port Chip Select Bar. Reset, Active High. Interrupt Request. Analog Common. Pin No. 73 Mnemonic IPTAT 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VREF I120 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 1 Description Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. Voltage Reference Output. 120 μA Reference Current. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. Analog Common. Analog Common. Differential DAC Current Output, Channel 2. Differential DAC Current Output, Channel 2. Analog Common. Auxiliary DAC Current Output, Channel 2. Auxiliary DAC Current Output, Channel 2. Analog Common. Auxiliary DAC Current Output, Channel 1. Auxiliary DAC Current Output, Channel 1. Analog Common. Differential DAC Current Output, Channel 1. Differential DAC Current Output, Channel 1. Analog Common. Analog Common. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. The combined differential clock input at the CLK+ and CLK– pins are referred to as REFCLK. Rev. A | Page 10 of 56 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 AD9776/AD9778/AD9779 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 PIN 1 2 CGND 3 ANALOG DOMAIN 75 I120 74 VREF 73 IPTAT CGND 4 72 AGND CLK+ 5 71 IRQ CLK– 6 70 RESET CGND 7 69 CSB CGND 8 68 SCLK DIGITAL DOMAIN CVDD18 9 AD9778 67 SDIO CVDD18 10 TOP VIEW (Not to Scale) 66 SDO 65 PLL_LOCK AGND 12 64 DGND SYNC_I+ 13 63 SYNC_O+ SYNC_I– 14 62 SYNC_O– DGND 15 61 DVDD33 DVDD18 16 60 DVDD18 P1D<13> 17 59 NC P1D<12> 18 58 NC P1D<11> 19 57 P2D<0> P1D<10> 20 56 P2D<1> P1D<9> 21 55 P2D<2> DGND 22 54 DGND DVDD18 23 53 DVDD18 P1D<8> 24 52 P2D<3> P1D<7> 25 51 P2D<4> CGND 11 P2D<5> P2D<6> P2D<7> P2D<8> P2D<9> P2D<10> DGND DVDD18 P2D<11> P2D<12> P2D<13> TXENABLE DVDD33 DATACLK NC NC P1D<0> DVDD18 DGND P1D<1> P1D<2> P1D<3> P1D<4> P1D<5> 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P1D<6> NC = NO CONNECT 05361-003 CVDD18 Figure 4. AD9778 Pin Configuration Table 7. AD9778 Pin Function Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic CVDD18 CVDD18 CGND CGND CLK+ 1 CLK−1 CGND CGND CVDD18 CVDD18 CGND AGND SYNC_I+ SYNC_I− DGND DVDD18 P1D<13> P1D<12> P1D<11> P1D<10> Description 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Common. Clock Common. Differential Clock Input. Differential Clock Input. Clock Common. Clock Common. 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Common. Analog Common. Differential Synchronization Input. Differential Synchronization Input. Digital Common. 1.8 V Digital Supply. Port 1, Data Input D13 (MSB). Port 1, Data Input D12. Port 1, Data Input D11. Port 1, Data Input D10. Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Rev. A | Page 11 of 56 Mnemonic P1D<9> DGND DVDD18 P1D<8> P1D<7> P1D<6> P1D<5> P1D<4> P1D<3> P1D<2> P1D<1> DGND DVDD18 P1D<0> NC NC DATACLK DVDD33 TXENABLE P2D<13> Description Port 1, Data Input D9. Digital Common. 1.8 V Digital Supply. Port 1, Data Input D8. Port 1, Data Input D7. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Port 1, Data Input D2. Port 1, Data Input D1. Digital Common. 1.8 V Digital Supply. Port 1, Data Input D0 (LSB). No Connect. No Connect. Data Clock Output. 3.3 V Digital Supply. Transmit Enable. Port 2, Data Input D13 (MSB). AD9776/AD9778/AD9779 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Mnemonic P2D<12> P2D<11> DVDD18 DGND P2D<10> P2D<9> P2D<8> P2D<7> P2D<6> P2D<5> P2D<4> P2D<3> DVDD18 DGND P2D<2> P2D<1> P2D<0> NC NC DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET IRQ AGND IPTAT Description Port 2, Data Input D12. Port 2, Data Input D11. 1.8 V Digital Supply. Digital Common. Port 2, Data Input D10. Port 2, Data Input D9. Port 2, Data Input D8. Port 2, Data Input D7. Port 2, Data Input D6. Port 2, Data Input D5. Port 2, Data Input D4. Port 2, Data Input D3. 1.8 V Digital Supply. Digital Common. Port 2, Data Input D2. Port 2, Data Input D1. Port 2, Data Input D0 (LSB). No Connect. No Connect. 1.8 V Digital Supply. 3.3 V Digital Supply. Differential Synchronization Output. Differential Synchronization Output. Digital Common. PLL Lock Indicator. SPI Port Data Output. SPI Port Data Input/Output. SPI Port Clock. SPI Port Chip Select Bar. Reset, Active High. Interrupt Request. Analog Common. Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. Pin No. 74 75 76 77 78 79 80 81 82 83 Mnemonic VREF I120 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P 84 OUT2_N 85 86 AGND AUX2_P 87 AUX2_N 88 89 AGND AUX1_N 90 AUX1_P 91 92 AGND OUT1_N 93 OUT1_P 94 95 96 97 98 99 100 AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 1 Description Voltage Reference Output. 120 μA Reference Current. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. Analog Common. Analog Common. Differential DAC Current Output, Channel 2. Differential DAC Current Output, Channel 2. Analog Common. Auxiliary DAC Current Output, Channel 2. Auxiliary DAC Current Output, Channel 2. Analog Common. Auxiliary DAC Current Output, Channel 1. Auxiliary DAC Current Output, Channel 1. Analog Common. Differential DAC Current Output, Channel 1. Differential DAC Current Output, Channel 1. Analog Common. Analog Common. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. The combined differential clock input at the CLK+ and CLK– pins are referred to as REFCLK. Rev. A | Page 12 of 56 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 AD9776/AD9778/AD9779 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 75 I120 74 VREF 73 IPTAT 4 72 AGND CLK+ 5 71 IRQ CLK– 6 70 RESET CGND 7 69 CSB CGND 8 68 SCLK CVDD18 9 AD9779 67 SDIO TOP VIEW (Not to Scale) 66 SDO 65 PLL_LOCK AGND 12 64 DGND SYNC_I+ 13 63 SYNC_O+ SYNC_I– 14 62 SYNC_O– DGND 15 61 DVDD33 DVDD18 16 60 DVDD18 P1D<15> 17 59 P2D<0> P1D<14> 18 58 P2D<1> P1D<13> 19 57 P2D<2> P1D<12> 20 56 P2D<3> P1D<11> 21 55 P2D<4> DGND 22 54 DGND DVDD18 23 53 DVDD18 P1D<10> 24 52 P2D<5> P1D<9> 25 51 P2D<6> CVDD18 2 CGND 3 CGND PIN 1 ANALOG DOMAIN DIGITAL DOMAIN CVDD18 10 CGND 11 05361-004 P2D<7> P2D<8> P2D<9> P2D<10> P2D<11> P2D<12> DGND DVDD18 P2D<13> P2D<14> P2D<15> TXENABLE DVDD33 DATACLK P1D<0> P1D<1> P1D<2> DVDD18 DGND P1D<3> P1D<4> P1D<5> P1D<6> P1D<7> P1D<8> 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 5. AD9779 Pin Configuration Table 8. AD9779 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Mnemonic CVDD18 CVDD18 CGND CGND CLK+ 1 CLK−1 CGND CGND CVDD18 CVDD18 CGND AGND SYNC_I+ SYNC_I− DGND DVDD18 P1D<15> P1D<14> P1D<13> P1D<12> P1D<11> Description 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Common. Clock Common. Differential Clock Input. Differential Clock Input. Clock Common. Clock Common. 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Common. Analog Common. Differential Synchronization Input. Differential Synchronization Input. Digital Common. 1.8 V Digital Supply. Port 1, Data Input D15 (MSB). Port 1, Data Input D14. Port 1, Data Input D13. Port 1, Data Input D12. Port 1, Data Input D11. Pin No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Rev. A | Page 13 of 56 Mnemonic DGND DVDD18 P1D<10> P1D<9> P1D<8> P1D<7> P1D<6> P1D<5> P1D<4> P1D<3> DGND DVDD18 P1D<2> P1D<1> P1D<0> DATACLK DVDD33 TXENABLE P2D<15> P2D<14> P2D<13> Description Digital Common. 1.8 V Digital Supply. Port 1, Data Input D10. Port 1, Data Input D9. Port 1, Data Input D8. Port 1, Data Input D7. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Digital Common. 1.8 V Digital Supply. Port 1, Data Input D2. Port 1, Data Input D1. Port 1, Data Input D0 (LSB). Data Clock Output. 3.3 V Digital Supply. Transmit Enable. Port 2, Data Input D15 (MSB). Port 2, Data Input D14. Port 2, Data Input D13. AD9776/AD9778/AD9779 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Mnemonic DVDD18 DGND P2D<12> P2D<11> P2D<10> P2D<9> P2D<8> P2D<7> P2D<6> P2D<5> DVDD18 DGND P2D<4> P2D<3> P2D<2> P2D<1> P2D<0> DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SPI_SDO SPI_SDIO SCLK SPI_CSB RESET IRQ AGND IPTAT Description 1.8 V Digital Supply. Digital Common. Port 2, Data Input D12. Port 2, Data Input D11. Port 2, Data Input D10. Port 2, Data Input D9. Port 2, Data Input D8. Port 2, Data Input D7. Port 2, Data Input D6. Port 2, Data Input D5. 1.8 V Digital Supply. Digital Common. Port 2, Data Input D4. Port 2, Data Input D3. Port 2, Data Input D2. Port 2, Data Input D1. Port 2, Data Input D0 (LSB). 1.8 V Digital Supply. 3.3 V Digital Supply. Differential Synchronization Output. Differential Synchronization Output. Digital Common. PLL Lock Indicator. SPI Port Data Output. SPI Port Data Input/Output. SPI Port Clock. SPI Port Chip Select Bar. Reset, Active High. Interrupt Request. Analog Common. Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. Pin No. 74 75 76 77 78 79 80 81 82 83 Mnemonic VREF I120 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P 84 OUT2_N 85 86 87 88 89 90 91 92 AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N 93 OUT1_P 94 95 96 97 98 99 100 AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 1 Description Voltage Reference Output. 120 μA Reference Current. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. Analog Common. Analog Common. Differential DAC Current Output, Channel 2. Differential DAC Current Output, Channel 2. Analog Common. Auxiliary DAC Current Output, Channel 2. Auxiliary DAC Current Output, Channel 2. Analog Common. Auxiliary DAC Current Output, Channel 1. Auxiliary DAC Current Output, Channel 1. Analog Common. Differential DAC Current Output, Channel 1. Differential DAC Current Output, Channel 1. Analog Common. Analog Common. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. Analog Common. 3.3 V Analog Supply. The combined differential clock input at the CLK+ and CLK– pins are referred to as REFCLK. Rev. A | Page 14 of 56 AD9776/AD9778/AD9779 TYPICAL PERFORMANCE CHARACTERISTICS 4 100 3 fDATA = 160MSPS 2 90 fDATA = 200MSPS 0 SFDR (dBc) INL (16-BIT LSB) 1 –1 –2 80 70 fDATA = 250MSPS –3 –4 60 0 10k 20k 30k 40k 50k 50 05361-005 –6 60k CODE 0 20 40 60 80 100 fOUT (MHz) Figure 6. AD9779 Typical INL 05361-008 –5 Figure 9. AD9779 In-Band SFDR vs. fOUT, 2× Interpolation 100 1.5 fDATA = 200MSPS fDATA = 100MSPS 1.0 90 SFDR (dBc) DNL (16-BIT LSB) 0.5 0 –0.5 80 fDATA = 150MSPS 70 –1.0 60 10k 20k 30k 40k 50k 60k 50 CODE 0 40 60 80 100 50 fOUT (MHz) Figure 10. AD9779 In-Band SFDR vs. fOUT, 4× Interpolation Figure 7. AD9779 Typical DNL 100 100 90 20 05361-009 0 05361-006 –2.0 05361-010 –1.5 fDATA = 160MSPS fDATA = 100MSPS fDATA = 50MSPS 90 SFDR (dBc) 80 fDATA = 200MSPS 70 60 50 80 fDATA = 125MSPS 70 60 0 20 40 60 80 fOUT (MHz) 100 05361-007 SFDR (dBc) fDATA = 250MSPS Figure 8. AD9779 In-Band SFDR vs. fOUT, 1x Interpolation 50 0 10 20 30 40 fOUT (MHz) Figure 11. AD9779 In-Band SFDR vs. fOUT, 8× Interpolation Rev. A | Page 15 of 56 AD9776/AD9778/AD9779 100 100 90 90 PLL OFF PLL ON SFDR (dBc) fDATA = 200MSPS 70 fDATA = 250MSPS 50 0 20 40 60 80 80 70 60 100 fOUT (MHz) 50 0 10 20 30 40 fOUT (MHz) Figure 12. AD9779 Out-of-Band SFDR vs. fOUT, 2× Interpolation 05361-014 60 05361-011 SFDR (dBc) fDATA = 160MSPS 80 Figure 15. AD9779 In-Band SFDR, 4× Interpolation, fDATA = 100 MSPS, PLL On/Off 100 100 0dBFS –3dBFS 90 80 SFDR (dBc) SFDR (dBc) 90 fDATA = 150MSPS 70 80 –6dBFS 70 fDATA = 100MSPS 20 40 60 80 100 fOUT (MHz) 50 0 20 40 60 80 05361-015 0 05361-012 50 60 fDATA = 200MSPS 80 05361-016 60 fOUT (MHz) Figure 13. AD9779 Out-of-Band SFDR vs. fOUT, 4× Interpolation Figure 16. AD9779 In-Band SFDR vs. Digital Full-Scale Input 100 100 10mA 90 90 SFDR (dBc) fDATA = 50MSPS 80 fDATA = 100MSPS 70 80 70 30mA fDATA = 125MSPS 60 50 0 10 20 30 60 40 50 fOUT (MHz) 05361-013 SFDR (dBc) 20mA Figure 14. AD9779 Out-of-Band SFDR vs. fOUT, 8× Interpolation 50 0 20 40 60 fOUT (MHz) Figure 17. AD9779 In-Band SFDR vs. Output Full-Scale Current Rev. A | Page 16 of 56 AD9776/AD9778/AD9779 100 100 fDATA = 160MSPS fDATA = 200MSPS 90 fDATA = 250MSPS 80 IMD (dBc) IMD (dBc) 90 70 80 fDATA = 75MSPS 70 fDATA = 100MSPS 450 fOUT (MHz) Figure 18. AD9779 Third-Order IMD vs. fOUT, 1× Interpolation Figure 21. AD9779 Third-Order IMD vs. fOUT, 8× Interpolation 100 100 05361-020 425 400 375 350 325 300 275 250 225 200 175 150 fOUT (MHz) fDATA = 125MSPS 50 125 120 100 75 80 100 60 50 40 0 20 25 0 05361-017 50 fDATA = 50MSPS 60 60 90 90 80 80 IMD (dBc) IMD (dBc) fDATA = 160MSPS fDATA = 200MSPS 70 PLL OFF 70 PLL ON fDATA = 250MSPS 0 20 40 60 80 100 120 140 160 180 200 220 fOUT (MHz) 50 0 20 40 60 80 100 120 140 160 180 200 fOUT (MHz) Figure 19. AD9779 Third-Order IMD vs. fOUT, 2× Interpolation Figure 22. AD9779 Third-Order IMD vs. fOUT, 4× Interpolation, fDATA = 100 MSPS, PLL On vs. PLL Off 100 100 05361-021 50 60 05361-018 60 95 90 90 IMD (dBc) 80 fDATA = 150MSPS 70 fDATA = 100MSPS 75 70 60 fDATA = 200MSPS 0 40 80 120 160 200 240 280 320 55 360 400 fOUT (MHz) Figure 20. AD9779 Third-Order IMD vs. fOUT, 4× Interpolation 50 0 40 80 120 160 200 240 fOUT (MHz) 280 320 360 400 05361-022 50 80 65 60 05361-019 IMD (dBc) 85 Figure 23. AD9779 Third-Order IMD vs. fOUT, over 50 Parts,4× Interpolation, fDATA = 200 MSPS Rev. A | Page 17 of 56 AD9776/AD9778/AD9779 100 95 90 EXT REF DC COUPLED 0dBFS 85 –3dBFS 80 75 LGAV 51 W1 S2 S3 FC AA £(f): FTUN SWP –6dBFS 70 65 60 50 0 40 80 120 160 200 240 280 320 360 400 fOUT (MHz) 05361-117 55 START 1.0MHz *RES BW 20kHz 05361-024 IMD (dBc) *ATTEN 20dB REF 0dBm *PEAK Log 10dB/ STOP 400.0MHz SWEEP 1.203s (601 pts) VBW 20kHz Figure 27. AD9779 Two-Tone Spectrum, 4× Interpolation, fDATA = 100 MSPS, fOUT = 30 MHz, 35 MHz Figure 24. IMD Performance vs. Digital Full-Scale Input, 4× Interpolation, fDATA = 200 MSPS 100 –142 95 –146 90 20mA 10mA 80 NSD (dBm/Hz) IMD (dBc) 85 75 30mA 70 65 –150 –3dBFS –154 0dBFS –158 –6dBFS –162 60 0 40 80 120 160 200 240 280 320 360 400 fOUT (MHz) –170 05361-118 50 20 40 60 80 fOUT (MHz) Figure 25. IMD Performance vs. Full-Scale Output Current, 4× Interpolation, fDATA = 200 MSPS REF 0dBm *PEAK Log 10dB/ 0 05361-025 –166 55 Figure 28. AD9779 Noise Spectral Density vs. Digital Full-Scale of Single-Tone Input, fDATA = 200 MSPS, 2× Interpolation –150 *ATTEN 20dB EXT REF DC COUPLED –154 NSD (dBm/Hz) fDAC = 400MSPS LGAV 51 W1 S2 S3 FC AA £(f): FTUN SWP –162 fDAC = 800MSPS 05361-023 VBW 20kHz STOP 400.0MHz SWEEP 1.203s (601 pts) 0 20 40 60 80 100 fOUT (MHz) Figure 29. AD9779 Noise Spectral Density vs. fDAC, Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS Figure 26. AD9779 Single Tone, 4× Interpolation, fDATA = 100 MSPS, fOUT = 30 MHz Rev. A | Page 18 of 56 05361-026 –166 –170 START 1.0MHz *RES BW 20kHz fDAC = 200MSPS –158 AD9776/AD9778/AD9779 –150 –55 –60 –154 –158 ACLR (dBc) NSD (dBm/Hz) –65 fDAC = 200MSPS fDAC = 400MSPS –162 fDAC = 800MSPS –70 0dBFS – PLL ON –75 –6dBFS –80 –3dBFS –166 –85 40 60 80 100 fOUT (MHz) 05361-027 20 0 –90 –55 –60 –60 0dBFS – PLL ON 60 80 100 120 140 160 180 200 220 240 260 –65 –3dBFS ACLR (dBc) ACLR (dBc) 40 Figure 32. AD9779 ACLR for Second Adjacent Band WCDMA, 4× Interpolation, fDATA = 122.88 MSPS. On-Chip Modulation Translates Baseband Signal to IF –55 –70 0dBFS –75 –6dBFS –80 20 fOUT (MHz) Figure 30. AD9779 Noise Spectral Density vs. fDAC, Single-Tone Input at −6 dBFS –65 0 05361-029 0dBFS –170 –70 0dBFS – PLL ON –75 –6dBFS –80 –3dBFS –85 –85 –90 –90 20 40 60 80 100 120 140 160 180 200 220 240 260 fOUT (MHz) Figure 31. AD9779 ACLR for First Adjacent Band WCDMA, 4× Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF 0 20 40 60 80 100 120 140 160 180 200 220 240 260 fOUT (MHz) 05361-030 0 05361-028 0dBFS Figure 33. AD9779 ACLR for Third Adjacent Band WCDMA, 4× Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF Rev. A | Page 19 of 56 AD9776/AD9778/AD9779 1.5 *ATTEN 4dB REF –25.28dBm *AVG Log 10dB/ 1.0 INL (14-BIT LSB) EXT REF 0.5 0 –0.5 –1.5 VBW 300kHz RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz 10.00MHz –12.49dBm/ 15.00MHz 3.84000MHz SPAN 50MHz SWEEP 162.2ms (601 pts) 3.840MHz 3.840MHz 3.840MHz LOWER dBm dBc –76.75 –89.23 –80.94 –93.43 –79.95 –92.44 UPPER dBm dBc –77.42 –89.91 –80.47 –92.96 –78.96 –91.45 0 2k 6k 8k 10k CODE Figure 34. AD9779 WCDMA Signal, 4× Interpolation, fDATA =122.88 MSPS, fDAC/4 Modulation Figure 36. AD9778 Typical INL 0.6 *ATTEN 4dB REF –30.28dBm *AVG Log 10dB/ 4k 05361-031 CENTER 143.88MHz *RES BW 30kHz 05361-033 –1.0 PAVG 10 W1 S2 0.4 0.2 DNL (14-BIT LSB) EXT REF 0 –0.2 –0.4 –0.6 –1.0 SPAN 50MHz SWEEP 162.2ms (601 pts) VBW 300kHz TOTAL CARRIER POWER –12.61dBm/15.3600MHz REF CARRIER POWER –17.87dBm/3.84000MHz 1 –17.87dBm 2 –20.65dBm 3 –18.26dBm 4 –18.23dBm FREQ OFFSET 5.000MHz 10.00MHz 15.00MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz LOWER dBc dBm –67.70 –85.57 –70.00 –97.87 –71.65 –99.52 UPPER dBc dBm –67.70 –85.57 –69.32 –87.19 –71.00 –88.88 0 2k 4k 6k 8k 10k CODE 05361-032 CENTER 151.38MHz *RES BW 30kHz Figure 37. AD9778 Typical DNL Figure 35. AD9779 Multicarrier WCDMA Signal, 4× Interpolation, fDAC =122.88 MSPS, fDAC/4 Modulation Rev. A | Page 20 of 56 12k 14k 16k 05361-034 –0.8 PAVG 10 W1 S2 AD9776/AD9778/AD9779 *ATTEN 4dB REF –25.39dBm *AVG Log 10dB/ 100 90 IMD (dBc) 4× 150MSPS 80 4× 200MSPS 70 4× 100MSPS PAVG 10 W1 S2 CENTER 143.88MHz *RES BW 30kHz 0 40 80 120 160 200 240 280 320 360 400 fOUT (MHz) 05361-035 RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz –12.74dBm/ 10.00MHz 3.84000MHz 15.00MHz 100 LOWER dBc dBm –76.49 –89.23 –80.13 –92.87 –80.90 –93.64 UPPER dBc dBm –76.89 –89.63 –80.02 –92.76 –79.53 –92.27 –150 90 –154 fDATA = 200MSPS fDATA = 160MSPS fDAC = 200MSPS NSD (dBm/Hz) SFDR (dBc) 3.884MHz 3.840MHz 3.840MHz Figure 41. AD9778 ACLR, fDATA = 122.88 MSPS, 4× Interpolation, fDAC/4 Modulation Figure 38. AD9778 IMD, 4× Interpolation 80 fDATA = 250MSPS 70 60 –158 fDAC = 400MSPS –162 fDAC = 800MSPS –166 0 20 40 60 100 80 fOUT (MHz) –170 05361-036 50 SPAN 50MHz SWEEP 162.2ms (601 pts) VBW 300kHz 0 20 40 60 80 100 fOUT (MHz) 05361-039 50 05361-038 60 Figure 42. AD9778 Noise Spectral Density vs. fDAC Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS Figure 39. AD9778 In-Band SFDR, 2× Interpolation –150 –60 –154 NSD (dBm/Hz) –70 1ST ADJ CHAN 3RD ADJ CHAN fDAC = 400MSPS –158 –162 fDAC = 800MSPS –80 –90 0 25 50 75 100 125 150 175 200 225 250 fOUT (MHz) Figure 40. AD9778 ACLR, Single-Carrier WCDMA, 4× Interpolation, fDATA = 122.88 MSPS, Amplitude = −3 dBFS –170 0 20 40 60 80 100 fOUT (MHz) Figure 43. AD9778 Noise Spectral Density vs. fDAC Single-Tone Input at −6 dBFS, fDATA = 200 MSPS Rev. A | Page 21 of 56 05361-040 –166 2ND ADJ CHAN 05361-037 ACLR (dBc) fDAC = 200MSPS AD9776/AD9778/AD9779 0.4 100 0.3 90 fDATA = 160MSPS 0.1 SFDR (dBc) INL (12-BIT LSB) 0.2 0 –0.1 80 fDATA = 250MSPS 70 fDATA = 200MSPS –0.2 60 512 1024 1536 2048 2560 3072 3584 4096 CODE 50 0 60 80 100 250 Figure 47. AD9776 In-Band SFDR, 2× Interpolation 0.20 –55 0.15 –60 0.10 –65 1ST ADJ CHAN 0.05 ACLR (dBc) DNL (12-BIT LSB) 40 fOUT (MHz) Figure 44. AD9776 Typical INL 0 –0.05 –70 3RD ADJ CHAN –75 –80 –0.10 2ND ADJ CHAN –85 –0.15 0 512 1024 1536 2048 2560 3072 3584 4096 CODE –90 05361-042 –0.20 20 05361-044 0 05361-041 –0.4 05361-045 –0.3 0 25 50 75 100 125 150 175 200 225 FOUT (MHz) Figure 45. AD9776 Typical DNL Figure 48. AD9776 ACLR, fDATA = 122.88 MSPS, 4× Interpolation, fDAC/4 Modulation REF –25.29dBm *AVG Log 10dB/ 100 95 *ATTEN 4dB 90 80 75 4× 100MSPS 4× 200MSPS 70 65 60 0 40 80 120 160 200 240 280 320 fOUT (MHz) 360 400 CENTER 143.88MHz *RES BW 30kHz VBW 300kHz RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz 10.00MHz –12.67dBm/ 15.00MHz 3.84000MHz 3.884MHz 3.840MHz 3.840MHz SPAN 50MHz SWEEP 162.2ms (601 pts) LOWER dBm dBc –75.00 –87.67 –78.05 –90.73 –77.73 –90.41 UPPER dBm dBc –75.30 –87.97 –77.99 –90.66 –77.50 –90.17 Figure 49. AD9776, Single Carrier WCDMA, 4× Interpolation, fDATA = 122.88 MSPS, Amplitude = −3 dBFS Figure 46. AD9776 IMD, 4× Interpolation Rev. A | Page 22 of 56 05361-046 50 PAVG 10 W1 S2 4× 150MSPS 55 05361-043 IMD (dBc) 85 AD9776/AD9778/AD9779 –150 –150 fDAC = 200MSPS fDAC = 200MSPS –154 –158 NSD (dBm/Hz) NSD (dBm/Hz) fDAC = 400MSPS –154 fDAC = 400MSPS fDAC = 800MSPS –162 –158 fDAC = 800MSPS –162 –166 0 10 20 30 40 50 60 70 80 90 100 fOUT (MHz) –170 0 10 20 30 40 50 60 70 80 90 fOUT (MHz) Figure 50. AD9776 Noise Spectral Density vs. fDAC, Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS Figure 51. AD9776 Noise Spectral Density vs. fDAC, Single-Tone Input at −6 dBFS, fDATA = 200 MSPS Rev. A | Page 23 of 56 100 05361-048 –170 05361-047 –166 AD9776/AD9778/AD9779 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1. B Gain Error The difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. In-Band Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Out-of-Band Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the band that starts at the frequency of the input data rate and ends at the Nyquist frequency of the DAC output sample rate. Normally, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) The ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. A | Page 24 of 56 AD9776/AD9778/AD9779 THEORY OF OPERATION The AD9776/AD9778/AD9779 combine many features that make them very attractive DACs for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. The speed and performance of the parts allow wider bandwidths and more carriers to be synthesized than in previously available DACs. The digital engine uses a breakthrough filter architecture that combines the interpolation with a digital quadrature modulator. This allows the parts to conduct digital quadrature frequency upconversion. They also have features that allow simplified synchronization with incoming data and between multiple parts. The serial port configuration is controlled by Register 0x00, Bits<6:7>. It is important to note that the configuration changes immediately upon writing to the last bit of the byte. For multibyte transfers, writing to this register can occur during the middle of a communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply to setting the software reset, RESET (Register 0x00, Bit 5) or pulling the RESET pin (Pin 70) high. All registers are set to their default values, except Register 0x00 and Register 0x04, which remain unchanged. Use of only single-byte transfers when changing serial port configurations or initiating a software reset is recommended to prevent unexpected device behavior. As described in this section, all serial port data is transferred to/from the device in synchronization to the SCLK pin. If synchronization is lost, the device has the ability to asynchronously terminate an I/O operation, putting the serial port controller into a known state and, thereby, regaining synchronization. SPI PORT A logic high on the CSB pin followed by a logic low resets the SPI port timing to the initial state of the instruction cycle. From this state, the next eight rising SCLK edges represent the instruction bits of the current I/O operation, regardless of the state of the internal registers or the other signal levels at the inputs to the SPI port. If the SPI port is in an instruction cycle or a data transfer cycle, none of the present data is written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes as determined by the instruction byte. Using one multibyte transfer is preferred. Single-byte data transfers are useful in reducing CPU overhead when register access requires only one byte. Registers change immediately upon writing to the last bit of each transfer byte. Instruction Byte The instruction byte contains the information shown in Table 9. I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0 R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic high indicates a read operation. Logic 0 indicates a write operation. 05361-049 SPI_CSB 69 There are two phases to a communication cycle with the AD977x. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle, Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device. MSB I7 R/W SPI_SDO 66 SPI_SCLK 68 General Operation of the Serial Interface Table 9. SPI Instruction Byte SERIAL PERIPHERAL INTERFACE SPI_SDI 67 ported, as well as MSB-first or LSB-first transfer formats. The serial interface ports can be configured as a single pin I/O (SDIO) or two unidirectional pins for input/output (SDIO/SDO). Figure 52. SPI Port The serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9776/ AD9778/AD9779. Single or multiple byte transfers are sup- N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are listed in Table 10. A4, A3, A2, A1, and A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0, respectively, of the instruction byte determine the register that is accessed during the data transfer portion of the communication cycle. Rev. A | Page 25 of 56 AD9776/AD9778/AD9779 For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the device based on the LSB-first bit (Register 0x00, Bit 6). Table 10. Byte Transfer Count Description Transfer one byte Transfer three bytes Transfer two bytes Transfer four bytes The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first mode is active. The serial port controller address increments from the data address written toward 0x1F for multibyte I/O operations if the LSB-first mode is active. Chip Select (CSB) Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. Serial Data I/O (SDIO) Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, configuring the SDIO pin as unidirectional. Serial Data Out (SDO) Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the device operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. MSB/LSB TRANSFERS INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 SDO D7 D6N D5N D30 D20 D10 D00 D7 D6N D5 N D30 D20 D10 D00 05361-050 Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and to run the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. Figure 53. Serial Register Interface Timing MSB-First INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5N D6N D7 N D00 D10 D20 D4N D5 N D6N D7N SDO 05361-051 Serial Interface Port Pin Descriptions Figure 54. Serial Register Interface Timing LSB-First tDS tSCLK CSB tPWH tPWL SCLK The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by Register Bit LSB_FIRST (Register 0x00, Bit 6). The default is MSB-first (LSB-first = 0). When LSB-first = 0 (MSB-first) the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow from high address to low address. In MSB-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. tDS SDIO tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 05361-052 N0 0 1 0 1 Figure 55. Timing Diagram for SPI Register Write CSB SCLK tDV SDIO SDO DATA BIT n DATA BIT n–1 Figure 56. Timing Diagram for SPI Register Read Rev. A | Page 26 of 56 05361-053 N1 0 0 1 1 When LSB-first = 1 (LSB-first) the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. AD9776/AD9778/AD9779 SPI REGISTER MAP Table 11. Register Name Comm Digital Control Address 0x00 00 Bit 7 SDIO Bidirectional Bit 6 LSB/MSB First Bit 5 Software Reset Bit 3 Bit 2 Auto PowerDown Enable Filter Modulation Mode<3:0> 0x01 01 0x02 02 0x03 03 0x04 04 Data Clock Delay Enable Data Clock Delay Mode<1:0> Data Clock Divide Ratio<1:0> Data Clock Delay<3:0> 0x05 05 Sync Out Delay<3:0> 0x06 0x07 06 07 0x08 08 0x09 09 0x0A 10 0x0B 0x0C 11 12 Aux DAC1 Control Register 0x0D 0x0E 13 14 Q DAC Control Register 0x0F 0x10 15 16 Aux DAC2 Control Register 0x11 0x12 17 18 0x13 to 0x18 0x19 19 to 24 0x1A to 0x1F 26 to 31 Sync Control PLL Control Misc Control I DAC Control Register Interrupt Register 25 Filter Interpolation Factor<1:0> Bit 4 PowerDown Mode Data Format Sync Receiver Enable PLL Enable Dual/Interleaved Data Bus Mode Real Mode Sync Input Delay<3:0> Sync Driver Sync Enable Triggering Edge PLL Band Select<5:0> PLL VCO Divider Ratio<1:0> Inverse Sinc Enable DATACLK Invert TxEnable Invert Bit 0 Def. 0x00 Zero Stuffing Enable Q First 0x00 Reserved Sync Out Delay<4> Input Sync Pulse Frequency Ratio<2:0> Sync Input Delay<4> Input Sync Pulse Timing Error Tolerance<3:0> DAC Clock Offset<4:0> PLL VCO AGC Gain<1:0> PLL Bias Setting<2:0> PLL Loop Bandwidth Adjustment<4:0> I DAC Power Down Auxiliary DAC1 Sign Auxiliary DAC1 Current Direction Q DAC Sleep Q DAC PowerDown Auxiliary DAC2 Sign Auxiliary DAC2 Current Direction I DAC Gain Adjustment<9:8> Auxiliary DAC1 Data<7:0> Auxiliary DAC1 PowerDown Q DAC Gain Adjustment<7:0> Auxiliary DAC1 Data<9:8> Q DAC Gain Adjustment<9:8> Auxiliary DAC2 Data<7:0> Auxiliary DAC2 PowerDown Reserved Sync Delay IRQ Auxiliary DAC2 Data<9:8> Sync Delay IRQ Enable Reserved Rev. A | Page 27 of 56 0x00 0x00 0x00 0x00 0xCF 0x37 0x38 I DAC Gain Adjustment<7:0> I DAC Sleep 0x00 0x00 Output Sync Pulse Divide<2:0> PLL Loop Divide Ratio<1:0> PLL Control Voltage Range<2:0> (Read Only) Bit 1 PLL Lock Indicator (Read Only) Internal Sync Loopback 0xF9 0x01 0x00 0x00 0xF9 0x01 0x00 0x00 0x00 AD9776/AD9778/AD9779 Table 12. SPI Register Description Register Name Comm Register Digital Control Register Sync Control Register Address Reg. No. Bits 00 7 Description SDIO bidirectional 00 6 LSB/MSB first 00 5 Software reset 00 4 Power-down mode 00 3 Auto power-down enable 00 1 PLL lock (read only) 01 7:6 Filter interpolation factor 01 01 5:2 0 Filter modulation mode Zero stuffing 02 7 Data format 02 6 Dual/interleaved data bus mode 02 5 Real mode 02 4 DATACLK delay enable 02 3 Inverse sinc enable 02 2 DATACLK invert 02 1 TxEnable invert 02 0 Q first 03 03 7:6 5:4 Data clock delay mode Extra data clock divide ratio 03 04 04 04 05 05 3:0 7:4 3:1 0 7:4 3:1 Reserved Data clock delay Output sync pulse divide Sync out delay Sync out delay Input sync pulse frequency 05 0 Sync input delay Rev. A | Page 28 of 56 Function 0: use SDIO pin as input data only 1: use SDIO as both input and output data 0: first bit of serial data is MSB of data byte 1: first bit of serial data is LSB of data byte Bit must be written with a 1, then 0 to soft reset SPI register map 0: all circuitry is active 1: disable all digital and analog circuitry, only SPI port is active Controls auto power-down mode, see the Power-Down and Sleep Modes section 0: PLL is not locked 1: PLL is locked 00: 1× interpolation 01: 2× interpolation 10: 4× interpolation 11: 8× interpolation See Table 21 for filter modes 0: zero stuffing off 1: zero stuffing on 0: signed binary 1: unsigned binary 0: both input data ports receive data 1: Data Port 1 only receives data 0: enable Q path for signal processing 1: disable Q path data (internal Q channel clocks disabled, I and Q modulators disabled) See the Using Data Delay to Meet Timing Requirements section. 0: inverse sinc filter disabled 1: inverse sinc filter enabled 0: output DATACLK same phase as internal capture clock 1: output DATACLK opposite phase as internal capture clock Inverts the function of TxEnable Pin 39, see the Interleaved Data Mode section 0: first byte of data is always I data at beginning of transmit 1: first byte of data is always Q data at beginning of transmit 00: manual Data clock output divider (see Table 22 for divider ratio) Sets delay of REFCLK in to DATACLK out Sets frequency of SYNC_O pulses Sync output delay, Bit 4 Sync output delay, Bits<3:0> Input sync pulse frequency divider, see the AN-822 application note Sync input delay, Bit 4 Default 0 0 0 0 0 00 0000 0 0 0 0 0 0 0 00 00 000 0000 000 0 000 0 AD9776/AD9778/AD9779 Register Name Sync Control Register PLL Control Misc Control I DAC Control Register Aux DAC1 Control Register Address Reg. No. Bits 06 7:4 Description Sync input delay 06 3:0 07 07 07 07 7 6 5 4:0 08 7:2 Input sync pulse timing error tolerance Sync receiver enable Sync driver enable Sync triggering edge SYNC_I to input data sampling clock offset PLL band select 08 1:0 VCO AGC gain control 09 7 PLL enable 09 6:5 PLL VCO divide ratio 09 4:3 PLL loop divide ratio 09 0A 2:0 7:5 PLL bias setting PLL control voltage range 0A 4:0 PLL loop bandwidth adjustment 0B 7:0 I DAC gain adjustment 0C 7 I DAC sleep 0C 6 I DAC power-down 0C 1:0 I DAC gain adjustment 0D 7:0 Aux DAC1 gain adjustment 0E 7 Aux DAC1 sign 0E 6 Aux DAC1 current direction 0E 5 Aux DAC1 power-down 0E 1:0 Aux DAC1 gain adjustment Rev. A | Page 29 of 56 Function See the Multiple DAC Synchronization section for details on using these registers to synchronize multiple DACs Default 0 0 0 0 0 0 VCO frequency range vs. PLL band select value (see Table 18) Lower number (low gain) is generally better for performance 0: PLL off, DAC rate clock supplied by outside source 1: PLL on, DAC rate clock synthesized internally from external reference clock via PLL clock multiplier FVCO/fDAC 00 × 1 01 × 2 10 × 4 11 × 8 fDAC/fREF 00 × 2 01 × 4 10 × 8 11 × 16 Always set to 010 000 to 111, proportional to voltage at PLL loop filter output, readback only See PLL Loop Filter Bandwidth section for details (7:0) LSB slice of 10-bit gain setting word for I DAC 0: I DAC on 1: I DAC off 0: I DAC on 1: I DAC off (9:8) MSB slice of 10-bit gain setting word for I DAC (7:0) LSB slice of 10-bit gain setting word for Aux DAC1 0: positive 1: negative 0: source 1: sink 0: Aux DAC1 on 1: Aux DAC1 off (9:8) MSB slice of 10-bit gain setting word for Aux DAC1 111001 11 0 010 11111001 0 0 01 00000000 0 0 00 AD9776/AD9778/AD9779 Register Name Q DAC Control Register Aux DAC2 Control Register Interrupt Register Address Reg. No. Bits 0F 7:0 Description Q DAC gain adjustment 10 7 Q DAC sleep 10 6 Q DAC power-down 10 1:0 Q DAC gain adjustment 11 7:0 Aux DAC2 gain adjustment 12 7 Aux DAC2 sign 12 6 Aux DAC2 current direction 12 5 Aux DAC2 power-down 12 1:0 Aux DAC2 gain adjustment 19 19 19 19 19 19 19 7 6 5 3 2 1 0 Sync delay IRQ Function (7:0) LSB slice of 10-bit gain setting word for Q DAC 0: Q DAC on 1: Q DAC off 0: Q DAC on 1: Q DAC off (9:8) MSB slice of 10-bit gain setting word for Q DAC (7:0) LSB slice of 10-bit gain setting word for Aux DAC2 0: positive 1: negative 0: source 1: sink 0: Aux DAC2 on 1: Aux DAC2 off (9:8) MSB slice of 10-bit gain setting word for Aux DAC2 Readback, must write 0 to clear Sync delay IRQ enable Internal sync loopback Rev. A | Page 30 of 56 Default 11111001 0 0 00000000 0 0 00 0 0 0 0 0 0 0 AD9776/AD9778/AD9779 INTERPOLATION FILTER ARCHITECTURE Integer Value −4 0 +13 0 −34 0 +72 0 −138 0 +245 0 −408 0 +650 0 −1003 0 +1521 0 −2315 0 +3671 0 −6642 0 +20,755 +32,768 Upper Coefficient H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) Integer Value −39 0 +273 0 −1102 0 +4964 +8192 Table 16. Inverse Sinc Filter Lower Coefficient H(1) H(2) H(3) H(4) H(5) Upper Coefficient H(9) H(8) H(7) H(6) Integer Value +2 −4 +10 −35 +401 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –4 –3 –2 –1 0 1 2 3 4 fOUT (× Input Data Rate) Figure 57. 2× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off) 10 0 –10 –20 Table 14. Half-Band Filter 2 Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) Upper Coefficient H(15) H(14) H(13) H(12) H(11) H(10) H(9) Integer Value −2 0 +17 0 −75 0 +238 0 −660 0 +2530 +4096 –30 –40 –50 –60 –70 –80 –90 –100 –4 –3 –2 –1 0 1 fOUT (× Input Data Rate) 2 3 4 05361-055 Upper Coefficient H(55) H(54) H(53) H(52) H(51) H(50) H(49) H(48) H(47) H(46) H(45) H(44) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) ATTENUATION (dB) Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28) Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) 05361-054 Table 13. Half-Band Filter 1 Table 15. Half-Band Filter 3 ATTENUATION (dB) The AD9776/AD9778/AD9779 can provide up to 8× interpolation, or the interpolation filters can be entirely disabled. It is important to note that the input signal should be backed off by approximately 0.01 dB from full scale to avoid overflowing the interpolation filters. The coefficients of the low-pass filters and the inverse sinc filter are given in Table 13, Table 14, Table 15, and Table 16. Spectral plots for the filter responses are shown in Figure 57, Figure 58, and Figure 59. Figure 58. 4× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off) Rev. A | Page 31 of 56 AD9776/AD9778/AD9779 10 0 –10 –10 –20 –20 –30 –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 –4 –3 –2 –1 0 1 2 3 4 fOUT (× Input Data Rate) –100 –4 Figure 59. 8× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off) –3 –2 –1 0 1 2 3 4 fOUT (× Input Data Rate) 05361-059 ATTENUATION (dB) 0 05361-056 ATTENUATION (dB) 10 Figure 62. Interpolation/Modulation Combination of −3 fDAC/8 Filter 10 The Nyquist regions of up to 4× the input data rate can be seen in Figure 60. –8 –7 –6 –5 –4 –3 –2 –1 1 2 3 4 5 6 7 0 –10 –20 ATTENUATION (dB) With the interpolation filter and modulator combined, the incoming signal can be placed anywhere within the Nyquist region of the DAC output sample rate. When the input signal is complex, this architecture allows modulation of the input signal to positive or negative Nyquist regions (see Table 17). –30 –40 –50 –60 –70 8 –2× –1× DC 1× 2× 3× 4× –90 –100 –4 Figure 60. Nyquist Zones –3 –2 –1 0 1 2 3 4 fOUT (× Input Data Rate) 10 0 –10 ATTENUATION (dB) –20 Figure 63. Interpolation/Modulation Combination of −2 fDAC/8 Filter 10 0 –10 –20 ATTENUATION (dB) Figure 57, Figure 58, and Figure 59 show the low-pass response of the digital filters with no modulation. By turning on the modulation feature, the response of the digital filters can be tuned to anywhere within the DAC bandwidth. As an example, Figure 61 to Figure 67 show the nonshifted mode filter responses (refer to Table 17 for shifted/nonshifted mode filter responses). –30 –40 –50 –60 –70 –30 –80 –40 –90 –50 –100 –4 –60 –3 –2 –1 0 1 fOUT (× Input Data Rate) –70 2 3 4 Figure 64. Interpolation/Modulation Combination of −1 fDAC/8 Filter –80 –3 –2 –1 0 1 fOUT (× Input Data Rate) 2 3 4 05361-058 –90 –100 –4 05361-060 –3× 05361-061 –4× 05361-057 –80 Figure 61. Interpolation/Modulation Combination of 4 fDAC/8 Filter Rev. A | Page 32 of 56 AD9776/AD9778/AD9779 10 Shifted mode filter responses allow the pass band to be centered around ±0.5 fDATA, ±1.5 fDATA, ±2.5 fDATA, and ±3.5 fDATA. Switching to the shifted mode response does not modulate the signal. Instead, the pass band is simply shifted. For example, picture the response shown in Figure 67 and assume the signal in-band is a complex signal over the bandwidth 3.2 fDATA to 3.3 fDATA. If the even mode filter response is then selected, the pass band becomes centered at 3.5 fDATA. However, the signal remains at the same place in the spectrum. The shifted mode capability allows the filter pass band to be placed anywhere in the DAC Nyquist bandwidth. 0 –10 ATTENUATION (dB) –20 –30 –40 –50 –60 –70 –80 –100 –4 –3 –2 –1 0 1 2 3 4 fOUT (× Input Data Rate) 05361-062 –90 Figure 65. Interpolation/Modulation Combination of fDAC/8 Filter 10 0 –10 ATTENUATION (dB) –20 The AD9776/AD9778/AD9779 are dual DACs with internal complex modulators built into the interpolating filter response. In dual channel mode, the devices expect the real and the imaginary components of a complex signal at Digital Input Port 1 and Digital Input Port 2 (I and Q, respectively). The DAC outputs then represent the real and imaginary components of the input signal, modulated by the complex carrier fDAC/2, fDAC/4, or fDAC/8. –30 With Register 2, Bit 6 set, the device accepts interleaved data on Port 1 in the I, Q, I, Q . . . sequence. Note that in interleaved mode, the channel data rate at the beginning of the I and the Q data paths are now half the input data rate because of the interleaving. The maximum input data rate is still subject to the maximum specification of the device. This limits the synthesis bandwidth available at the input in interleaved mode. –40 –50 –60 –70 –80 –3 –2 –1 0 1 2 3 4 fOUT (× Input Data Rate) 05361-063 –90 –100 –4 Figure 66. Interpolation/Modulation Combination of 2 fDAC/8 Filter in Shifted Mode With Register 0x02, Bit 5 (real mode) set, the Q channel and the internal I and Q digital modulation are turned off. The output spectrum at the I DAC then represents the signal at Digital Input Port 1, interpolated by 1×, 2×, 4×, or 8×. 10 The general recommendation is that if the desired signal is within ±0.4 × fDATA, the odd filter mode should be used. Outside of this, the even filter mode should be used. In any situation, the total bandwidth of the signal should be less than 0.8 × fDATA. 0 –10 –30 –40 –50 –60 –70 –80 –90 –100 –4 –3 –2 –1 0 1 2 3 fOUT (× Input Data Rate) 4 05361-064 ATTENUATION (dB) –20 Figure 67. Interpolation/Modulation Combination of 3 fDAC/8 Filter in Shifted Mode Rev. A | Page 33 of 56 AD9776/AD9778/AD9779 Table 17. Interpolation Filter Modes, (Register 0x01, Bits<5:2>) Interpolation Factor <7:6> 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 4 4 4 4 4 4 4 4 2 2 2 2 1 Filter Mode <5:2> 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x00 0x01 0x02 0x03 Modulation DC DC shifted F/8 F/8 shifted F/4 F/4 shifted 3F/8 3F/8 shifted F/2 F/2 shifted −3F/8 −3F/8 shifted −F/4 −F/4 shifted −F/8 −F/8 shifted DC DC shifted F/4 F/4 shifted F/2 F/2 shifted −F/4 −F/4 shifted DC DC shifted F/2 F/2 shifted Nyquist Zone Pass Band 1 2 3 4 5 6 7 8 −8 −7 −6 −5 −4 −3 −2 −1 1 2 3 4 −4 −3 −2 −1 1 2 −2 −1 F_Low 1 −0.05 0.0125 0.075 0.1375 0.2 0.2625 0.325 0.3875 −0.55 −0.4875 −0.425 −0.3625 −0.3 −0.2375 −0.175 −0.1125 −0.1 0.025 0.15 0.275 −0.6 −0.475 −0.35 −0.225 −0.2 0.05 −0.7 −0.45 Frequency normalized to fDAC. Rev. A | Page 34 of 56 Center1 0 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 −0.5 −0.4375 −0.375 −0.3125 −0.25 −0.1875 −0.125 −0.0625 0 0.125 0.25 0.375 −0.5 −0.375 −0.25 −0.125 0 0.25 −0.5 −0.25 F_High1 +0.05 0.1125 0.175 0.2375 0.3 0.3625 0.425 0.4875 −0.45 −0.3875 −0.343 −0.2625 −0.2 −0.1375 −0.075 −0.0125 +0.1 0.225 0.35 0.475 −0.4 −0.275 −0.15 −0.025 +0.2 0.45 −0.3 −0.05 Comments In 8× interpolation; BW (min) = 0.0375 × fDAC BW (max) = 0.1 × fDAC In 4× interpolation; BW (min) = 0.075 × fDAC BW (max) = 0.2 × fDAC In 2× interpolation; BW (min) = 0.15 × fDAC BW (max) = 0.4 × fDAC AD9776/AD9778/AD9779 –3 –2 –1 0 2 ASSUMING 8× INTERPOLATION –30 SHIFTED –3 × fDAC/8 SHIFTED –fDAC/4 SHIFTED –fDAC/8 1 fOUT (× Input Data Rate), 3 4 05361-067 –80 –4 +fDAC/2 +fDAC/4 +fDAC/8 BASEBAND –fDAC/8 –70 –fDAC/4 SHIFTED –DC –50 0 –20 SHIFTED –DC –40 SHIFTED –fDAC/8 –30 –60 –fDAC/2 ATTENUATION (dB) –20 10 –10 Figure 70. Shifted Bandwidths Accessible with the Filter Architecture –40 –50 –60 –80 –4 –3 –2 –1 0 1 2 4 3 fOUT (× Input Data Rate), ASSUMING 8× INTERPOLATION 05361-065 –70 Figure 68. Traditional Bandwidth Options for TxDAC Output IF The filter architecture not only allows the interpolation filter pass bands to be centered in the middle of the input Nyquist zones (as explained in this section), but also allows the possibility of a 3 × fDAC/8 modulation mode. With all of these filter combinations, a carrier of given bandwidth can be placed anywhere in the spectrum and fall into a possible pass band of the interpolation filters. The possible bandwidths accessible with the filter architecture are shown in Figure 69 and Figure 70. Note that the shifted and nonshifted filter modes are all accessible by programming the filter mode for the particular interpolation rate. 10 +fDAC /2 +3 × fDAC /8 +fDAC /4 +fDAC /8 BASEBAND –fDAC /8 –fDAC /4 –20 –3 × fDAC /8 –10 –fDAC /2 0 ATTENUATION (dB) –10 ATTENUATION (dB) The AD977x uses a novel interpolation filter architecture that allows DAC IF frequencies to be generated anywhere in the spectrum. Figure 68 shows the traditional choice of DAC IF output bandwidth placement. Note that there are no possible filter modes in which the carrier can be placed near 0.5 × fDATA, 1.5 × fDATA, 2.5 × fDATA, and so on. SHIFTED –fDAC/4 0 SHIFTED –3 × fDAC/8 10 INTERPOLATION FILTER MINIMUM AND MAXIMUM BANDWIDTH SPECIFICATIONS The REFCLK input requires a low jitter differential drive signal. It is a PMOS input differential pair powered from the 1.8 V supply, therefore, it is important to maintain the specified 400 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p about the 400 mV common-mode voltage. While these input levels are not directly LVDS-compatible, REFCLK can be driven by an offset ac-coupled LVDS signal, as shown in Figure 71. –40 –50 –60 –2 –1 0 1 fOUT (× Input Data Rate), 2 ASSUMING 8× INTERPOLATION 3 4 05361-066 –70 –3 The maximum bandwidth condition exists if the carrier is placed directly in the center of one of the filter pass bands. In this case, the total 0.1 dB bandwidth of the interpolation filters is equal to 0.8 × fDATA. As Table 17 shows, the synthesis bandwidth as a fraction of DAC output sample rate drops by a factor of 2 for every doubling of interpolation rate. The minimum bandwidth condition exists, for example, if a carrier is placed at 0.25 × fDATA. In this situation, if the nonshifted filter response is enabled, the high end of the filter response cuts off at 0.4 × fDATA, thus limiting the high end of the signal bandwidth. If the shifted filter response is enabled instead, then the low end of the filter response cuts off at 0.1 × fDATA, thus limiting the low end of the signal bandwidth. The minimum bandwidth specification that applies for a carrier at 0.25 × fDATA is therefore 0.3 × fDATA. The minimum bandwidth behavior is repeated over the spectrum for carriers placed at (±n ± 0.25) × fDATA, where n is any integer. DRIVING THE REFCLK INPUT –30 –80 –4 With this filter architecture, a signal placed anywhere in the spectrum is possible. However, the signal bandwidth is limited by the input sample rate of the DAC and the specific placement of the carrier in the spectrum. The bandwidth restriction resulting from the combination of filter response and input sample rate is often referred to as the synthesis bandwidth, since this is the largest bandwidth that the DAC can synthesize. Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture Rev. A | Page 35 of 56 AD9776/AD9778/AD9779 0.1μF PLL Enabled (Register 0x09, Bit 7 = 1) CLK+ 50Ω VCM = 400mV CLK– 0.1μF 05361-068 50Ω LVDS_N_IN Figure 71. LVDS REFCLK Drive Circuit If a clean sine clock is available, it can be transformer-coupled to REFCLK, as shown in Figure 71. Use of a CMOS or TTL clock is also acceptable for lower sample rates. It can be routed through a CMOS to LVDS translator, then ac-coupled, as described in this section. Alternatively, it can be transformercoupled and clamped, as shown in Figure 72. 0.1μF 50Ω CLK+ CLK– 50Ω BAV99ZXCT HIGH SPEED DUAL DIODE VCM = 400mV PLL Disabled (Register 0x09, Bit 7 = 0) The PLL enable switch shown in Figure 74 is connected to the reference clock input. The differential reference clock input is the same as the DAC output sample rate. N3 determines the interpolation rate. 0x0A (4:0) LOOP FILTER BANDWIDTH REFERENCE CLOCK (PINS 5 AND 6) A simple bias network for generating VCM is shown in Figure 73. It is important to use CVDD18 and CGND for the clock bias circuit. Any noise or other signal that is coupled onto the clock is multiplied by the DAC digital input signal and can degrade DAC performance. VCO ÷N2 ÷N1 0x09 (4:3) PLL LOOP DIVIDE RATIO 0x09 (6:5) PLL VCO DIVIDE RATIO ÷N3 DAC INTERPOLATION RATE DATACLK OUT (PIN 37) 0x01 (7:6) 0x09 (7) PLL ENABLE VCM = 400mV INTERNAL DAC SAMPLE RATE CLOCK CVDD18 1kΩ 1nF CGND 05361-070 Figure 74. Internal Clock Architecture 1nF 0.1μF 0x08 (7:2) VCO RANGE INTERNAL LOOP FILTER PHASE DETECTION Figure 72. TTL or CMOS REFCLK Drive Circuit 287Ω 0x0A (7:5) PLL CONTROL VOLTAGE RANGE ADC 05361-069 TTL OR CMOS CLK INPUT The PLL enable switch shown in Figure 74 is connected to the junction of the N1 dividers (PLL VCO divide ratio) and N2 dividers (PLL loop divide ratio). Divider N3 determines the interpolation rate of the DAC, and the ratio N3/N2 determines the ratio of reference clock/input data rate. The VCO runs optimally over the range of 1.0 GHz to 2.0 GHz, so that N1 keeps the speed of the VCO within this range, although the DAC sample rate can be lower. The loop filter components are entirely internal and no external compensation is necessary. Figure 73. REFCLK VCM Generator Circuit INTERNAL PLL CLOCK MULTIPLIER/CLOCK DISTRIBUTION The internal clock structure on the devices allows the user to drive the differential clock inputs with a clock at 1× or an integer multiple of the input data rate or at the DAC output sample rate. An internal PLL provides input clock multiplication and provides all the internal clocks required for the interpolation filters and data synchronization. The internal clock architecture is shown in Figure 74. The reference clock is the differential clock at Pin 5 and Pin 6. This clock input can be run differentially or singled-ended by driving Pin 5 with a clock signal and biasing Pin 6 to the midswing point of the signal at Pin 5. The clock architecture can be run in the following configurations: Rev. A | Page 36 of 56 05361-071 LVDS_P_IN AD9776/AD9778/AD9779 Table 18. VCO Frequency Range vs. PLL Band Select Value PLL Band Select 111111 (63) 111110 (62) 111101 (61) 111100 (60) 111011 (59) 111010 58) 111001 (57) 111000 (56) 110111 (55) 110110 (54) 110101 (53) 110100 (52) 110011 (51) 110010 (50) 110001 (49) 110000 (48) 101111 (47) 101110 (46) 101101 (45) 101100 (44) 101011 (43) 101010 (42) 101001 (41) 101000 (40) 100111 (39) 100110 (38) 100101 (37) 100100 (36) 100011 (35) 100010 (34) 100001 (33) 100000 (32) 011111 (31) 011110 (30) 011101 (29) 011100 (28) 011011 (27) 011010 (26) 011001 (25) 011000 (24) 010111 (23) 010110 (22) 010101 (21) 010100 (20) 010011 (19) 010010 (18) 010001 (17) 010000 (16) 001111 (15) Typical PLL Lock Ranges VCO Frequency Range in MHz Typ at 25°C Typ over Temp fHIGH fLOW fHIGH fLOW Auto mode Auto mode 2056 2170 2105 2138 2002 2113 2048 2081 1982 2093 2029 2061 1964 2075 2010 2043 1947 2057 1992 2026 1927 2037 1971 2006 1907 2016 1951 1986 1894 2003 1936 1972 1872 1981 1913 1952 1852 1960 1892 1931 1841 1948 1881 1920 1816 1923 1855 1895 1796 1903 1835 1874 1789 1895 1828 1867 1764 1871 1803 1844 1746 1853 1784 1826 1738 1842 1776 1815 1714 1820 1752 1794 1700 1804 1737 1779 1689 1790 1726 1764 1657 1757 1695 1734 1641 1738 1679 1714 1610 1707 1649 1684 1597 1689 1635 1666 1568 1661 1607 1639 1553 1641 1592 1617 1525 1613 1562 1592 1511 1595 1548 1572 1484 1570 1519 1549 1470 1552 1506 1528 1441 1525 1474 1504 1429 1509 1463 1487 1403 1485 1433 1464 1390 1469 1422 1447 1362 1443 1391 1423 1352 1429 1380 1407 1325 1405 1352 1385 1314 1390 1340 1369 1290 1368 1315 1350 1276 1351 1302 1332 1253 1331 1277 1313 1239 1313 1264 1295 1183 1255 1205 1240 1204 1275 1227 1259 1151 1221 1172 1207 1171 1240 1193 1224 1148 1218 1170 1204 1137 1204 1159 1189 PLL Band Select 001110 (14) 001101 (13) 001100 (12) 001011 (11) 001010 (10) 001001 (9) 001000 (8) 000111 (7) 000110 (6) 000101 (5) 000100 (4) 000011 (3) 000010 (2) 000001 (1) 000000 (0) Typical PLL Lock Ranges VCO Frequency Range in MHz Typ at 25°C Typ over Temp fHIGH fLOW fHIGH fLOW 1116 1184 1137 1170 1106 1171 1127 1157 1086 1152 1106 1138 1075 1138 1095 1124 1055 1119 1075 1106 1045 1107 1065 1093 1027 1090 1047 1076 1016 1076 1034 1062 998 1059 1016 1046 987 1046 1005 1032 960 1017 977 1004 933 989 949 976 908 962 923 950 883 936 898 925 859 911 873 899 VCO Frequency Ranges Because the PLL band covers greater than a 2× frequency range, there can be two options for the PLL band select: one at the low end of the range and one at the high end of the range. Under these conditions, the VCO phase noise is optimal when the user selects the band select value corresponding to the high end of the frequency range. Figure 75 shows how the VCO bandwidth and the optimal VCO frequency varies with the band select value. VCO Frequency Ranges over Temperature The specifications given over temperature in Table 18 are for a single part in a single lot. Part-to-part, and lot-to-lot, these specifications can exhibit a mean shift of several register settings. Systems should be designed to take this potential shift into account to maintain optimal PLL performance. PLL Loop Filter Bandwidth The loop filter bandwidth of the PLL is programmed via SPI Register 0x0A, Bits<4:0>. Changing these values switches capacitors on the internal loop filter. No external loop filter components are required. This loop filter has a pole at 0 (P1), and then a zero (Z1) pole (P2) combination. Z1 and P2 occur within a decade of each other. The location of the zero pole is determined by Bits<4:0>. For a setting of 00000, the zero pole occurs near 10 MHz. By setting Bits<4:0> to 11111, the Z1/P2 combination can be lowered to approximately 1 MHz. The relationship between Bits<4:0> and the position of the zero pole between 1 MHz and 10 MHz is linear. The internal components are not low tolerance, however, and can drift by as much as ±30%. For optimal performance, the bandwidth adjustment (Register 0x0A, Bits<4:0>) should be set to 11111 for all operating modes with PLL enabled. The PLL bias settings Rev. A | Page 37 of 56 AD9776/AD9778/AD9779 (Register 0x09, Bits<2:0>) should be set to 111. The PLL control voltage (Register 0x0A, Bits<7:5>) is read back and is proportional to the dc voltage at the internal loop filter output. With the PLL bias settings given in this section, the readback from the PLL control voltage should typically be 010, or possibly 001 or 011. Anything outside of this range indicates that the PLL is not operating correctly. 60 56 52 external resistor is 10 kΩ, which sets up an IREFERENCE in the resistor of 120 μA, which in turn provides a DAC output fullscale current of 20 mA. Because the gain error is a linear function of this resistor, a high precision resistor improves gain matching to the internal matching specification of the devices. Internal current mirrors provide a current-gain scaling, where I DAC or Q DAC gain is a 10-bit word in the SPI port register (Register 0x0A, Register 0x0B, Register 0x0E, and Register 0x0F). The default value for the DAC gain registers gives an IFS of approximately 20 mA, where IFS is equal to 48 1.2 V ⎛ 27 ⎛ 6 ⎞ ×⎜ + ⎜ × DAC gain ⎞⎟ ⎟ × 32 R ⎠⎠ ⎝ 12 ⎝ 1024 44 36 32 28 AD9779 24 20 16 I DAC VREF 12 0.1μF 8 4 2150 Q DAC Q DAC GAIN 05361-072 2050 1950 1850 1750 1650 1550 1450 1350 1250 1150 1050 950 FVCO (MHz) DAC FULL-SCALE REFERENCE CURRENT CURRENT SCALING I120 10kΩ 0 850 I DAC GAIN 1.2V BAND GAP 05361-073 PLL BAND 40 Figure 77. Reference Circuitry Figure 75. Typical PLL Band Select vs. Frequency at 25°C 35 60 30 56 52 25 48 IFS (mA) 44 PLL BAND 40 36 32 20 15 28 24 10 20 16 8 0 4 2150 2050 0 200 400 600 800 DAC GAIN CODE 05361-113 FVCO (MHz) 1950 1850 1750 1650 1550 1450 1350 1250 1150 1050 850 950 0 1000 05361-074 5 12 Figure 78. IFS vs. DAC Gain Code Application of Auxiliary DACs in Single Sideband Transmitter Figure 76. Typical PLL Band Select vs. Frequency over Temperature The AD977x has an autosearch feature that determines the optimal settings for the PLL. To enable the autosearch mode, set Register 0x08, Bits<7:2> to 11111b, and read back the value from Register 0x08, Bits<7:2>. Autosearch mode is intended to find the optimal PLL settings only, after which the same settings should be applied in manual mode. It is not recommended that the PLL be set to autosearch mode during regular operation. FULL-SCALE CURRENT GENERATION Internal Reference Full-scale current on the I DAC and Q DAC can be set from 8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external resistor connected to I120 (Pin 75). A simplified block diagram of the reference circuitry is shown in Figure 77. The recommended value for the Two auxiliary DACs are provided on the AD977x. The full-scale output current on these DACs is derived from the 1.2 V band gap reference and external resistor. The gain scale from the reference amplifier current IREFERENCE to the auxiliary DAC reference current is 16.67 with the auxiliary DAC gain set to full scale (10-bit values, SPI Register 0x0D and SPI Register 0x11), this gives a full-scale current of approximately 2 mA for auxiliary DAC1 and auxiliary DAC2. The auxiliary DAC outputs are not differential. Only one side of the auxiliary DAC (P or N) is active at one time. The inactive side goes into a high impedance state (>100 kΩ). In addition, the P or N outputs can act as current sources or sinks. The control of the P and N side for both auxiliary DACs is via Register 0x0E and Register 0x10, Bits<7:6>. When sourcing current, the output compliance Rev. A | Page 38 of 56 AD9776/AD9778/AD9779 0.7 8× INTERPOLATION 0.6 4× INTERPOLATION 0.5 2× INTERPOLATION, ZERO STUFFING 0.4 2× INTERPOLATION 0.3 1× INTERPOLATION, ZERO STUFFING 0.2 1× INTERPOLATION 0.1 0 0 50 75 100 125 150 175 200 225 250 Figure 81. Total Power Dissipation, I Data Only, Real Mode 0.4 AD9779 AUX DAC1 8× INTERPOLATION POWER (W) 0.1μF AD9779 AUX DAC2 QUAD MOD I INPUTS 4× INTERPOLATION 0.3 QUADRATURE MODULATOR V+ OPTIONAL PASSIVE FILTERING 25 fDATA (MSPS) QUADRATURE MODULATOR V+ AD9779 I DAC 4× INTERPOLATION, ZERO STUFFING 8× INTERPOLATION, ZERO STUFFING 05361-076 The auxiliary DACs can be used for local oscillator (LO) cancellation when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the DAC output offset voltage mismatch) and can degrade system performance. Typical DAC-to-quadrature modulator interfaces are shown in Figure 79 and Figure 80. Often, the input common-mode voltage for the modulator is much higher than the output compliance range of the DAC, so that ac coupling or a dc level shift is necessary. If the required common-mode input voltage on the quadrature modulator matches that of the DAC, then the dc blocking capacitors in Figure 79 can be removed. A low-pass or band-pass passive filter is recommended when spurious signals from the DAC (distortion and DAC images) at the quadrature modulator inputs can affect the system performance. Placing the filter at the location shown in Figure 79 and Figure 80 allows easy design of the filter, as the source and load impedances can easily be designed close to 50 Ω. of the 3.3 V supply (mode and speed independent) in single DAC mode is 102 mW/31 mA. In dual DAC mode, this is 182 mW/55 mA. Furthermore, when the PLL is enabled, it adds 90 mW/50 mA to the 1.8 V clock supply regardless of the mode of the AD9779. POWER (W) voltage is 0 V to 1.6 V. When sinking current, the output compliance voltage is 0.8 V to 1.6 V. 0.1μF 2× INTERPOLATION 0.2 25Ω TO 50Ω 0.1μF 0.1 QUAD MOD Q INPUTS 1× INTERPOLATION 05361-115 0.1μF 25Ω TO 50Ω 0 Figure 79. Typical Use of Auxiliary DACs AC Coupling to Quadrature Modulator 0 25 50 75 100 125 150 175 200 225 250 fDATA (MSPS) 05361-078 OPTIONAL PASSIVE FILTERING AD9779 Q DAC Figure 82. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode, Does Not Include Zero Stuffing QUADRATURE MODULATOR V+ 0.08 QUAD MOD I OR Q INPUTS 25Ω TO 50Ω OPTIONAL PASSIVE FILTERING 25Ω TO 50Ω 05361-116 AD9779 I OR Q DAC POWER (W) 0.06 8× INTERPOLATION 4× INTERPOLATION 0.04 2× INTERPOLATION 0.02 1× INTERPOLATION Figure 80. Typical Use of Auxiliary DACs DC Coupling to Quadrature Modulator with DC Shift 0 POWER DISSIPATION Figure 81 to Figure 89 show the power dissipation of the 1.8 V and 3.3 V digital and clock supplies in single DAC and dual DAC modes. In addition to this, the power dissipation/current 0 25 50 75 100 125 150 fDATA (MSPS) 175 200 225 250 05361-079 AD9779 AUX DAC1 OR 2 Figure 83. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode, Includes Modulation Modes, Does Not Include Zero Stuffing Rev. A | Page 39 of 56 AD9776/AD9778/AD9779 0.125 0.075 8× INTERPOLATION, fDAC/8, fDAC/4, fDAC/2, NO MODULATION 0.100 4× INTERPOLATION ALL INTERPOLATION MODES POWER (W) POWER (W) 0.050 0.075 2× INTERPOLATION 0.050 0.025 0.025 25 50 75 100 125 150 175 200 225 250 fDATA (MSPS) Figure 84. Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation Modes and Zero Stuffing 1.0 0.9 25 50 75 100 125 150 175 200 225 250 Figure 87. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC Mode, Does Not Include Zero Stuffing 0.075 4× INTERPOLATION, ALL MODULATION MODES 0.8 0.7 ALL INTERPOLATION MODES 0.050 0.6 POWER (W) POWER (W) 0 fDATA (MSPS) 8× INTERPOLATION, ALL MODULATION MODES 8× INTERPOLATION, ZERO STUFFING 1× INTERPOLATION, NO MODULATION 05361-082 0 0 05361-080 0 2× INTERPOLATION, ALL MODULATION MODES 0.5 0.4 0.025 0.3 0.2 2× INTERPOLATION, ZERO STUFFING 4× INTERPOLATION, ZERO STUFFING 0.1 1× INTERPOLATION, ZERO STUFFING 25 50 75 100 125 150 175 200 225 250 275 300 fDATA (MSPS) 0 05361-077 0 75 100 125 150 175 200 225 250 0.16 8× INTERPOLATION, fDAC/8, fDAC/4, 0.7 fDAC/2, NO MODULATION 0.14 4× INTERPOLATION 0.12 0.5 0.4 POWER (W) 2× INTERPOLATION 0.3 0.2 0.10 0.08 0.06 0.04 1× INTERPOLATION, NO MODULATION 0 25 50 75 100 125 150 fDATA (MSPS) 175 200 225 0.02 250 05361-081 0.1 Figure 86. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC Mode, Does Not Include Zero Stuffing Rev. A | Page 40 of 56 0 0 200 400 600 800 1000 fDAC (MSPS) Figure 89. Power Dissipation of Inverse Sinc Filter 1200 05361-084 POWER (W) 50 Figure 88. Digital 3.3 V Supply, I and Q Data, Dual DAC Mode 0.8 0 25 fDATA (MSPS) Figure 85. Total Power Dissipation, Dual DAC Mode 0.6 0 05361-083 1× INTERPOLATION 0 AD9776/AD9778/AD9779 POWER-DOWN AND SLEEP MODES INTERLEAVED DATA MODE The AD977x has a variety of power-down modes, so that the digital engine, main TxDACs, or auxiliary DACs can be powered down individually or together. Via the SPI port, the main TxDACs can be placed in sleep or power-down mode. In sleep mode, the TxDAC output is turned off, thus reducing power dissipation. The reference remains powered on, however, so that recovery from sleep mode is very fast. With the power-down mode bit set (Register 0x00, Bit 4), all analog and digital circuitry, including the reference, is powered down. The SPI port remains active in this mode. This mode offers more substantial power savings than sleep mode, but the turn-on time is much longer. The auxiliary DACs also have the capability to be programmed into sleep mode via the SPI port. The auto power-down enable bit (Register 0x00, Bit 3) controls the power-down function for the digital section of the devices. The auto power-down function works in conjunction with the TXENABLE pin (Pin 39) according to the following: The TxEnable bit is dual function. In dual port mode, it is simply used to power down the digital section of the devices. In interleaved mode, the IQ data stream is synchronized to TXENABLE. Therefore, to achieve IQ synchronization, TXENABLE should be held low until an I data word is present at the inputs to Data Port 1. If a DATACLK rising edge occurs while TXENABLE is at a high logic level, IQ data becomes synchronized to the DATACLK output. TXENABLE can remain high and the input IQ data remains synchronized. To be backwards-compatible with previous DACs from Analog Devices, Inc. such as the AD9777 and AD9786, the user can also toggle TXENABLE once during each data input cycle, thus continually updating the synchronization. If TXENABLE is brought low and held low for multiple REFCLK cycles, then the devices flush the data in the interpolation filters, and shut down the digital engine after the filters are flushed. The amount of REFCLK cycles it takes to go into this power-down mode is then a function of the length of the equivalent 2×, 4×, or 8× interpolation filter. The timing of TXENABLE, I/Q select, filter flush, and digital power-down are shown in Figure 91. TXENABLE (Pin 39) = 0: autopower-down enable = 0: flush data path with 0s 1: flush data for multiple REFCLK cycles; then automatically place the digital engine in power-down state. DACs, reference, and SPI port are not affected. INTERLEAVED INPUT DATA I1 Q1 I2 Q2 TxENABLE TxENABLE CAN REMAIN HIGH OR TOGGLE FOR I/Q SYNCHRONIZATION 1: normal operation As shown in Figure 90, the power dissipation saved by using the power down mode is nearly proportional to the duty cycle of the signal at the TXENABLE pin. 0.9 2× INT fDATA = 50MSPS 2× INT fDATA = 200MSPS 4× INT fDATA = 50MSPS 4× INT fDATA = 200MSPS 8× INT fDATA = 50MSPS 8× INT fDATA = 200MSPS 0.8 POWER SAVINGS 0.7 0.6 0.5 0.4 FLUSHING INTERPOLATION FILTERS POWER DOWN DIGITAL SECTION 05361-085 or TXENABLE (Pin 39) = Figure 91. TXENABLE Function The TXENABLE function can be inverted by changing the status of Register 0x02, Bit 1. The other bit that controls IQ ordering is the Q-first bit (Register 0x02, Bit 0). With the Q-first bit reset to the default of 0, the IQ pairing that is latched is the I1Q1, I2Q2, and so on. With IQ first set to 1, the first I data is discarded and the pairing is I2Q1, I3Q2, and so on. Note that with IQ-first set, the I data is still routed to the internal I channel, the Q data is routed to the internal Q channel, and only the pairing changes. 0.3 TIMING INFORMATION 0.2 0 0 20 40 60 80 100 DUTY CYCLE (%) Figure 90. Power Savings Based on Duty Cycle of TxEnable If the TxEnable invert bit (Register 0x02, Bit 1) is set, the function of this TXENABLE pin is inverted. 05361-119 0.1 Figure 92 to Figure 95 show some of the various timing possibilities when the PLL is enabled. The combination of the settings of N2 and N3 from Figure 74 means that the reference clock frequency can be a multiple of the actual input data rate. Figure 92 to Figure 95 show, respectively, what the timing looks like when N2/N3 = 1 and 2. In interleaved mode, set-up and hold times of DATACLK out to data in are the same as those shown in Figure 92 to Figure 95. It is recommended that any toggling of TXENABLE occur concurrently with the digital data input updating. In this way, timing margins between DATACLK, TXENABLE, and digital input data are optimized. Rev. A | Page 41 of 56 AD9776/AD9778/AD9779 REFERENCE CLOCK IN tSREFCLK tSDATACLK tHREFCLK tHDATACLK INPUT DATA 05361-120 DATA CLOCK OUT Figure 92. Timing Specifications, PLL Enabled or Disabled, Interpolation = 1× SYNC_IN tH_SYNC tS_SYNC REFERENCE CLOCK IN DATA CLOCK OUT tSDATACLK tHDATACLK INPUT DATA 05361-121 tHREFCLK tSREFCLK Figure 93. Timing Specifications, PLL Enabled or Disabled, Interpolation = 2× SYNC_IN tH_SYNC tS_SYNC REFERENCE CLOCK IN tSREFCLK tSDATACLK tHREFCLK tHDATACLK INPUT DATA 05361-122 DATA CLOCK OUT Figure 94. Timing Specifications, PLL Enabled or Disabled, Interpolation = 4× SYNC_IN tH_SYNC tS_SYNC REFERENCE CLOCK IN tSREFCLK tSDATACLK tHREFCLK tHDATACLK INPUT DATA Figure 95. Timing Specifications, PLL Enabled or Disabled, Interpolation = 8× Rev. A | Page 42 of 56 05361-123 DATA CLOCK OUT AD9776/AD9778/AD9779 and must be no greater than DATACLK for proper synchronization. There is no limit on how slow the SYNC_I signal can be driven. As long as the set up and hold timing relationship between SYNC_I and REFCLK given in Table 19 is met, the input data is latched on the immediate next rising edge of REFCLK. Note that a rising edge of DATACLK out occurs concurrently with the next REFCLK rising edge, after a short propagation delay. Although this propagation delay is not specified, input data setup and hold timing information is given with respect to REFCLK in and DATACLK out in Figure 92 to Figure 95. Also, note that in 1× interpolation, because there is no phase ambiguity, there is no need to use the SYNC_I signal. Specifications are given in Table 19 for the drift of input data set up and hold time vs. temperature, as well as the data keep out window (KOW). Note that although these specifications do drift, the length of the keep out window, where input data is invalid, changes very little over temperature. Table 19. AD9779 Timing Specifications vs. Temperature Timing Parameter REFCLK to DATA DATACLK to DATA SYNC_I to REFCLK Temperature −40°C +25°C +85°C −40°C +25°C +85°C −40°C to +85°C Min tS (ns) −0.8 −1.1 −1.3 +1.8 +2.1 +2.5 −0.2 Min tH (ns) +2.2 +2.5 +2.9 −0.4 −0.7 −0.9 +1.0 Max KOW (ns) +1.3 +1.4 +1.5 +1.3 +1.4 +1.5 +0.8 Valid Timing Window In addition to the timing requirements of SYNC_I with respect to REFCLK, it is important to understand that the valid timing window for SYNC_I is limited by the internal DAC sample rate. This is shown in Figure 96. When the tS and tH requirements are met, the valid timing window for SYNC_I extends only as far as one period of the internal DAC sample rate (minus tS and tH). Failure to meet this timing specification can potentially result in erroneous data being latched into the AD9779 digital inputs. SYNCHRONIZATION OF INPUT DATA TO DATACLK OUTPUT (PIN 37) Synchronizing the input data bus to the DATACLK out signal is achieved by meeting the timing relationships between DATACLK and DATA timing specified in Table 19. If the user is synchronizing the input data to the DATACLK out, the sync input (SYNC_I) signal does not need to be applied and can be ignored (connect to GND). As an example, if the AD9779 input data rate is 122.88 MSPS and the REFCLK is the same, with the AD9779 in 4× interpolation, the DAC sample rate is 1/491.52 MHz or about 2 ns. With a tS of −0.2 ns and tH of 1.0 ns, this gives a valid timing window for SYNC_I of SYNCHRONIZATION OF INPUT DATA TO THE REFCLK INPUT (PIN 5 AND PIN 6) WITH PLL ENABLED OR DISABLED The timing window of the digital input data to REFCLK can be moved in increments of one internal REFCLK cycle by using the REFCLK OFFSET register (Register 0x7, Bits<4:0>). 2 ns − 0.8 ns = 1.2 ns Synchronizing the input data bus to the REFCLK input requires the use of the SYNC_I input pins (Pin 13 and Pin 14). If the SYNC_I input is not used, there is a phase ambiguity between the DATACLK out and the REFCLK in. This ambiguity matches the interpolation rate in which the AD9779, for example, is currently operating. Because input data is latched on the rising edge of DATACLK, it is impossible for the user to determine onto which one of the multiple internal DACCLK edges (as an example, one of four edges in 4× interpolation) the input data actually latches. For the user to specifically determine the exact edge of REFCLK on which the data is being latched, a rising edge must be periodically applied to SYNC_I. The frequency of the SYNC_I signal must be equal to fDAC/2N, N being an integer, Because SYNC_I can be run at the same frequency as REFCLK when the PLL is enabled, best practice suggests that in this condition, REFCLK and SYNC_I originate from the same source. This limits the variation in time between these two signals and makes the overall timing budget easier to achieve. A slight delay may be necessary on the REFCLK path in this configuration to add more timing margin between REFCLK and SYNC_I (see Table 19 for timing relationship). REFCLK tS tH tDAC_SAMPLE 05361-124 tDAC_SAMPLE SYNC_I Figure 96. Valid Timing Relationship for SYNC_I to REFCLK Rev. A | Page 43 of 56 AD9776/AD9778/AD9779 TEK RUN: 5.00GS/s To meet strict timing requirements at input data rates of up to 250 MSPS, the AD977x has a fine timing feature. Fine timing adjustments are made by programming values into the data clock delay register (Register 0x04, Bits<7:4>). This register can be used to add delay between the REFCLK in and the DATACLK out. Figure 97 shows the default delay present when DATACLK delay is disabled. The disable function bit is found in Register 0x02, Bit 4. Figure 98 shows the delay present when DATACLK delay is enabled and set to 0000. Figure 99 indicates the delay when DATACLK delay is enabled and set to 1111. Note that the setup and hold times specified for data to DATACLK are defined for DATACLK delay disabled. TEK RUN: 5.00GS/s SAMPLE Δ: 7.84nS @: 32.44nS 2 05361-091 Using Data Delay to Meet Timing Requirements 1 CH1 1.00VΩ CH2 500mVΩ M2.00ns CH1 420mV Figure 99. Delay from REFCLK to DATACLK Out with DATACLK Delay = 1111 SAMPLE The difference between the minimum delay shown in Figure 98 and the maximum delay shown in Figure 99 is the range programmable using the DATACLK delay register. The delay (in absolute time) when programming DATACLK delay between 0000 and 1111 is a linear extrapolation between these two figures. The typical delays per increment over temperature are shown in Table 20. Δ: 4.48nS @: 40.28nS 2 05361-089 Table 20. Data Delay Line Typical Delays Over Temperature 1 CH1 1.00VΩ CH2 500mVΩ M2.00ns CH1 420mV Figure 97. Delay from REFCLK to DATACLK with DATACLK Delay Disabled TEK RUN: 5.00GS/s SAMPLE Δ: 4.76nS @: 35.52nS Delays Delay Between Disabled and Enabled Average Delay per Increment −40°C 370 +25°C 416 +85°C 432 Unit ps 171 183 197 ps The frequency of DATACLK out depends on several programmable settings: interpolation, zero stuffing, and interleaved/ dual port mode, all of which have an effect on the REFCLK frequency. The divisor function between REFCLK and DATACLK is equal to the values shown in Table 21. Table 21. REFCLK to DATACLK Divisor Ratio 1 CH1 1.00VΩ CH2 500mVΩ M2.00ns CH1 420mV 05361-090 2 Figure 98. Delay from REFCLK to DATACLK Out with DATACLK Delay = 0000 Interpolation 1 2 4 8 1 2 4 8 1 2 4 8 1 2 4 8 Rev. A | Page 44 of 56 Zero Stuffing Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Input Mode Dual port Dual port Dual port Dual port Interleaved Interleaved Interleaved Interleaved Dual port Dual port Dual port Dual port Interleaved Interleaved Interleaved Interleaved Divisor 1 2 4 8 Invalid 1 2 4 2 4 8 16 1 2 4 8 AD9776/AD9778/AD9779 In addition to this divisor function, DATACLK can be divided by up to an additional factor of 4, according to the state of the DATACLK divide register (Register 0x03, Bits<5:4>). For more details, see Table 22). Table 22. Extra DATACLK Divisor Ratio Register 0x03, Bits<5:4> 00 01 10 11 Divider Ratio 1 2 4 1 Necessary corrections can be made by adjusting DATACLK delay and the DATACLK invert bit (Register 2, Bit 2). DATACLK delay can then be swept to find the range over which the timing is valid. The final value for data delay should be the value that corresponds to the middle of the valid timing range. If a valid timing range is not found during this sweep, the user should invert the DATACLK invert bit and repeat the process. Multiple DAC Synchronization The maximum divisor resulting from the combination of the values in Table 21, and the DATACLK divide register is 32. Manual Input Timing Correction The AD9779 has programmable features that allow the CMOS digital data bus inputs and internal filters on multiple devices to be synchronized. This means that the DATACLK output signal on one AD9779 can be used to register the output data for a data bus delivering data to multiple AD9779s. The details of this operation are given in the Analog Devices Application Note AN-822. Correction of input timing can be achieved manually. The correction function is controlled by Register 0x03, Bits<7:6>. The function is programmed as shown in Table 23. Table 23. Input Timing Correction Mode Register 0x03, Bits<7:6> 00 01 10 11 Function Error check disabled Reserved Reserved Reserved Rev. A | Page 45 of 56 AD9776/AD9778/AD9779 EVALUATION BOARD OPERATION The AD977x evaluation board is designed to optimize the DAC performance and the speed of the digital interface, yet remains user friendly. To operate the board, the user needs a power source, a clock source, and a digital data source. The user also needs a spectrum analyzer or an oscilloscope to look at the DAC output. The diagram in Figure 100 illustrates the test setup. A sine or square wave clock works well as a clock source. The dc offset on the clock is not a problem, since the clock is ac-coupled on the evaluation board before the REFCLK inputs. All necessary connections to the evaluation board are shown in more detail in Figure 101. The evaluation board comes with software that allows the user to program the SPI port. Via the SPI port, the devices can be programmed into any of its various operating modes. When first operating the evaluation board, it is useful to start with a simple configuration, that is, a configuration in which the SPI port settings are as close as possible to the default settings. The default software window is shown in Figure 102. The arrows indicate which settings need to be changed for an easy first time evaluation. Note that this implies that the PLL is not being used and that the clock being used is at the speed of the DAC output sample rate. For a more detailed description of how to use the PLL, see the PLL Loop Filter Bandwidth section. CLOCK GENERATOR ADAPTER CABLES CLKIN DIGITAL PATTERN GENERATOR SPI PORT SPECTRUM ANALYZER AD9779 EVALUATION BOARD CLOCK IN 3.3V POWER SUPPLY 05361-097 1.8V POWER SUPPLY DATACLK OUT Figure 100. Typical Test Setup AUX33 DVDD18 DVDD33 P4 Digital Input Connector CVDD18 J1 CLOCK IN AD9779 JP4 JP15 JP8 JP14 JP3 JP16 JP2 JP17 AVDD33 J2 5V Supply MODULATOR OUTPUT S5 OUTPUT 1 AD8349 +5V GND S6 OUTPUT 2 LOCAL OSC INPUT S7 DCLKOUT ANALOG DEVICES AD9779/8/6 REV D 05361-098 SPI PORT Figure 101. AD977x Evaluation Board Showing All Connections Rev. A | Page 46 of 56 AD9776/AD9778/AD9779 1. SET INTERPOLATION RATE 2. SET INTERPOLATION FILTER MODE 3. SET INPUT DATA FORMAT 05361-099 4. SET DATACLK POLARITY TO MATCH INPUT TIMING Figure 102. SPI Port Software Window The default settings for the evaluation board allow the user to view the differential outputs through a transformer that converts the DAC output signal to a single-ended signal. On the evaluation board, these transformers are designated T1A, T2A, T3A, and T4A. There are also four common-mode transformers on the board that are designated T1B, T2B, T3B, and T4B. The recommended operating setup places the transformer and common-mode transformer in series. A pair of transformers and common-mode transformers are installed on each DAC output, so that the pairs can be set up in either order. As an example, for the frequency range of dc to 30 MHz, it is recommended that the transformer be placed right after the DAC. Above DAC output frequencies of 30 MHz, it is recommended that the common-mode transformer is placed right after the DAC outputs, followed by the transformer. Rev. A | Page 47 of 56 AD9776/AD9778/AD9779 MODIFYING THE EVALUATION BOARD TO USE THE AD8349 ON-BOARD QUADRATURE MODULATOR The evaluation board contains an Analog Devices AD8349 quadrature modulator. The AD977x and AD8349 provide an easy-to-interface DAC/modulator combination that can be easily evaluated on the evaluation board. To route the DAC output signal to the quadrature modulator, the following jumper settings must be made: Unsoldered: JP14, JP15, JP16, JP17 Soldered: JP2, JP3, JP4, JP8 05361-100 The DAC output area of the evaluation board is shown in Figure 103. The jumpers that need to be changed to use the AD8349 are circled. Also circled are the 5 V and GND connections for the AD8349. Figure 103. Photo of Evaluation Board, DAC Output Area Rev. A | Page 48 of 56 Figure 104. Evaluation Board, Rev. D, Power Supply Decoupling and SPI Interface Rev. A | Page 49 of 56 DPWR33_IN TP7 RED DVDD33_IN TP6 RED AVDD33_IN TP5 RED DVDD18_IN 05361-101 C77 22μF 16V C22 22μF 16V C21 22μF 16V C20 22μF 16V C76 22μF 16V TP3 RED CVDD18_IN + + + + + TP1 RED TP21 RED TP20 RED TP19 RED TP18 RED TP17 RED L6 L7 EXC-CL4532U1 C48 0.1μF L15 EXC-CL4532U1 L5 EXC-CL4532U1 C45 0.1μF L14 EXC-CL4532U1 L4 EXC-CL4532U1 C28 0.1μF L13 EXC-CL4532U1 L3 EXC-CL4532U1 C71 0.1μF EXC-CL4532U1 L2 EXC-CL4532U1 C68 0.1μF EXC-CL4532U1 L1 C49 0.1μF C42 0.1μF C26 0.1μF C70 0.1μF C69 0.1μF TP10 BLACK DPWR33 TP9 BLACK DVDD33 TP8 BLACK AVDD33 TP4 BLACK DVDD18 TP2 BLACK CVDD18 R55 10kΩ SPI_CSB SPI_CLK SPI_SDI SPI_SDO DGND2 TP15 BLACK + 2 U5 U5 11 1 2 74AC14 U6 13 12 R54 9kΩ R53 9kΩ R51 9kΩ 74AC14 U6 74AC14 10 13 74AC14 3 U5 74AC14 12 74AC14 U5 8 9 U5 1 EXC-CL4532U1 C67 0.1μF L16 EXC-CL4532U1 L12 74AC14 U5 6 5 4 74AC14 R52 10kΩ C46 22μF 16V TP14 RED VDDM_IN 3 1 3 2 S3 SWSECMA SDI 1 2 1 1 S2 SWSECMA 3 2 TP16 RED S4 SWSECMA SDO 3 2 SCLK DGND2 VDDM S1 SWSECMA CSB 2 C66 0.1μF TP13 RED U6 4 P1 74AC14 74AC14 U6 6 74AC14 U6 8 FCI-68898 TJAK06RAP CLASS = IO 1 2 3 4 5 6 5 9 74AC14 U6 11 10 3 AD9776/AD9778/AD9779 EVALUATION BOARD SCHEMATICS S2 C55 0.1µF C14 0.1µF C6 4.7µF 2 JP13 TC1-1T C24 1nF C59 1nF C9 0.1µF C1 4.7µF R11 50Ω JP3 AVDD33 C58 1nF DATACLK S7 1 R32 25Ω + + VOLT 4 2 DPWR33 5 C78 VOLT 4.7µF Y VCC 6 D2N JP2 JP8 D1N C18 1nF VOLT C8 10µF R56 10Ω 1 U11 3 GND 2 A 1 NC R64 1kΩ R26 22Ω C84 0.1µF Rev. A | Page 50 of 56 T3A S D2P 4 6 4 P 1 2 JP18 R26 22Ω SN74LVC1G34 C32 0.1µF Figure 105. Evaluation Board, Rev. D, Circuitry Local to Devices 3 2 1 3 1 ADTL1-12 CLK_N CLK_P 1 2 3 4 3 J 1 2 K PRE CLR T4A TC1-1T T3B 6 S C31 1nF JP7 6 5 4 Q Q_ 5 6 4 4 P R64 1kΩ C57 0.1µF CVDD18 2 6 DPWR33 R63 10Ω C38 0.1µF CR1 VAL C25 1nF 6.3V CR2 VAL C10 0.1µF VOLT R59 22Ω R58 22Ω C2 4.7µF DVDD33 DVDD18 VOLT + C4 4.7µF VOLT 1 U10 11 J 13 12 K 15 14 74LCX112 74LCX112 + C60 0.1µF D1P JP15 R11 50Ω + JP4 R5 0Ω R8 0Ω 3 2 1 9779TQFP C33 1nF JP14 R9 50Ω JP17 1 4 1 2 3 R6 0Ω 2 T1A SW1 ADTL1-12 T2A R7 0Ω U1 C56 1nF 6 4 JP16 P2D5 P2D6 C37 0.1µF R10 50Ω 3 C61 1nF 6 P2D0 P2D1 P2D2 P2D3 P2D4 4 T1B SPI_CSB SPI_CLK SPI_SDI SPI_SDO ADTL1-12 TP11 RED TP12 RED TC1-1T S + C62 0.1µF P IOUT2_P 3 IOUT2_N 4 05361-102 S15 1 + VOLT 6 AUX2_N AUX2_P 4 1 2 3 IOUT1_P T2B IOUT1_N 1 AUX1_P AUX1_N + 6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PAD S5 S VDDA33_100 VSSA_99 VDDA33_98 VSSA_97 VDDA33_96 VSSA_95 VSSA_94 IOUT1_P IOUT1_N VSSA_91 AUX1_P AUX1_N VSSA_88 AUX2_N AUX2_P VSSA_85 IOUT2_N IOUT2_P VSSA_82 VSSA_81 VDDA33_80 VSSA_79 VDDA33_78 VSSA_77 VDDA33_76 I120 VREF_74 IPTAT VSS_72 IRQ RESET SPI_CSB SPI_CLK SPI_SDI SPI_SDO PLL_LOCK VSSD_64 SYNC_OP SYNC_ON VDDD33_61 VDDD18_60 P2D0 P2D1 P2D2 P2D3 P2D4 VSSD_54 VDDD18_53 P2D5 P2D6 PAD 1 VDDC18_1 VDDC18_2 VSSC_3 VSSC_4 CLK_P CLK_N VSSC_7 VSSC_8 VDDC18_9 VDDC18_10 VSSC_11 VSS_12 SYNC_1P SYNC_1N VSSD_15 VDDD18 P1D15 P1D14 P1D13 P1D12 P1D11 VSSD_22 VDDD18_23 P1D10 P1D9 P1D8 P1D7 P1D6 P1D5 P1D4 P1D3 VSSD_32 VDDD18_33 P1D2 P1D1 P1D0 DCLK VDDD33_38 TX P2D15 P2D14 P2D13 VDD18_43 VSSD_44 P2D12 P2D11 P2D10 P2D9 P2D8 P2D7 2 P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 3 + AD9776/AD9778/AD9779 S6 1 TC1-1T T4B 3 1 ADTL1-12 DGND;5 C34 1nF C40 0.1µF C35 1nF C39 0.1µF C36 1nF C27 1nF C11 0.1µF C3 4.7µF C29 1nF C12 0.1µF C30 1nF C13 0.1µF C5 4.7µF DVDD33 DVDD18 P2D15 2 S16 DPWR33 DPWR33 10 PRE CLR U10 Q_ Q 9 7 C7 4.7µF C15 1nF AD9776/AD9778/AD9779 D1N C80 2.1pF R15 20Ω C64 17.2pF R17 150Ω C50 17.2pF L10 55nH AUX1_N R4 150Ω C53 0.1µF R20 40Ω R19 300Ω C81 2.1pF JP13 AUX1_P R12 150Ω C63 17.2pF C52 17.2pF L11 55nH R22 147.5Ω R21 40Ω 3 P C47 100pF 4 S T5 6 ADTL1-12 R16 20Ω 1 D1P VDDM C72 0.1µF QBBP QBBN G4B G4A VPS2 VOUT G3 G2 1 2 3 4 5 6 7 8 J4 DGND2 VDDM U9 2 DGND2 1 2 2 DGND2 IBBP IBBN G1A G1B LOIN LOIP VPS1 ENBL C73 0.1µF 16 15 14 13 12 11 10 9 + AD8349 C41 10µF 10V MODULATED OUTPUT R14 1kΩ JP1 2 C51 0.1µF DGND2 C74 100pF 1 2 S 3 2 C44 17.2pF R25 150Ω R27 300Ω 6 C54 0.1µF R60 40Ω JP9 JP10 2 JP13 DGND2 AUX2_P C79 17.2pF L11 55nH R62 147.5Ω R61 40Ω 05361-103 C43 17.2pF R23 20Ω Figure 106. Evaluation Board, Rev. D, AD8349 Quadrature Modulator CLK_P T2 J1 CLKIN 4 R13 VAL 5 P 3 2 S 1 ETC1-1-13 C19 0.1μF C23 0.1μF R28 25Ω R30 1kΩ C16 DNB R29 25Ω R31 300Ω C17 0.1μF CVDD18 CLK_N Figure 107. Evaluation Board, Rev. D, DAC Clock Interface Rev. A | Page 51 of 56 05361-104 D2P 2 DGND2 DGND2 T3 S C65 17.2pF C82 2.1pF R3 150Ω 2 4 ETC1-1-13 L10 55nH AUX2_N R2 150Ω P J5 1 C83 2.1pF R24 20Ω C75 100pF 1 5 P ADTL1-12 3 4 DGND2 D2N LOCAL OSC OUTPUT T4 AD9776/AD9778/AD9779 P4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 P4 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 P4 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 PKG_TYPE = MOLEX110 VAL PKG_TYPE = MOLEX110 VAL PKG_TYPE = MOLEX110 VAL DGND BLK P4 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 P4 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 PKG_TYPE = MOLEX110 VAL PKG_TYPE = MOLEX110 VAL CSB SD1 P2D0 P2D2 P2D4 P2D6 P2D8 P2D10 P2D12 P2D14 P1D1 P1D3 P1D5 P1D7 P1D9 P1D11 P1D13 P1D15 05361-105 P1D0 P1D2 P1D4 P1D6 P1D8 P1D10 P1D12 P1D14 SCLK SD0 P2D1 P2D3 P2D5 P2D7 P2D9 P2D11 P2D13 P2D15 DGND1 BLK Figure 108. Evaluation Board, Rev. D, Digital Input Buffers 5V 1 2 U2 1 2 3 P2 1 2 VAL CNTERM_2P C86 1μF C85 1μF 4 CVDD18_IN JP19 ADP3339-1-8 U3 1 2 3 C89 1μF C88 1μF 4 DVDD18_IN JP20 ADP3339-1-8 U4 1 2 3 C92 1μF C91 1μF 4 DVDD33_IN JP21 ADP3339-3-3 U7 1 2 3 C93 1μF C94 1μF 4 AVDD33_IN JP22 ADP3339-3-3 U8 1 2 3 C96 1μF C97 1μF 4 DPWR33_IN JP23 ADP3339-3-3 Figure 109. Evaluation Board, On-Board Voltage Regulators Rev. A | Page 52 of 56 05361-106 J2 05361-107 AD9776/AD9778/AD9779 05361-108 Figure 110. Evaluation Board, Rev. D, Top Silk Screen Figure 111. Evaluation Board, Rev. D, Top Layer Rev. A | Page 53 of 56 05361-109 AD9776/AD9778/AD9779 05361-110 Figure 112. Evaluation Board, Rev. D, Layer 2 Figure 113. Evaluation Board, Rev. D, Layer 3 Rev. A | Page 54 of 56 05361-111 AD9776/AD9778/AD9779 05361-112 Figure 114. Evaluation Board, Rev. D, Bottom Layer Figure 115. Evaluation Board, Rev. D, Bottom Silkscreen Rev. A | Page 55 of 56 AD9776/AD9778/AD9779 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 1 SEATING PLANE 76 76 75 100 1 75 PIN 1 BOTTOM VIEW (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 25 26 0.20 0.09 51 50 25 50 1.05 1.00 0.95 7° 3.5° 0° 0.50 BSC 0.27 0.22 0.17 0.15 0.05 26 6.50 NOM COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 116. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9776BSVZ 1 AD9776BSVZRL1 −40°C to +85°C −40°C to +85°C Temperature Range Package Description 100-lead TQFP_EP 100-lead TQFP_EP Package Option SV-100-1 SV-100-1 AD9778BSVZ1 AD9778BSVZRL1 −40°C to +85°C −40°C to +85°C 100-lead TQFP_EP 100-lead TQFP_EP SV-100-1 SV-100-1 AD9779BSVZ1 AD9779BSVZRL1 −40°C to +85°C −40°C to +85°C 100-lead TQFP_EP 100-lead TQFP_EP SV-100-1 SV-100-1 AD9776-EB AD9778-EB AD9779-EBZ1 1 Evaluation Board Evaluation Board Evaluation Board Z = RoHS Compliant Part. ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05361-0-3/07(A) Rev. A | Page 56 of 56