[AK5806]
AK5806
8ch Analog Front End IC
1. General description
The AK5806 is an 8 channels analog baseband IC with third order HPF, whose cutoff frequency is
variable, and programmable gain amplifiers.
It is capable of adjusting the baseband signal gain and the frequency band widely.
2. Features
- Signal Processing: 8-channel Differential I/O
- Signal band width: up to 5MHz
- Programmable Gain Amplifier:
(Coarse) 0dB to 42dB, 6dB/step
(Fine) −6dB to +5.625dB, 0.375dB/step
- 3rd-order HPF with Adjustable Cutoff Frequency: 25 kHz to 1MHz
- Offset Cancelling Function
- Operational Temperature: −40 to 125ºC
- Package: 64-pins HTQFP
3. Application
- Millimeter wave radar
- Laser rangefinder
- Ultrasonic sensor
- Signal conditioning before AD conversion
etc.
4. Block diagram
VDD
AOUT1P
AIN1P
PGA1
AIN1N
HPF
&
Buffer
PGA2
&
Fine gain
Output buffer
AOUT1N
Offset
calibration
AINnP
AOUTnP
Ch.2 to Ch.8
AINnN
VCOM
IREF
AOUTnN
Voltage
reference
Diagnostic
function
Reset control
SPI control
CSN
CCLK
CDTI
CDTO
RSTN
VSS
Figure 1
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5. Table of Contents
1. General description····························································································· 1
2. Features ············································································································ 1
3. Application ········································································································ 1
4. Block diagram ···································································································· 1
5. Table of Contents ································································································ 2
6. Pin layout and functions ······················································································ 3
6.1. Pin layout ·················································································································· 3
6.2. Pin functions ············································································································· 4
7. Absolute Maximum Ratings ·················································································· 5
8. Recommended Operating Conditions ···································································· 5
9. Electrical characteristics······················································································ 6
9.1. DC Characteristics······································································································ 6
9.2. AC Timing ················································································································· 6
9.2.1. Reset input··········································································································· 6
9.2.2. Power Up Sequence ······························································································ 6
9.2.3. Serial Communication Interface Timing···································································· 7
9.3. Analog Characteristics ································································································ 7
9.3.1. Analog Input Signal ······························································································· 7
9.3.2. Analog Output Signal ···························································································· 7
9.3.3. Input Referred Noise Density ·················································································· 8
9.3.4. Internal High Pass Filter ························································································· 8
9.3.5. Coarse Gain Control ······························································································ 8
9.3.6. Fine Gain Control ·································································································· 8
9.3.7. Reference Voltage ································································································· 8
9.3.8. Detection Function ································································································ 8
9.3.9. Current Consumption ···························································································· 9
9.3.10. Channel to channel mismatch ··············································································· 9
9.3.11. Others ················································································································ 9
10. Functional Descriptions ····················································································· 9
10.1. Analog input ············································································································ 9
10.2. Internal High Pass Filter ··························································································· 10
10.3. Coarse Gain Control ································································································· 10
10.4. Fine Gain Control ····································································································· 10
10.5. Reference Voltage ···································································································· 10
10.6. Power Management ·································································································· 10
10.7. Offset Cancellation ·································································································· 11
10.8. Serial Communication Interface (SPI) ········································································· 12
10.8.1. Write format ······································································································· 12
10.8.2. Read Format ······································································································ 12
11. Register ········································································································· 13
11.1. Register Map ··········································································································· 13
11.2. Register Definitions ·································································································· 13
Sub Address 0x00 ·········································································································· 13
Sub Address 0x01 ·········································································································· 13
Sub Address 0x02 ·········································································································· 14
Sub Address 0x03 ·········································································································· 14
Sub Address 0x04 ·········································································································· 14
Sub Address 0x05 ·········································································································· 14
Sub Address 0x06 ·········································································································· 14
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Sub Address 0x07 ·········································································································· 14
Sub Address 0x08 ·········································································································· 15
Sub Address 0x09 – Sub Address 0x10 ·············································································· 15
Sub Address 0x11 ·········································································································· 15
12. Example of External Connection Diagram ··························································· 16
13. Package ········································································································· 16
13.1. Outline Dimensions ·································································································· 16
13.2. Foot Pattern ············································································································ 17
13.3. Marking ·················································································································· 17
IMPORTANT NOTICE ···························································································· 18
6. Pin layout and functions
NC
NC
AIN7N
AIN7P
NC
NC
AIN8N
AIN8P
NC
TEST
CSN
RSTN
AOUT8P
AOUT8N
AOUT7P
AOUT7N
6.1. Pin layout
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AOUT6N
AIN5P
53
28
AOUT5P
AIN5N
54
27
AOUT5N
NC
55
26
VDD
VCOM
56
25
VSS
IREF
57
24
VSS
NC
58
23
VDD
AIN4P
59
22
AOUT4P
AIN4N
60
21
AOUT4N
NC
61
20
AOUT3P
NC
62
19
AOUT3N
AIN3P
63
18
VDD
AIN3N
64
17
VSS
2
3
4
5
6
7
8
AIN1N
1
9
10
11
12
13
14
15
16
AOUT2P
29
AOUT2N
52
AOUT1P
NC
AOUT1N
AOUT6P
CDTI
30
CDTO
51
CCLK
NC
NC
VDD
AIN1P
31
NC
50
NC
AIN6N
AIN2N
VSS
AIN2P
32
NC
49
NC
AIN6P
TOP View
Figure 2
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[AK5806]
6.2. Pin functions
Pin #
Pin name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
NC
NC
AIN2P
AIN2N
NC
NC
AIN1P
AIN1N
NC
CCLK
CDTO
CDTI
AOUT1N
AOUT1P
AOUT2N
AOUT2P
VSS
VDD
AOUT3N
AOUT3P
AOUT4N
AOUT4P
VDD
VSS
VSS
VDD
AOUT5N
AOUT5P
AOUT6N
AOUT6P
VDD
VSS
AOUT7N
AOUT7P
AOUT8N
AOUT8P
RSTN
CSN
TEST
NC
AIN8P
AIN8N
NC
I
I
I
I
I
I
I
I
I
I
O
I
O
O
O
O
O
O
O
O
-
No connect pin. Connect to No.64 pin.
No connect pin. Connect to No.3 pin.
Analog Signal Input Pin
Analog Signal Input Pin
No connect pin. Connect to No.4 pin.
No connect pin. Connect to No.7 pin.
Analog Signal Input Pin
Analog Signal Input Pin
No connect pin. Connect to No.8 pin.
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Clock Input Pin for SPI Communication
Data Output Pin for SPI Communication
Data Input Pin for SPI Communication
Analog Signal Output Pin
Analog Signal Output Pin
Analog Signal Output Pin
Analog Signal Output Pin
Ground pin
Power Supply pin
Analog Signal Output Pin
Analog Signal Output Pin
Analog Signal Output Pin
Analog Signal Output Pin
Power Supply pin
Ground pin
Ground pin
Power Supply pin
Analog Signal Output Pin
Analog Signal Output Pin
Analog Signal Output Pin
Analog Signal Output Pin
Power Supply pin
Ground pin
Analog Signal Output Pin
Analog Signal Output Pin
Analog Signal Output Pin
Analog Signal Output Pin
Reset Input Pin (Internal Pull-down)
Chip Select Input Pin for SPI Communication
AKM Test Mode Pin. It must be connected to VSS.
No connect pin. Connect to No.41 pin.
Analog Signal Input Pin
Analog Signal Input Pin
No connect pin. Connect to No.42 pin.
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[AK5806]
Pin #
Pin name
I/O
Function
44
45
46
47
48
49
50
51
52
53
54
55
NC
AIN7P
AIN7N
NC
NC
AIN6P
AIN6N
NC
NC
AIN5P
AIN5N
NC
I
I
I
I
I
I
I
I
I
I
I
I
56
VCOM
O
57
IREF
O
58
59
60
61
62
63
64
NC
AIN4P
AIN4N
NC
NC
AIN3P
AIN3N
I
I
I
I
I
I
I
No connect pin. Connect to No.45 pin.
Analog Signal Input Pin
Analog Signal Input Pin
No connect pin. Connect to No.46 pin.
No connect pin. Connect to No.49 pin.
Analog Signal Input Pin
Analog Signal Input Pin
No connect pin. Connect to No.50 pin.
No connect pin. Connect to No.53 pin.
Analog Signal Input Pin
Analog Signal Input Pin
No connect pin. Connect to No.54 pin.
Internal Common Voltage Output Pin
This pin should be connected to VSS via a 1.0µF (±10%) ceramic capacitor.
Analog Reference Current Output Pin
This pin should be connected to VSS via a 6.8kΩ (±1%) resistor.
No connect pin. Connect to No.59 pin.
Analog Signal Input Pin
Analog Signal Input Pin
No connect pin. Connect to No.60 pin.
No connect pin. Connect to No.63 pin.
Analog Signal Input Pin
Analog Signal Input Pin
7. Absolute Maximum Ratings
Item
Min.
Max.
Unit
Supply Voltage
−0.3
4.4
V
Digital Input Pin Voltage
−0.3
4.4
V
Input/Output Pin Voltage
−0.3
VDD+0.3 (4.4)
V
Input Current (Iin)
−10
10
mA
Storage Temperature
−65
150
°C
Notes
CSN, CDTI, CCLK, RSTN pins
Except Power Supply Pin
- All voltages are with respect to ground at 0V (Reference Voltage).
- If digital output pins are connected to the data bus, the data bus operating voltage should be in the
same range as shown above Input/Output Pin Voltage.
- Operation at or beyond these limits may result in permanent damage to the device.
8. Recommended Operating Conditions
Item
Min.
Typ.
Max.
Unit
Supply Voltage (VDD)
3.135
3.300
3.465
V
125
°C
Operating Temperature Range (Ta)
40
- All voltages are with respect to ground at 0V (Reference Voltage).
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Notes
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[AK5806]
9. Electrical characteristics
9.1. DC Characteristics
(Ta: −40°C to 125°C / VDD: 3.135 to 3.465V)
Item
Pin
Min.
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Pull-up Current
CSN
CCLK
CDTI
Typ.
Max.
Unit
0.7xVDD
3.465
V
0
0.3xVDD
V
−10
µA
0V Input
−66
−33
Condition
Input Leak Current
−10
+10
µA
VDD Input
High Level Output Voltage (VOH)
VDD−0.5
VDD
V
IOH = −2mA
0
0.5
V
IOL = 2mA
Output Leak Current
−10
+10
µA
High Level Reset Input Voltage
0.7xVDD
3.465V
V
0
0.3xVDD
V
66
µA
VDD Input
+10
µA
0V Input
66
µA
Low Level Output Voltage (VOL)
Low Level Reset Input Voltage
CDTO
RSTN
Reset Input Current
10
Reset Input Leak Current
−10
TEST Pin Pull-down Current
TEST
33
10
33
9.2. AC Timing
Ta: −40°C to 125°C / VDD: 3.135 to 3.465V
9.2.1. Reset input
nRSTN
RSTN
0.3xVDD
Figure 3
Item
Symbol
Min.
Typ.
Max.
Reset Filter
nRSTN
10
100
Low input under 10µs will be rejected. A reset input does not synchronized with the CCLK.
Unit
µs
9.2.2. Power up Sequence
VDD
RSTN
RSTRL
VIH
REGSTRT
Resister
Access
Resister Access
Disable
Resister Access
Enable
Figure 4
Item
Symbol
Min.
RESET Release
RSTRL
100
µs
Register access start
REGSTRT
1
ms
016011439-E-00
Typ.
Max.
Unit
2016/09
-6-
[AK5806]
9.2.3. Serial Communication Interface Timing
Item
Symbol Min.
CCLK period
TSCLK
100
TCSC
16
from CSN to CCLK
TASC
16
from CCLK to CSN
Clock high time
TSDC
30
Clock low time
TSDC
30
CDTI data input setup time
TSUI
5
CDTI data input hold time
THI
11
CDTO data output delay time
TSUO
CDTO data output hold time
THO
6
CSN negate time
TNEG
2xTSCLK
TCCZ
from CSN to CDTO Hi-Z
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
24
21
Condition
VIH
TNEG
CSN
TSCLK
TCSC
TSDCH
VIL
TASC
TSDCL
VIH
CCLK
VIL
TSUI
CDTI
THI
R/W
CDTO
A3
VIH
Ch0
TSUO
Hi-Z
VIL
THO
D7
TCCZ
VOH
D0
VOL
: High or Low
Figure 5
9.3. Analog Characteristics
Conditions:
Fin= 500Hz to 5MHz, HPF-Fc (3dB degraded frequency) = 25 kHz or Bypass, PGA1= 24dB, PGA2=
18dB, Fine gain= +5.625dB, VDD= 3.135 to 3.465V, Ta = −40 to 125ºC, the external load capacitance
is less than 33pF, the external load resistance is more than 2kΩ via the external capacitor of AOUT pin,
unless otherwise specified. Analog characteristics may degrade during SPI communication.
9.3.1. Analog Input Signal
Item
Min.
Typ.
Differential Input Voltage
Amplitude
Input Leak Current
1
9.3.2. Analog Output Signal
Item
Min.
Maximum Output Voltage
2.0
Output Offset Voltage
100
THD (Distortion)
Typ.
0.15
Max.
Unit
Notes
4.0
Vpp
0dB gain
+1
µA
1MΩ or more,
Differential Input Voltage: under 1.0Vpp
Max.
Unit
Condition
Vpp
The amplitude should satisfy the THD value.
+100
mV
After offset calibration
0.8
%
Differential Input Voltage: 1.0Vpp
Differential Output Voltage: 2.0Vpp
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9.3.3. Input Referred Noise Density
(PGA1=24dB, PGA2=0dB, Fine gain=0dB)
Item
Min.
Input Referred Noise density
Typ.
Max.
150
146
150
146
150
142
150
145
9.3.4. Internal High Pass Filter
Item
Min.
Unit
Condition
dBm/Hz
Bypass mode
dBm/Hz
HPF mode (25kHz)
Typ.
Max.
Unit
Minimum Cutoff Frequency
25
kHz
Maximum Cutoff Frequency
1000
kHz
47
Cutoff Frequency Accuracy
+47
9.3.5. Coarse Gain Control
Item
Min.
Typ.
Max.
0dB setting
−2
0
+2
6dB setting
4
6
8
12dB setting
10
12
14
18dB setting
16
18
20
24dB setting
22
24
26
30dB setting
28
30
32
36dB setting
34
36
38
42dB setting
40
42
44
Unit
Condition
dB
Fine gain: 0dB
Min.
Typ.
Max.
Unit
Maximum gain
+5.225
+5.625
+6.025
dB
Minimum gain
−6.4
−6
−5.6
dB
Gain step
0.1
0.375
0.6
dB
9.3.7. Reference Voltage
Item
Min.
Typ.
Max.
Unit
Output Voltage (VCOM)
1.19
1.25
1.31
V
Min.
VCOM Pin Over Voltage Detection
100kHz
1MHz
Condition
Condition
Condition
Max.
Unit
1.35
1.55
V
VCOM Pin Low Voltage Detection
0.95
1.15
V
IREF Pin Over Current Detection
170
430
µA
IREF Pin Low Current Detection
50
130
µA
016011439-E-00
Typ.
1MHz
%
9.3.6. Fine Gain Control
Item
9.3.8. Detection Function
Item
100kHz
Condition
2016/09
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[AK5806]
9.3.9. Current Consumption
(PGA1=6dB, PGA2=0dB, Fine gain=0dB)
Item
Symbol
Normal Operation
IDD
Min.
Typ.
Max.
Unit
Condition
300
mA
HPF Mode
270
mA
Bypass Mode
Sleep Mode
SLIDD
30
mA
Channel Off Setting
COIDD
10
mA
During Reset
SIDD
100
µA
9.3.10. Channel to channel mismatch
Item
Gain
Mode
Min.
Typ.
Condition: HPF-Fc(3dB)=25kHz
Max.
Unit
Condition
Bypass Mode
1
HPF Mode
1
5MHz
2
1MHz
Bypass Mode
4
Phase
dB
8
deg.
2
Bypass Mode
5
9.3.11. Others
Item
Min.
In-band Ripple Mode
(Bypass Mode)
Channel Separation (Isolation)
Typ.
Max.
0.1
0.5
2.0
3.0
52
60
52
60
9
Unit
dB
dB
10
dB
10
dB
PSRR
5MHz
5MHz
1MHz
5MHz
Condition
500Hz to 500kHz
5MHz
500Hz
5MHz
PGA1=24dB,PGA2=18dB,
Fine gain=+5.625dB,100kHz
PGA1=24dB,PGA2=18dB,
Fine gain=+5.625dB, 500kHz
10. Functional Descriptions
10.1. Analog input
There are 8 channels for analog input signal and they support differential inputs. The path using
internal HPF filter and the path not using the internal HPF can be chosen externally.
1.0Vpp
AIN1P
Buffer
PGA1
AIN1N
Figure 6
AFEPD [8:1] bits control the ON/OFF of the signal processing for each channel. Input pins of unused
channel should be connected to VSS.
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10.2. Internal High Pass Filter
The AK5806 integrates 3rd-order high pass filter and the filter characteristics can be changed by
changing internal resistance. The HPF setting range is from 25 kHz to 1 MHz as attenuating the
output amplitude frequency for 3dB when the input frequency is 5 MHz. (HPFC [2:0] bits)
Figure 7
10.3. Coarse Gain Control
The AK5806 integrates two amplifiers that are capable of adjusting the gain in about 6dB steps for
each channel. (PGA1, PGA2)
AOUT1P
AIN1P
PGA1
AIN1N
HPF
&
Buffer
PGA2
&
Fine gain
Output buffer
AOUT1N
Offset
calibration
Figure 8
- PGA1: 0dB to 24dB (PGA1G[2:0] register)
- PGA2: 0dB to 18dB (PGA2G[1:0] register)
10.4. Fine Gain Control
The AK5806 integrates a gain amplifier that is capable of monotonic increase by about 0.375dB steps.
10.5. Reference Voltage
VCOM
IREF
1uF
Voltage
reference
6.8k
Figure 9
The AK5806 generates reference voltage for analog circuits from the internal band gap voltage.
10.6. Power Management
AK5806 has the two kind of power save mode as follows.
- Sleep Mode：PGA1, PGA2 and HPF are power downed.
- Signal Processing off Mode: PGA1, PGA2, HPF and Output buffer are power downed.
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[AK5806]
10.7. Offset Cancellation
The AK5806 has an offset cancellation circuit to correct the output offset voltage. Input path for
external signals will be OFF when the offset cancelling is started by register setting. Offset
cancellation value changes as the output offset will be in the range of ±100mV while internal offset
compensation value is kept by registers. Registers for offset cancellation are shown below.
- ENDOFCAL-bit: Offset Cancellation Operation Status Register
- EROF [8:1]-bit: Offset Cancellation Result Status Register; It shows whether the offset cancelling
result is in the correction range or not.
- OFCAL-bit: Offset Cancellation Start Setting Register
- OFCAL_E-bit: Offset Cancellation Function Enable Register; It shows whether the offset cancelling
result is included in the output signal or not.
Offset cancellation sequence is shown below.
μP
AK5806
OFCAL_E is set to [1]
ENDOFCAL=[0]
OFCAL is set to [1]
Analog signal path is OFF
Offset cancel start
Offset cancel finish
0.2ms to
～2ms
The result of cancel is
writed to EROF
ENDOFCAL=[1]
OFCAL is set to [0]
ENDOFCAL=[1]
Analog signal path is ON
Read EROF
EROF read
EROF=[0]
EROF result output
EORF inittialized
Finish
Figure 10
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[AK5806]
10.8. Serial Communication Interface (SPI)
VDD
VDD
VDD
CSN
VDD
CCLK
Serial interface
VDD
Serial interface
CDTI
CDTO
AK5806
MCU etc.
VSS
Figure 11
15
bit
14
13
R/W
12
11
Address[5:0]
10
9
8
7
6
5
4
D [7:0]
3
MSB
LSB
MSB
- R/W bit: ”[0]:Write”, “[1]:Read” - Address bit: Register address bit
- D bit: Register data bit
The D0 bit is assigned for parity check (EVEN Parity).
Example:
Parity Data = "0" when {Address [5:0], D [7:0]} = {00000000000000}
Parity Data = "1" when {Address [5:0], D [7:0]} = {10000000000000}
2
1
LSB
0
P
10.8.1. Write format
CSN
CCLK
A5
W MSB A4
CDTI
CDTO
A3 A2
A0 D7
D0
A1 LSB MSB D6 D5 D4 D3 D2 D1 LSB
P
Hi-Z
: High or Low
Figure 12
10.8.2. Read Format
CSN
CCLK
CDTI
CDTO
A5
R MSB A4
Hi-Z
A3 A2
A0
A1 LSB
D7
MSB
D0
D6 D5 D4 D3 D2 D1 LSB
P
: High or Low
Figure 13
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[AK5806]
11. Register
11.1. Register Map
Address
D7
D0
D6 D5
D4
D3
D2
D1
(MSB)
(LSB)
[5:0]
0x00
CPID[3:0]
VER[3:0]
0x01
Reserved
ERVCOM ERSPI
Reserved
ERIREF
0x02
Reserved
ENDOFCAL
0x03
EROF[8:1]
0x04
Reserved
0x05
Reserved
OFCAL_E
OFCAL
0x06
Reserved
SLP
0x07
AFEPD[8:1]
0x08
Reserved
PGA2G[1:0]
PGA1G[2:0]
0x09
Reserved
FG1C[4:0]
0x0A
Reserved
FG2C[4:0]
0x0B
Reserved
FG3C[4:0]
0x0C
Reserved
FG4C[4:0]
0x0D
Reserved
FG5C[4:0]
0x0E
Reserved
FG6C[4:0]
0x0F
Reserved
FG7C[4:0]
0x10
Reserved
FG8C[4:0]
0x11
Reserved
PE
HPF_E
HPFC[2:0]
0x12
Reserved
0x1F
Register write is not available on “Reserved” bits.
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Value
0x61
0x80
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x10
0x10
0x10
0x10
0x10
0x10
0x10
0x10
0x00
R/W
0x00
R/W
11.2. Register Definitions
Sub Address 0x00
D[7:0]
Name
[3:0]
VER[3:0]
[7:4]
CHIPID[3:0]
Definition
Chip Version ID
Chip Information ID
Notes
4’b0001 (Read only)
4’b0110 (Read only)
Sub Address 0x01
D[7:0] Name
Definition
Notes
IREF pin Abnormal Current Monitoring Register
[0]
ERIREF
(Read only)
0: Normal Status, 1: IREF pin Over Current Status*
[2:1]
Reserved Reserved
SPI communication Error Monitoring Register
[3]
ERSPI
(Clock Count result or parity check result when CSN input mode)
(Read only)
0: No SPI Communication Error, 1: SPI Communication Error
VCOM pin Abnormal Voltage Monitoring Register
[4]
ERVCOM
(Read only)
0: Normal Status, 1: Abnormal Voltage Status*
[7:5]
Reserved Reserved
*All blocks except SPI communication block are powered down. Their states are cleared by the RSTN
pin.
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[AK5806]
Sub Address 0x02
D[7:0]
Name
[0]
ENDOFCAL
[7:1]
Reserved
Sub Address 0x03
D[7:0]
Name
[7:0]
Definition
Offset Cancellation Result Status Register
0: No error (Default) , 1: Error
EROF[8:1]
Sub Address 0x04
D[7:0]
[7:0]
Name
Reserved
Sub Address 0x05
D[7:0] Name
[0]
OFCAL
[1]
OFCAL_E
[7:2]
Reserved
Sub Address 0x06
D[7:0]
Name
[0]
SLP
[7:1]
Reserved
Definition
Offset Cancellation Operation Status Register
0: During Calibration , 1: Calibration Finished
Reserved
Sub Address 0x07
D[7:0]
Name
[0]
AFEPD 1
[1]
AFEPD 2
[2]
AFEPD 3
[3]
AFEPD 4
[4]
AFEPD 5
[5]
AFEPD 6
[6]
AFEPD 7
[7]
AFEPD 8
Definition
Reserved
Definition
Offset Cancellation Start
Setting Register
0: Cancellation Stop
1: Cancellation Start
Offset Cancellation Function
Enable Register
0: Cancellation Disable
1: Cancellation Enable
Reserved
(Read only)
Notes
EROF1: Channel: 1
~
EROF8:Channel 8
(Read only)
Notes
Notes
Offset cancellation function is disabled
when OFCAL_E-bit= “0”.
Definition
Sleep Mode Setting Register (All Channels)
0: Normal Operation
1: Sleep Mode
Reserved
Definition
Signal Process Circuit Stop Register
0: Circuit is in operation (Default)
1: Circuit is stopped
016011439-E-00
Notes
Notes
Notes
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
2016/09
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[AK5806]
Sub Address 0x08
D[7:0]
Name
[2:0]
PGA1G[2:0]
[4:3]
PGA2G[1:0]
[7:5]
Reserved
Definition
PGA1 gain (All channels)
000: 0dB (Default), 001: 6dB
010: 12dB, 011: 18dB, 1XX: 24dB
PGA2 gain (All channels)
00: 0dB (Default), 01: 6dB
10: 12dB, 11: 18dB
Reserved
Sub Address 0x09 – Sub Address 0x10
D[7:0] Name
FG1C [4:0] (Sub address 0x09, channel 1)
FG2C [4:0] (Sub address 0x0A, channel 2)
FG3C [4:0] (Sub address 0x0B, channel 3)
FG4C [4:0] (Sub address 0x0C, channel 4)
[4:0]
FG5C [4:0] (Sub address 0x0D, channel 5)
FG6C [4:0] (Sub address 0x0E, channel 6)
FG7C [4:0] (Sub address 0x0F, channel 7)
FG8C [4:0] (Sub address 0x10, channel 8)
[7:5]
Reserved
Sub Address 0x11
D[7:0] Name
[2:0]
HPFC [2:0]
[3]
HPF_E
[4]
PE
Definition
HPF Characteristics Control
(All Channels)
000:25kHz, 001:42kHz
010:72kHz, 011:121kHz
100:250kHz, 101:349kHz
110:590kHz, 111:1000kHz
Internal HPF Enable HPF
(All Channels)
0: Bypass Mode (Default)
1: HPF Mode
Parity Bit Detection
Setting
0: Detection Disable (Default)
1: Detection Enable
Definition
Fine Gain Control
00000: −6dB
|
10000: 0dB (Default)
|
11111: +5.625dB
Notes
Notes
(Typical: 0.375dB/LSB)
Reserved
Notes
(Detection Disable)
Register Write: Ignore Parity Bit
Register Read: Add Parity Bit
(Detection Enable):
Register Write: Execute Parity Bit Error
Detection*
Register Read: Add Parity Bit
*When a parity error is detected, register
writing is ignored and the error status is
shown in ERSPI bit.
[7:5]
Reserved
Reserved
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[AK5806]
12. Example of External Connection Diagram
NC
22uF
6.8k
6.8k
22uF
Pin.6
AIN1P
HPF
&
Buffer
Pin.7
PGA1
Pin.8
PGA2
&
Fine gain
Pin.14
AOUT1P
Pin.13
AOUT1N
Output buffer
AIN1N
NC
Pin.9
1uF
Offset
calibration
NC
AOUTnP
AINnP
Ch.2 to Ch.8
AINnN
AOUTnN
NC
VCOM
IREF
1uF
Voltage
reference
Diagnostic
function
Reset control
SPI control
CSN
CCLK
CDTI
CDTO
MCU
RSTN
1uF
6.8k
VDD
VSS
0.1uF
VDD
VSS
VDD
0.1uF
VSS
0.1uF
VDD
VSS
0.1uF
Figure 14
13. Package
13.1. Outline Dimensions
64pin-HTQFP package, Pin pitch: 0.5mm
Figure 15
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[AK5806]
13.2. Foot Pattern
This figure is an example. It should be designed to be appropriate design for each PCB board.
Figure 16
13.3. Marking
AKM
AK5806
XXXXXXX
1
Figure 17
Logo: AKM
Marketing code: AK5806
Date code: XXXXXXX
14. Ordering Guide
AK5806
−40ºC to 125 ºC
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[AK5806]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application of
AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM
or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to
any intellectual property rights or any other rights of AKM or any third party with respect to the
information in this document. You are fully responsible for use of such information contained in this
document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY
LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH
INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including
but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices,
elevators and escalators, devices related to electric power, and equipment used in finance-related
fields. Do not use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible
for complying with safety standards and for providing adequate designs and safeguards for your
hardware, software and systems which minimize risk and avoid situations in which a malfunction or
failure of the Product could cause loss of human life, bodily injury or damage to property, including
data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and
regulations. The Products and related technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable domestic
or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth
in this document shall immediately void any warranty granted by AKM for the Product and shall not
create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
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