CS5461
Single Phase Bi-Directional Power/Energy IC
Features
Description
z Energy
The CS5461 is an integrated power measurement device which combines two ∆Σ ADCs, high
speed power calculation functions, and a serial
interface on a single chip. It is designed to accurately measure Instantaneous Current and
Voltage, and calculate: Instantaneous Power,
Average Power, IRMS, and VRMS, for single-phase 2- or 3-wire power metering
applications. The CS5461 can interface to a
low-cost shunt resistor or transformer for current
measurement, and to a resistive divider or potential transformer for voltage measurement. The
CS5461 features a bi-directional serial interface
for communication with a micro-controller and a
programmable energy-to-pulse output function.
CS5461 has on-chip functionality to facilitate AC
or DC system-level calibration. Additional features include on-chip temperature sensor,
voltage sag detection, and phase compensation.
Data Linearity: ±0.1% of Reading
over 1000:1 Dynamic Range
z On-Chip Functions: Energy, I ∗ V,
IRMS and VRMS, Energy-to-Pulse Conversion
z AC/DC System Calibrations
z Meets Accuracy Spec for IEC 687/1036, JIS
z Power Consumption <12 mW
z On-Chip Temperature Sensor
z Voltage Sag Detect
z Adjustable Input Range on Current Channel
z Phase Compensation
z GND-Referenced Signals with Single Supply
z On-chip 2.5 V Reference (25 ppm/°C typ)
z Simple Three-Wire Digital Serial Interface
z Power Supply Monitor
z Interface Optimized for Shunt Sensor
z Mechanical Counter/Stepper Motor Drive
z Smart “Auto-Boot” Mode from Serial
EEPROM with no microcontroller.
z Power Supply Configurations
ORDERING INFORMATION:
CS5461-IS
-40°C to +85°C
VA+ = +5 V; VA- = 0 V; VD+ = +3.3 V to +5 V
VA+
24-pin SSOP
VD+
RESET
High Pass
Filter
IIN+
IIN-
PGA
x10,x50
4th Order ∆Σ
Modulator
Digital
Filter
MODE
CS
VIN+
VIN-
x10
SDI
Power
Calculation
Engine
2nd Order ∆Σ
Modulator
Serial
Interface
INT
Digital
Filter
VREFIN
VREFOUT
x1
Temperature
Sensor
Voltage
Reference
Power
Monitor
VA-
http://www.cirrus.com
PFMON
E-to-F
High Pass
Filter
System
Clock
SDO
SCLK
Clock
Generator
/K
XIN
EOUT
EDIR
FOUT
Calibration
XOUT CPUCLK
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
DGND
Aug 04
DS546F2
1
CS5461
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ....................................................................................................... 5
2. PIN DESCRIPTION ................................................................................................................... 6
3. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 8
ANALOG CHARACTERISTICS ................................................................................................ 8
VOLTAGE REFERENCE........................................................................................................ 10
5 V DIGITAL CHARACTERISTICS......................................................................................... 11
3 V DIGITAL CHARACTERISTICS......................................................................................... 11
SWITCHING CHARACTERISTICS ........................................................................................ 13
3.1 Theory of Operation ......................................................................................................... 13
3.1.1 High-Rate Digital Low-Pass Filters ..................................................................... 15
3.1.2 Digital Compensation Filters ............................................................................... 15
3.1.3 Digital High-Pass Filters ...................................................................................... 15
3.1.4 Gain and DC Offset Adjustment .......................................................................... 15
3.1.5 Average (Real) Power Computation ................................................................... 15
3.1.6 RMS Computations ............................................................................................. 16
3.2 Performing Measurements ............................................................................................... 16
3.3 CS5461 Linearity Performance ........................................................................................ 16
4. FUNCTIONAL DESCRIPTION ............................................................................................... 17
4.1 Analog Inputs ................................................................................................................... 17
4.2 Voltage Reference ........................................................................................................... 17
4.3 Oscillator Characteristics ................................................................................................. 17
4.4 Calibration ........................................................................................................................ 18
4.4.1 Overview of Calibration Process ......................................................................... 18
4.4.2 Calibration Sequence .......................................................................................... 18
4.4.3 Calibration Signal Input Level ............................................................................. 18
4.4.4 Calibration Signal Frequency .............................................................................. 18
4.4.5 Input Configurations for Calibrations ................................................................... 18
4.4.6 Description of Calibration Algorithms .................................................................. 19
4.4.6.1 AC Offset Calibration Sequence ......................................................... 19
4.4.6.2 DC Offset Calibration Sequence ......................................................... 19
4.4.6.3 AC Gain Calibration Sequence ........................................................... 19
4.4.6.4 DC Gain Calibration Sequence ........................................................... 20
4.4.7 Duration of Calibration Sequence ....................................................................... 20
4.4.8 Order of Calibration Sequences .......................................................................... 21
4.5 Power Offset .................................................................................................................... 21
4.6 Phase Compensation ....................................................................................................... 21
4.7 Time-Base Calibration ..................................................................................................... 22
4.8 On-Chip Temperature Sensor .......................................................................................... 22
4.9 Interrupt ........................................................................................................................... 22
4.9.1 Typical use of the INT pin ................................................................................... 22
4.9.2 INT Active State .................................................................................................. 23
4.10 Voltage Sag-Detect Feature .......................................................................................... 23
5. ENERGY PULSE OUTPUTS .................................................................................................. 24
5.1 Pulse-Rate Output (EOUT and EDIR) ............................................................................. 24
5.2 Pulse Output for Normal Format, Stepper Motor Format and Mechanical
Counter Format ............................................................................................................ 24
5.2.1 Normal Format .................................................................................................... 24
5.2.2 Mechanical Counter Format ................................................................................ 25
5.2.3 Stepper Motor Format ......................................................................................... 25
5.3 FOUT Pulse Output ......................................................................................................... 25
5.4 Anti-Creep for the Pulse Outputs ..................................................................................... 26
5.5 Design Examples ............................................................................................................. 26
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DS546F2
CS5461
5.6 Auto-Boot Mode Using EEPROM .................................................................................... 27
5.6.1 Auto-Boot Configuration ...................................................................................... 27
5.6.2 Auto-Boot Data for EEPROM .............................................................................. 28
5.6.3 Which EEPROMs Can Be Used? ....................................................................... 28
6. SERIAL PORT OVERVIEW .................................................................................................... 29
6.1 Commands ...................................................................................................................... 29
6.2 Serial Port Interface ......................................................................................................... 32
6.3 Serial Read and Write ..................................................................................................... 32
6.4 System Initialization ......................................................................................................... 32
6.5 Serial Port Initialization .................................................................................................... 32
6.6 CS5461 Power States ..................................................................................................... 33
7. REGISTER DESCRIPTION .................................................................................................... 34
7.1 Configuration Register ...................................................................................................... 34
7.2 DC Current Offset Register and DC Voltage Offset Register ........................................... 35
7.3 AC/DC Current Gain Register and AC/DC Voltage Gain Register ................................... 35
7.4 Cycle Count Register........................................................................................................ 35
7.5 PulseRateE Register ........................................................................................................ 36
7.6 I, V, P, & PAvg: Instantaneous Current, Voltage, Power, and Average Power (Signed)
Output Register............................................................................................................. 36
7.7 IRMS, VRMS Unsigned Output Register .......................................................................... 36
7.8 Timebase Calibration Register ......................................................................................... 36
7.9 Power Offset Register ...................................................................................................... 37
7.10 Status Register and Mask Register ................................................................................ 37
7.11 AC Current Offset Register and AC Voltage Offset Register ......................................... 38
7.12 PulseRateF Register ...................................................................................................... 39
7.13 Temperature Sensor Output Register ............................................................................ 39
7.14 Pulsewidth ...................................................................................................................... 39
7.15 VSAGLevel: Voltage Sag-Detect Threshold Level ........................................................ 39
7.16 VSAGDuration: Voltage Sag-Detect Duration Level...................................................... 40
7.17 Control Register.............................................................................................................. 40
8. BASIC APPLICATION CIRCUITS .......................................................................................... 41
9. PACKAGE DIMENSIONS ...................................................................................................... 44
10. REVISIONS .......................................................................................................................... 45
DS546F2
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CS5461
LIST OF FIGURES
Figure 1. CS5461 Read and Write Timing Diagrams .................................................................... 13
Figure 2. Data Flow. ...................................................................................................................... 14
Figure 3. Oscillator Connection ..................................................................................................... 17
Figure 4. System Calibration of Gain. ........................................................................................... 18
Figure 5. System Calibration of Offset. ......................................................................................... 18
Figure 6. Calibration Data Flow..................................................................................................... 19
Figure 7. Example of AC Gain Calibration .................................................................................... 20
Figure 8. Another Example of AC Gain Calibration....................................................................... 20
Figure 9. Example of DC Gain Calibration .................................................................................... 20
Figure 10. Time-plot representation of pulse output for a typical burst of pulses (Normal Format)24
Figure 11. Mechanical Counter Format on EOUT and EDIR ........................................................ 25
Figure 12. Stepper Motor Format on EOUT and EDIR ................................................................. 25
Figure 13. Typical Interface of EEPROM to CS5461 .................................................................... 27
Figure 14. Typical Connection Diagram (One-Phase 2-Wire, Direct Connect to Power Line) ...... 41
Figure 15. Typical Connection Diagram (One-Phase 2-Wire, Isolated from Power Line) ............. 42
Figure 16. Typical Connection Diagram (One-Phase 3-Wire)....................................................... 42
Figure 17. Typical Connection Diagram (One-Phase 3-Wire - No Neutral Available)................... 43
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DS546F2
CS5461
1. GENERAL DESCRIPTION
The CS5461 is a CMOS monolithic power measurement device with a real power/energy computation engine. The CS5461 combines two programmable gain amplifiers, two ∆Σ modulators, two high-rate filters,
system calibration, and calculation functions. The device provides instantaneous voltage and current data
samples and calculates average (real) power, VRMS, IRMS, and instantaneous power data samples.
The CS5461 functionality is optimized for power measurement applications and is optimized to interface
to a shunt or current transformer for current measurement, and to a resistive divider or potential transformer for voltage measurement. To accommodate various input voltage levels from a multitude of current sensors, the CS5461’s current channel has a front-end-programmable gain amplifier (PGA), which allows for
two available full-scale differential input signal ranges on the current channel: 100 mVP-P and 500 mVP-P,
while the voltage channel has a set input range of 500 mVP-P. With single +5 V (common-mode) supply
across VA+/VA-, both of the CS5461’s input channels can accommodate (common-mode + signal) levels
between -0.25 V and VA+. This allows for a completely bipolar differential input configuration. The common-mode voltage level of the differential input signals can be anywhere between the supply voltage levels
on the VA+/VA- pins, as long as enough voltage margin is left over so that the addition of the differential
signals will not cause the total swing to go below -0.25 V or above +5 V.
The CS5461 includes two high-rate digital filters, which decimate the output from the two ∆Σ modulators.
These filters integrate the output of the ∆Σ modulators for both channels to yield instantaneous voltage and
current waveform output data at a (MCLK/K)/1024 output word rate (OWR).
To facilitate communication to a microcontroller, the CS5461 includes a simple three-wire serial interface
which is SPI™ and Microwire™ compatible.
DS546F2
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CS5461
2. PIN DESCRIPTION
Crystal Out
CPU Clock Output
Positive Power Supply
Digital Ground
Serial Clock
Serial Data Ouput
Chip Select
Mode Select
Differential Voltage Input
Differential Voltage Input
Voltage Reference Output
Voltage Reference Input
XOUT
CPUCLK
VD+
DGND
SCLK
SDO
CS
MODE
VIN+
VINVREFOUT
VREFIN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
XIN
SDI
EDIR
EOUT
INT
RESET
FOUT
PFMON
IIN+
IINVA+
VA-
Crystal In
Serial Data Input
Energy Direction Indicator
Energy Output
Interrupt
Reset
High Frequency Output
Power Fail Monitor
Differential Current Input
Differential Current Input
Positive Analog Supply
Analog Ground
Clock Generator
Crystal Out
Crystal In
CPU Clock Output
1,24
2
XOUT, XIN - A gate inside the chip is connected to these pins and can be used with a
crystal to provide the system clock for the device. Alternatively, an external (CMOS
compatible) clock can be supplied into XIN pin to provide the system clock for the device.
CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
Control Pins and Serial Data I/O
Serial Clock Input
5
SCLK - A clock signal on this pin determines the input and output rate of the data for the
SDI and SDO pins respectively. This is a Schmitt Trigger input to allow for slow rise time
signals. The SCLK pin will recognize clocks only when CS is low.
Serial Data Output
6
SDO -The serial data port output pin. Its output is in a high impedance state when CS is
high.
Chip Select
7
CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO
pin to a high impedance state.
Mode Select
8
MODE - When at logic high, the CS5461 will operate in auto-boot mode. For normal
operation this pin must be left unconnected.
High-Frequency
Energy Output
18
FOUT - Issues active-low pulses, such that the number of pulses is proportional to the
measured real energy. The energy-to-pulse ratio is programmed in the PulseRateF Register.
Reset
19
RESET - When reset is taken low, all internal registers are set to their default states.
Interrupt
20
INT - When INT goes low it signals that an enabled event has occurred.
Energy Output
21
EOUT - Issues fixed-width pulses, such that the number of pulses is proportional to the
real energy registration of the device. The energy-to-pulse ratio is programmed in the
PulseRateE Register.
Energy Direction
Indicator
22
Serial Data Input
23
6
EDIR - Indicates if the measured energy is negative.
SDI - The serial data port input pin. Data will be input at a rate determined by SCLK.
DS546F2
CS5461
Measurement and Reference Input
Differential
Voltage Inputs
9,10
VIN+, VIN- - Differential analog input pins for the voltage channel.
Differential
Current Inputs
15,16
IIN+, IIN- - Differential analog input pins for the current channel.
Voltage
Reference Output
11
VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal
magnitude of 2.5 V and is referenced to the VA- pin on the converter.
Voltage
Reference Input
12
VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.
Positive
Digital Supply
3
VD+ - The positive digital supply relative to DGND.
Digital Ground
4
DGND - The common-mode potential of digital ground must be equal to or above the
common-mode potential of VA-.
Positive
Analog Supply
14
VA+ - The positive analog supply relative to VA-.
Analog Ground
13
VA- - The analog ground pin must be at the lowest potential.
Power Fail Monitor
17
PFMON - The power fail Monitor pin monitors the analog supply. Typical threshold level
(PMLO) is 2.45 V with respect to the VA- pin. If PFMON voltage threshold is tripped, the
LSD (low-supply detect) bit is set in the Status Register. Once the LSD bit has been set, it
cannot be reset until the PFMON voltage increases ~100 mV (typical) above the PMLO
voltage.
Power Supply Connections
DS546F2
7
CS5461
3. CHARACTERISTICS/SPECIFICATIONS
•
Min / Max characteristics and specifications are guaranteed over all Operating Conditions.
•
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C.
•
DGND = 0 V. All voltages with respect to 0 V.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Positive Digital Power Supply
VD
3.135
3.3
5.25
V
Positive Analog Power Supply
VA+
4.75
5
5.25
V
Negative Analog Power Supply
VA-
-0.25
0
0.25
V
VREF
-
2.5
-
V
TA
-40
-
+85
°C
Voltage Reference
Specified Temperature Range
ANALOG CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
CMRR
80
-
-
dB
-
5
-
nV/°C
0
0
-
500
100
mVP-P
mVP-P
Accuracy (Both Channels)
Common Mode Rejection
(DC, 50, 60 Hz)
Offset Drift (Without the High Pass Filter)
Analog Inputs (Current Channel)
Differential Input Voltage Range
{(IIN+) - (IIN-)}
(Gain = 10)
(Gain = 50)
Total Harmonic Distortion
Common Mode + Signal
IIN
THD
All Gain Ranges
80
-
-
dB
-0.25
-
VA+
V
-
-
-115
dB
Crosstalk with Voltage Channel at Full Scale
(50, 60 Hz)
Input Capacitance
(Gain = 10)
(Gain = 50)
IC
-
25
25
-
pF
pF
Effective Input Impedance
(Note 2)
(Gain = 10)
(Gain = 50)
EII
30
30
-
-
kΩ
kΩ
Noise (Referred to Input)
(Gain = 10)
(Gain = 50)
NI
-
-
22.5
4.5
µVrms
µVrms
Accuracy (Current Channel)
Bipolar Offset Error
(Note 1)
VOS
-
-
±0.001
%F.S.
Full-Scale Error
(Note 1)
FSE
-
-
±0.001
%F.S.
Notes: 1. Applies after system calibration
2. Effective Input Impedance (EII) is determined by clock frequency (DCLK) and Input Capacitance (IC).
EII = 1/(IC*DCLK/4). Note that DCLK = MCLK / K.
8
DS546F2
CS5461
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
VIN
0
-
500
mVP-P
THD
65
-
-
dB
-0.25
-
VA+
V
Analog Inputs (Voltage Channel)
Differential Input Voltage Range
{(VIN+) - (VIN-)}
Total Harmonic Distortion
Common Mode + Signal
All Gain Ranges
Crosstalk with Current Channel at Full Scale (50, 60 Hz)
Input Capacitance
Effective Input Impedance
-
-
-70
dB
All Gain Ranges
IC
-
0.2
-
pF
(Note 2)
EII
5
-
-
MΩ
NV
-
-
150
µVrms
Noise (Referred to Input)
Accuracy (Voltage Channel)
Bipolar Offset Error
(Note 1)
VOS
-
-
±0.01
%F.S.
Full-Scale Error
(Note 1)
FSE
-
-
±0.01
%F.S.
-2.8
-
+2.8
°
OWR
-
DCLK/1024
-
Hz
-
DCLK/8
-
Hz
FSCR
25
-
100
%F.S.
Dynamic Characteristics
Phase Compensation Range
(Voltage Channel, 60 Hz)
High Rate Filter Output Word Rate
Input Sampling Rate
(Both Channels)
DCLK = MCLK/K
Full Scale DC Calibration Range
(Note 3)
Channel-to-Channel Time-Shift Error
(when PC[6:0] bits are set to “0000000”)
High Pass Filter Pole Frequency
1.0
-3 dB
-
0.5
µs
-
Hz
Notes: 3. The minimum FSCR is limited by the maximum allowed gain register value.
DS546F2
9
CS5461
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
PSCA
PSCD
PSCD
-
1.3
2.9
1.7
-
mA
mA
mA
PC
-
21
11.6
6.75
10
30
-
mW
mW
mW
µW
Power Supplies
Power Supply Currents (Active State)
Power Consumption
(Note 5)
IA+
ID+ (VD+ = 5 V)
ID+ (VD+ = 3.3 V)
Active State (VD+ = 5 V)
Active State (VD+ = 3.3 V)
Stand-By State
Sleep State
Power Supply Rejection Ratio (Note 6)
Current Channel (50, 60 Hz)
(Gain = 10)
(Gain = 50)
PSRR
PSRR
56
70
-
-
dB
dB
Power Supply Rejection Ratio (Note 6)
Voltage Channel (50, 60 Hz)
(Gain = 10)
PSRR
-
55
-
dB
PFMON Low-Voltage Trigger Threshold
(Note 7)
PMLO
2.3
2.45
-
V
PFMON High-Voltage Power-On Trip Point
(Note 8)
PMHI
-
2.55
2.7
V
Notes: 4. The minimum FSCR is limited by the maximum allowed gain register value.
5. All outputs unloaded. All inputs CMOS level.
6. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply
voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. Then the CS5461 is commanded to continuous
conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output
signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be
applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):
⎧ 150 ⎫
PSRR = 20 ⋅ log ⎨ --------- ⎬
⎩ V eq ⎭
7. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.
8. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on
PFMON at which the LSD bit can be permanently reset back to 0.
VOLTAGE REFERENCE
Parameter
Symbol
Min
Typ
Max
Unit
REFOUT
2.4
-
2.6
V
(Note 9)
TC
-
25
60
ppm/°C
(Output Current 1 µA Source or Sink)
∆VR
-
6
10
mV
VREFIN
2.4
2.5
2.6
V
Input Capacitance
-
4
-
pF
Input CVF Current
-
25
-
nA
Reference Output
Output Voltage
Temperature Coefficient
Load Regulation
Reference Input
Input Voltage Range
Notes: 9. The voltage at VREFOUT is measured across the temperature range. From these measurements the
following formula is used to calculate the VREFOUT Temperature Coefficient:.
AVG
MIN)
(
MAX
(T
AMAX
1
- TAMIN
(
10
- VREFOUT
( (VREFOUT
VREFOUT
( 1.0 x 10
6
(
TCVREF =
DS546F2
CS5461
5 V DIGITAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
High-Level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIH
0.6 VD+
(VD+) - 0.5
0.8 VD+
-
-
V
V
V
Low-Level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIL
-
-
0.8
1.5
0.2 VD+
V
V
V
High-Level Output Voltage
Iout = +5 mA
VOH
(VD+) - 1.0
-
-
V
Low-Level Output Voltage
Iout = -5 mA
VOL
-
-
0.4
V
Input Leakage Current
Iin
-
±1
±10
µA
3-State Leakage Current
IOZ
-
-
±10
µA
Digital Output Pin Capacitance
Cout
-
5
-
pF
Parameter
Symbol
Min
Typ
Max
Unit
High-Level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIH
0.6 VD+
(VD+) - 0.5
0.8 VD+
-
-
V
V
V
Low-Level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIL
-
-
0.48
0.3
0.2 VD+
V
V
V
High-Level Output Voltage
Iout = +5 mA
VOH
(VD+) - 1.0
-
-
V
Low-Level Output Voltage
Iout = -5 mA
VOL
-
-
0.4
V
Input Leakage Current
Iin
-
±1
±10
µA
3-State Leakage Current
IOZ
-
-
±10
µA
Digital Output Pin Capacitance
Cout
-
5
-
pF
3 V DIGITAL CHARACTERISTICS
DS546F2
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CS5461
SWITCHING CHARACTERISTICS
50
50
Max
20
60
60
1.0
100
1.0
100
-
Unit
MHz
%
%
µs
µs
ns
µs
µs
ns
-
60
-
ms
SCLK
t1
t2
200
200
-
2
-
MHz
ns
ns
SDI Timing
CS Falling to SCLK Rising
t3
50
-
-
ns
Data Set-up Time Prior to SCLK Rising
t4
50
-
-
ns
Data Hold Time After SCLK Rising
t5
100
-
-
ns
SDO Timing
CS Falling to SDI Driving
t7
-
20
50
ns
SCLK Falling to New Data Bit (hold time)
t8
-
20
50
ns
CS Rising to SDO Hi-Z
t9
-
20
50
ns
Master Clock Frequency
Master Clock Duty Cycle
CPUCLK Duty Cycle
Rise Times
(Note 12)
Parameter
Internal Gate Oscillator (Note 10)
Fall Times
(Note 12)
Start-up
Oscillator Start-Up Time
(Note 11)
Any Digital Input Except SCLK
SCLK
Any Digital Output
Any Digital Input Except SCLK
SCLK
Any Digital Output
XTAL = 4.096 MHz (Note 13)
Serial Port Timing
Serial Clock Frequency
Serial Clock
Auto-Boot Timing
Serial Clock
Pulse Width High
Pulse Width Low
Pulse Width High
Pulse Width Low
Symbol
MCLK
Min
2.5
40
40
-
Typ
4.096
-
tost
trise
tfall
8
8
t10
t11
MCLK
MCLK
MODE setup time to RESET Rising
t12
50
ns
RESET rising to CS falling
t13
48
MCLK
CS falling to SCLK rising
t14
100
SCLK falling to CS rising
t15
CS rising to driving MODE low (to end auto-boot sequence).
t16
50
ns
SDO guaranteed setup time to SCLK rising
t17
100
ns
8
MCLK
16
MCLK
Notes: 10. Device parameters are specified with a 4.096 MHz clock. If a crystal is used, then XIN frequency must
remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used, full XIN frequency range is
2.5 MHz - 20 MHz.
11. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec.
12. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
13. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
3.1 Theory of Operation
12
A computational flow diagram for the two data
paths is shown in Fig. 2. The analog waveforms at
DS546F2
CS5461
t3
CS
t1
t2
t6
SC LK
C o m m a n d T im e 8 S C L K s
H ig h B y te
LSB
MSB
MSB-1
LSB
MSB-1
LSB
MSB
t5
MSB-1
LSB
MSB
MSB
SDI
MSB-1
t4
M id B y te
L o w B y te
SDI Write Timing (Not to Scale)
CS
t1
t9
LSB
MSB-1
LSB
MSB
L o w B y te
MSB-1
LSB
MSB-1
MSB
SDO
M id B y te
MSB
H ig h B y te
t7
t8
t2
LSB
MSB
SDI
MSB-1
SC LK
C o m m a n d T im e 8 S C L K s
SYNC0 Com m and
SYNC0 Com m and
SYNC0 Com m and
SDO Read Timing (Not to Scale)
t12
t16
MODE
(IN P U T )
RESET
(IN P U T )
CS
t15
t13
t8
t14
(O U T P U T )
SCLK
(O U T P U T )
t11
t17
t10
t4
SDO
t5
STOP bit
(O U T P U T )
SDI
(IN P U T )
Last 8
B it s
D a ta fro m E E P R O M
Auto-Boot Sequence Timing (Not to Scale)
Figure 1. CS5461 Read and Write Timing Diagrams
DS546F2
13
CS5461
V DCoff* V gn *
VOLTAGE
PGA
∆Σ
DELAY
REG
SINC 3
DELAY
REG
4th-order
IIR
HPF
+
V*
V ACoff*
+
Σ
x
+
x
-
Σ
Σ
N
N
V RMS *
÷N
PulseRateF *
Poff *
Configuration Register *
PC[ 6:0] Bits
x
+
Σ
Σ
N
x
P*
x
PGA
∆Σ
SINC 3
4th-order
IIR
HPF
+
Σ
x
x
I DCoff* I gn *
+
Energy to - Pulse
I*
Σ
E out
E dir
N
Σ
-
+
PAvg*
÷N
PulseRateE*
CURRENT
Fout
Energy to - Pulse
x
TBC *
N
÷N
I RMS *
I ACoff*
* DENOTES REGISTER NAME
Figure 2. Data Flow.
the voltage/current channel inputs are subject to the
gains of the input PGAs. These waveforms are then
sampled by the delta-sigma modulators at a rate of
(MCLK/K) / 8.
3.1.1 High-Rate Digital Low-Pass Filters
The data is then low-pass filtered, to remove
high-frequency noise from the modulator output.
Referring to Figure 2, the high rate filters on both
channels are implemented as fixed Sinc3 filters.
Also note from Figure 2 that the digital data on the
voltage channel is subjected to a variable time-delay filter. The delay depends on the value of the
seven phase compensation bits (see Phase Compensation) set in the configuration register.
3.1.2 Digital Compensation Filters
The data from both channels is then passed through
two 4th-order IIR “compensation” filters, whose
purpose is to correct (compensate) for the magnitude roll-off of the low-pass filtering operation.
These filters “re-flatten” the magnitude response of
the I and V channels over the relevant frequency
range, by correcting for the magnitude roll-off effects that are induced onto the I and V signal spectrums by the Sinc3 low-pass filter stages.
14
3.1.3 Digital High-Pass Filters
Both channels provide an optional high-pass filter
(“HPF” in Figure 2) which can be engaged into the
signal path, in order to remove the DC content from
the current/voltage signal before the RMS/energy
calculations are made. These filters are activated by
enabling certain bits in the Configuration Register.
3.1.4 Gain and DC Offset Adjustment
After the filtering, the instantaneous voltage and
current digital codes are both subjected to value adjustments, based on the values in the DC Offset
Registers (additive) and the Gain Registers (multiplicative). These registers are used for calibration
of the device (see Section 4.4, Calibration). After
offset and gain, the data is available to the user by
reading the Instantaneous Voltage and Current
Registers.
3.1.5 Average (Real) Power Computation
The digital instantaneous voltage and current data
is then processed further. Referring to Figure 2, the
instantaneous voltage/current data samples are
multiplied together (one multiplication for each
pair of voltage/current samples) to form instantaneous power data. The instantaneous power data is
then averaged over N instantaneous conversions
(N = value in Cycle Count Register) to form the result in the Average Power Register. The average
DS546F2
CS5461
power can be multiplied by the time duration of the
computation cycle, to generate a value for the accumulated real energy over the last computation cycle.
3.1.6 RMS Computations
RMS calculations are performed on the instantaneous voltage/current data and can be read from the
RMS Voltage Register and the RMS Current Register. The results are computed once every computation cycle. Using N instantaneous current
samples (In), the RMS computations for the current
(and likewise for voltage, using Vn) is performed
using the formula:
N -1
RMS =
Σ
In
n=0
N
3.2 Performing Measurements
The CS5461 performs measurements of instantaneous voltage, instantaneous current, instantaneous
power at an output word rate (sampling rate) of
(MCLK/K) / 1024. From these instantaneous samples, average (real) power, IRMS, and VRMS are
computed, using the most recent N instantaneous
samples that were acquired. All of the measurements/results are available as a percentage of full
scale. The signed output format is a two’s complement format, and the output data words represent a
normalized value between -1 and +1. The unsigned data in the CS5461 output registers represent normalized values between 0 and 1. A register
value of 1 represents the maximum possible value.
Note that a value of 1.0 is never actually obtained,
the true maximum register value is [(2^23 - 1) /
(2^23)] = 0.999999880791.
After each A/D conversion, the CRDY bit will be
asserted in the Status Register, and the INT pin will
also become active if the CRDY bit is unmasked
(in the Mask Register). The assertion of the CRDY
DS546F2
bit indicates that new instantaneous samples have
been collected.
The unsigned VRMS, IRMS, and average power calculations are updated every N conversions (which
is known as 1 “computation cycle”) where N is the
value in the Cycle Count Register. At the end of
each computation cycle, the DRDY bit in the Mask
Register will be set, and the INT pin will become
active if the DRDY bit is unmasked.
DRDY is set only after each computation cycle has
completed, whereas the CRDY bit is asserted after
each individual A/D conversion. When these bits
are asserted, they must be cleared by the user before they can be asserted again. If the Cycle Count
Register value (N) is set to 1, all output calculations
are instantaneous, and DRDY will indicate when
instantaneous calculations are finished, just like the
CRDY bit. For the RMS results to be valid, the Cycle-Count Register must be set to a value greater
than 10.
A computation cycle is derived from the master
clock and its frequency is (MCLK/K)/(1024*N).
Under default conditions with a 4.096 MHz clock
at XIN, instantaneous A/D conversions for voltage,
current, and power are performed at a 4000 Hz rate,
whereas IRMS, VRMS, and energy calculations are
performed at a 1 Hz rate.
3.3 CS5461 Linearity Performance
Avg Power
Vrms
Irms
Range (% of FS)
0.1% - 100%
1% - 100%
0.2% - 100%
Linearity
0.1% of
reading
0.1% of
reading
0.1% of
reading
Table 1. Available range of ±0.1% output linearity,
with default settings in the gain/offset registers.
Table 1 lists the range of input levels (as a percentage of full-scale registration in the Average Power,
Irms, and Vrms Registers) over which the output
linearity of the Vrms, Irms and Average Power
Register measurements are guaranteed to be within
15
CS5461
±0.1%.
This linearity is guaranteed for all four of
the available full-scale input voltage ranges.
Note that until the CS5461 is calibrated (see Calibration) the accuracy of the CS5461 (with respect
to a reference line-voltage and line-current level on
the power mains) is not guaranteed to within
±0.1%. But the linearity of any given sample of
CS5461, before calibration, will be within ±0.1%
of reading over the ranges specified, with respect to
the input voltage levels required to cause full-scale
readings in the Irms/Vrms Registers. Table 1 describes linearity + variation specs after the completion of each successive computation cycle.
The accuracy of the internal calculations can often
be improved by selecting a value for the Cycle-Count Register that will cause the time duration
of one computation cycle to be equal (or very close
to) a whole-number of power-line cycles (and N
must be greater than or equal to 4000). For example, with the cycle count set to 4200, the ±0.1% of
reading linearity range for measurement of a 60 Hz
sinusoidal current-sense voltage signal can be increased beyond the range of 0.2% - 70.7%. The linearity range can be increased because (4200
samples / 60 Hz) is a whole number of cycles (70).
4. FUNCTIONAL DESCRIPTION
4.1 Analog Inputs
4.2 Voltage Reference
The CS5461 has two available full-scale differential input voltage ranges on the current channel and
one full-scale differential input voltage range on
the voltage channel.
The CS5461 is specified for operation with a
+2.5 V reference between the VREFIN and VApins. The converter includes an internal 2.5 V reference (60 ppm/°C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of
the device. If higher accuracy/stability is required,
an external reference can be used.
The input ranges are the maximum sinusoidal signals that can be applied to the current and voltage
channels, yet these values will not result in full
scale registration in the instantaneous current and
voltage registers.
If the current and voltage channels are set to
500 mVP-P, only a 250 mVRMS signal will register
full scale. Yet it would not be practical to inject a
sinusoidal signal with a value of 250 mVRMS.
When such a sine wave enters the higher levels of
its positive crest region (over each cycle), the voltage level of this signal exceeds the maximum differential input voltage range of the input channels.
The largest sine wave voltage signal that can be
placed across the inputs, with no saturation is:
500mV P-P
2
2
= ~176.78mV RMS
which is ~70.7% of full-scale. So for sinusoidal inputs at the full scale peak-to-peak level the full
scale registration is ~.707.
16
4.3 Oscillator Characteristics
XIN and XOUT are the input and output of an inverting amplifier to provide oscillation and can be
configured as an on-chip oscillator, as shown in
Figure 3. The oscillator circuit is designed to work
with a quartz crystal or a ceramic resonator. To reduce circuit cost, two load capacitors C1 and C2 are
integrated in the device. With these load capacitors,
the oscillator circuit is capable of oscillation up to
20 MHz. To drive the device from an external
clock source, XOUT should be left unconnected
while XIN is driven by the external circuitry. There
is an amplifier between XIN and the digital section
which provides CMOS level signals. This amplifier
works with sinusoidal inputs so there are no problems with slow edge times.
DS546F2
CS5461
The CS5461 can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must be set such that the internal DCLK will run
somewhere between 2.5 MHz and 5 MHz. The K
divider value is set with the K[3:0] bits in the Configuration Register. As an example, if XIN =
MCLK = 15 MHz, and K is set to 5, then DCLK is
3 MHz, which is a valid value for DCLK.
C1
Oscillator
Circuit
XIN
C2
C1 = C2 = 22 pF
Figure 3. Oscillator Connection
4.4 Calibration
4.4.1 Overview of Calibration Process
The CS5461 offers digital calibration for both
channels; AC/DC offset and AC/DC gain. For both
the voltage channel and the current channel, the AC
offset calibration sequence performs an entirely
different function than the DC offset calibration sequence. The AC gain and DC gain calibration sequences perform the same function, but accomplish
the function using different techniques.
Since both the voltage and current channels have
separate offset and gain registers associated with
them, system offset or system gain can be performed on either channel without the calibration
results from one channel affecting the other.
DS546F2
1. Before Calibration the CS5461 must be operating in its active state, and ready to accept valid
commands. The ‘DRDY’ bit in the Status Register
should also be cleared.
2. Apply appropriate calibration signals to the inputs of the voltage/current channels (discussed next
in Sections 4.4.3 and 4.4.4.)
3. Send the 8-bit calibration command to the
CS5461 serial interface. Various bits within this
command specify the exact type of calibration.
XOUT
DGND
4.4.2 Calibration Sequence
4. After the CS5461 finishes the desired internal
calibration sequence, the DRDY bit is set in the
Status Register to indicate that the calibration sequence is complete. The results of the calibration
are now available in the appropriate gain/offset
registers.
4.4.3 Calibration Signal Input Level
For AC/DC gain calibrations, there is an absolute
limit on the RMS/DC voltage levels that are selected for the gain calibration input signals. The maximum value that the gain register can attain is 4.
Therefore, for either channel, if the voltage level of
a gain calibration input signal is low enough that it
causes the CS5461 to attempt to set either gain register higher than 4, the gain calibration result will
be invalid and all CS5461 results obtained while
running A/D conversions will be invalid.
4.4.4 Calibration Signal Frequency
Optimally, the frequency of the calibration signal is
the same frequency as the fundamental power line
frequency of the metered power system.
4.4.5 Input Configurations for Calibrations
Figure 4 shows the basic setup for gain calibration.
When performing a DC gain calibration a positive
DC voltage level must be applied at the inputs of
the voltage/current channels. This voltage should
17
CS5461
be set to the level that represents the absolute maximum instantaneous voltage level that needs to be
measured across the inputs (including the maximum over-range level that must be accurately measured). When performing AC gain calibration, an
AC reference signal should be applied that represents the desired maximum RMS level. A typical
sinusoidal calibration value which allows for reasonable over-range margin would be 0.6 or 60% of
the voltage/current channel’s maximum input voltage level.
External
Connections
+
Full Scale
(DC or AC)
+
AIN+
+
XGAIN
-
-
AIN-
CM +-
-
External
Connections
+
CM +-
+
AIN+
XGAIN
AIN-
-
-
Figure 5. System Calibration of Offset.
For both AC and DC offset calibrations, the “+”
and “-’ pins of the voltage/current channels should
be connected to their ground reference level. (See
Figure 5.)
If offset and gain calibration command bits are set,
only the offset calibration will be performed.
4.4.6 Description of Calibration Algorithms
The computational flow of the CS5461’s AC and
DC gain/offset calibration sequences are illustrated
in Figure 6. This figure applies to both the voltage
channel and the current channel.
18
4.4.6.1 AC Offset Calibration Sequence
The AC offset calibration obtains an offset value
that reflects the RMS output level when the inputs
are grounded. During normal operation, this AC
offset register value will be subtracted from each
successive voltage/current sample in order to nullify the AC offset that may be inherent in the signal
path.
4.4.6.2 DC Offset Calibration Sequence
Figure 4. System Calibration of Gain.
0V +-
Note: For proper AC calibration, the value of the
Voltage/Current Gain Registers must be set to default
(1.0) before running the gain calibration(s), and the
value in the AC Offset Registers must be set to default
(0) before running calibrations. This can be
accomplished by a software or hardware reset of the
device. The values in the voltage/current calibration
registers do affect the results of the calibration
sequences.
The DC Offset Registers hold the negative of the
simple average of N samples taken while the DC
offset calibration was executed. The inputs should
be grounded during DC offset calibration. The DC
offset value is added to the signal path to nullify the
DC offset in the system.
4.4.6.3 AC Gain Calibration Sequence
The AC gain calibration algorithm attempts to adjust the Gain Register value such that the calibration reference signal level presented at the voltage
inputs will result in a value of 0.6 in the RMS Voltage Register. The rms level of the calibration signal
must be determined by the user. During AC voltage
gain calibration, the value in the RMS Voltage
Register is divided into 0.6 and stored in the Voltage Gain Register.
Two examples of AC calibration and the resulting
shift in the digital output codes of the channel’s instantaneous data registers are shown in Figures 7
and 8. Figure 8 shows that a positive (or negative)
DC level signal can be used even though an AC
gain calibration is being executed. However, an AC
signal cannot be used for DC gain calibration.
DS546F2
CS5461
4.4.6.4 DC Gain Calibration Sequence
calibration signal applied to the inputs during the
DC gain calibration (see Figure 9).
Based on the level of the positive DC calibration
voltage applied across the “+’ and “-” inputs, the
CS5461 determines the DC Gain Register value by
averaging the Instantaneous Register’s output signal values over one computation cycle (N samples)
and then dividing this average into 1. Therefore, after the DC gain calibration, the Instantaneous Register will read at full-scale whenever the DC level
of the input signal is equal to the level of the DC
4.4.7 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines the number of conversions performed by the
CS5461 during a given calibration sequence. For
DC offset/gain calibrations, the calibration sequence takes at least N + 30 conversion cycles to
complete. For AC offset/gain calibrations, the calibration sequence takes at least 6N + 30 A/D conBefore AC Gain Calibration (Vgain Register = 1)
Before AC Gain Calibration (Vgain Register = 1)
Sinewave
250 mV
0.9999...
250 mV
0.9999...
230 mV
0.92
230 mV
0.92
DC Signal
Instantaneous Voltage
Register Values
INPUT
0V
SIGNAL
-230 mV
-0.92
-250 mV
-1.0000...
Instantaneous Voltage
Register Values
INPUT 0 V
SIGNAL
-1.0000...
-250 mV
VRMS Register = 230/250 x 1/√2 ≈ 0.65054
VRMS Register = 230/250 = 0.92
After AC Gain Calibration (Vgain Register changed to ~0.9223)
Sinewave
250 mV
0.92231
230 mV
0.84853
INPUT
0V
SIGNAL
After AC Gain Calibration (Vgain Register changed to ~0.65217)
-0.84853
-250 mV
-0.92231
0.65217
230 mV
0.6000
DC Signal
Instantaneous Voltage
Register Values
-230 mV
250 mV
INPUT
0V
SIGNAL
Instantaneous Voltage
Register Values
-0.65217
-250 mV
VRMS Register = 0.6000...
VRMS Register = 0.6000...
Figure 7. Example of AC Gain Calibration
Figure 8. Another Example of AC Gain Calibration
to V *, I*, P *, E * R egisters
In
M odulator
Filter
+
+
x
X
+
D C O ffse t*
2
+
+
S IN C
N
2
X
÷ N
V R M S*
G a in *
N
Σ
A C O ffse t*
X
1
x
2
÷N
-X
0 .6
x
* Denotes readable/writable register
Figure 6. Calibration Data Flow
DS546F2
19
CS5461
Before DC Gain Calibration (Vgain Register = 1)
250 mV
0.9999...
230 mV
0.92
DC Signal
Instantaneous Voltage
Register Values
INPUT 0 V
SIGNAL
-1.0000...
-250 mV
VRMS Register = 230/250 = 0.92
4.6 Phase Compensation
After DC Gain Calibration (Vgain Register changed to 1.0870)
230 mV
0.9999...
DC Signal
Instantaneous Voltage
Register Values
INPUT 0 V
SIGNAL
VRMS Register = 0.9999...
Figure 9. Example of DC Gain Calibration
version cycles to complete, (about 6 computation
cycles). As N is increased, the accuracy of calibration results will increase.
4.4.8 Order of Calibration Sequences
1. If the measured signal needs to include any DC
content that may be present in the voltage/current
and power/energy signals, run DC offset calibration first. However, if the HPF options are turned
on, then any DC component that may be present in
the power/energy signals will be removed from the
CS5461’s power/energy results.
2. If the energy registration accuracy needs to be
within ±0.1% (with respect to reference calibration
levels on the voltage/current inputs) then either the
AC or the DC gain calibration is recommended for
the voltage/current channels.
3. Finally, run AC offset calibration on the voltage
and current channels.
4.5 Power Offset
The Power Offset Register can be used to offset
system power sources that may be resident in the
system, but do not originate from the power line
20
signal. These sources of extra energy in the system
contribute undesirable and false offsets to the power/energy measurement results. After determining
the amount of stray power, the Power Offset Register can be set to nullify the effects of this unwanted energy.
Bits 23 to 17 of the Configuration Register are used
to program the amount of phase delay added to the
voltage channel signal path. This phase delay is applied to the voltage channel signal in order to compensate for phase delay that may be introduced by
the voltage and current sensor circuitry external to
the CS5461. Voltage and current transformers, as
well as other sensor equipment applied to the
front-end of the CS5461 inputs can often introduce
a phase delay in the system, which distorts the
phase relationship between the voltage and current
signals being measured. The phase compensation
bits PC[6:0] can be set to nullify this undesirable
phase distortion between the two channels.
The default value of the phase compensation bits is
0000000(b). This setting represents the shortest
time-delay (smallest phase delay) between the voltage and current channel signal paths. With the default setting, the phase delay on the voltage channel
is 0.995 µs (~0.0215 degrees assuming a 60 Hz
power signal). With MCLK = 4.096 MHz and
K = 1, the range of the internal phase compensation
ranges from -2.8 degrees to +2.8 degrees when the
input voltage/current signals are at 60 Hz. In this
condition, each step of the phase compensation register (value of one LSB) is ~0.04 degrees. For values of MCLK other than 4.096 MHz, the range
(-2.8 to +2.8 degrees) and step size (0.04 degrees)
should be scaled by 4.096 MHz / (MCLK / K). For
power line frequencies other than 60Hz, the values
of the range and step size of the PC[6:0] bits can be
determined by converting the above values to
time-domain (seconds), and then computing the
DS546F2
CS5461
new range and step size (in degrees) with respect to
the new line frequency.
To calibrate the phase delay, use a purely resistive
load and adjust the phase compensation bits until
the Average Power Register value is maximized.
4.7 Time-Base Calibration
The Time-Base Calibration Register (notated as
“TBC” in Figure 2) is used to compensate for slight
errors in the XIN frequency. External oscillators
and crystals have certain tolerances. To improve
the accuracy of the clock for energy measurements,
the Time-Base Calibration Register can be manipulated to compensate for the frequency error. Note
from Figure 2 that the TBC Register only affects
the value in the Average Power Register.
As an example, if the desired XIN frequency is
4.096 MHz, but during production-level testing the
average frequency of the crystal on a particular
board is measured to be 4.091 MHz. The ratio of
the desired frequency to the actual frequency is
4.096 MHz / 4.091 MHz = ~1.00122219506. The
Time-Base Calibration Register can be set to
1.00122213364 = 0x80280C(h), which is close to
the desired ratio.
4.8 On-Chip Temperature Sensor
After a few minutes of normal-active operation in
‘continuous conversions’ data acquisition mode,
the CS5461 will stabilize to a constant steady-state
operating temperature. However, the CS5461’s operating temperature may be influenced by changes
in the ambient temperature. Such ambient temperature fluctuations will cause some drift in the gain
of the CS5461’s two A/D converters. The on-chip
temperature sensor provides the option to calibrate
such drift.
The output code value in the Temperature Register
is the relative temperature reading of the on-chip
temperature sensor.
By recording the digitized temperature readings
and comparing these readings to the fluctuations in
the A/D output codes of the Vrms and Irms Register readings, the fluctuation of the A/D converter
can be characterized over a wide range of ambient
temperatures.
Once a temperature drift characterization of the device has been performed, a temperature compensation algorithm can be integrated into the firmware
within the on-board MCU to compensate for this
temperature drift.
4.9 Interrupt
The INT pin is used to indicate that an event has
taken place in the converter that needs attention.
These events inform the system about operation
conditions and internal error conditions. The INT
signal is created by combining the Status Register
with the Mask Register. Whenever a bit in the Status Register becomes active, and the corresponding
bit in the Mask Register is a logic 1, the INT signal
becomes active. The interrupt condition is cleared
when the bits of the Status Register are returned to
their inactive state.
4.9.1 Typical use of the INT pin
The steps below show how interrupts can be handled.
•
Initialization:
Step I0 - All Status bits are cleared by writing
FFFFFF (Hex) into the Status Register.
Step I1 - The conditional bits which will be
used to generate interrupts are then set to
logic 1 in the Mask Register.
Step I3 - Enable interrupts.
•
Interrupt Handler Routine:
Step H0 - Read the Status Register.
Step H1 - Disable all interrupts.
Step H2 - Branch to the proper interrupt service
routine.
DS546F2
21
CS5461
Step H3 - Clear the Status Register by writing
back the read value in step H0.
Step H4 - Re-enable interrupts.
Step H5 - Return from interrupt service routine.
This handshaking procedure insures that any
new interrupts activated between steps H0 and
H3 are not lost (cleared) by step H3.
4.9.2 INT Active State
The behavior of the INT pin is controlled by the
IMODE and IINV bits of the Configuration Register. The pin can be active low (default), active high,
active on a return to logic 0 (pulse-low), or active
on a return to logic 1 (pulse-high). If the interrupt
output signal format is set for either pulse-high or
pulse-low, the duration of the INT pulse will be at
least one DCLK cycle (DCLK = MCLK / K).
22
4.10 Voltage Sag-Detect Feature
The CS5461 includes Status Register bit, VSAG;
which indicates a sag in the power line voltage.
In order for sag condition to be identified, the measured VRMS must remain below a set sag threshold
level for a specified period of time.
To activate this feature, a voltage threshold value
must be specified in the Voltage Sag Level Register
(VSAGLevel); and a time-duration must be specified
in the Voltage Sag Duration Register (VSAGDuration). This Time Duration is specified in terms of
A/D cycles.
If VRMS is measured below the level specified in
the VSAGLevel Register for a duration of time greater than or equal to the number of A/D conversions
specified in the VSAGDuration Register, then the
VSAG bit in the Status Register will be asserted.
DS546F2
CS5461
5. ENERGY PULSE OUTPUTS
5.1 Pulse-Rate Output (EOUT and EDIR)
EOUT and EDIR pins provide pulses which represent a predetermined magnitude of energy. With
MCLK = 4.096 MHz, and default settings, the
pulses will have an average frequency equal to the
frequency setting in the PulseRateE Register when
the input signals into the voltage and current channels cause full-scale readings in the Instantaneous
Voltage and Current Registers. When MCLK/K is
not equal to 4.096 MHz, the user should scale the
pulse-rate by a factor of 4.096 MHz / (MCLK / K)
to get the actual output pulse-rate.
5.2 Pulse Output for Normal Format,
Stepper Motor Format and Mechanical
Counter Format
EOUT and EDIR pins can be set in three different
output formats. The default setting is normal output
pulse format. When the pulse is set to either of the
other two formats, the time duration and/or the relative timing of the EOUT and EDIR pulses is varied such that the pulses can drive either an
electro-mechanical counter or a stepper motor. The
ability to set the pulse output format to one of the
three available formats is controlled by setting certain bits in the Control Register.
5.2.1 Normal Format
In Normal format the EOUT and EDIR pulse output format is illustrated in Figure 10. These are acPositive Energy Burst
EOUT
...
EDIR
...
t
tive-low pulses of short duration. A positive energy
pulse is represented by a pulse on the EOUT pin
while the EDIR will remain high. A negative energy pulse is represented by synchronous pulses on
both the EOUT pin and the EDIR pin.
The pulse duration is an integer multiple of MCLK
cycles, approximately equal to 1/16 of the period of
the contents of the Pulse-Rate Register. However
for Pulse-Rate Register settings less than the sampling rate (which is [MCLK/8]/1024), the pulse duration remains constant and is equal to the duration
of the pulses when the Pulse-Rate Register is set to
[MCLK/K]/1024. The maximum pulse frequency
from the EOUT pin is therefore [MCLK / K] / 8.
When DCLK is not equal to 4.096 MHz, the pulse
duration can be predicted by using the pulse duration values in Table RR and dividing them by
(MCLK/K) / 4.096 MHz.
In Normal pulse output format, the number of pulses depends on the value of the PulseRateE Register
and on the amount of energy registered over the
most recent A/D sampling period. A running total
of the energy accumulation is maintained in an internal register inside the CS5461 (not available to
the user). After each A/D conversion cycle, the result in the Power Register is multiplied by the value
in the PulseRateE Register, and also by the value in
the TBC (Time-Base Calibration) Register, and
then added to this internal energy accumulation
register. Once a certain amount of positive or negNegative Energy Burst
...
...
Figure 10. Time-plot representation of pulse output for a typical burst of pulses (Normal ForDS546F2
23
CS5461
128 ms
EOUT
EDIR
...
...
128 ms
Positive Energy
...
...
Negative Energy
Figure 11. Mechanical Counter Format on EOUT and EDIR
ative energy accumulation is reached in this register, the CS5461 will issue either a positive or
negative energy pulse on the EOUT/EDIR pins.
After the pulse or pulses are issued, a certain residual amount of energy may be left over in this internal energy accumulation register. In this situation,
the residual energy is not lost or discarded, but rather it is maintained and added to the energy that is
accumulated during the next update period.
5.2.2 Mechanical Counter Format
Setting the MECH bit in the Control Register to ‘1’
and the STEP bit to ‘0’ enables wide-stepping pulses for mechanical counters and similar discrete
counter instruments. In default mechanical mode
format, active-low pulses are 128 ms wide when
using a 4.096 MHz crystal and K = 1. When energy
is positive, the pulses appear on EOUT. When energy is negative, pulses appear on EDIR (see Figure 11). The pulse width is set in the Pulsewidth
register and will limit the pulse frequency available. It is up to the user to insure that pulses will not
occur at a rate faster than the 128 ms pulse duration, or faster than the mechanical counter can accommodate. This is done by verifying that the
PulseRateE Register is set to an appropriate value.
Because in the default state the duration of each
pulse is set to 128 ms, the maximum output pulse
frequency is limited to ~7.8 Hz (for
MCLK/K = 4.096 MHz). For values of MCLK/K
different than 4.096 MHz, the duration of one pulse
is (128*4.096 MHz)/(MCLK/K) milliseconds.
5.2.3 Stepper Motor Format
Setting the STEP bit in the Control Register to ‘1’
and the MECH bit to ‘0’ transforms the EOUT and
EDIR pins into two-phase stepper motor outputs.
When an energy pulse occurs, one of the outputs
changes state. When the next energy pulse occurs,
the other output changes state. The direction the
motor will rotate is determined by the order of the
state changes. When energy is positive, EOUT will
lead EDIR. When energy is negative, EDIR will
lead EOUT (see Figure 12).
5.3 FOUT Pulse Output
In many metering applications, the pulse frequency
to power rate on the EOUT pin may be set to a relatively low value, such that the pulse frequency is
on the order of 1-100 Hz at nominal power consumption levels. However, calibration can take a
long time at such output frequencies. In order to reduce the time needed to verify the meter an extra
pulse frequency-to-power output is provided on the
FOUT pin. The pulse frequency-to-power rate can
EOUT
...
...
EDIR
...
...
Positive Energy
Negative Energy
Figure 12. Stepper Motor Format on EOUT and EDIR
24
DS546F2
CS5461
be set to a value much higher than the EOUT pulse
rate.
values to use in the front-end voltage/current sensor networks.
The FOUT pin outputs negative and positive energy, but has no energy direction indicator. The maximum FOUT pulse frequency is set by the value in
the PulseRateF Register.
For a sinewave, the largest RMS value that can be
accurately measured (without over-driving the inputs) will register ~0.707 of the maximum DC input level. Since power signals are often not
perfectly sinusoidal in real-world situations, and to
provide for some over-range capability, the RMS
Voltage Register and RMS Current Register is set
to measure 0.6 when the RMS-values of the
line-voltage and line-current levels are 250 V and
20 A. Therefore, when the RMS registers measure
0.6, the voltage level at the inputs will be
0.6 x 250 mV = 150 mV. The sensor gain constants, KV and KI, are determined by demanding
that the voltage and current channel inputs should
be 150 mV RMS when the power line voltage and
current are at the maximum values of 250 V and
20 A.
5.4 Anti-Creep for the Pulse Outputs
Anti-Creep can be enabled/disabled for both
EOUT/EDIR and FOUT pulse output systems in
the Control Register. Anti-creep allows the electronic meter to maintain a “buffer” energy band,
defined by positive/negative energy threshold levels, such that when the magnitude of the accumulated energy is below this level, no energy pulses
are issued. The anti-creep feature is especially useful when the meter demands that the energy pulse
outputs are set to relatively high frequency. A higher frequency pulse rate means that less energy registration is required to generate a pulse; and so it is
more likely that random noise present in the power
line and/or current-sense circuit can generate a
pulse that does not represent billable energy.
5.5 Design Examples
EXAMPLE #1: For a power line with maximum
rated levels of 250 V (RMS) and 20 A (RMS), the
pulse-frequency on the EOUT pin needs to be
‘IR’ = 100 pulses-per-second (100 Hz) when the
RMS-voltage and RMS-current levels on the power
line are 220 V and 15 A respectively. To meet this
requirement, the pulse-rate frequency (‘PR’) in the
Pulse-Rate Register must be set accordingly.
After calibration, the first step to finding the value
of ‘PR’ is to set the voltage and current sensor gain
constants, KV and KI, such that there will be acceptable voltage levels on the CS5461 inputs when the
power line voltage and current levels are at the
maximum values of 250 V and 20 A. KV and KI are
needed to determine the appropriate ratios of the
voltage/current transformers and/or shunt resistor
DS546F2
KV = 150 mV / 250 V = 0.0006
KI = 150 mV / 20 A = 0.0075 Ω
These sensor gain constants are used to calculate
what the input voltage levels will be on the CS5461
inputs when the line-voltage and line-current are
220 V and 15 A. These values are VVnom and VInom.
VVnom = KV * 220 V = 132 mV
VInom = KI * 15 A = 112.5 mV
The pulse rate on EOUT will be at ‘PR’ pulses per
second (Hz) when the RMS-levels of voltage/current inputs are at 250 mV. When the voltage/current inputs are set at VVnom and VInom, the pulse
rate needs to be ‘IR’ = 100 pulses per second. IR
will be some percentage of PR. The percentage is
defined by the ratios of VVnom/250 mV and
VInom/250 mV with the following formula:
V Vnom V Inom
PulseRate = IR = PR ⋅ ------------------- ⋅ ------------------250mV 250mV
25
CS5461
From this equation the value of ‘PR’ is shown as:
100Hz
IR
- = ----------------------------------------------PR = ------------------------------------------132mV
V Vnom V Inom
------------------ × 112.5mV
---------------------------------------- × -----------------250mV 250mV
250mV 250mV
Therefore the Pulse-Rate Register is set to
~420.875 Hz, or 0x00349C.
When MCLK/K is not equal to 4.096 MHz, the result for ‘PR’ that is calculated for the Pulse-Rate
Register must be scaled by a correction factor of:
4.096 MHz / (MCLK/K). For MCLK/K of
3.05856 MHz the result is scaled by 4.096/3.05856
to get a final PR result of ~2.583 Hz.
EXAMPLE #2: The required number of pulses per
unit energy present at EOUT is specified to be
500 pulses/kW-hr; given that the maximum
line-voltage is 250 V (RMS) and the maximum
line-current is 20 A (RMS). In such a situation, the
nominal line voltage and current do not determine
the appropriate pulse-rate setting. Instead, the maximum line levels must be considered. As before, the
given maximum line-voltage and line-current levels are used to determine KV and KI:
5.6 Auto-Boot Mode Using EEPROM
KV = 150 mV / 250 V = 0.0006
Figure 13 shows the typical connections between
the CS5461 and a serial EEPROM for proper auto-boot operation. In this mode, CS and SCLK are
driven outputs. During the auto-boot sequence, the
CS5461 drives CS low, provides a clock output on
SCLK, and drives out-commands on SDO. It receives the EEPROM data on SDI. The serial EEPROM must be programmed with the
user-specified commands and register data that will
be used by the CS5461 to change any of the default
register values and begin conversions.
KI = 150 mV / 20 A = 0.0075 Ω
Again the sensor gains are calculated such that the
maximum line-voltage and line-current levels will
measure as 0.6 in the RMS Voltage Register and
RMS Current Register.
With voltage and current channel input ranges set
to 10x, the required Pulse-Rate Register setting is
determined using the following equation:
pulses 1hr
1kW 250mV 250mV
PR = 500 ------------------ ⋅ -------------- ⋅ ------------------ ⋅ ------------------ ⋅ -----------------kW ⋅ hr 3600s 1000W
KV
KI
Therefore PR = ~1.929 Hz.
Note that the Pulse-Rate Register cannot be set to a
frequency of exactly 1.929 Hz. The closest setting
that the Pulse-Rate Register can obtain is
0x00003E = 1.9375 Hz. To improve the accuracy,
either gain register can be programmed to correct
for the round-off error in PR. This value would be
calculated as
PR
Ign or Vgn = ------------- ≅ 1.00441 = 0x404830
1.929
26
When the CS5461 MODE pin is left unconnected,
the CS5461 is in normal operating mode, called
host mode. When this pin is set to logic high, the
CS5461 auto-boot mode is enabled. In auto-boot
mode, the CS5461 is configured to request a memory download from an external serial EEPROM.
Auto-Boot mode allows the CS5461 to operate
without the need for a microcontroller.
5.6.1 Auto-Boot Configuration
VD+
/EOUT
/EDIR
5K
Mech. Counter
or
Stepper Motor
EEPROM
CS5461
SCK
SCK
MODE
SDI
SO
SDO
SI
5K
/CS
/CS
Connector to Calibrator
Figure 13. Typical Interface of EEPROM to
DS546F2
CS5461
Figure 13 also shows the external connections that
would be made to a calibrator device, such as a PC
or custom calibration board. When the metering
system is installed, the calibrator would be used to
control calibration and/or to program user-specified commands and calibration values into the EEPROM. The user-specified commands/data will
determine the CS5461’s exact operation, when the
auto-boot initialization sequence is running. Any of
the valid commands can be used.
E8
;Start continuous conversions
78 00 01 40
;Write STOP bit to Control
Register, to terminate auto-boot initialization sequence, and set the EOUT
pulse output to Mechanical
Counter Format.
5.6.2 Auto-Boot Data for EEPROM
5.6.3 Which EEPROMs Can Be Used?
Below is an example code set for an auto-boot sequence. This code is written into the EEPROM by
the user. The serial data for such a sequence is
shown below in single-byte hexidecimal notation:
Several industry-standard serial EEPROMs that
will successfully run auto-boot with the CS5461
are listed below:
•
Atmel
;In Configuration Register,
turn high-pass filters on, set
K=1.
•
National Semiconductor
44 7F C4 A9
;Write value of 0x7FC4A9 to
Current Gain Register.
•
Xicor
46 7F B2 53
;Write value of 0xFFB253 to
DC Voltage Offset Register.
4C 00 00 14
;Set PulseRateE Register to
0.625 Hz.
74 00 00 04
;Unmask bit #2 (“LSD” bit in
the Mask Register).
40 00 00 61
DS546F2
AT25010
AT25020
AT25040
NM25C040M8
NM25020M8
X25040SI
These types of serial EEPROMs expect a specific
8-bit command word (00000011) in order to perform a memory download. The CS5461 has been
hardware programmed to transmit this 8-bit command word to the EEPROM at the beginning of the
auto-boot sequence.
27
CS5461
6. SERIAL PORT OVERVIEW
The CS5461's serial port incorporates a state machine with transmit/receive buffers. The state machine interprets 8 bit command words on the rising
edge of SCLK. Upon decoding of the command
word, the state machine performs the requested
command or prepares for a data transfer of the addressed register. Request for a read requires an internal register transfer to the transmit buffer, while
a write waits until the completion of 24 SCLKs before performing a transfer. The internal registers
are used to control the ADC's functions. All registers are 24-bits in length.
The CS5461 is initialized and fully operational in
its active state upon power-on. After a power-on,
the device will wait to receive a valid command
(the first 8-bits clocked into the serial port). Upon
receiving and decoding a valid command word, the
state machine instructs the converter to either perform a system operation, or transfer data to or from
an internal register.
6.1 Commands
All command words are 1 byte in length. Any 8-bit word that is not listed in this section is considered an invalid command word. Commands that write to a register must be followed by 3 bytes of register data. Commands that read
data can be chained with other commands (e.g., while reading data, a new command can be sent to SDI which can
execute before the original read is completed).
6.1.1 Start Conversions
B7
1
B6
1
B5
1
B4
0
B3
C
B2
0
B1
0
B0
0
This command indicates to the state machine to begin acquiring measurements and calculating results. The device
has two modes of acquisition.
C=
Modes of acquisition/measurement
0 = Perform a single computation cycle
1 = Perform continuous computation cycles
6.1.2 SYNC0 Command
B7
1
B6
1
B5
1
B4
1
B3
1
B2
1
B1
1
B0
0
This command is the end of the serial port re-initialization sequence. The command can also be used as a NOP
command. The serial port is resynchronized to byte boundaries by sending three or more consecutive SYNC1 commands followed by a SYNC0 command.
6.1.3 SYNC1 Command
B7
1
B6
1
B5
1
B4
1
B3
1
B2
1
B1
1
B0
1
This command is part of the serial port re-initialization sequence. The command also serves as a NOP command.
28
DS546F2
CS5461
6.1.4 Power-Up/Halt
B7
1
B6
0
B5
1
B4
0
B3
0
B2
0
B1
0
B0
0
If the device is powered-down, this command will initiate a power on reset. If the part is already powered-on, all computations will be halted.
6.1.5 Power-Down and Software Reset
B7
1
B6
0
B5
0
B4
S1
B3
S0
B2
0
B1
0
B0
0
The device has two power-down states to conserve power. If the chip is put in stand-by state, all circuitry except the
analog/digital clock generators is turned off. In the sleep state, all circuitry except the digital clock generator and the
instruction decoder is turned off. Bringing the CS5461 out of sleep state requires more time than out of stand-by
state, because of the extra time needed to re-start and re-stabilize the analog clock signal.
S1,S0
Power-down state
00 = Software Reset
01 = Halt and enter stand-by power saving state. This state allows quick power-on time
10 = Halt and enter sleep power saving state. This state requires a slow power-on time
11 = Reserved
6.1.6 Calibration
B7
1
B6
1
B5
0
B4
V
B3
I
B2
R
B1
G
B0
O
The device can perform a system AC offset calibration, DC offset calibration, AC gain calibration, and DC gain calibration. Offset and gain calibrations should NOT be performed at the same time (must do one after the other). Only
one gain calibration sequence should be performed for any given application. If calibration is needed, calibrate either
AC gain or DC gain, but not both. The user must supply the proper inputs to the device before initiating calibration.
V,I
Designates calibration channel
00 = Calibrate neither channel
01 = Calibrate the current channel
10 = Calibrate the voltage channel
11 = Calibrate voltage and current channel simultaneously
R
Designates calibration
0 = DC calibration
1 = AC calibration
G
Designates gain calibration
0 = No gain calibration
1 = Perform gain calibration
O*
Designates offset calibration
0 = No offset calibration
1 = Perform offset calibration
*If O is set then G is ignored.
DS546F2
29
CS5461
6.1.7 Register Read/Write
B7
0
B6
W/R
B5
RA4
B4
RA3
B3
RA2
B2
RA1
B1
RA0
B0
0
The Read/Write informs the state machine that a register access is required. During a read operation, the addressed
register is loaded into the device’s output buffer and clocked out by SCLK. During a write operation, the data is
clocked into the input buffer and, and all 24 bits are transferred to the addressed register on the 24th SCLK.
W/R
Write/Read control
0 = Read register
1 = Write register
RA[4:0]
Register address bits (bits 1 through 5) of the read/write command.
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RA[4-0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Abbreviation
Config
IDCoff
Ign
VDCoff
Vgn
Cycle Count
PulseRateE
I
V
P
PAvg
IRMS
VRMS
TBC
Poff
Status
IACoff
VACoff
PulseRateF
T
Res
PW
Res
VSAGLevel
VSAGDuration
Res
Mask
Res
Ctrl
Res
Res
Res
Name/Description
Configuration Register
Current Offset Register
Current Gain Register
Voltage Offset Register
Voltage Gain Register
Number of A/D conversions used in one computation cycle (N)).
Sets the EOUT/EDIR energy-to-frequency output pulse rate.
Instantaneous Current Register (last current value)
Instantaneous Voltage Register (last voltage value)
Instantaneous Power Register (Last Power value)
Average Power Register (avg. power over last computation cycle)
RMS Current Register (RMS value over last comp. cycle)
RMS Voltage Register (RMS value over last comp. cycle)
Timebase Calibration Register
Power Offset Calibration Register
Status Register (Write of ‘1’ to status bit will clear the bit.)
AC (RMS) Current Offset Register
AC (RMS) Voltage Offset Register
Sets the FOUT power-to-frequency output pulse rate.
Temperature Register
Reserved †
Pulse width register for mechanical counter output mode
Reserved †
Voltage Sag Level Threshold Register.
Voltage Sag Duration Register.
Reserved †
Mask Register
Reserved †
Control Register
Reserved †
Reserved †
Reserved †
† These registers are for internal use only. For proper device operation, the user must not attempt to write
to these registers.
30
DS546F2
CS5461
6.2 Serial Port Interface
The CS5461’s serial interface consists of four control lines, which have the following pin-names: CS,
SDI, SDO, and SCLK.
1) CS is the control line which enables access to
the serial port. If the CS pin is tied to logic 0,
the port can function as a three wire interface.
2) SDI is the data signal used to transfer data to the
converter.
3) SDO is the data signal used to transfer output
data from the converter. The SDO output will
be held at high impedance any time CS is at
logic 1.
4) SCLK is the serial bit-clock which controls the
shifting of data to or from the ADC’s serial
port. The CS pin must be held at logic 0 before
SCLK transitions can be recognized by the port
logic. To accommodate opto-isolators SCLK is
designed with a Schmitt-trigger input to allow
an opto-isolator with slower rise and fall times
to directly drive the pin.
6.3 Serial Read and Write
The state machine decodes the command word as it
is received. Data is written to and read from the
CS5461 by using the Register Read/Write operation. A transfer of data is always initiated by sending the appropriate 8-bit command (MSB first) to
the serial port (SDI pin). Figure 1 illustrates the serial sequence necessary to write to, or read from the
serial port’s buffers.
During a write operation, the serial port will continue to clock in the data bits (MSB first) on the SDI
pin for the 24 SCLK cycles.
When a read command is initiated, the serial port
will start transferring register content bits serial
(MSB first) on the SDO pin for 8, 16, or 24 SCLK
cycles. Command words instructing a register read
may be terminated at 8-bit boundaries. Also data
register reads allow “command chaining”. This
DS546F2
means the micro-controller can send a new command while reading register data. The new command will be acted upon immediately and could
possibly terminate the first register read. For example, if only the 16 most significant bits of data from
the first read are required, a second read command
on SDI can be initiated after the first 8 data bits are
read from SDO.
During a read cycle, the SYNC0 command
(NOP) should be strobed on the SDI port while
clocking the data from the SDO port.
6.4 System Initialization
A software or hardware reset can be initiated at any
time. The software reset is initiated by sending the
command 0x80.
A hardware reset is initiated when the RESET pin
is forced low with a minimum pulse width of 50 ns.
The RESET signal is asynchronous, requiring no
MCLKs for the part to detect and store a reset
event. The RESET pin is a Schmitt Trigger input,
which allows it to accept slow rise times and/or
noisy control signals. Once the RESET pin is inactive, the internal reset circuitry remains active for 5
MCLK cycles to insure resetting the synchronous
circuitry in the device. The modulators are held in
reset for 12 MCLK cycles after RESET becomes
inactive. After a hardware or software reset, the internal registers (some of which drive output pins)
will be reset to their default values on the first
MCLK received after detecting a reset event. The internal register values are also set to their default values after initial power-on of the device. The CS5461
will then assume its active state.
6.5 Serial Port Initialization
It is possible for the serial interface to become unsynchronized, with respect to the SCLK input. If
this occurs, any attempt to clock valid CS5461
commands into the serial interface may result in
unexpected operation. The CS5461’s serial port
must then be re-initialized. To initialize the serial
31
CS5461
port, any of the following actions can be performed:
1) Drive the CS pin low [or if CS pin is already
low, drive the pin high, then back to low].
2) Hardware Reset (drive RESET pin low, for at
least 10 µs).
3) Issue the Serial Port Initialization Sequence,
which is performed by clocking 3 (or more)
SYNC1 command bytes (0xFF) followed by
one SYNC0 command byte (0xFE).
6.6 CS5461 Power States
Active state denotes the operation of CS5461 when
the device is fully powered on (not in sleep state or
stand-by state). To insure that the CS5461 is operating in the active state; perform one of the three
actions below:
1) Power on the CS5461. (Or if the device is already powered on, recycle the power.)
2) Software Reset
3) Hardware Reset
If the device is in sleep state or in stand-by state, issuing the Power-Up/Halt command will also insure
that the device is in active state. In order to send the
Power-Up/Halt command to the device, the serial
port must be initialized. Therefore, after applying
power to the CS5461, a hardware reset should always be performed.
32
DS546F2
CS5461
7. REGISTER DESCRIPTION
1. “Default**” => bit status after power-on or reset
2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
7.1 Configuration Register
Address: 0
23
PC6
22
PC5
21
PC4
20
PC3
19
PC2
18
PC1
17
PC0
Igain
16
15
EWA
14
13
12
IMODE
11
IINV
10
EPP
9
EOP
8
EDP
7
6
VHPF
5
IHPF
4
iCPU
3
K3
2
K2
1
K1
0
K0
Default** = 0x000001
PC[6:0]
Phase compensation. A 2’s complement number which sets the delay in the voltage channel.
When MCLK=4.096 MHz and K=1, the phase adjustment range is about -2.8 to +2.8 degrees
and each step is about 0.04 degrees (assuming a power line frequency of 60 Hz). If (MCLK / K)
is not 4.096 MHz, the values for the range and step size should be scaled by the factor
4.096MHz / (MCLK / K).
Default setting is 0000000 = 0.0215 degrees phase delay at 60 Hz (when MCLK = 4.096 MHz).
Igain
Sets the gain of the current PGA
0 = gain is 10 (default)
1 = gain is 50
EWA
Allows the EOUT and EDIR pins to be configured as open-collector output pins.
0 = normal outputs (default)
1 = only the pull-down device of the EOUT and EDIR pins are active
[IMODE IINV] Soft interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = active low level (default)
01 = active high level
10 = falling edge (INT is normally high)
11 = rising edge (INT is normally low)
EPP
Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can
also be accessed using the Status Register.
0 = Normal operation of the EOUT and EDIR pins. (default)
1 = EOP and EDP bits control the EOUT and EDIR pins.
EOP
When EPP = 1, EOUT becomes a user defined pin, and EOP sets the value of the EOUT pin.
Default = '0'
EDP
When EPP = 1, EDIR becomes a user defined pin, EDP sets the value of the EDIR pin.
Default = '0'
VHPF
Control the use of the High Pass Filter on the voltage Channel.
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
IHPF
Control the use of the High Pass Filter on the Current Channel.
DS546F2
33
CS5461
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
iCPU
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = normal operation (default)
1 = minimize noise when CPUCLK is driving rising edge logic
K[3:0]
Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. Note that a value of “0000” will set K to 16 (not zero).
7.2 DC Current Offset Register and DC Voltage Offset Register
Address: 1 (DC Current Offset Register); 3 (DC Voltage Offset Register)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default** = 0.000
The DC Offset Registers are initialized to zero on reset, allowing for uncalibrated normal operation. If DC Offset
Calibration is performed, this register is updated after one computation cycle with the current or voltage offset if
the proper DC input signals are applied. DRDY will be asserted at the end of the calibration. This register may
be read and stored for future system offset compensation. The value is in the range ± full scale. The numeric
format of this register is two’s complement notation.
7.3 AC/DC Current Gain Register and AC/DC Voltage Gain Register
Address: 2 (Current Gain Register); 4 (Voltage Gain Register)
MSB
21
LSB
20
2-1
2-2
2-3
2-4
2-5
2-6
.....
2-16
2-17
2-18
2-19
2-20
2-21
2-22
Default** = 1.000
The Gain Registers are initialized to 1.0 on reset, allowing for uncalibrated normal operation. The Gain registers
hold the result of either the AC or DC gain calibrations, whichever was most recently performed. If DC calibration
is performed, the register is updated after one computation cycle with the system gain when the proper DC input
is applied. If AC calibration is performed, then after ~(6N + 30) A/D conversion cycles (where N is the value of
the Cycle-Count Register) the register(s) is updated with the system gain when the proper AC input is applied.
DRDY will be asserted at the end of the calibration. The register may be read and stored for future system gain
compensation. The value is in the range 0.0 ≤ Gain < 3.9999.
7.4 Cycle Count Register
Address: 5
MSB
223
LSB
222
221
220
219
218
217
216
.....
26
25
24
23
22
21
20
Default** = 4000
The Cycle Count Register value (denoted as ‘N’) determines the length of one energy and RMS computation
cycle. During continuous conversions, the computation cycle frequency is (MCLK/K)/(1024∗N).
34
DS546F2
CS5461
7.5 PulseRateE Register
Address: 6
MSB
218
LSB
217
216
215
214
213
212
211
.....
21
20
2-1
2-2
2-3
2-4
2-5
Default** = 32000.00 Hz
The PulseRateE Register determines the average frequency of the pulses issued on the EOUT output pin. The
register’s smallest valid value is 2-4 but can be in 2-5 increments. A pulserate higher than MCLK/K/8 will result
in a pulse rate setting of MCLK/K/8.
7.6 I, V, P, & PAvg: Instantaneous Current, Voltage, Power, and Average Power (Signed)
Output Register
Address: 7 - 10
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
These signed registers contain the last measured value of I, V, P, and PAVG. The results will be within in the
range of -1.0 ≤ I,V,P,PAvg< 1.0. The value is represented in two's complement notation, with the binary point
place to the right of the MSB (MSB has a negative weighting). These values are 22 bits in length. The two least
significant bits have no meaning, and will always have a value of “0”.
7.7 IRMS, VRMS Unsigned Output Register
Address: 11,12
MSB
2-1
LSB
2-2
2-3
2-4
2-5
2-6
2-7
2-8
.....
2-18
2-19
2-20
2-21
2-22
2-23
2-24
These unsigned registers contain the last values of IRMS and VRMS. The results are in the range of
0.0 ≤ IRMS,VRMS < 1.0. The value is represented in (unsigned) binary notation, with the binary point place to the
left of the MSB. These results are updated after each computation cycle.
7.8 Timebase Calibration Register
Address: 13
MSB
20
LSB
2
-1
2
-2
-3
2
-4
2
-5
2
-6
2
-7
2
.....
2-17
2
-18
2
-19
2
-20
2
-21
2
-22
2-23
Default** = 1.000
This register can be set with a clock frequency error compensation value, to correct for a gain/timing error
caused by the crystal/oscillator tolerance. The value is in the range 0.0 ≤ TBC < 2.0.
DS546F2
35
CS5461
7.9 Power Offset Register
Address:
14
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
.....
2-18
2-19
2-20
2-21
2-22
2-23
Default** = 0.000
This offset value is added to each power value that is computed for each voltage/current sample pair before
being accumulated in the Energy Register. This register can be used to offset contributions to the energy result
that are caused by undesirable sources of energy that are inherent in the system. This value is in two’s complement notation.
7.10 Status Register and Mask Register
Address:
15 (Status Register); 26 (Mask Register)
23
DRDY
22
EOUT
21
EDIR
20
CRDY
19
18
17
IOR
16
VOR
15
14
IROR
13
VROR
12
11
EOOR
10
9
8
7
6
5
4
VOD
3
IOD
2
LSD
1
VSAG
0
IC
Default** = 0x000000 (Status Register)
0x000000 (Mask Register)
The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit
to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user
can simply write to the Status Register to clear the bits that have been seen, without concern of clearing any
newly set bits. Even if a status bit is masked to prevent an interrupt, the status bit will still be set in the Status
Register.
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will
allow the corresponding bit in the Status Register to activate the INT pin when the status bit is asserted.
36
DRDY
Data Ready. When running in single or continuous conversion acquisition mode, this bit will indicate the end of computation cycles. When running calibrations, this bit indicates the end of a
calibration sequence.
EOUT
Indicates that the energy limit has been reached for the EOUT Energy Accumulation Register,
and so this register will be cleared, and one pulse will be generated on the EOUT pin (if enabled). If EOUT is asserted, this bit will be cleared automatically just after the beginning of any
subsequent A/D conversion cycle in which no EOUT pulses need to be issued. The bit can also
be cleared by writing to the Status Register. This status bit is set with a maximum frequency of
4 kHz (when MCLK/K is 4.096 MHz). When MCLK/K is not equal to 4.096 MHz, the user should
scale the pulse-rate would be expected with MCLK/K = 4.096 MHz by a factor of 4.096 MHz /
(MCLK/K), to get the actual pulse-rate.
EDIR
Set whenever the EOUT bit is asserted as long as the energy result is negative. Reset/Clear
behavior of the EDIR status bit is similar to the EOUT status bit.
IOR
Current Out of Range. Set when the magnitude of the calibrated current value is too large or
too small to fit in the Instantaneous Current Register.
DS546F2
CS5461
CRDY
Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate.
VOR
Voltage Out of Range.
VSAG
Indicates that the voltage threshold/duration conditions, specified in the VSAGlevel
and VSAGduration Registers, have been met.
VROR
RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the
RMS Voltage Register.
IROR
RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the
RMS Current Register.
EOOR
EOUT Energy Summation Register Out of Range. Assertion of this bit can be caused by having
a pulse output frequency that is too small for the power being measured. This problem can be
corrected by specifying a higher frequency in the PulseRateE register.
VOD
Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to
an input above Full Scale. Note that the level at which the modulator oscillates is significantly
higher than the voltage channel’s Differential Input Voltage Range.
IOD
Modulator oscillation detect on the current channel. Set when the modulator oscillates due to
an input above Full Scale. Note that the level at which the modulator oscillates is significantly
higher than the current channel’s Differential Input Voltage Range.
Note:
The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the
power line. This event should not be confused with a DC overload situation at the
inputs, when the IOD and VOD bits will re-assert themselves even after being
cleared, multiple times.
LSD
Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage threshold (PMLO), with respect to VA- pin. For a given part, PMLO can be as low as 2.3 V. LSD bit
cannot be permanently reset until the voltage at PFMON pin rises back above the high-voltage
threshold (PMHI), which is typically 100 mV above the device’s low-voltage threshold. PMHI will
never be greater than 2.7 V.
IC
Invalid Command. Normally logic 1. Set to logic 0 if the host interface is strobed with an 8-bit
word that is not recognized as one of the valid commands (see Section 6.1, Commands).
7.11 AC Current Offset Register and AC Voltage Offset Register
Address:
16 (AC Current Offset Register); 17 (AC Voltage Offset Register)
MSB
2-1
LSB
2
-2
2
-3
-4
2
-5
2
-6
2
-7
2
-8
2
.....
2-18
2
-19
2
-20
2
-21
2
-22
2
-23
2-24
Default** = 0x000000
The AC Offset Registers are initialized to zero on reset, allowing for uncalibrated normal operation. When AC
Offset Calibration is performed, the offset register(s) is updated with the square of the system AC offset value.
This sequence lasts ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register).
DRDY will be asserted at the end of the calibration. The register value may be read and stored for future system
offset compensation.
DS546F2
37
CS5461
7.12 PulseRateF Register
Address: 18
MSB
218
LSB
217
216
215
214
213
212
211
.....
21
20
2-1
2-2
2-3
2-4
2-5
Default** = 32000.00 Hz
The PulseRateF Register sets the average pulse frequency of the FOUT output pin. The register’s smallest valid
value is 2-4 but can be in 2-5 increments. A pulserate higher than MCLK/K/8 will result in a pulse rate setting of
MCLK/K/8.
7.13 Temperature Sensor Output Register
Address: 19
MSB
-(27)
LSB
26
25
24
23
22
21
20
.....
2-10
2-11
2-12
2-13
2-14
2-15
2-16
This signed register contains the output of the On-Chip Temperature Sensor. The results are in the range of
-128.0 ≤ T < 128.0. The value is represented in unsigned binary notation, with the binary point place to the left
of the MSB. This result is updated after each computation cycle.
7.14 Pulsewidth
Address: 21
MSB
223
LSB
222
221
220
219
218
217
216
.....
26
25
24
23
22
21
20
Default** = 512 sample periods
This signed register determines the pulsewidth of EOUT and EDIR pulses in Mechanical Counter Mode. The
width is set in number of sample periods. The default is 512. This corresponds to a pulsewidth of
512 samples / [(MCLK/K)/1024] = 128 msec with MCLK = 4.096 MHz and K = 1. Although this is a signed register a negative value will have no meaning; pulsewidth settings must be positive.
7.15 VSAGLevel: Voltage Sag-Detect Threshold Level
Address: 23
MSB
-(20)
2-1
LSB
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default** = 0x000000
This signed register sets the threshold level for the Voltage Sag Detect feature. To activate the VSAG bit the
Status Register, the value of the VRMS register must remain below this threshold level for a set number of samples (defined in the VSAGDuration Register). Voltage threshold levels must be positive values; a negative value
can be used to disable the feature. For more information about the voltage sag detect functionality, refer to Section 4.10 of the data sheet.
38
DS546F2
CS5461
7.16 VSAGDuration: Voltage Sag-Detect Duration Level
Address: 24
MSB
LSB
223
222
221
220
219
218
217
216
26
.....
25
24
23
22
21
20
Default** = 0x000000
This Register sets the number of conversions over to accumulate RMS voltage for comparison against the VSAGLEVEL. Setting this register to zero will disable the VSAG feature.
7.17 Control Register
Register Address: 28
23
22
21
20
19
18
17
16
15
14
13
12
11
10
FAC
9
EAC
8
STOP
7
6
MECH
5
4
INTOD
3
2
NOCPU
1
NOOSC
0
STEP
Default** = 0x000000
FAC
1 = enable anti-creep for FOUT pulse output function.
EAC
1 = enable anti-creep for EOUT pulse output function.
STOP
1 = used to terminate the new EEBOOT sequence.
MECH
1 = widens EOUT and EDIR pulses for mechanical counters.
INTOD
1 = Converts INT output to open drain configuration.
NOCPU
1 = saves power by disabling the CPUCLK external drive pin.
NOOSC
1 = saves power by disabling the crystal oscillator circuit.
STEP
1 = enables stepper-motor signals on the EOUT/EDIR pins.
DS546F2
39
CS5461
8. BASIC APPLICATION CIRCUITS
Figure 14 shows the CS5461 connected to a service
to measure power in a single-phase 2-wire system
while operating in a single supply configuration.
Note that in this diagram the shunt resistor used to
monitor the line current is connected on the “Line”
(hot) side of the power mains. In most residential
power metering applications, the power meter’s
current-sense shunt resistor is intentionally placed
on the hot side of the power mains in order to detect
a subscriber’s attempt to steal power. In this type of
shunt-resistor configuration, the common-mode
level of the CS5461 must be referenced to the hot
side of the power line; which means the common-mode potential of the CS5461 will typically
oscillate to very high voltage levels with respect to
earth ground potential. If digital communication
networks require that the CMOS-level digital interface be referenced to an earth ground, the serial in-
terface pins on the CS5461 must be isolated from
the external digital interface.
Figure 15 shows the same single-phase two-wire
system with complete isolation from the power
lines. This isolation is achieved using three transformers: a general purpose transformer to supply
the on-board DC power; a high-precision, low impedance voltage transformer, with very little
roll-off/phase-delay, to measure voltage; and a current transformer to sense the line current. Because
the CS5461 is not directly connected to the power
mains, no isolation is necessary on the CS5461’s
digital interface.
Figure 16 shows a single-phase 3-wire system. In
many 3-wire residential power systems within the
United States, only the two line terminals are available (neutral is not available). Figure 17 shows the
CS5461 configured to meter a three-wire system
with no neutral available.
10 kΩ
5 kΩ
120 VAC
N
L
500 Ω
10 Ω
500
100 µF
470 nF
0.1 µF
0.1 µF
14
VA+
3
VD+
CS5461
R2
VIN+
C V+
R1
R V-
10
15
VIN-
XIN
RESET
RShunt
R I+
16
C I+
IIN+
12
VREFIN
11
VREFOUT
0.1 µF
17
2
1
2.5 MHz to
20 MHz
Optional
Clock
Source
24
IIN-
R I-
To Service
PFMON
CPUCLK
XOUT
VA13
CS
SDI
SDO
SCLK
INT
EDIR
EOUT
19
7
23
6
5
ISOLATION
9
Serial
Data
Interface
20
22
21
DGND
4
Mech. Counter
or
Stepper Motor
Figure 14. Typical Connection Diagram (One-Phase 2-Wire, Direct Connect to
40
DS546F2
CS5461
10 kΩ
5 kΩ
120 VAC
N
L
Voltag
Transforme
e
r
200 Ω
10 Ω
200 Ω
0.1 µF
0.1µF
12 VAC
14
VA+
200µF
12 VAC
3
VD+
CS5461
M:1
9
1kΩ
R V+
C Vdiff
RV-
1kΩ
10
Low Phase-Shift
Potential Transformer
RI-
N:1
15
1kΩ
IIN-
1kΩ
16
RI+
12
11
0.1 µF
2.5 MHz to
20 MHz
Optional
Clock
Source
24
XIN
VIN-
19
RESET
7
CS
23
SDI
6
SDO
5
SCLK
C Idiff
RBurden
Current
Transformer
17
PFMON
2
CPUCLK
1
XOUT
VIN+
IIN+
20
INT
VREFIN
VREFOUT
22
EDIR
21
EOUT
VA13
Serial
Data
Interface
DGND
4
Mech. Counter
or
Stepper Motor
To Service
Figure 15. Typical Connection Diagram (One-Phase 2-Wire, Isolated from Power Line)
240 VAC
120 VAC
L1
5 kΩ
120 VAC
N
L2
500 Ω
500 Ω
10 Ω
100 µF
470 nF
0.1 µF
Earth
Ground
R2
3
VD+
VIN+
CIdiff
R4
R1
10
VIN16 IIN+
1kΩ
XIN
RESET
C Idiff
1kΩ
15
R I-
0.1 µF
To Service
17
PFMON
2
CPUCLK
1
XOUT
R I+
RBurden
To Service
0.1 µF
14
VA+
CS5461
9
R3
10 kΩ
IIN-
12
VREFIN
11
VREFOUT
VA13
2.5 MHz to
20 MHz
Optional
Clock
Source
24
19
7
CS
23
SDI
6
SDO
5
SCLK
20
INT
Serial
Data
Interface
22
EDIR
21
EOUT
DGND
4
Mech. Counter
or
Stepper Motor
Figure 16. Typical Connection Diagram (One-Phase 3-Wire)
DS546F2
41
CS5461
5 kΩ
240 VAC
L1
L2
500 Ω
1 kΩ
10 Ω
100 µF
235 nF
10 kΩ
0.1 µF
0.1 µF
3
VD+
14
VA+
CS5461
9
C V+
R2
R V-
10
16
1kΩ
VINIIN+
XIN
RESET
CS
SDI
SDO
SCLK
1kΩ
15
R I-
0.1 µF
To Service
2.5 MHz to
20 MHz
Optional
Clock
Source
24
R I+
RBurden
To Service
17
PFMON
2
CPUCLK
1
XOUT
IIN-
12
VREFIN
11
VREFOUT
VA13
INT
19
7
23
6
5
20
ISOLATION
R1
VIN+
Serial
Data
Interface
22
EDIR
21
EOUT
DGND
4
Mech. Counter
or
Stepper Motor
Figure 17. Typical Connection Diagram (One-Phase 3-Wire - No Neutral Avail-
42
DS546F2
CS5461
9. PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11
A2
E
e
b2
SIDE VIEW
A
∝
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.064
0.009
0.311
0.291
0.197
0.022
0.025
0°
INCHES
NOM
-0.006
0.068
-0.323
0.307
0.209
0.026
0.03
4°
MAX
0.084
0.010
0.074
0.015
0.335
0.323
0.220
0.030
0.041
8°
MIN
-0.05
1.62
0.22
7.90
7.40
5.00
0.55
0.63
0°
MILLIMETERS
NOM
-0.13
1.73
-8.20
7.80
5.30
0.65
0.75
4°
NOTE
MAX
2.13
0.25
1.88
0.38
8.50
8.20
5.60
0.75
1.03
8°
2,3
1
1
JEDEC #: MO-150
Controlling Dimension is Millimeters.
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS546F2
43
CS5461
10. REVISIONS
Revision
Date
A1
March 2003
Changes
Initial Release
PP1
13 October 2003 Initial release for Preliminary Product Information
PP2
5 December 2003 1) Added Auto-boot Feature Description (Page 1, 6, 12, 27, 28, 37, 13)
2) Added Mode Pin Functionality (Page 6, 12, 27)
F1
8 June 2004
1) Specification change: THD, Nv, PSRR (Page 8, 9, 10)
F2
10 Aug 2004
Changed Noise Spec from 125uV to 150uV.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet
available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and
reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind
(express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders,
that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No
responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or
sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by
furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights,
trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information
contained herein and gives consent for copies to be made of the information only for use within your organization with respect to
Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general
distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH,
PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS
PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY
APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER
CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR
AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS
UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY,
EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED W ARRANTIES OF MERCHANTABILITY AND FITNESS FOR
PARTICULAR PURPOSE, W ITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE
CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS,
EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND
COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in
this document may be trademarks or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
44
DS546F2
CS5461
DS546F2
45