AD AD8145YCPZ-R7 High speed, triple differential receiver with comparator Datasheet

High Speed, Triple Differential Receiver
with Comparators
AD8145
REF_G
2
GAIN_G
3
IN+_G
4
IN–_G
5
REF_R
6
GND
GAIN_B
VS–
IN+_B
25
+
–
AD8145
C
+
–
R
R
24
GND
23
OUT_B
22
OUT_G
21
OUT_R
20
VS+
19
COMPB_IN+
18
COMPB_IN–
17
GND
B
A
9
10
11
12
13
14
15
16
COMPA_IN+
COMPA_IN–
COMPA_OUT
COMPB_OUT
GND
–
IN–_R
8
R
+
GND
R
26
IN+_R
7
R
27
GND
GAIN_R
+
–
28
C
R
C
DIS/PD
IN–_B
29
REF_B
GND
30
06307-001
1
31
–
RGB video receivers
YPbPr video receivers
KVM (keyboard, video, mouse)
UTP (unshielded twisted pair) receivers
GND
32
+
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
+
High speed: 500 MHz, 2000 V/μs @ G = 1, VO = 2 V p-p
0.1 dB flatness out to 75 MHz
High CMRR: 69 dB @ 10 MHz
High differential input impedance: 1 MΩ
Wide input common-mode range: ± 3.8 V (±5 V supplies)
On-chip gain-setting resistors
Can be configured for gain of 1 or 2
Fast settling: 15 ns to 0.1% @ 2 V p-p
Low input referred noise: 13nV/√Hz
Disable feature
Small packaging: 32-lead, 5 mm × 5 mm LFCSP
–
FEATURES
Figure 1.
GENERAL DESCRIPTION
The AD8145 is a triple, low cost, differential-to-single-ended
receiver specifically designed for receiving red-green-blue
(RGB) video signals over twisted pair cable or differential
printed circuit board traces. It can also be used to receive any
type of analog signal or high speed data transmission. Two
auxiliary comparators with hysteresis are provided, which can
be used to decode video sync signals that are encoded on the
received common-mode voltages, to receive digital signals, or as
general-purpose comparators. The AD8145 can be used in
conjunction with the AD8133 or AD8134 triple differential
drivers to provide a complete low cost solution for RGB over
Category 5 UTP cable applications, including KVM.
The AD8145 can be configured for a differential-to-singleended gain of 1 or 2 by connecting the GAIN pin of each
channel to its respective output (G = 1) or connecting it to a
reference voltage (G = 2), which is normally grounded.
A REF input is provided on each channel that allows designers
to level shift the output signals.
The AD8145 is available in a 5 mm × 5 mm, 32-lead LFCSP and
is rated to work over the extended industrial temperature range
of −40°C to +105°C.
The excellent common-mode rejection (69 dB @ 10 MHz) of
the AD8145 allows for the use of low cost, unshielded twisted
pair cables in noisy environments.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8145
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications..................................................................................... 15
Applications....................................................................................... 1
Overview ..................................................................................... 15
Functional Block Diagram .............................................................. 1
Basic Closed-Loop Gain Configurations ................................ 15
General Description ......................................................................... 1
Terminating the Input................................................................ 16
Revision History ............................................................................... 2
Input Clamping........................................................................... 17
Specifications..................................................................................... 3
Printed Circuit Board Layout Considerations ....................... 18
Absolute Maximum Ratings............................................................ 7
Driving a Capacitive Load......................................................... 19
Thermal Resistance ...................................................................... 7
Power-Down ............................................................................... 19
ESD Caution.................................................................................. 7
Comparators ............................................................................... 20
Pin Configuration and Function Description .............................. 8
Sync Pulse Extraction Using Comparators............................. 20
Typical Performance Characteristics ............................................. 9
Outline Dimensions ....................................................................... 21
Theory of Operation ...................................................................... 14
Ordering Guide .......................................................................... 21
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8145
SPECIFICATIONS
TA = 25°C, VS = ±5 V, REF = 0 V, RL = 150 Ω, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +105°C, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Output Overdrive Recovery
NOISE/DISTORTION
Second Harmonic
Third Harmonic
Crosstalk
Input Voltage Noise (RTI)
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Common-Mode Rejection
Common-Mode Voltage Range
Differential Operating Range
Resistance
Capacitance
DC PERFORMANCE
Closed-Loop Gain
Output Offset Voltage
Input Bias Current (+IN, −IN)
Input Bias Current Drift
Input Offset Current
OUTPUT PERFORMANCE
Voltage Swing
Output Current
Short-Circuit Current
Conditions
Min
Typ
Max
Unit
VOUT = 0.2 V p-p
VOUT = 2 V p-p
VOUT = 0.2 V p-p, G = 2
VOUT = 2 V p-p, G = 2
VOUT = 2 V p-p
VOUT = 2 V p-p, G = 2
VOUT = 2 V p-p
VOUT = 2 V p-p, G = 2
VOUT = 2 V p-p, 0.1%
530
500
200
200
75
100
2100
2100
15
20
MHz
MHz
MHz
MHz
MHz
MHz
V/μs
V/μs
ns
ns
VOUT = 2 V p-p, 1 MHz
VOUT = 2 V p-p, 1 MHz
VOUT = 2 V p-p, 10 MHz
f ≥ 10 kHz
NTSC, 200 IRE, RL ≥ 150 Ω
NTSC, 200 IRE, RL ≥ 150 Ω
−67
−88
−62
13
0.25
0.1
dBc
dBc
dB
nV/√Hz
%
Degrees
81
90
69
41
±3.5
±2.5
1
1.3
1
2
dB
dB
dB
V
V
MΩ
MΩ
pF
pF
1.955
−17.5
1.985
7.0
−18
−3.4
25
−65
DC, VCM = −3.5 V to +3.5 V
VCM = 1 V p-p, f = 10 MHz
VCM = 1 V p-p, f = 100 MHz
V+IN − V−IN = 0 V
Differential
Common mode
Differential
Common mode
DC, G = 2
G=2
TMIN to TMAX
6
TMIN to TMAX (+IN, −IN)
−400
−4.04
Short to GND, source/sink
Rev. 0 | Page 3 of 24
2.020
1.0
−0.9
300
3.55
50
195/−230
V/V
mV
μV/°C
μA
nA/°C
nA
V
mA
mA
AD8145
Parameter
COMPARATOR PERFORMANCE
VOH
VOL
Input Offset Voltage
Hysteresis Width
Input Bias Current
Propagation Delay, tPLH
Propagation Delay, tPHL
Rise Time
Fall Time
POWER-DOWN PERFORMANCE
Power-Down VIH
Power-Down VIL
Power-Down IIH
Power-Down IIL
Power-Down Assert Time
POWER SUPPLY
Operating Range
Quiescent Current, Positive Supply
Conditions
Min
Typ
RL = 1 kΩ
RL = 1 kΩ
3.205
3.310
0.390
±2.5
18
1.5
6
6
6
2
10% to 90%
10% to 90%
0.420
VS+ − 1.65
VS+ − 2.65
0.5
−250
1
4.5
Disabled
Quiescent Current, Negative Supply
PSRR, Positive Supply
PSRR, Negative Supply
Max
−52
−13.9
Disabled
DC
DC
Rev. 0 | Page 4 of 24
48.5
16
−43.5
−11
−79
−68
Unit
V
V
mV
mV
μA
ns
ns
ns
ns
V
V
μA
μA
μs
11
57.5
19.5
−70
−57
V
mA
mA
mA
mA
dB
dB
AD8145
TA = 25°C, VS = ±2.5 V, REF = 0 V, RL = 1 kΩ, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +105°C, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Output Overdrive Recovery
NOISE/DISTORTION
Second Harmonic
Third Harmonic
Crosstalk
Input Voltage Noise (RTI)
INPUT CHARACTERISTICS
Common-Mode Rejection
Common-Mode Voltage Range
Differential Operating Range
Resistance
Capacitance
DC PERFORMANCE
Closed-Loop Gain
Output Offset Voltage
Input Bias Current (+IN, −IN)
Input Bias Current Drift
Input Offset Current
OUTPUT PERFORMANCE
Voltage Swing
Output Current
Short-Circuit Current
POWER-DOWN PERFORMANCE
Power-Down VIH
Power-Down VIL
Power-Down IIH
Power-Down IIL
Power-Down Assert Time
Conditions
Min
Typ
Max
Unit
VOUT = 0.2 V p-p
VOUT = 2 V p-p
VOUT = 0.2 V p-p, G = 2, RL = 150 Ω
VOUT = 2 V p-p, G = 2, RL = 150 Ω
VOUT = 2 V p-p
VOUT = 2 V p-p, G = 2, RL = 150 Ω
VOUT = 2 V p-p
VOUT = 2 V p-p, G = 2, RL = 150 Ω
VOUT = 2 V p-p, 0.1%
450
425
180
180
53
100
2000
2000
16
10
MHz
MHz
MHz
MHz
MHz
MHz
V/μs
V/μs
ns
ns
VOUT = 1 V p-p, 1 MHz
VOUT = 1 V p-p, 1 MHz
VOUT = 1 V p-p, 10 MHz
f ≥ 10 kHz
−71
−76
−62
13
dBc
dBc
dB
nV/√Hz
78
86
72
43
±1.25
±1.6
1
1.3
1
2
dB
dB
dB
V
V
MΩ
MΩ
pF
pF
1.960
−13.5
1.985
−4.5
−18
−3.5
25
−60
DC, VCM = −3.5 V to +3.5 V
VCM = 1 V p-p, f = 10 MHz
VCM = 1 V p-p, f = 100 MHz
V+IN − V−IN = 0 V
Differential
Common mode
Differential
Common mode
DC, G = 2
G=2
TMIN to TMAX
−6
TMIN to TMAX (+IN, −IN)
−400
RL = 150 Ω/1 kΩ
Short to GND, source/sink
Rev. 0 | Page 5 of 24
−1.35
2.016
2
−0.9
300
1.3
V/V
mV
μV/°C
μA
nA/°C
nA
25
100/−100
V
mA
mA
VS+ − 1.5
VS+ − 2.5
0.25
50
1
V
V
μA
μA
μs
AD8145
Parameter
POWER SUPPLY
Operating Range
Quiescent Current, Positive Supply
Conditions
Min
4.5
Disabled
Quiescent Current, Negative Supply
PSRR, Positive Supply
PSRR, Negative Supply
Typ
−43.5
−12.5
Disabled
DC
DC
Rev. 0 | Page 6 of 24
40
13.5
−36
−10
−83
−67
Max
Unit
11
47
16
V
mA
mA
−73
−62
dB
dB
AD8145
ABSOLUTE MAXIMUM RATINGS
Maximum Power Dissipation
Table 3.
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature Range (Soldering 10 sec)
Junction Temperature
Rating
12 V
See Figure 2
–65°C to +125°C
–40°C to +105°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface, which is
thermally connected to a copper plane.
Table 4. Thermal Resistance
Package Type
5 mm × 5 mm, 32-Lead LFCSP
θJA
47
θJC
8.5
Unit
°C/W
MAXIMUM POWER DISSIPATION (W)
4.5
4.0
The maximum safe power dissipation in the AD8145 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8145. Exceeding a junction temperature
of 150°C for an extended period of time can result in changes in
the silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through-holes, ground, and power planes reduces
the θJA. The exposed paddle on the underside of the package
must be soldered to a pad on the PCB surface, which is
thermally connected to a copper plane to achieve the specified θJA.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 32-lead LFCSP
(47°C/W) on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad, which is thermally
connected to a PCB plane.
3.5
3.0
2.5
2.0
1.5
ESD CAUTION
1.0
0
–40
–20
0
20
40
60
AMBIENT TEMPERATURE (°C)
80
100
06307-002
0.5
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
Rev. 0 | Page 7 of 24
AD8145
32
31
30
29
28
27
26
25
GND
IN–_B
IN+_B
GAIN_B
REF_B
DIS/PD
VS–
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD8145
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
GND
OUT_B
OUT_G
OUT_R
VS+
COMPB_IN+
COMPB_IN–
GND
NOTES
1. EXPOSED PAD ON UNDERSIDE OF DEVICE
MUST BE CONNECTED TO GROUND.
06307-003
GND
IN+_R
IN–_R
COMPA_IN+
COMPA_IN–
COMPA_OUT
COMPB_OUT
GND
9
10
11
12
13
14
15
16
GND
REF_G
GAIN_G
IN+_G
IN–_G
REF_R
GAIN_R
GND
Figure 3. 32-Lead LFCSP Pin Configuration
Table 5. 32-Lead LFCSP Pin Function Descriptions
Pin No.
1, 8, 9,16, 17, 24, 25, 32
2
3
4
5
6
7
10
11
12
13
14
15
18
19
20
21
22
23
26
27
28
29
30
31
Exposed Underside Pad
Mnemonic
GND
REF_G
GAIN_G
IN+_G
IN−_G
REF_R
GAIN_R
IN+_R
IN−_R
COMPA_IN+
COMPA_INCOMPA_OUT
COMPB_OUT
COMPB_INCOMPB_IN+
VS+
OUT_R
OUT_G
OUT_B
VS−
DIS/PD
REF_B
GAIN_B
IN+_B
IN−_B
GND
Description
Signal Ground and Thermal Plane Connection. (See the Absolute Maximum Ratings section.)
Reference Input, Green Channel.
Gain Connection, Green Channel.
Noninverting Input, Green Channel.
Inverting Input, Green Channel.
Reference Input, Red Channel.
Gain Connection, Red Channel.
Noninverting Input, Red Channel.
Inverting Input, Red Channel.
Positive Input, Comparator A.
Negative Input, Comparator A.
Output, Comparator A.
Output, Comparator B.
Negative Input, Comparator B.
Positive Input, Comparator B.
Positive Power Supply.
Output, Red Channel.
Output, Green Channel.
Output, Blue Channel.
Negative Power Supply.
Disable/Power Down.
Reference Input, Blue Channel.
Gain Connection, Blue Channel.
Noninverting Input, Blue Channel.
Inverting Input, Blue Channel.
Signal Ground and Thermal Plane Connection.
Rev. 0 | Page 8 of 24
AD8145
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, G = 1, RL = 150 Ω, CL = 2 pF, REF = midsupply, VS = ±5 V, TA = 25°C. Refer to the circuit in Figure 35.
3
3
2
2
+5V
+5V
1
1
0
–1
–2
–3
–3
–4
–5
–6
VOUT = 0.2V p-p
10
1000
100
–7
06307-004
Figure 4. Small Signal Frequency Response at Various Power Supplies, G = 1
8
7
7
6
6
5
5
GAIN (dB)
8
4
3
3
1
1
1000
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response at Various Power Supplies, G = 2
2
2
1
1
0
0
–1
–1
GAIN (dB)
CL = 10 + 2pF, RSNUB = 20Ω
CL = 0 + 2pF, RSNUB = 0Ω
CL = 10 + 2pF, RSNUB = 20Ω
CL = 0 + 2pF, RSNUB = 0Ω
–3
–4
–5
–5
–6
VOUT = 0.2V p-p
1
10
100
1000
FREQUENCY (MHz)
06307-006
–7
G
G
G
G
–2
–4
–6
100
1000
Figure 8. Large Signal Frequency Response at Various Power Supplies, G = 2
3
–3
10
FREQUENCY (MHz)
3
= 2,
= 2,
= 1,
= 1,
VOUT = 2V p-p
1
06307-008
100
–1
06307-005
10
G
G
G
G
±5V
0
VOUT = 0.2V p-p
–2
+5V
±5V
2
1
1000
4
2
0
100
Figure 7. Large Signal Frequency Response at Various Power Supplies, G = 1
9
–1
10
1
FREQUENCY (MHz)
9
+5V
VOUT = 2V p-p
Figure 6. Small Signal Frequency Response at Various Gains
and 10 pF Capacitive Load Buffered by 20 Ω Resistor
–7
= 2,
= 2,
= 1,
= 1,
CL = 10 + 2pF, RSNUB = 20Ω
CL = 0 + 2pF, RSNUB = 0Ω
CL = 10 + 2pF, RSNUB = 20Ω
CL = 0 + 2pF, RSNUB = 0Ω
VOUT = 2V p-p
1
10
100
1000
FREQUENCY (MHz)
Figure 9. Large Signal Frequency Response at Various Gains
and 10 pF Capacitive Load Buffered by 20 Ω Resistor
Rev. 0 | Page 9 of 24
06307-009
1
FREQUENCY (MHz)
GAIN (dB)
–2
–5
–7
GAIN (dB)
–1
–4
–6
±5V
06307-007
±5V
GAIN (dB)
GAIN (dB)
0
AD8145
3
3
2
2
1
G=1
0
–1
–1
GAIN (dB)
0
–2
G=2
–3
–3
–5
–5
–6
10
1
100
1000
FREQUENCY (MHz)
–7
INPUT VOLTAGE NOISE (nV/ Hz)
G = 1, VS = ±5V
0.2
0.1
0
G = 2, VS = +5V
G = 2, VS = ±5V
–0.2
–0.3
–0.4
VOUT = 2V p-p
10
1
100
1000
FREQUENCY (MHz)
100
10
0.01
06307-011
–0.5
0.1
1
10
100
1000
100000
10000
FREQUENCY (kHz)
Figure 14. Input Referred Voltage Noise vs. Frequency
Figure 11. 0.1 dB Flatness for Various Power Supplies and Gains
110
4
100
3
90
OUTPUT VOLTAGE (V)
80
VS = +5V
70
VS = ±5V
60
50
40
RL = OPEN CIRCUIT
G=1
VS = ±5V
2
1
0
–1
–2
30
–3
10
0.1
1
10
FREQUENCY (MHz)
100
1000
06307-012
20
Figure 12. Common-Mode Rejection vs. Frequency at Various Supplies
Rev. 0 | Page 10 of 24
–4
–5
–4
–3
–2
–1
0
1
2
3
DIFFERENTIAL INPUT VOLTAGE (V)
Figure 15. Differential Input Operating Range
4
5
06307-047
COMMON-MODE REJECTION (dB)
1000
1000
0.3
–0.1
100
Figure 13. Large Signal Frequency Response at Various Gains
G = 1, VS = +5V
0.4
10
1
FREQUENCY (MHz)
Figure 10. Small Signal Frequency Response at Various Gains
0.5
VOUT = 2V p-p
06307-013
VOUT = 0.2V p-p
06307-046
–7
GAIN (dB)
G=2
–4
–6
G=1
–2
–4
06307-010
GAIN (dB)
1
AD8145
150
1.5
100
1.0
BLACK = +5V
GRAY = ±5V
0.5
VOLTAGE (V)
50
0
0
–50
–0.5
–100
–1.0
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
–1.5
Figure 16. Small Signal Transient Response at Various Power Supplies, G = 1
0
10
20
30
80
90
100
1.0
BLACK = +5V
GRAY = ±5V
0.5
VOLTAGE (V)
50
0
0
–50
–0.5
–100
–1.0
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
–1.5
Figure 17. Small Signal Transient Response at Various Power Supplies, G = 2
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
06307-020
VOUT = 2V p-p
VOUT = 0.2V p-p
06307-017
VOLTAGE (mV)
70
1.5
BLACK = +5V
GRAY = ±5V
Figure 20. Large Signal Transient Response at Various Power Supplies, G = 2
150
1.5
G = 1, CL = 0 + 2pF, RSNUB = 0Ω
G = 1, CL = 10 + 2pF, RSNUB = 20Ω
G = 1, CL = 0 + 2pF, RSNUB = 0Ω
G = 1, CL = 10 + 2pF, RSNUB = 20Ω
100
1.0
0.5
VOLTAGE (V)
50
VOUT = 0.2V p-p
0
–50
VOUT = 2V p-p
0
–0.5
–100
–1.0
G = 2, CL = 0 + 2pF, RSNUB = 0Ω
G = 2, CL = 10 + 2pF, RSNUB = 20Ω
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
06307-018
VOLTAGE (mV)
60
Figure 19. Large Signal Transient Response at Various Power Supplies, G = 1
100
–150
50
TIME (ns)
150
–150
40
06307-019
VOUT = 2V p-p
VOUT = 0.2V p-p
Figure 18. Small Signal Transient Response at Various Gains
and 10 pF Capacitive Load Buffered by 20 Ω Resistor
–1.5
G = 2, CL = 0 + 2pF, RSNUB = 0Ω
G = 2, CL = 10 + 2pF, RSNUB = 20Ω
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
Figure 21. Large Signal Transient Response at Various Gains
and 10 pF Capacitive Load Buffered by 20 Ω Resistor
Rev. 0 | Page 11 of 24
06307-021
–150
06307-016
VOLTAGE (mV)
BLACK = +5V
GRAY = ±5V
AD8145
4000
1.2
0.3
0.8
0.2
0.1
0.4
ERROR
0
0
2500
2000
–0.1
–0.8
–0.2
–1.2
–0.3
–1.6
–0.4
500
–0.5
50
0
0
5
10
15
20
25
30
35
40
45
1500
1000
TIME (ns)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 25. Slew Rate vs. Input Voltage Swing
–50
–50
–60
–55
VS = +5V
–70
–60
–65
DISTORTION (dBc)
VS = ±5V
–70
–80
VS = ±5V
–90
–100
VS = +5V
–75
–110
VOUT = 2V p-p
1
10
100
FREQUENCY (MHz)
VOUT = 2V p-p
–120
0.1
06307-023
–80
0.1
Figure 23. Second Harmonic Distortion vs. Frequency and Power Supplies,
VO = 2 V p-p, G = 1
1
100
10
FREQUENCY (MHz)
06307-026
DISTORTION (dBc)
0
OUTPUT VOLTAGE (V p-p)
Figure 22. Settling Time
–50
NEGATIVE
SLEW RATE
3000
–0.4
–2.0
POSITIVE
SLEW RATE
3500
06307-048
VOLTAGE (V)
0.4
06307-049
OUTPUT
INPUT
4500
SLEW RATE (V/µs)
1.6
0.5
ERROR (%)
2.0
Figure 26. Third Harmonic Distortion vs. Frequency and Power Supplies,
VO = 2 V p-p, G = 1
–50
VOUT = 2V p-p
–60
–55
VS = +5V
DISTORTION (dBc)
–60
–65
VS = ±5V
–75
–80
0.1
–90
–100
VS = +5V
1
VS = ±5V
–80
–110
10
FREQUENCY (MHz)
100
VOUT = 2V p-p
–120
0.1
Figure 24. Second Harmonic Distortion vs. Frequency and Power Supplies,
VO = 2 V p-p, G = 2
1
10
FREQUENCY (MHz)
100
06307-027
–70
06307-024
DISTORTION (dBc)
–70
Figure 27. Third Harmonic Distortion vs. Frequency and Power Supplies,
VO = 2 V p-p, G = 2
Rev. 0 | Page 12 of 24
AD8145
4
3
ICC (±5V)
50
2
VOLTAGE (V)
SUPPLY CURRENT (mA)
55
IEE (±5V)
45
40
35
IEE (±2.5V)
30
25
1
0
–1
+5V OUTPUT
–2
+5V 2 × VIN
–3
ICC (±2.5V)
20
–4
15
–60
–5
±5V OUTPUT
±5V 2 × VIN
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
06307-050
G=2
0
10
0
0
–10
–10
PSRR (dB)
BLACK = +5V
GRAY = ±5V
–30
–40
–50
–30
250
300
350
400
450
500
1000
–50
–60
–70
–70
–80
–80
0.1
1
10
100
1000
FREQUENCY (MHz)
3.5
3.0
2.5
2.0
1.5
1.0
0
5
VIN (mV)
10
15
06307-051
0.5
–5
–90
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 32. Negative Power Supply Rejection Ratio vs. Frequency
Figure 29. Positive Power Supply Rejection Ratio vs. Frequency
–10
BLACK = ±2.5V
GRAY = ±5V
–40
–60
06307-029
PSRR (dB)
200
–20
–20
VOUT (V)
150
Figure 31. Output Overdrive Recovery
10
0
–15
100
TIME (ns)
Figure 28. Power Supply Current vs. Temperature
–90
0.01
50
06307-030
60
5
RL = OPEN CIRCUIT
06307-032
65
Figure 30. Comparator Hysteresis
Rev. 0 | Page 13 of 24
AD8145
THEORY OF OPERATION
The AD8145 amplifiers use an architecture called active feedback,
which differs from that of conventional op amps. The most
obvious differentiating feature is the presence of two separate
pairs of differential inputs compared to a conventional op amp’s
single pair. Typically, for the active-feedback architecture, one of
these input pairs is driven by a differential input signal, while
the other is used for the feedback. This active stage in the feedback
path is where the term active feedback is derived. The AD8145
has an internal feedback resistor from each amplifier output to
the negative input of its feedback input stage. This limits the
possible closed-loop gain configurations for the AD8145.
The active feedback architecture offers several advantages over a
conventional op amp in several types of applications. Among
these are excellent common-mode rejection, wide input commonmode range, and a pair of inputs that are high impedance and
completely balanced in a typical application. In addition, while
an external feedback network establishes the gain response as in
a conventional op amp, its separate path makes it entirely
independent of the signal input. This eliminates any interaction
between the feedback and input circuits, which traditionally
causes problems with CMRR in conventional differential-input
op amp circuits.
The two differential input stages of the AD8145 are each
transconductance stages that are well matched. These stages
convert the respective differential input voltages to internal
currents. The currents are then summed and converted to a
voltage, which is buffered to drive the output. The compensation
capacitor is included in the summing circuit. When the
feedback path is closed around the part, the output drives
the feedback input to that voltage which causes the internal
currents to sum to zero. This occurs when the two differential
inputs are equal and opposite; that is, their algebraic sum is zero.
In a closed-loop application, a conventional op amp has its
differential input voltage driven to near zero under nontransient conditions. The AD8145 generally has differential
input voltages at each of its input pairs, even under equilibrium
conditions. As a practical consideration, it is necessary to
internally limit the differential input voltage with a clamp
circuit. Thus, the input dynamic ranges are limited to about
2.5 V for the AD8145 (see the Specifications section for more
detail). For this and other reasons, it is not recommended to
reverse the input and feedback stages of the AD8145, even
though some apparently normal functionality may be observed
under some conditions.
Another advantage of active feedback is the ability to change the
polarity of the gain merely by switching the differential inputs.
A high input impedance inverting amplifier can therefore be
made. Besides high input impedance, a unity-gain inverter with
the AD8145 has noise gain of unity, producing lower output
noise and higher bandwidth than op amps that have noise gain
equal to 2 for a unity-gain inverter.
Rev. 0 | Page 14 of 24
AD8145
APPLICATIONS
+5V
OVERVIEW
The AD8145 contains three independent active feedback amplifiers
that can be effectively applied as differential line receivers for
red-green-blue (RGB) signals or component video signals, such
as YPbPr, transmitted over unshielded twisted pair (UTP) cable.
The AD8145 also contains two general-purpose comparators
with hysteresis that can be used to receive digital signals or to
extract video synchronization pulses from received commonmode signals that contain encoded synchronization signals.
0.01µF
VIN
OUT
VOUT
REF
VREF
R
The comparators, which receive power from the positive
supply, are referenced to GND and require greater than 4.5 V
on the positive supply for proper operation. If the comparators
are not used, then a split ±2.5 V can be used with the amplifiers
operating normally.
GAIN
C
06307-034
The AD8145 includes a power-down feature that can be
asserted to reduce the supply current when a particular device
is not in use.
R
0.01µF
–5V
Figure 33. Basic Gain = 1 Circuit: VOUT = VIN + VREF
The gain equation for the circuit in Figure 33 is
BASIC CLOSED-LOOP GAIN CONFIGURATIONS
VOUT = VIN + VREF
The AD8145 contains on-chip feedback networks between each
amplifier output and its respective feedback input. Closed-loop
gain of an amplifier is set to 1 by connecting the amplifier output
directly to its respective GAIN pin. Doing this places the onchip resistors and capacitor in parallel across the amplifier
output and feedback pin. The small feedback capacitor
mitigates the effects of summing-node capacitance, which is
most problematic in the unity gain case. Closed-loop gain of an
amplifier is set to 2 by connecting the respective GAIN pin to a
reference voltage, often directly to ground. In Figure 1, R = 350 Ω
and C = 2 pF.
(1)
In this configuration, the voltage applied to the REF pin appears
at the output with a gain of 1.
Figure 34 illustrates one way to operate an AD8145 amplifier
with a gain of 2.
+5V
0.01µF
VIN
REF
VREF
VOUT
C
GAIN
R
R
0.01µF
–5V
06307-035
Each amplifier in the AD8145 comprises two transconductance
amplifiers—one for the input signal and one for negative feedback.
It is important to note that the closed-loop gain of the amplifier
used in the signal path is defined as the single-ended output
voltage of the amplifier divided by its differential input voltage.
Therefore, each amplifier in the AD8145 provides differentialto-single-ended gain. Additionally, the amplifier used for
feedback has two high impedance inputs—the feedback input,
where the negative feedback is applied, and the REF input,
which can be used as an independent single-ended input to
apply a dc offset to the output signal.
Figure 34. Basic Gain = 2 Circuit: VOUT = 2(VIN + VREF)
The gain equation for the circuit in Figure 34 is
Some basic gain configurations implemented with an AD8145
amplifier are shown in Figure 33 through Figure 36.
Rev. 0 | Page 15 of 24
VOUT = 2(VIN + VREF)
(2)
AD8145
To achieve unity gain from VREF to VOUT in this configuration,
divide VREF by the same factor used in the feedback loop; the
divider resistors, RD, need not be the same values used in the
internal feedback loop. Figure 35 illustrates this approach.
TERMINATING THE INPUT
One of the key benefits of the active feedback architecture is the
separation that exists between the differential input signal and
the feedback network. Because of this separation, the differential
input maintains its high CMRR and provides high differential
and common-mode input impedances, making line termination
a simple task.
+5V
0.01µF
Most applications that use the AD8145 involve transmitting
broadband video signals over 100 Ω UTP cable and use
dc-coupled terminations. The two most common types of
dc-coupled terminations are differential and common-mode.
Differential termination of 100 Ω UTP is implemented by
simply connecting a 100 Ω resistor across the amplifier input,
as shown in Figure 37.
VIN
RD
RD
GAIN
VOUT
C
R
R
+5V
06307-036
VREF
REF
0.01µF
–5V
0.01µF
Figure 35. Basic Gain Circuit: VOUT = 2VIN + VREF
100Ω
UTP
The gain equation for the circuit in Figure 35 is
VOUT = 2VIN + VREF
100Ω
VIN
(3)
OUT
VOUT
REF
Another configuration that provides the same gain equation as
Equation 3 is shown in Figure 36. In this configuration, it is
important to keep the source resistance of VREF much smaller
than 350 Ω to avoid gain errors.
R
R
+5V
GAIN
C
06307-038
0.01µF
0.01µF
–5V
VIN
Figure 37. Differential-Mode Termination with G = 1
VOUT
Some applications require common-mode terminations for
common-mode currents generated at the transmitter. In these
cases, the 100 Ω termination resistor is split into two 50 Ω
resistors. The required common-mode termination voltage is
applied at the tap between the two resistors. In many of these
applications, the common-mode tap is connected to ground
(VTERM (CM) = 0). This scheme is illustrated in Figure 38.
C
R
VREF
0.01µF
–5V
06307-037
R
GAIN
Figure 36. Basic Gain Circuit: VOUT = 2VIN + VREF
+5V
For stability reasons, the inductance of the trace connected to
the REF pin must be kept to less than 10 nH. The typical
inductance of 50 Ω traces on the outer layers of the FR-4 boards
is 7 nH/in, and on the inner layers, it is typically 9 nH/in. Vias
must be accounted for as well. The inductance of a typical via in
a 0.062 inch board is on the order of 1.5 nH. If longer traces are
required, a 200 Ω resistor should be placed in series with the
trace to reduce the Q-factor of the inductance.
0.01µF
50Ω
100Ω
UTP
VIN
50Ω
VTERM (CM)
OUT
VOUT
REF
R
In many dual-supply applications, VREF can be directly
connected to ground right at the device.
R
GAIN
C
0.01µF
–5V
Figure 38. Common-Mode Termination with G = 1
Rev. 0 | Page 16 of 24
06307-039
REF
AD8145
INPUT CLAMPING
The differential input that is assigned to receive the input signal
includes clamping diodes that limit the differential input swing
to approximately 5.5 V p-p at 25°C. Because of this, the input
and feedback stages should never be interchanged.
The supply current drawn by the AD8145 has a strong
dependence on input signal magnitude because the input
transconductance stages operate with differential input signals
that can be up to a few volts peak-to-peak. This behavior is
distinctly different from that of traditional op amps, where the
differential input signal is driven to essentially 0 V by negative
feedback.
For most applications, including receiving RGB video signals,
the input signal magnitudes encountered are well within the
safe operating limits of the AD8145 over its full power supply
and operating temperature ranges. In some extreme applications
where large differential and/or common-mode voltages are
encountered, external clamping may be necessary. Another
application in which external common-mode clamping is
sometimes required is when an unpowered AD8145 receives a
signal from an active driver. In this case, external diodes are
required when the current drawn by the internal ESD diodes
cannot be kept to less than 5 mA.
A diode is a simple example of such a clamp. Schottky diodes
generally have lower clamping voltages than typical signal
diodes. The clamping voltage should be larger than the largest
expected signal amplitude, with enough margin to ensure that
the received signal passes without being distorted.
A simple way to implement a clamp is to use a number of
diodes in series. The resultant clamping voltage is then the sum
of the clamping voltages of individual diodes.
A 1N4448 diode has a forward voltage of approximately 0.70 V
to 0.75 V at typical current levels that are seen when it is being
used as a clamp, and 2 pF maximum capacitance at 0 V bias.
(The capacitance of a diode decreases as its reverse bias voltage
is increased.) The series connection of two 1N4448 diodes,
therefore, has a clamping voltage of 1.4 V to 1.5 V. Figure 40
shows how to limit the differential input voltage applied to an
AD8145 amplifier to ±1.4 V to ±1.5 V (2.8 V p-p to 3.0 V p-p).
Note that the capacitance of the two series diodes is half that of
one diode. Different numbers of series diodes can be used to
obtain different clamping voltages.
RT is the differential termination resistor, and the series
resistances, RS, limit the current into the diodes. The series
resistors should be highly matched in value to preserve high
frequency CMRR.
+5V
Figure 39 shows a general approach to external differentialmode clamping.
POSITIVE CLAMP NEGATIVE CLAMP
+
VIN
–
POSITIVE CLAMP
+
+5V
VIN
0.01µF
RS
–
NEGATIVE CLAMP
0.01µF
RS
RT
OUT
RS
VOUT
REF
RT
OUT
RS
VOUT
REF
R
R
R
GAIN
C
0.01µF
GAIN
C
0.01µF
–5V
06307-040
–5V
Figure 39. Differential-Mode Clamping with G = 1
The positive and negative clamps are nonlinear devices that
exhibit very low impedance when the voltage across them
reaches a critical threshold (clamping voltage), thereby limiting
the voltage across the AD8145 input. The positive clamp has a
positive threshold, and the negative clamp has a negative
threshold.
06307-041
R
Figure 40. Using Two 1N4448 Diodes in Series as a Clamp
There are many other nonlinear devices that can be used as
clamps. The best choice for a particular application depends
upon the desired clamping voltage, response time, parasitic
capacitance, and other factors.
When using external differential-mode clamping, it is
important to ensure that the series resistors (RS), the sum of
the parasitic capacitance of the clamping devices, and the input
capacitance of the AD8145 are small enough to preserve the
desired signal bandwidth.
Rev. 0 | Page 17 of 24
AD8145
Figure 41 shows a specific example of external common-mode
clamping.
V+
2
RS
HBAT-540C
VIN
–
+5V
3
+
RT
0.01µF
1
V–
V+
2
RS
HBAT-540C
OUT
3
VOUT
REF
Broadband power supply decoupling networks should be placed
as close as possible to the supply pins. Small surface-mount
ceramic capacitors are recommended for these networks, and
tantalum capacitors are recommended for bulk supply
decoupling.
R
1
V–
R
0.01µF
–5V
06307-042
GAIN
C
Typically, the input signals are received over 100 Ω differential
transmission lines. A 100 Ω differential transmission line is
readily realized on the printed circuit board using two wellmatched, closely-spaced, 50 Ω single-ended traces that are
coupled through the ground plane. The traces that carry the
single-ended output signals are most often 75 Ω for video
signals. Output signal connections should include series
termination resistors that are matched to the impedance of the
line they are driving. When driving high impedance loads over
very short traces, impedance matching is not required. In these
cases, small series resistors should be used to buffer the
capacitance presented by the load.
Figure 41. External Common-Mode Clamping
The series resistances, RS, limit the current in each leg,
and the Schottky diodes limit the voltages on each input to
approximately 0.3 V to 0.4 V over the positive power supply,
V+, and to 0.3 V to 0.4 V below the negative power supply, V−.
The maximum value of RS is determined by the required signal
bandwidth, the line impedance, and the effective differential
capacitance due to the AD8145 inputs and the diodes.
As with the differential clamp, the series resistors should be
highly matched in value to preserve high frequency CMRR.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Minimizing Parasitic Feedback Reactances
Parasitic trace capacitance and inductance are both reduced in
the unity-gain configuration when the feedback trace that
connects the OUT pin to the GAIN pin is reduced in length.
Removing the copper from all planes below the trace reduces
trace capacitance, but increases trace inductance, since the loop
area formed by the trace and ground plane is increased. A
reasonable compromise that works well is to void all copper
directly under the feedback trace and component pads with
margins on each side approximately equal to one trace width.
Combining this technique with minimizing trace length is
effective in keeping parasitic trace reactance in the unity-gain
feedback loop to a minimum.
Maximizing Heat Removal
The two most important issues with regard to printed circuit
board (PCB) layout are minimizing parasitic signal trace
reactances in the feedback network and providing sufficient
thermal relief.
A 5 × 5 array of thermal vias works well to connect the exposed
paddle to internal ground planes. The vias should be placed
inside the PCB pad that is soldered to the exposed paddle, and
should connect to all ground planes.
Excessive parasitic reactances in the feedback network cause
excessive peaking in the frequency response of the amplifier
and excessive overshoot in its step response due to a reduction
in phase margin. Oscillation occurs when these parasitic
reactances are increased to a critical point where the phase
margin is reduced to zero. Minimizing these reactances is
important to obtain optimal performance from the AD8145.
General high speed layout practices should be adhered to when
applying the AD8145. Controlled impedance transmission lines
are required for incoming and outgoing signals, referenced to a
ground plane.
The AD8145 includes ground connections on its corner pins.
These pins can be used to provide additional heat removal from
the AD8145 by connecting them between the PCB pad that is
soldered to the exposed paddle and a ground plane on the
component side of the board. This layout technique lowers the
overall package thermal resistance. Use of this technique is not
required, but it does result in a lower junction temperature.
Designs must often conform to design for manufacturing
(DFM) rules that stipulate how to lay out PCBs in such a way as
to facilitate the manufacturing process. Some of these rules
require thermal relief on pads that connect to planes, and the
rules may limit the extent to which this technique can be used.
Rev. 0 | Page 18 of 24
AD8145
+5V
DRIVING A CAPACITIVE LOAD
The AD8145 typically drives either high impedance loads over
short PCB traces, such as crosspoint switch inputs, or doubly
terminated coaxial cables. A gain of 1 is commonly used in the
high impedance case since the 6 dB transmission line termination
loss is not incurred. A gain of 2 is required when driving cables
to compensate for the 6 dB termination loss.
VIN
OUT
RS
REF
CIN
VREF
R
R
GAIN
C
06307-043
In all cases, the output must drive the parasitic capacitance
of the feedback loop, conservatively estimated to be 1 pF, in
addition to the capacitance presented by the actual load. When
driving a high impedance input, it is recommended that a small
series resistor be used to buffer the input capacitance of the
device being driven. Clearly, the resistor value must be small
enough to preserve the required bandwidth. In the ideal doubly
terminated cable case, the AD8145 output sees a purely resistive
load. In reality, there is some residual capacitance, and this is
buffered by the series termination resistor. Figure 42 illustrates
the high impedance case, and Figure 43 illustrates the cabledriving case.
0.01µF
0.01µF
–5V
Figure 42. Buffering the Input Capacitance of a High-Z Load with G = 1
+5V
POWER-DOWN
0.01µF
VIN
OUT RS
REF
VREF
CS
C
GAIN
R
R
0.01µF
–5V
Figure 43. Driving a Doubly Terminated Cable with G = 2
Rev. 0 | Page 19 of 24
RL
06307-044
The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use, and does
not place the output in a high-Z state when asserted. The
power-down feature is asserted when the voltage applied to the
power-down pin drops to approximately 2 V below the positive
supply. The AD8145 is enabled by pulling the power-down pin
to the positive supply.
AD8145
not embedded in the color signals, it is advantageous to
transmit them using a simple scheme that encodes them among
the three common-mode voltages of the RGB signals. The
AD8134 triple differential driver is a natural complement to the
AD8145 and performs the sync pulse encoding with the
necessary circuitry on-chip.
COMPARATORS
In addition to general-purpose applications, the two on-chip
comparators can be used to decode video sync pulses from the
received common-mode voltages, or to receive differential digital
information. Built-in hysteresis helps to eliminate false triggers
from noise.
The AD8134 encoding equations are given in Equation 4,
Equation 5, and Equation 6.
The comparator outputs are designed to drive source-terminated
transmission lines. The source termination technique uses a
resistor in series with each comparator output such that the sum
of the comparator source resistance (≈ 20 Ω) and the series
resistor equals the transmission line characteristic impedance.
The load end of the transmission line is high impedance. When
the signal is launched into the source termination, its initial
value is one-half of its source value, since its amplitude is
divided by two by the voltage divider formed by the source
termination and the transmission line. At the load, the signal
experiences nearly 100% positive reflection due to the high
impedance load, and is restored to nearly its full value. This
technique is commonly used in PCB layouts that involve high
speed digital logic.
Red VCM =
[
K
V −H
2
(4)
[
]
(5)
K
V +H
2
]
(6)
Green VCM =
Blue VCM =
]
K
−2 V
2
[
where:
Red VCM, Green VCM, and Blue VCM are the transmitted commonmode voltages of the respective color signals.
K is an adjustable gain constant that is set by the AD8134.
An internal linear voltage regulator derives power for the
comparators from the positive supply; therefore, the AD8145
must always have a minimum positive supply voltage of 4.5 V.
V and H are the vertical and horizontal sync pulses, defined
with a weight of −1 when the pulses are in their low states, and a
weight of +1 when they are in their high states.
SYNC PULSE EXTRACTION USING COMPARATORS
The AD8134 data sheet contains further details regarding the
encoding scheme. Figure 44 illustrates how the AD8145
comparators can be used to extract the horizontal and vertical
sync pulses that are encoded on the RGB common-mode
voltages by the AD8134.
The AD8145 is particularly useful in keyboard, video, mouse
(KVM) applications. KVM networks transmit and receive
computer video signals, which typically comprise red, green,
and blue (RGB) video signals and separate horizontal and
vertical sync signals. Because the sync signals are separate and
RECEIVED
RED VIDEO
50Ω
RED CMV
RS
50Ω
HSYNC
1kΩ
RECEIVED
GREEN VIDEO
50Ω
GREEN CMV
47pF
475Ω
RS
50Ω
VSYNC
47pF
1kΩ
50Ω
BLUE CMV
06307-045
RECEIVED
BLUE VIDEO
50Ω
Figure 44. Extracting Sync Signals from Received Common-Mode Signal
Rev. 0 | Page 20 of 24
AD8145
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
25
24
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
32
1
EXPOSED
PAD
(BOTTOM VIEW)
17
16
3.45
3.30 SQ
3.15
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 45. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8145YCPZ-R2 1
AD8145YCPZ-RL1
AD8145YCPZ-R71
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Z = Pb-free part.
Rev. 0 | Page 21 of 24
Package Option
CP-32-3
CP-32-3
CP-32-3
AD8145
NOTES
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AD8145
NOTES
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AD8145
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06307-0-10/06(0)
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