TI ISO7520CDWR Low-power 5 kv(rms) dual digital isolator Datasheet

ISO7520
ISO7521
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SLLSE39 – JUNE 2010
Low-Power 5 KV(rms) Dual Digital Isolators
Check for Samples: ISO7520, ISO7521
FEATURES
1
•
•
•
•
•
•
•
Highest Signaling Rate: 1 Mbps
Propagation Delay Less Than 20 ns
Low Power Consumption
Wide Ambient Temperature: –40°C to 105°C
Safety and Regulatory Approvals
– 5 KV(rms) for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A
– IEC 60747-5-2 (VDE 0884 Rev. 2)
– IEC 60601-1, 60950-1, & 61010-1 End
Equipment Standards
50 kV/µs Transient Immunity Typical
Operates From 3.3V or 5V Supply and Logic
Levels
APPLICATIONS
•
Opto-Coupler Replacement in:
– Medical Applications for IEC 60601-1
5KVrms Rated
– Industrial Field-Bus
– ProfiBus
– ModBus
– DeviceNetTM Data Buses
– Servo Control Interface
– Motor Control
– Power Supply
– Battery Packs
The devices have TTL input thresholds and require
two supply voltages, 3.3V or 5V, or any combination.
All inputs are 5-V tolerant when supplied from a 3.3-V
supply.
Note: The ISO7520 and ISO7521 are specified for
signaling rates up to 1 Mbps. Due to their fast
response time, under most cases, these devices will
also transmit data with much shorter pulse widths.
Designers should add external filtering to remove
spurious signals with input pulse duration < 20 ns if
desired.
ISO 7520
GND 1
NC
VCC 1
INA
INB
NC
GND 1
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND 2
NC
VCC 2
OUTA
OUTB
NC
NC
GND 2
ISO 7521
GND 1
NC
VCC 1
OUTA
INB
NC
GND 1
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND 2
NC
VCC 2
INA
OUTB
NC
NC
GND 2
NC = No Internal Connection
DESCRIPTION
The ISO7520 and ISO7521 provide double galvanic
isolation of up to 5KVrms for 1 minute per UL. These
digital isolators have two isolated channels with
uni-directional (ISO7520) and bi-directional (ISO7521)
channel configurations. Each isolation channel has a
logic input and output buffer separated by a silicon
oxide (SiO2) insulation barrier. Used in conjunction
with isolated power supplies, these devices prevent
noise currents on a data bus or other circuits from
entering the local ground and interfering with or
damaging sensitive circuitry.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
ISO7520
ISO7521
SLLSE39 – JUNE 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE FUNCTION TABLE
INPUT SIDE (VCC) (1)
OUTPUT SIDE (VCC) (1)
PU
OUTPUT (OUT) (1)
H
H
PU
PD
(1)
INPUT (IN) (1)
PU
L
L
Open
H
X
H
PU = Powered Up (Vcc ≥ 3.15V); PD = Powered Down (Vcc ≤ 2.4V); X = Irrelevant; H = High Level; L
= Low Level
AVAILABLE OPTIONS
PRODUCT
RATED TA
MARKED AS
ISO7520C
–40°C to 105°C
ISO7520CDW
ISO7521C
–40°C to 105°C
ISO7521CDW
ORDERING NUMBER
ISO7520CDW (rail)
ISO7520CDWR (reel)
ISO7521CDW (rail)
ISO7521CDWR (reel)
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5 V to 6
V
VI
Voltage at IN, OUT
–0.5 V to 6
V
IO
Output Current
±15
mA
±4
kV
±1
kV
±200
V
150
°C
ESD
TJ
(1)
(2)
2
Electrostatic
discharge
Human Body Model
JEDEC Standard 22, Test Method
A114-C.01
Field-Induced-Charged Device
Model
JEDEC Standard 22, Test Method C101
Machine Model
ANSI/ESDS5.2-1996
Maximum junction temperature
All pins
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
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THERMAL INFORMATION
ISO752xC
THERMAL METRIC
DW
UNITS
16 PINS
qJA
Junction-to-ambient thermal resistance (1)
79.9
qJCtop
Junction-to-case (top) thermal resistance (2)
44.6
qJB
Junction-to-board thermal resistance (3)
51.2
(4)
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter (5)
42.2
qJCbot
Junction-to-case (bottom) thermal resistance (6)
n/a
PD
Device power dissipation, Vcc1 = Vcc2 = 5.25 V, TJ = 150°C, CL = 15 pF, Input a 0.5
MHz 50% duty cycle square wave
42
(1)
(2)
(3)
(4)
(5)
(6)
°C/W
18.0
mW
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VCC1, VCC2
MIN
TYP
MAX
UNIT
Supply voltage - 3.3V Operation
3.15
3.3
3.45
V
Supply voltage - 5V Operation
4.75
5
5.25
IOH
High-level output current
IOL
Low-level output current
VIH
High-level output voltage
2
VCC
V
VIL
Low-level output voltage
0
0.8
V
TA
Ambient Temperature
-40
105
°C
TJ (1)
Junction temperature
–40
136
1/tui
Signaling rate
tui
Input pulse duration
(1)
–4
mA
4
0
1
mA
°C
Mbps
1
us
To maintain the recommended operating conditions for TJ, see the Package Thermal Characteristics table and the Icc Equations section
of this data sheet
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ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 105°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
MIN
TYP
IOH = –4 mA; See Figure 1
TEST CONDITIONS
VCC –0.8
4.6
IOH = –20 µA; SeeFigure 1
VCC –0.1
5
IOL = 4 mA; SeeFigure 1
IOL = 20 µA; See Figure 1
MAX
V
0.2
0.4
0
0.1
400
–10
VI = VCC or 0 V; See Figure 3
25
V
mV
10
INx at 0 V or VCC
UNIT
µA
µA
50
kV/µs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7520
ICC1
Supply current for VCC1
DC to 1 Mbps VI = VCC or 0 V, 15 pF load
0.4
1
mA
ICC2
Supply current for VCC2
DC to 1 Mbps VI = VCC or 0 V, 15 pF load
3
6
mA
ISO7521
ICC1
Supply current for VCC1
DC to 1 Mbps VI = VCC or 0 V, 15 pF load
2
4
mA
ICC2
Supply current for VCC2
DC to 1 Mbps VI = VCC or 0 V, 15 pF load
2
4
mA
TYP
MAX
9
14
ns
0.3
3.5
ns
4
ns
3.6
ns
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 105°C
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(pp)
Part-to-part skew time
tsk(o)
Channel-to-channel output skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
4
See Figure 1
See Figure 1
See Figure 2
MIN
UNIT
1
ns
1
ns
6
ns
Also known as pulse skew.
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ELECTRICAL CHARACTERISTICS
VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C
PARAMETER
VOH
High-level output voltage
TEST CONDITIONS
IOH = –4 mA;
See Figure 1
MIN
TYP
ISO7521 (5-V side)
VCC –0.8
4.6
ISO7520/7521(3.3-V side)
VCC –0.4
3
VCC –0.1
VCC
IOH = –20 µA; See Figure 1
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
MAX
UNIT
V
IOL = 4 mA; See Figure 1
0.2
0.4
IOL = 20 µA; See Figure 1
0
0.1
V
400
mV
10
INx at 0 V or VCC
µA
–10
VI = VCC or 0 V; See Figure 3
25
µA
40
kV/µs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7520
ICC1
Supply current for VCC1
DC to 1 Mbps
VI = VCC or 0 V, 15 pF load
0.4
1
mA
ICC2
Supply current for VCC2
DC to 1 Mbps
VI = VCC or 0 V, 15 pF load
2
4.5
mA
ICC1
Supply current for VCC1
DC to 1 Mbps
VI = VCC or 0 V, 15 pF load
2
4
mA
ICC2
Supply current for VCC2
DC to 1 Mbps
VI = VCC or 0 V, 15 pF load
1.5
3.5
mA
ISO7521
SWITCHING CHARACTERISTICS
VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C
PARAMETER
tPLH, tPHL
PWD
(1)
TEST CONDITIONS
Propagation delay time
See Figure 1
TYP
MAX
10
17
UNIT
ns
0.5
4
ns
tsk(pp)
Part-to-part skew time
5
ns
tsk(o)
Channel-to-channel output skew time
4
ns
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
Pulse width distortion |tPHL – tPLH|
MIN
See Figure 1
See Figure 2
2
ns
2
ns
6
ns
Also known as pulse skew.
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ELECTRICAL CHARACTERISTICS
VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 105°C
PARAMETER
VOH
High-level output voltage
TEST CONDITIONS
IOH = –4 mA;
See Figure 1
MIN
TYP
ISO7520/7521 (5-V side)
VCC –0.8
4.6
ISO7521 (3.3-V side)
VCC –0.4
3
VCC –0.1
VCC
IOH = –20 µA; See Figure 1
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
MAX
V
IOL = 4 mA; See Figure 1
0.2
0.4
IOL = 20 µA; See Figure 1
0
0.1
400
–10
VI = VCC or 0 V; See Figure 3
25
V
mV
10
INx at 0 V or VCC
UNIT
µA
µA
40
kV/µs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7520
ICC1
Supply current for VCC1
DC to 1 Mbps
VI = VCC or 0 V, 15 pF load
0.2
0.7
mA
ICC2
Supply current for VCC2
DC to 1 Mbps
VI = VCC or 0 V, 15 pF load
3
6
mA
ICC1
Supply current for VCC1
DC to 1 Mbps
VI = VCC or 0 V, 15 pF load
1.5
3.5
mA
ICC2
Supply current for VCC2
DC to 1 Mbps
VI = VCC or 0 V, 15 pF load
2
4
mA
TYP
MAX
10
17
ns
0.5
ISO7521
SWITCHING CHARACTERISTICS
VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 105°C
PARAMETER
tPLH, tPHL
PWD
(1)
TEST CONDITIONS
Propagation delay time
See Figure 1
UNIT
4
ns
tsk(pp)
Part-to-part skew time
5
ns
tsk(o)
Channel-to-channel output skew time
4
ns
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
6
Pulse width distortion |tPHL – tPLH|
MIN
See Figure 1
See Figure 2
2
ns
2
ns
6
ns
Also known as pulse skew.
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ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
MIN
TYP
IOH = –4 mA; See Figure 1
TEST CONDITIONS
VCC –0.4
3
IOH = –20 µA; See Figure 1
VCC –0.1
3.3
MAX
UNIT
V
IOL = 4 mA; See Figure 1
0.2
0.4
IOL = 20 µA; See Figure 1
0
0.1
V
400
mV
µA
INx at 0 V or VCC
–10
VI = VCC or 0 V; See Figure 3
25
µA
40
kV/µs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7520
ICC1
Supply current for VCC1
DC to 1 Mbps VI = VCC or 0 V, 15 pF load
0.2
0.7
mA
ICC2
Supply current for VCC2
DC to 1 Mbps VI = VCC or 0 V, 15 pF load
2
4.5
mA
ISO7521
ICC1
Supply current for VCC1
DC to 1 Mbps VI = VCC or 0 V, 15 pF load
1.5
3.5
mA
ICC2
Supply current for VCC2
DC to 1 Mbps VI = VCC or 0 V, 15 pF load
1.5
3.5
mA
TYP
MAX
UNIT
12
20
ns
1
5
ns
6
ns
5.5
ns
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(pp)
Part-to-part skew time
tsk(o)
Channel-to-channel output skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
See Figure 1
See Figure 1
See Figure 2
MIN
2
ns
2
ns
6
ns
Also known as pulse skew.
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PARAMETER MEASUREMENT INFORMATION
ISOLATION BARRIER
IN
Input
Generator
VI
VCC1
50 W
VI
1.4V
1.4V
OUT
0V
t PHL
tPLH
VO
CL
VOH
90%
NOTE
B
NOTE A
Vcc/2
VO
10%
tf
tr
Vcc/2
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤
3ns, tf ≤ 3ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
VI
Vcc1
ISOLATION BARRIER
Vcc1
0V
IN
or
Vcc1
2.7 V
VI
OUT
VO
0V
tfs
CL
VO
VOH
50%
FAILSAFE HIGH
VOL
NOTE
B
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms
IN
S1
C = 0.1 µF +1 %
ISOLATION BARRIER
V CC1
GND 1
V CC2
C = 0.1 µ F +1 %
Pass-fail criteria –
output must remain
stable .
OUT
NOTE B
V OH or V OL
GND 2
V CM
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Common-Mode Transient Immunity Test Circuit
8
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DEVICE INFORMATION
PACKAGE CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
L(I01)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum air gap (Clearance)
Shortest terminal to terminal distance through air
8.34
mm
L(I02)
Minimum external tracking (Creepage)
Shortest terminal to terminal distance across the
package surface
8.1
mm
CTI
Tracking resistance (Comparative Tracking
DIN IEC 60112 / VDE 0303 Part 1
Index)
≥400
V
Minimum internal gap (Internal Clearance)
Distance through the insulation
0.016
mm
RIO
Isolation resistance, input to output (1)
Input to output, VIO = 500 V, all pins on each side
of the barrier tied together creating a two-terminal
device
CIO
Barrier capacitance input to output (1)
CI
Input capacitance to ground (2)
(1)
(2)
>1012
Ω
VIO = 0.4 sin(2pft), f = 1 MHz
2
pF
VI = Vcc/2 + 0.4 sin(2pft), f = 1 MHz, Vcc = 5 V
2
pF
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
empty para for space above the NOTE
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed circuit board do not reduce this distance
Creepage and clearance on a printed circuit board become equal according to the
measurement techniques shown in the Isolation Glossary. Techniques such as inserting
grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
Basic Isolation Group
Installation Classification
TEST CONDITIONS
Material Group
SPECIFICATION
II
Rated mains voltages <= 150 Vrms
I - IV
Rated mains voltages <= 300 Vrms
I - IV
Rated mains voltages <= 400 Vrms
I - III
Rated mains voltages <= 600 Vrms
I - III
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INSULATION CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPECIFICATION
UNIT
1300/920
Vpeak/
Vrms
VIORM
Maximum working insulation voltage
VTEST = 1.875 × VIORM, PD ≤ 5pC,
t = 10 sec (qualification)
t = 1 sec (100% production)
VIOTM
Transient overvoltage
VTEST = VIOTM,
t = 60 sec (qualification)
t= 1 sec (100% production)
4000/2858
Vpeak/
Vrms
VISO
Isolation voltage per UL
VTEST = VISO
t = 60 sec (qualification), VTEST = 1.2 × VISO,
t = 1 sec (100% production)
7000/5000
8400/6000
Vpeak/
Vrms
RS
Insulation resistance
VTEST = 500 V at TS = 150C
>109
Ω
Pollution degree
2
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC 60747-5-2
Approved under CSA Component Acceptance
Notice
Recognized under 1577 Component
Recognition Program
File Number: pending
File Number: pending
File Number: pending
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
Is
Ts
Safety input, output, or supply current
TEST CONDITIONS
MIN
TYP
MAX
qJA =79.9 °C/W, VI = 5.25 V, TJ = 150 °C, TA = 25
°C
298
qJA =79.9 °C/W, VI = 3.45 V, TJ = 150 °C, TA = 25
°C
453
Maximum Case Temperature
UNIT
mA
150
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed on a High-K Test Board for Leaded Surface Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
10
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Safety Limiting Current - mA
500
VCC1 and VCC2 at 3.45 V
400
300
VCC1 and VCC2 at 5.25 V
200
100
0
0
50
100
150
200
250
Case Temperature - °C
Figure 4. DW-16 Theta-JC Thermal Derating Curve per IEC 60747-5-2
GND1
NC
0.1? F
2 mm max. from VCC1
VCC1
INA
INB
NC
GND1
NC
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
0.1? F
2 mm max. from VCC2
VCC2
OUTA
OUTB
NC
NC
GND2
ISO7520
Figure 5. Typical ISO7520 Application Circuit
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Figure 6. I/O Schematic
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TYPICAL CHARACTERISTICS
INPUT VOLTAGE SWITCHING THRESHOLD vs
FREE-AIR TEMPERATURE
FAIL-SAFE VOLTAGE THRESHOLD vs
FREE-AIR TEMPERATURE
2.62
VIT+, 5 V
1.5
Fail-Safe Voltage Threshold − V
Input Voltage Switching Threshold − V
1.6
1.4
VIT+, 3.3 V
1.3
1.2
1.1
VIT−, 5 V
1.0
VIT−, 3.3 V
0.9
0.8
−55
−35
−15
5
25
45
65
85
105
TA − Free-Air Temperature − °C
FS+
2.60
2.59
2.58
2.57
2.56
2.55
FS−
2.54
2.53
2.52
−55
125
−35
−15
25
45
65
85
105
125
G006
Figure 7.
Figure 8.
HIGH-LEVEL OUTPUT CURRENT vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT vs
LOW-LEVEL OUTPUT VOLTAGE
80
IOL − Low-Level Output Current − mA
TA = 25°C
−10
−20
−30
−40
VCC1, VCC2 at 3.3 V
−50
−60
−70
VCC1, VCC2 at 5 V
−80
−90
TA = 25°C
70
60
VCC1, VCC2 at 5 V
50
40
VCC1, VCC2 at 3.3 V
30
20
10
0
0
1
2
3
4
5
VOH − High-Level Output Voltage − V
6
0
1
G007
Figure 9.
12
5
TA − Free-Air Temperature − °C
G005
0
IOH − High-Level Output Current − mA
2.61
2
3
4
VOL − Low-Level Output Voltage − V
5
6
G008
Figure 10.
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PACKAGE OPTION ADDENDUM
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3-Jul-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
ISO7520CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
ISO7520CDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
ISO7521CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
ISO7521CDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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