ON NCP81245MNTXG Three-rail output controller Datasheet

NCP81245
Three-Rail Output
Controller with Single Intel
Proprietary Interface for
Desktop and Notebook CPU
Applications
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The NCP81245 (3+3+1 phase) three−output buck solution is
optimized for Intel’s IMVP8 CPUs.
The two multi−phase rail control systems are based on Dual−Edge
pulse−width modulation (PWM) combined with DCR current sensing
providing an ultra fast initial response to dynamic load events and
reduced system cost.
The single−phase rail makes use of ON Semiconductor’s patented
high performance RPM operation. RPM control maximizes transient
response while allowing for smooth transitions between
discontinuous−frequency−scaling operation and continuous−mode
full−power operation. The NCP81245 has an ultra−low offset current
monitor amplifier with programmable offset compensation for
high−accuracy current monitoring.
MARKING
DIAGRAM
1 52
NCP81245
FAWLYYWW
G
QFN52
MN SUFFIX
CASE 485BE
F
A
WL
YY
WW
G
= Wafer Fab
= Assembly Site
= Lot ID
= Year
= Work Week
= Pb−Free Package
Three−Phase Rails Feature
• Dual Edge Modulation for Fastest Initial Response to Transient
•
•
•
•
•
•
•
•
•
•
•
•
•
Loading
High Performance Operational Error Amplifier
Digital Soft Start Ramp
Dynamic Reference Injection
Accurate Total Summing Current Amplifier
Dual High Impedance Differential Voltage and Total Current Sense
Amplifiers
Phase−to−Phase Dynamic Current Balancing
True Differential Current Balancing Sense Amplifiers for Each Phase
Adaptive Voltage Positioning (AVP)
Switching Frequency Range of 300 kHz − 750 kHz
Vin range 4.5 V to 20 V
Startup into Pre−Charged Loads While Avoiding False OVP
UltraSonic Operation
These are Pb−Free Devices
Single−Phase Rail Features
•
•
•
•
•
•
July, 2016 − Rev. 5
Device
NCP81245MNTXG
Package
Shipping†
QFN52
(Pb−Free)
2500 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• UltraSonic Operation
• Adjustable Vboot
• Digitally Controlled Operating Frequency
Enhanced RPM Control System
Ultra Low Offset IOUT Monitor
Dynamic VID Feed−Forward
Programmable Droop Gain
Zero Droop Capable
Thermal Monitor
© Semiconductor Components Industries, LLC, 2016
ORDERING INFORMATION
Applications
• Desktop & Notebook Processors
• Gaming
1
Publication Order Number:
NCP81245/D
NCP81245
+5V
SKT_SNS+
VSP
VCC
VSN
GND
VDRV
SKT_SNS−
DIFFOUT
VIN
LG HG
BST
PWM1
PWM
DRON
EN
VCC
FB
VIN
ON DrMOS
SW
PGND
GND SMOD ZCD
CSP1
COMP
VDRV
BST
PWM
PWM2
EN
VCC
TSENSE
VIN
Vcc_Rail1
ON DrMOS
SW
PGND
GND SMOD ZCD
NTC
Vpu
VIN
LG HG
IOUT
CSP2
VDRV
VRHOT
Vpu
BST
PWM
PWM3
SDIO
EN
VCC
ALERT
PSYS
VIN
ON DrMOS
SW
PGND
GND SMOD ZCD
CSP3
SCLK
batt chrgr
VIN
LG HG
Vpu
CSREF
CSSUM
ILIM
CSCOMP
NTC
VDRV
TSENSE
VIN
LG HG
NCP81245
BST
NTC
PWM1
PWM
DRON
EN
VCC
VIN
ON DrMOS
SW
PGND
GND SMOD ZCD
IOUT
CSP1
VDRV
SKT_SNS+
BST
SKT_SNS−
VSN
VIN
LG HG
VSP
PWM
PWM2
EN
VCC
DIFFOUT
VIN
Vcc_Rail2
ON DrMOS
SW
PGND
GND SMOD ZCD
FB
CSP2
VDRV
BST
EN
VRRDY
PWM
PWM3
EN
VCC
VIN
VIN
ON DrMOS
SW
PGND
GND SMOD ZCD
CSP3
VRMP
VIN
LG HG
COMP
CSREF
CSSUM
SKT_SNS+
SKT_SNS−
VSP
ILIM
VSN
CSCOMP
NTC
VDRV
COMP
VIN
LG HG
BST
IOUT
PWM
PWM
ILIM
CSP
EN
VCC
CSN
VIN
Vcc_Rail3
ON DrMOS
SW
PGND
GND SMOD ZCD
NTC
Figure 1.
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2
NCP81245
VSP_3PH_A
VSN_3PH_A
IMON_3PH_A
DIFFOUT_3PH_A
FB_3PH_A
COMP_3PH_A
ILIM_3PH_A
CSCOMP_3PH_A
CSSUM_3PH_A
CSREF_3PH_A
CSP1_3PH_A
CSP2_3PH_A
CSP3_3PH_A
1
2
3
4
5
6
7
8
9
10
11
12
13
NCP81245
TAB: GROUND
Figure 2. Pinout
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3
39
38
37
36
35
34
33
32
31
30
29
28
27
VRHOT#
VSP_3PH_B
VSN_3PH_B
IMON_3PH_B
DIFFOUT_3PH_B
FB_3PH_B
COMP_3PH_B
ILIM_3PH_B
CSCOMP_3PH_B
CSSUM_3PH_B
CSREF_3PH_B
CSP1_3PH_B
CSP2_3PH_B
NCP81245
1.3V
VRHOT# 31
VSP
THERMAL
MONITOR
OVP
VSN
47 VSP_2ph
_
ENABLE
ALERT# 33
OCP
OVP
SCLK 34
48 VSN_2ph
DAC
DAC
SVID
INTERFACE
& LOGIC
SDIO 32
VSP
VSN
DIFF
AMP
OVP
DRVON
CSCOMP
DAC
FEED−
FORWARD
_
PS#
ENABLE
CSREF
2
DIFFOUT_2ph
3
FB_2ph
4
COMP_2ph
+
VR_RDY 38
DATA
REGISTERS
VR READY
LOGIC
ERROR
AMP
1.3V
ROSC_COREGT14
ROSC_SAUS 15
MUX
ICCMAX_2ph 18
ICCMAX_1a 19
ICCMAX_1b 20
CURRENT
SENSE
AMP
IOUT_2ph
ADC
IOUT_1a
OVP
ADDR_VBOOT21
IOUT_1b
6
CSCOMP_2ph
_
7
CSSUM_2ph
+
8
CSREF_2ph
Buffer OVERCURRENT
PROGRAMMING
5
ILIM_2ph
OVERCURRENT
COMPARATORS
MAX
OVP
TSENSE_2ph 11
TSENSE_1ph 23
ENABLE
PSYS 46
OCP
VRMP 12
1
PS#
OSCILLATOR
& RAMP
GENERATORS
VRMP
DRVON
COMP
OVP
OCP
ENABLE
PWM
GENERATORS
PWM1
EN 37
UVLO & EN
COMPARATORS
PWM2
VCC 13
PS#
GROUND 49
PS#
IOUT
CURRENT
BALANCE
AMPLIFIERS
IPH2
IPH1
ZERO
CURRENT
DETECTION
POWER
STATE
GATE
IOUT_2ph
CURRENT
MONITOR
35 DRVON
9
CSP2_2ph
10 CSP1_2ph
16 PWM1_2ph
17 PWM2_2ph
Figure 3. Block Diagram of Dual Edge Architecture
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4
NCP81245
DAC
FEED−
FORWARD
CURRENT
DAC
DAC
VSN
gm
VSP
25 VSN_1a
24 VSP_1a
26 COMP_1a
gm
DROOP
CURRENT
+
Av=1
_
FROM SVID
INTERFACE
DAC FEEDFORWARD
OVP OVP REF
DRVON
COMP
gm
OVP
CURR
PWM
GENERATOR
OCP
RAMP
OVERCURRENT
PROGRAMMING
OVERCURRENT
COMPARATORS
OCP OCP REF
FREQ
IOUT
RAMP
GENERATOR
27 ILIM_1a
gm
DAC
VRMP
29 CSP_1a
CURRENT
SENSE AMP 28 CSN_1a
PWM
PS#
ZERO
CURRENT
DETECTION
Figure 4. Block Diagram of Enhanced RPM Architecture
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5
CURRENT
MONITOR
30 IOUT_1a
22 PWM_1a
NCP81245
Table 1. QFN52 PIN LIST DESCRIPTION
Pin
Name
1
VSP_3PH_A
Differential output voltage sense positive for multi−phase rail “A”
Description
2
VSN_3PH_A
Differential output voltage sense negative for multi−phase rail “A”
3
IMON_3PH_A
A resistor to ground programs IOUT gain for multi−phase rail “A”
4
DIFFOUT_3PH_A
Output of multi−phase rail “A” differential remote sense amplifier
5
FB_3PH_A
6
COMP_3PH_A
7
ILIM_3PH_A
8
CSCOMP_3PH_A
9
CSSUM_3PH_A
Inverting input of total−current−sense amplifier for multi−phase rail “A”
10
CSREF_3PH_A
Total−current−sense amplifier reference voltage input for multi−phase rail “A”
11
CSP1_3PH_A
Current−balance amplifier positive input for Phase 1 of multi−phase rail “A”
12
CSP2_3PH_A
Current−balance amplifier positive input for Phase 2 of multi−phase rail “A”
13
CSP3_3PH_A
Current−balance amplifier positive input for Phase 3 of multi−phase rail “A”
14
TTSENSE_3PH_A
15
VRMP
16
VCC
17
DRON
18
PWM1_3PH_A /
ICCMAX_3PH_A
Phase 1 PWM output of multi−phase rail “A” /
A resistor to ground programs ICCMAX for multi−phase rail “A”
19
PWM2_3PH_A /
ADDR
Phase 2 PWM output of multi−phase rail “A” /
A resistor to ground configures Intel proprietary interface addresses for all 3 rails (ADDR)
20
PWM3_3PH_A /
VBOOT
Phase 3 PWM output of multi−phase rail “A” /
A resistor to ground configures boot voltage for all 3 rails (VBOOT)
21
PWM3_3PH_B /
ROSC_3PH
Phase 3 PWM output of multi−phase rail “B” / Phase 4 PWM output of multi−phase rail “A” /
A resistor to ground configures Fsw for both “A” and “B” multi−phase rails (ROSC_3PH)
22
PWM2_3PH_B /
ROSC_1PH
Phase 2 PWM output of multi−phase rail “B” /
A resistor to ground configures Fsw for 1ph rail (ROSC_1ph)
23
PWM1_3PH_B /
ICCMAX_3PH_B
Phase 1 PWM output of multi−phase rail “B” /
A resistor to ground programs ICCMAX for multi−phase rail “B”
24
TTSENSE_1PH /
PSYS
Temperature sense input for the single−phase rail /
System input power monitor. A resistor to ground scales this signal
25
TTSENSE_3PH_B
26
CSP3_3PH_B
Current−balance amplifier positive input for Phase 3 of multi−phase rail “B” / Phase 4 of multi−phase
rail “A”
27
CSP2_3PH_B
Current−balance amplifier positive input for Phase 2 of multi−phase rail “B”
28
CSP1_3PH_B
Current−balance amplifier positive input for Phase 1 of multi−phase rail “B”
29
CSREF_3PH_B
Total−current−sense amplifier reference voltage input for multi−phase rail “B”
30
CSSUM_3PH_B
Inverting input of total−current−sense amplifier for multi−phase rail “B”
31
CSCOMP_3PH_B
32
ILIM_3PH_B
33
COMP_3PH_B
34
FB_3PH_B
35
DIFFOUT_3PH_B
Output of multi−phase rail “B” differential remote sense amplifier
36
IMON_3PH_B
A resistor to ground programs IOUT gain for multi−phase rail “B”
37
VSN_3PH_B
Differential output voltage sense negative for multi−phase rail “B”
Error amplifier voltage feedback for multi−phase rail “A”
Error amplifier output and PWM comparator inverting input for multi−phase rail “A”
A resistor to CSCOMP_3PH_A programs the over−current threshold for multi−phase rail “A”
Total−current−sense amplifier output for multi−phase rail “A”
Temperature sense input for multi−phase rail “A”
Vin feed−forward input. Controls a current used to generate the ramps of the modulators
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground
External FET driver enable for discrete driver or DrMOS
Temperature sense input for multi−phase rail “B”
Total−current−sense amplifier output for multi−phase rail “B”
A resistor to CSCOMP_3PH_B programs the over−current threshold for multi−phase rail “B”
Error amplifier output and PWM comparator inverting input for multi−phase rail “B”
Error amplifier voltage feedback for multi−phase rail “B”
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NCP81245
Table 1. QFN52 PIN LIST DESCRIPTION
Pin
Name
38
VSP_3PH_B
39
VR_HOT#
40
SDIO
41
ALERT#
42
SCLK
43
EN
44
PWM_1PH /
ICCMAX_1PH
Description
Differential output voltage sense positive for multi−phase rail “B”
Thermal logic output for over−temperature condition on TTSENSE pins
Serial VID data interface
Serial VID ALERT#
Serial VID clock
Enable input. High enables all three rails
PWM output of the single−phase rail /
A resistor to ground programs ICCMAX for the single−phase rail
45
VR_RDY
46
IMON_1PH
VR_RDY indicates all three rails are ready to accept Intel proprietary interface commands
A resistor to ground programs IOUT gain for the single−phase rail
47
CSP_1PH
Differential current sense positive for the single−phase rail
48
CSN_1ph
Differential current sense negative for the single−phase rail
49
ILIM_1ph
A resistor to ground programs ILIM gain for the single−phase rail
50
COMP_1ph
51
VSN_1ph
Differential output voltage sense negative for single−phase rail
52
VSP_1ph
Differential output voltage sense positive for single−phase rail
53
Tab
Compensation for single−phase rail
GND
ELECTRICAL INFORMATION
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
COMPX
VCC + 0.3 V
−0.3 V
2 mA
2 mA
CSCOMPX
VCC + 0.3 V
−0.3 V
2 mA
2 mA
VSN
GND + 300 mV
GND−300 mV
1 mA
1 mA
VRDY
VCC + 0.3 V
−0.3 V
N/A
2 mA
VCC
6.5 V
−0.3 V
N/A
N/A
VRMP
+25 V
−0.3 V
All Other Pins
VCC + 0.3 V
−0.3 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to GND unless noted otherwise.
Table 3. THERMAL INFORMATION
Description
Thermal Characteristic
QFN Package (Note 1)
Operating Junction Temperature Range (Note 2)
Symbol
Typ
Unit
RJA
68
°C/W
TJ
−40 to +125
°C
−40 to +100
°C
°C
Operating Ambient Temperature Range
Maximum Storage Temperature Range
TSTG
−40 to +150
Moisture Sensitivity Level
QFN Package
MSL
1
*The maximum package power dissipation must be observed.
1. 2) JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. 3) JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
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NCP81245
Table 4. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V ; CVCC = 0.1mF
Test Conditions
Parameter
Min
Typ
Max
Unit
900
nA
ERROR AMPLIFIER
−900
Input Bias Current
Open Loop DC Gain
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
Open Loop Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
20
MHz
Slew Rate
DVin = 100 mV, G = −10 V/V,
DVout = 0.75 V − 1.52 V,
CL = 20 pF to GND,
DC Load = 10k to GND
5
V/ms
Maximum Output Voltage
ISOURCE = 2.0 mA
Minimum Output Voltage
ISINK = 2.0 mA
3.5
V
1
V
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current
−25
25
nA
VSP Input Voltage Range
−0.3
3.0
V
VSN Input Voltage Range
−0.3
0.3
V
−3dB Bandwidth
CL = 20 pF to GND,
RL = 10 k W to GND
22.5
MHz
Closed Loop DC gain
VS to DIFF
VS+ to VS− = 0.5 to 1.3 V
1.0
V/V
Maximum Output Voltage
ISOURCE = 2 mA
Minimum Output Voltage
ISINK = 2 mA
3.5
V
0.8
V
−300
300
mV
7.5
mA
7.5
nA
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos)
Input Bias Current
CSREF= 1 V
−7.5
Input Bias Current
CSSUM= 1 V
−7.5
Open Loop Gain
Current Sense Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
Maximum CSCOMP (A) Output Voltage
Isource = 2 mA
Minimum CSCOMP(A) Output Voltage
Isink = 500 uA
80
dB
15
MHz
3.5
V
0.15
V
−50
50
nA
0
2.3
V
CURRENT BALANCE AMPLIFIER
Input Bias Current
CSPX − CSPX + 1 = 1.2 V
Common Mode Input Voltage Range
CSPx = CSREF
Differential Mode Input Voltage Range
CSNx = 1.2 V
−100
100
mV
Closed loop Input Offset Voltage Matching
CSPx = 1.2 V,
Measured from the average
−1.5
1.5
mV
Current Sense Amplifier Gain
0V < CSPx < 0.1 V,
5.7
6.3
V/V
Multiphase Current Sense Gain Matching
CSREF = CSP = 10 mV to 30 mV
−3
−3dB Bandwidth
6.0
3
8
%
MHz
BIAS SUPPLY
4.75
Supply Voltage Range
VCC Quiescent Current
Enable high
VCC Quiescent Current
Enable low
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8
33
5.25
V
50
mA
60
mA
NCP81245
Table 4. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V ; CVCC = 0.1mF
Parameter
Test Conditions
Min
Typ
Max
Unit
4.5
V
BIAS SUPPLY
UVLO Threshold
VCC rising
VCC falling
4
VCC UVLO Hysteresis
250
mV
VRMP
4.5
Supply Range
UVLO Threshold
VRamp rising
VRamp falling
20
V
4.25
V
3
UVLO Hysteresis
V
675
mV
DAC SLEW RATE
>10
mV/ms
Soft Start Slew Rate
1/2 SR
Fast
mV/ms
Slew Rate Slow
1/2 SR
Fast
mV/ms
Slew Rate Fast
ENABLE INPUT
Enable High Input Leakage Current
Enable = 0
VIH
−1
1
0.8
V
VIL
Enable Delay Time
mA
Measure time from Enable transitioning HI , VBOOT is not 0 V
0.3
V
2.5
ms
DRON
Output High Voltage
Sourcing 500 mA
Output Low Voltage
Sinking 500 mA
3.0
V
0.1
Pull Up Resistances
V
2.0
kW
Rise/Fall Time
CL (PCB) = 20 pF,
DVo = 10% to 90%
160
ns
Internal Pull Down Resistance
VCC = 0 V
70
kW
OVERCURRENT PROTECTION
11
mA
16.5
mA
Ilim Threshold Current
(delayed OCP shutdown)
PS0
Ilim Threshold Current
(immediate OCP shutdown)
PS0
PS1, PS2, PS3
(N = PS0 phase count)
15/N
Shutdown Delay
Immediate
300
ns
Delayed
50
ms
ILIM Output Voltage Offset
9
PS1, PS2, PS3
(N = PS0 phase count)
10/N
13.5
Ilim sourcing 10 mA
10
15
−2
2
mV
0.25
mA
IOUT_3PH_A/IOUT_3PH_B OUTPUT
Output Offset Current
VIlim = 5 V
Output current max
Ilimit sink current 20 mA
Current Gain
(Iout current)/(Ilimit Current)
Rlim = 20k, Riout = 5k
DAC = 0.8 V, 1.25 V, 1.52 V
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9
mA
200
9.5
10
10.5
A/A
NCP81245
Table 4. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V ; CVCC = 0.1mF
Parameter
Test Conditions
Min
Typ
Max
Unit
300
1200
kHz
−10
10
%
OSCILLATOR
Switching Frequency Range
Switching Frequency Accuracy
300 kHz < Fsw < 1 MHz
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Threshold During Soft−Start
Over Voltage Threshold Above DAC
VSP rising
Over Voltage Delay
VSP rising to PWMx low
Under Voltage Threshold Below DAC−DROOP
VSP falling
Under−voltage Hysteresis
VSP rising
1.9
2.0
2.1
V
370
400
430
mV
25
225
Under−Voltage Delay
300
ns
370
mV
25
mV
5
ms
MODULATORS (PWM COMPARATORS) FOR A RAIL & B RAIL
Minimum Pulse Width
Fsw = 350 kHz
40
ns
0% Duty Cycle
COMP voltage when the PWM
outputs remain LO
1.3
V
100% Duty Cycle
COMP voltage when the PWM
outputs remain HI VRMP=12.0V
2.5
V
PWM Phase Angle Error
Between adjacent phases
±5
°
VRHOT Assert Threshold
468
mV
VRHOT Rising Threshold
488
mV
Alert Assertion Threshold
488
mV
Alert Rising Threshold
510
mV
TSENSE
125
mA
0.3
V
−1
1
mA
Voltage Range
0
2
V
Total Unadjusted Error (TUE)
−1
1
%
1
LSB
TSENSE Bias Current
115
120
VRHOT
Output Low Saturation Voltage
IVR_HOT = −4 mA
Output Leakage Current
High Impedance State
ADC
Differential Nonlinearity (DNL)
8−bit
Power Supply Sensitivity
+/−1
%
Conversion Time
7.4
ms
Round Robin
206
ms
VRDY OUTPUT
Output Low Saturation Voltage
IVR_RDY = 4 mA
0.3
V
Rise Time
External pull−up of 1 kW to 3.3 V
CTOT = 45 pF, DVo = 10% to 90%
150
ns
Fall Time
External pull−up of 1 KW to 3.3 V
CTOT = 45 pF, DVo = 90% to 10%
150
ns
Output Leakage Current When High
VR_RDY = 5.0 V
1
mA
VR_RDY Delay (falling)
Due to OCP or OVP
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10
−1
0.3
ms
NCP81245
Table 4. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V ; CVCC = 0.1mF
Parameter
Test Conditions
Min
Typ
Max
Unit
PWM OUTPUTS
Output High Voltage
Sourcing 500 mA
Output Mid Voltage
No Load
Output Low Voltage
Sinking 500 mA
Rise and Fall Time
CL (PCB) = 50 pF,
DVo =10% to 90% of VCC
Tri−State Output Leakage
Gx = 2.0 V, x = 1−2, EN = Low
VCC −
0.2
1.9
V
2.0
2.1
V
0.3
V
5
−1
ns
1
mA
PHASE DETECTION
4.75
CSPX Phase Disable Voltage
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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11
NCP81245
SINGLE PHASE ELECTRICAL TABLE FOLLOWS
Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C<TA<100°C; 4.75V<VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
Input Bias Current
−25
25
nA
VSP Input Voltage Range
−0.3
3.0
V
VSN Input Voltage Range
−0.3
0.3
V
gm
1.344
1.856
mS
15
mA
Output Offset Current
1.6
−15
Open loop Gain
Load = 1 nF in series with 1 kW
in parallel with 10 pF to ground
Source Current
70
73
dB
Input Differential −200 mV
280
mA
Sink Current
Input Differential 200 mV
280
mA
−3dB Bandwidth
Load = 1 nF in series with 1 kW
in parallel with 10 pF to ground
20
MHz
IOUT
0.97
CSP−CSN = 20 mV
Output Offset Current
CSP = CSN
1
−200
1.03
mS
200
nA
430
mV
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
2.0
Over Voltage Threshold During Soft−Start
370
V
Over Voltage Threshold Above DAC
VSP−VSN−VID setting
Over Voltage Delay
VSP rising to PWMx low
25
ns
Over Voltage VR_RDY Delay
VSP rising to VR_RDY low
350
ns
Under Voltage Threshold
VSP−VSN falling
Under−voltage Hysteresis
VSP−VSN falling/rising
25
mV
Under−voltage Blanking Delay
VSP−VSN falling to VR_RDY falling
5
ms
215
300
385
mV
DROOP
0.96
CSP−CSN − 20 mV
Output Offset Current
CSP = CSN
1
−1.5
1.04
mS
1.5
mA
1.325
V
OVERCURRENT PROTECTION
1.275
ILIMIT Threshold
ILIMIT Delay
ILIMIT Gain
1.3
200
CSP−CSN = 20 mV
0.925
1
ns
1.075
mS
CSP−CSN ZCD comparator
±1.5
Offset Accuracy
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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12
NCP81245
General
Serial VID
The NCP81245 is a three rail 3+3+1 phase PWM
controller with a single serial Intel proprietary interface
control interface.
For Intel proprietary interface communication details
please contact Intel®, Inc.
NCP81245 Configurations
The NCP81245 has four Configuration pins that are secondary−functions on PWM pins. On power up a 10 mA current is
sourced from these pins through a resistor connected to this pin and the resulting voltage is measured. The following features
will be programmed:
• Intel proprietary interface address
♦ For Intel proprietary interface address selection please see Table below.
♦ For more information regrading Intel proprietary interface addresses please contact Intel, Inc.
• Phase doubler
♦ The multi−phase A rail can use a Phase Doubler from ON Semiconductor.
♦ Options to enable doubling on the A rail is provided in the Vboot configuration table
• Switching Frequency
♦ Both multi−phase rails’ per−phase switching frequency will be the same programmable value.
♦ The 1−phase Fsw is programmed independently
♦ The Fsw values are shown in the ROSC table
• Vboot
♦ Addresses 00h, 01h, and 03 POR Vboot is 0V.
♦ Address 02h POR Vboot is 1.05V
♦ Vboot options are shown in the VBOOT table
Boot Voltage
Vboot for the NCP81245 is externally programmed using a single resistor.
See Vboot pin voltages and the corresponding Vboot level in the table below. During startup, the pin voltage is measured.
This value cannot be changed after the initial power up sequence is complete.
Table 6. VBOOT PIN 20 CONFIGURATION
Resistor
3PH_A VBOOT
3PH_B VBOOT
1PH VBOOT
Rail A Doubler
6.19 kW
0V
0V
0V
No
14.7 kW
0V
0V
0V
Yes
24.9 kW
0V
0V
1.05 V
No
37.4 kW
0V
0V
1.05 V
Yes
53.6 kW
0V
0V
0.95 V
No
73.2 kW
0V
0V
0.95 V
Yes
97.6 kW
0V
0V
0.8 V
No
130 kW
0V
0V
0.8 V
Yes
169 kW
1.05 V
1.05 V
1.05 V
No
215 kW
1.05 V
1.05 V
1.05 V
Yes
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NCP81245
Table 7. INTEL PROPRIETARY INTERFACE ADDRESS PIN 19 CONFIGURATION
Pull−Down Resistor
Slew Rate
mV/ms
3PH_A
Address
3PH_B
Address
1PH
Address
Pin 24 TSENSE/
PSYS
A max
Phases
B max
Phases
NCP81245 (3+3+1, Pin 21 = PWM3_3PH_B, Pin 26 = CSP3_3PH_B)
00h
01h
02h
PSYS
3
3
00h
01h
03h
TSENSE
3
3
01h
00h
02h
PSYS
3
3
31.6 kW
01h
00h
03h
TSENSE
3
3
49.9 kW
00h
01h
02h
PSYS
3
3
00h
01h
03h
TSENSE
3
3
01h
00h
02h
PSYS
3
3
01h
00h
03h
TSENSE
3
3
19.6 kW
30
78.7 kW
121 kW
10
174 kW
PSYS
constant is generally not required. The individual phase
current is summed into the PWM comparator feedback this
way current is balanced via a current mode control approach.
The PSYS pin is an analog input to the NCP81245. It is a
system input power monitor that facilitates the monitoring
of the total platform system power. For more information
regarding PSYS please contact Intel, Inc.
Remote Sense Amplifier (multiphase)
RCSN
A high performance high input impedance true
differential amplifier is provided to accurately sense the
output voltage of the regulator. The VSP and VSN inputs
should be connected to the regulator’s output voltage sense
points. The remote sense amplifier takes the difference of
the output voltage with the DAC voltage and adds the droop
voltage to
V DIFOUT + ǒV VSP * V VSNǓ ) ǒ1.3 V * V DACǓ
) ǒV DROOP * V CSREFǓ
CSNx
12.1 kW
CSPx
4.3 kW
CCSN
SWNx
VOUT
DCR
LPHASE
1
RCSN =
(eq. 1)
2
LPHASE
CCSN ∗ DCR
Figure 5.
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier. The non−inverting input of the error
amplifier is connected to the same 1.3 V reference used for
the differential sense amplifier output bias.
Total Current Sense Amplifier (multiphase)
The NCP81245 uses a patented approach to sum the phase
currents into a single temperature compensated total current
signal. This signal is then used to generate the output voltage
droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to
CSREF. The current signal is the difference between
CSCOMP and CSREF. The Ref(n) resistors sum the signals
from the output side of the inductors to create a low
impedance virtual ground. The amplifier actively filters and
gains up the voltage applied across the inductors to recover
the voltage drop across the inductor series resistance (DCR).
Rth is placed near an inductor to sense the temperature of the
inductor. This allows the filter time constant and gain to be
a function of the Rth NTC resistor and compensate for the
change in the DCR with temperature.
High Performance Voltage Error Amplifier (multiphase)
A high performance error amplifier is provided for high
bandwidth transient performance. A standard type III
compensation circuit is normally used to compensate the
system.
Differential Current Feedback Amplifiers (multiphase)
Each phase has a low offset differential amplifier to sense
that phase current for current balance. The inputs to the
CSPx pins are high impedance inputs. It is also
recommended that the voltage sense element be no less than
0.5 mW for accurate current balance. Fine tuning of this time
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14
NCP81245
Rcs1*Rth
Rcs1)Rth
Rph
Rcs2)
R LIMIT +
* ǒIout LIMIT * DCRǓ
(eq. 4)
10m
or
R LIMIT +
V CSCOM−CSREF@ILIMIT
(eq. 5)
10m
Programming DAC Feed−Forward Filter (multiphase)
The DAC feed−forward implementation is realized by
having a filter on the VSN pin. Programming Rvsn sets the
gain of the DAC feed−forward and Cvsn provides the time
constant to cancel the time constant of the system per the
following equations. Cout is the total output capacitance and
Rout is the output impedance of the system.
Figure 6.
The DC gain equation for the current sensing:
V CSCOMP−CSREF +
Rcs1*Rth
Rcs2 ) Rcs1)Rth
Rph
(eq. 2)
* ǒIout Total * DCRǓ
Set the gain by adjusting the value of the Rph resistors.
The DC gain should be set to the output voltage droop. If the
voltage from CSCOMP to CSREF is less than 100 mV at
ICCMAX then it is recommend increasing the gain of the
CSCOMP amp. This is required to provide a good current
signal to offset voltage ratio for the ILIMIT pin. When no
droop is needed, the gain of the amplifier should be set to
provide ~100 mV across the current limit programming
resistor at full load. The values of Rcs1 and Rcs2 are set
based on the 100k NTC and the temperature effect of the
inductor and should not need to be changed. The NTC
should be placed near the closest inductor. The output
voltage droop should be set with the droop filter divider.
The pole frequency in the CSCOMP filter should be set
equal to the zero from the output inductor. This allows the
circuit to recover the inductor DCR voltage drop current
signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning
of the time constant using commonly available values. It is
best to fine tune this filter during transient testing.
FZ +
Figure 7.
Rvsn + Cout * Rout * 453.6
Cvsn +
10 6
Rout * Cout
Rvsn
(eq. 6)
(eq. 7)
Programming DROOP (multiphase)
The signals CSCOMP and CSREF are differentially
summed with the output voltage feedback to add precision
voltage droop to the output voltage.
DCR@25° C
2 * PI * L Phase
(eq. 3)
Programming the Current Limit (multiphase)
Droop + DCR * ǒRcsńRphǓ
The current limit thresholds are programmed with a
resistor between the ILIMIT and CSCOMP pins. The
ILIMIT pin mirrors the voltage at the CSREF pin and
mirrors the sink current internally to IOUT (reduced by the
IOUT Current Gain) and the current limit comparators. The
100% current limit trips if the ILIMIT sink current exceeds
10 mA for 50 ms. The 150% current limit trips with minimal
delay if the ILIMIT sink current exceeds 15 mA. Set the
value of the current limit resistor based on the
CSCOMP−CSREF voltage as shown below.
Figure 8.
Programming IOUT (multiphase)
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
scaled with an external resistor to ground such that a load
equal to ICCMAX generates a 2 V signal on IOUT. A
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15
NCP81245
pull−up resistor from 5 V VCC can be used to offset the
IOUT signal positive if needed.
2 V * R LIMIT
R IOUT +
10 *
Rcs1*Rth
Rcs2)
Rcs1)Rth
Rph
TSENSE
(eq. 8)
Rcomp1
0.0
* ǒIout ICC_MAX * DCRǓ
Cfilter
0.1uF
Programming ICC_MAX (multiphase)
Rcomp2
8.2K
A resistor to ground on the IMAX pin programs these
registers at the time the part is enabled. 10 mA is sourced
from these pins to generate a voltage on the program resistor.
The resistor value should be no less than 10k.
ICC_MAX 21k +
R * 10 mA * 256 A
2V
AGND
RNTC
100K
AGND
Figure 9.
(eq. 9)
Programming TSENSE
Precision Oscillator
A temperature sense inputs are provided. A precision
current is sourced out the output of the TSENSE pin to
generate a voltage on the temperature sense network. The
voltage on the temperature sense input is sampled by the
internal A/D converter. A 100k NTC similar to the VISHAY
ERT−J1VS104JA should be used. Rcomp1 is mainly used
for noise. See the specification table for the thermal sensing
voltage thresholds and source current.
A programmable precision oscillator is provided. The
clock oscillator serves as the master clock to the ramp
generator circuit. This oscillator is programmed by a resistor
to ground on the ROSC pin. The oscillator frequency range
is between 300 kHz/phase to 1.2 MHz/phase. The ROSC
pin provides approximately 2 V out and the source current
is mirrored into the internal ramp oscillator. The oscillator
frequency is approximately proportional to the current
flowing in the ROSC resistor.
Table 8. 3 PHASE / 1 PHASE FSW V ROSC (PIN21 / PIN22)
Resistor
Per phase Fsw MPH_A
Per phase Fsw MPH_B
Per phase Fsw 1PH
6.19 kW
1.2 MHz
1.2 MHz
1.2 MHz
14.7 kW
1.1 MHz
1.1 MHz
1.1 MHz
24.9 kW
1.0 MHz
1.0 MHz
1.0 MHz
37.4 kW
900 kHz
900 kHz
900 kHz
53.6 kW
800 kHz
800 kHz
800 kHz
73.2 kW
700 kHz
700 kHz
700 kHz
97.6 kW
600 kHz
600 kHz
600 kHz
130 kW
500 kHz
500 kHz
500 kHz
169 kW
400 kHz
400 kHz
400 kHz
215 kW
300 kHz
300 kHz
300 kHz
Programming the Ramp Feed−Forward Circuit
The oscillator generates triangle ramps that are 0.5~2.5 V
in amplitude depending on the VRMP pin voltage to provide
input voltage feed forward compensation. The ramps are
equally spaced out of phase with respect to each other and
the single phase rail is set half way between phases 1 and 2
of the multi phase rail for minimum input ripple current.
For use with ON Semiconductor’s phase doubler, the
NCP81245 offers the user the ability to multiply the
frequency of multiphase rail A. On the NCP81245, the
switching frequency is increased by a factor of 2 when the
phase doubler configuration is used.
The ramp generator circuit provides the ramp used by the
PWM comparators. The ramp generator provides voltage
feed−forward control by varying the ramp magnitude with
respect to the VRMP pin voltage. The VRMP pin also has
a 4 V UVLO function. The VRMP UVLO is only active
after the controller is enabled. The VRMP pin is high
impedance input when the controller is disabled.
The PWM ramp time is changed according to the
following,
V RAMPpk+pkPP + 0.1 * V VRMP
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16
(eq. 10)
NCP81245
Vin
Vramp_pp
Comp −IL
Duty
Figure 10.
PWM Comparators
multi−phase rails can be disabled by pulling up CSP pins to
VCC.
For example, to configure one of the 3 phase rails of the
NCP81245 as a 1 phase rail, CSP2 and CSP3 of that rail must
be pulled up to Vcc on startup.
Both the single−phase rails and multi−phase rail B can be
disabled by pulling all of their associated CSP pins to Vcc.
Phase 1 of multi−phase rail A cannot be disabled.
The PWM outputs are logic−level devices intended for
driving fast response external gate drivers or DrMOS. As
each phase is monitored independently, operation
approaching 100% duty cycle is possible. In addition, more
than one PWM output can be on at the same time to allow
overlapping phases.
The non−inverting input of the comparator for each phase
is connected to the summed output of the error amplifier
(COMP) and each phase current (IL*DCR*Phase Balance
Gain Factor). The inverting input is connected to the
oscillator ramp voltage with a 1.3 V offset. The operating
input voltage range of the comparators is from 0 V to 3.0 V
and the output of the comparator generates the PWM output.
During steady state operation, the duty cycle is centered
on the valley of the sawtooth ramp waveform. The steady
state duty cycle is still calculated by approximately
Vout/Vin. During a transient event, the controller will
operate in a hysteretic mode with the duty cycles pull in for
all phases as the error amp signal increases with respect to
all the ramps.
PHASE DETECTION SEQUENCE
The NCP81245 normally operates as a 3−ph Vcc_Rail1 +
3−ph Vcc_Rail2 + 1−ph Vcc_Rail3. Phases of the
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NCP81245
PROTECTION FEATURES
Under voltage Lockouts
DRON low and prevents the controller from being enabled.
The gate driver will hold DRON low for a minimum period
of time to allow the controller to hold off its startup
sequence. In this case the PWM is set to the MID state to
begin soft start.
There are several under voltage monitors in the system.
Hysteresis is incorporated within the comparators.
NCP81245 monitors the 5 V VCC supply. The gate driver
monitors both the gate driver VCC and the BST voltage.
When the voltage on the gate driver is insufficient it will pull
If DRON is pulled low the
controller will hold off its
startup
DAC
Gate Driver Pulls DRON
Low during driver UVLO
and Calibration
Figure 11. Gate Driver UVLO Restart
Soft−start
the PWMs will be set to 2.0 V MID state to indicate that the
drivers should be in diode mode. DRON will then be
asserted. As the DAC ramps the PWM outputs will begin to
fire. Each phase will move out of the MID state when the
first PWM pulse is produced. When the controller is
disabled the PWM signal will return to the MID state.
Soft start is implemented internally. A digital counter
steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table. The PWM signals will
start out open with a test current to collect data on phase
count and for setting internal registers. After the
configuration data is collected, if the controller is enabled
Figure 12.
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18
NCP81245
Over Current Latch− Off Protection (multiphase)
CSSUM
The NCP81245 compares a programmable current−limit
set point to the voltage from the output of the
current−summing amplifier. The level of current limit is set
with the resistor from the ILIM pin to CSCOMP. The current
through the external resistor connected between ILIM and
CSCOMP is then compared to the internal current limit
current ICL. If the current generated through this resistor into
the ILIM pin (Ilim) exceeds the internal current−limit
threshold current (ICL), an internal latch−off counter starts,
and the controller shuts down if the fault is not removed after
50 ms(shut down immediately for 150% load current) after
which the outputs will remain disabled until the VCC voltage
or EN is toggled.
The voltage swing of CSCOMP cannot go below ground.
This limits the voltage drop across the DCR through the
current balance circuitry. An inherent per−phase current
limit protects individual phases if one or more phases stop
functioning because of a faulty component. The
over−current limit is programmed by a resistor on the ILIM
pin. The resistor value can be calculated by the following
equations,
Equation related to the NCP81245 multiphase rails:
R ILIM +
I LIM * DCR * RcsńRph
I CL
R CS
R PH
RPH
R PH
CSCOMP
RLIM
ILIM
CSREF
Figure 13.
Under Voltage Monitor
The output voltage is monitored at the output of the
differential amplifier for UVLO. If the output falls more
than 300 mV below the DAC−DROOP voltage the UVLO
comparator will trip sending the VR_RDY signal low. The
300 mV limit can be reprogrammed using the
VR_Ready_Low Limit register.
Over Voltage Protection
The output voltage is also monitored at the output of the
differential amplifier for OVP. During normal operation, if
the output voltage exceeds the DAC voltage by 400 mV, the
VR_RDY flag goes low, and the output voltage will be
ramped down to 0 V. The part will stay in this mode until the
VCC voltage or EN is toggled
(eq. 11)
Where ICL = 10 mA
Figure 14.
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19
NCP81245
OVP During Normal Operation Mode
During start up, the OVP threshold is set to 2.0 V. This allows the controller to start up without false triggering the OVP.
Figure 15. OVP Behavior at Startup
Single−Phase Rail
DAC
The architecture of the single−phase rail makes use of a
digitally enhanced, high performance, current mode RPM
control method that provides excellent transient response
while minimizing transient aliasing. The average operating
frequency is digitally stabilized to remove frequency drift
under all continuous mode operating conditions. At light
load the single−phase rail automatically transitions into
DCM operation to save power.
gm
VSP
VSP
RZ
CHF
CLF
Figure 16.
A high performance, high input impedance, true
differential transconductance amplifier is provided to
accurately sense the regulator output voltage and provide
high bandwidth transient performance. The VSP and VSN
inputs should be connected to the regulator’s output voltage
sense points through filter networks described in the
following Droop section and the DAC Feedforward filter
section. The remote sense error amplifier outputs a current
proportional to the difference between the output voltage
and the DAC voltage:
ƪVDAC * ǒVVSP * VVSNǓƫ
VSN
COMP
Single−phase Rail Remote Sense Error Amplifier
I COMP + gm
VSN
Single−phase Rail − Differential Current Feedback
Amplifier
The single−phase controller has a low offset, differential
amplifier to sense output inductor current. An external
lowpass filter can be used to superimpose a reconstruction
of the AC inductor current onto the DC current signal sensed
across the inductor. The lowpass filter time constant should
match the inductor L/DCR time constant by setting the filter
pole frequency equal to the zero of the output inductor. This
makes the filter AC output mimic the product of AC inductor
current and DCR, with the same gain as the filter DC output.
It is best to perform fine tuning of the filter pole during
transient testing.
(eq. 12)
This current is applied to a standard Type II compensation
network.
Single−phase rail voltage compensation
FZ +
The Remote Sense Amplifier outputs a current that is
applied to a Type II compensation network formed by
external tuning components CLF, RZ and CHF.
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20
DCR@25° C
2*p*L
(eq. 13)
NCP81245
FP +
2*p*
ǒ
1
R
ǒ
* Rth)R
PHSP
R
PHSP
Ǔ
CSSP
)Rth)R
CSSP
Ǔ
(eq. 14)
L PHASE
C CSSP +
R
* C CSSP
ǒ
* Rth)R
PHSP
R
PHSP
(eq. 15)
* DCR
CSSP
RPHSP
= 7.68 kW
= 14.3 kW
RCSSP
Rth
= 100 kW, Beta = 4300
Using 2 parallel capacitors in the lowpass filter allows fine
tuning of the pole frequency using commonly available
capacitor values.
The DC gain equation for the current sense amplifier
output is:
Forming the lowpass filter with an NTC thermistor (Rth)
placed near the output inductor, compensates both the DC
gain and the filter time constant for the inductor DCR change
with temperature. The values of RPHSP and RCSSP are set
based on the effect of temperature on both the thermistor and
inductor. The CSP and CSN pins are high impedance inputs,
but it is recommended that the lowpass filter resistance not
exceed 10 kW in order to avoid offset due to leakage current.
It is also recommended that the voltage sense element
(inductor DCR) be no less than 0.5 mW for sufficient current
accuracy. Recommended values for the external filter
components are:
V CURR +
Rth ) R CSSP
R PHSP ) Rth ) R CSSP
* Iout * DCR
(eq. 16)
RPHSP
CSP
+
CURRENT
SENSE AMP
Av=1
Ǔ
CSSP
)Rth)R
CSN
RCSSP
_
CCSSP
t
TO
INDUCTOR
Rth
COMP
PWM
GENERATOR
CURR
Figure 17.
The amplifier output signal is combined with the COMP
and RAMP signals at the PWM comparator inputs to
produce the Ramp Pulse Modulation (RPM) PWM signal.
maintain output voltage within limits during load transients
faster than those to which the regulation loop can respond.
In the NCP81245, a loadline is produced by adding a signal
proportional to output load current (VDROOP) to the output
voltage feedback signal − thereby satisfying the voltage
regulator at an output voltage reduced proportional to load
current. VDROOP is developed across a resistance between
the VSP pin and the output voltage sense point.
Single−phase Rail − Loadline Programming (DROOP)
An output loadline is a power supply characteristic
wherein the regulated (DC) output voltage decreases by a
voltage VDROOP, proportional to load current. This
characteristic can reduce the output capacitance required to
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21
NCP81245
VSN
RDRPSP
VSP
VSP
CSNSSP
TO
VCC_SENSE
CDRPSP
gm
+
Av=1
RPHSP
CSP
CURRENT
SENSE AMP
CSN
RCSSP
TO
t
_
CCSSP
V DROOP + R DRPSP
gm
Rth
Rth ) R CSSP
R PHSP ) Rth ) R CSSP
I OUT
DCR
Figure 18.
The loadline is programmed by choosing RDRPSP such
that the ratio of voltage produced across RDRPSP to output
current is equal to the desired loadline.
R DRPSP +
Loadline
gm
DCR
R PHSP ) Rth ) R CSSP
each increment of the internal DAC following a DVID UP
command. A parallel RC network inserted into the path from
VSN to the output voltage return sense point, VSS_SENSE,
causes these current pulses to temporarily decrease the
voltage between VSP and VSN. This causes the output
voltage during DVID to be regulated slightly higher, in order
to compensate for the response of the Droop function to the
inductor current flowing into the charging output capacitors.
RFFSP sets the gain of the DAC feed−forward and CFFSP
provides the time constant to cancel the time constant of the
system per the following equations. Cout is the total output
capacitance of the system.
(eq. 17)
Rth ) R CSSP
Single−phase Rail − Programming the DAC
Feed−Forward Filter
The DAC feed−forward implementation for the
single−phase rail is the same as for the multi−phase rails. The
NCP81245 outputs a pulse of current from the VSN pin upon
DAC
FEED−
FORWARD
FROM SVID
INTERFACE
DAC FEEDFORWARD
CURRENT
CFFSP
TO
VSS_SENSE
DAC
DAC
gm
VSN
VSN
VSP
VSP
RFFSP
CSNSSP
Figure 19.
R FFSP +
C FFSP +
Loadline * Cout
1.35 nF
latches the single−phase rail off immediately if the ILIM pin
voltage exceeds the ILIM Threshold. Set the value of the
current limit resistor based on the equation shown below. A
capacitor can be placed in parallel with the programming
resistor to slightly delay activation of the latch if some
tolerance of short overcurrent events is desired.
(eq. 18)
200 ns
R FFSP
(eq. 19)
Single−phase Rail − Programming the Current Limit
The current limit threshold is programmed with a resistor
(RILIMSP) from the ILIM pin to ground. The current limit
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22
NCP81245
RPHSP
CSP
+
CURRENT
SENSE AMP
Av=1
CSN
RCSSP
t
_
CCSSP
gm
TO
INDUCTOR
Rth
ILIM
OVERCURRENT
PROGRAMMING
OVERCURRENT
COMPARATORS
OCP OCP REF
RILIMSP
1.3 V
R ILIMSP +
gm @ R
Rth)R
CSSP
)Rth)R
PHSP
CSSP
Iout LIMIT
DCR
Figure 20.
Single−phase Rail − Programming IOUT
When selecting the current limit it is necessary to take into
account the additional inductor current due to the slew rate
of the output voltage across the output capacitance during
VID changes, as this excess current may cause the OCP limit
to be exceeded. This excess current is given by:
dVout
I + Cout
where
(eq. 20)
dt
dVout
dt
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
scaled with an external resistor to ground such that a load
equal to ICCMAX generates a 2 V signal on IOUT. A
pull−up resistor from 5 V VCC can be used to offset the
IOUT signal positive if needed.
is the maximum slew rate
RPHSP
CSP
+
CURRENT
SENSE AMP
Av=1
CSN
RCSSP
t
_
CCSSP
gm
TO
INDUCTOR
Rth
IOUT
CURRENT
MONITOR
IOUT
RIOUTSP
2V
R IOUTSP +
Rth)R
gm
R
CSSP
)Rth)R
PHSP
IccMax
DCR
CSSP
Figure 21.
Single−phase Rail PWM Comparators
event, the duty cycle can increase rapidly as the COMP
voltage increases with respect to the ramps, to provide a
highly linear and proportional response to the step load.
The non−inverting input of each comparator (one for each
phase) is connected to the summation of the output of the
error amplifier (COMP) and each phase current
(IL*DCR*Phase Current Gain Factor). The inverting input
is connected to the triangle ramp voltage of that phase. The
output of the comparator generates the PWM output.
A PWM pulse starts when the error amp signal (COMP
voltage) rises above the trigger threshold plus gained−up
inductor current, and stops when the artificial ramp plus
gained−up inductor current crosses the COMP voltage. Both
edges of the PWM signals are modulated. During a transient
Programming ICC_MAX (single phase)
A resistor to ground on the IMAX pin programs these
registers at the time the part is enabled. 10 mA is sourced
from these pins to generate a voltage on the program resistor.
The resistor value should be no less than 10k.
ICC_MAX 21h +
www.onsemi.com
23
R max * 10 mA * 256 A
4*2V
(eq. 21)
NCP81245
PACKAGE DIMENSIONS
QFN52 6x6, 0.4P
CASE 485BE
ISSUE B
PIN ONE
LOCATION
ÉÉÉ
ÉÉÉ
ÉÉÉ
L1
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
EXPOSED Cu
TOP VIEW
A
(A3)
DETAIL B
0.10 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
L2
ÉÉÉ
ÉÉÉ
0.10 C
0.10 C
L
L
A B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
0.08 C
A1
NOTE 4
SIDE VIEW
C
D2
DETAIL C
SEATING
PLANE
K
14
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.15
0.25
6.00 BSC
4.60
4.80
6.00 BSC
4.60
4.80
0.40 BSC
0.30 REF
0.25
0.45
0.00
0.15
0.15 REF
L2
DETAIL A
L2
27
DETAIL C
8 PLACES
E2
SOLDERING FOOTPRINT*
52X
6.40
4.80
L
1
52
52X
0.63
40
52X
e
BOTTOM VIEW
b
0.07 C A B
0.05 C
NOTE 3
4.80
6.40
0.11
0.49
DETAIL D
PKG
OUTLINE
8 PLACES
52X
0.40
PITCH
DETAIL D
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP81245/D