TI1 BQ25910YFFR I2c controlled 6-a three-level switch mode, single-cell parallel battery charger for fast charging Datasheet

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bq25910
SLVSDU0A – SEPTEMBER 2017 – REVISED FEBRUARY 2018
bq25910 I2C Controlled 6-A Three-Level Switch Mode,
Single-Cell Parallel Battery Charger for Fast Charging
1 Features
2 Applications
•
•
•
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•
•
1
•
•
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Parallel Charger Operation Provides Fast
Charging in Dual Charger Configuration
High Efficiency 750-kHz Switch Mode Three-Level
Buck Parallel Charger
– Reduced Ripple to Support Low Profile
Inductor
– 95.4% Charge Efficiency at 1.5 A from 5-V
Input
– 93.3% Charge Efficiency at 3 A from 9-V Input
– Superior Efficiency Compared to Traditional
Buck Converter in Compact Form Factor
Single Input to Support USB Input and Adjustable
High Voltage Adapters
– Support 3.9-V to 14-V Input Voltage Range
with 20-V Absolute Maximum Input Voltage
Rating
– Input Current Limit (500 mA to 3.6 A with 100mA resolution) to Support USB2.0 and USB
3.0 Standard and High Voltage Adaptors
– Maximum Power Tracking by Input Voltage
Limit (VINDPM) up to 14 V
Flexible I2C Mode for Optimal System
Performance
High Integration Includes all MOSFETs, Current
Sensing and Loop Compensation
– Lossless Charge Current Sensing without
Sense Resistor
< 10-µA Low Battery Leakage Current During
Stand-By Mode
High Accuracy
– ±0.4% Charge Voltage Regulation
– ±10% Charge Current Regulation
– ±7.5% Input Current Regulation
– Remote Differential Battery Sensing
Safety
– Thermal Regulation and Thermal Shutdown
– Input UVLO and Overvoltage Protection
– Battery OVP
– Input Dynamic Power Management (DPM)
– Charging Safety Timer
– Flying Capacitor Short Circuit Protection
– Output Voltage Short Circuit Protection
Available in 36-Ball WCSP Package
Smart Phone
Tablet
Wireless Charging
Portable Electronics
Electronic Point of Sales (ePOS)
3 Description
The bq25910 is an integrated three-level switch-mode
parallel battery charge management device for single
cell Li-ion and Li-polymer batteries. Utilization of the
three-level converter maintains highest switch-mode
operation efficiency while reducing solution footprint
and increasing power density. The device supports
fast charging with high input voltage for a wide range
of portable devices. The solution integrates reverseblocking FET (QBLK), and four switching FETs (QHSA,
QHSB, QLSB, QLSA). The I2C serial interface with
charging and system settings makes the device a
truly flexible solution.
Device Information(1)
PART NUMBER
PACKAGE
bq25910
BODY SIZE (NOM)
DSBGA (36)
2.41 mm x 2.44 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
USB
VBUS
SW
BTST
I2C Bus
SYS
Host
Control
BAT
Master
VBUS
CFLY+
ICHG
SW
I2C Bus
CFLY±
Host
Host
Control
BATP
+
BATN
bq25910
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq25910
SLVSDU0A – SEPTEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Timing Requirements .............................................. 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
14
15
21
7.5 Programming .......................................................... 24
7.6 Register Maps ......................................................... 28
8
Application and Implementation ........................ 43
8.1 Application Information............................................ 43
8.2 Typical Application ................................................. 43
9 Power Supply Recommendations...................... 50
10 Layout................................................................... 51
10.1 Layout Guidelines ................................................. 51
10.2 Layout Example .................................................... 52
11 Device and Documentation Support ................. 53
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
53
53
53
53
53
53
12 Mechanical, Packaging, and Orderable
Information ........................................................... 53
4 Revision History
Changes from Original (September 2017) to Revision A
•
2
Page
Changed from Advance Information to Production Data ....................................................................................................... 1
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5 Pin Configuration and Functions
bq25910-YFF (I2C controlled)
36-Pin DSBGA
Top View
1
2
3
4
5
6
A
VBUS
PMID
CFLY+
SW
CFLY±
GND
B
VBUS
PMID
CFLY+
SW
CFLY±
GND
C
VBUS
PMID
CFLY+
SW
CFLY±
GND
D
CDRV+
PMID
CFLY+
SW
CFLY±
GND
E
CDRV±
SDA
INT
SW
CFLY±
GND
F
SCL
CAUX
REGN
BATN
BATP
IND_
SNS
x
(1)
Top View = Xray through a soldered down part with A1 starting in upper left hand corner.
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Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BATN
F4
AI
Negative Battery Sense Terminal – Kelvin connect via 100-Ω resistor as close as possible
to negative battery terminal
BATP
F5
AI
Positive Battery Sense Terminal – Kelvin connect via 100-Ω resistor as close as possible
to positive battery terminal
CAUX
F2
P
Auxiliary Capacitor – Bypass CAUX to GND with at least a 4.7-μF, 10-V ceramic capacitor
CDRV+
D1
P
Gate Drive Supply Positive Terminal – CDRV is used to generate multilevel gate drive
rails.
Connect a 220-nF, 6.3-V ceramic capacitor across CDRV+ and CDRV-.
CDRV–
E1
P
Gate Drive Supply Negative Terminal – CDRV is used to generate multilevel gate drive
rails.
Connect a 220-nF, 6.3-V ceramic capacitor across DRV+ and DRV-.
P
Flying Capacitor Positive Terminal – Connect 20-μF, 16-V ceramic capacitor across
CFLY+ and CFLY–. Refer to Application and Implementation section for more information on
selecting CFLY.
P
Flying Capacitor Negative Terminal – Connect 20-μF, 16-V ceramic capacitor across
CFLY+ and CFLY–. Refer to Application and Implementation section for more information on
selecting CFLY.
-
Ground Return
A3
B3
CFLY+
C3
D3
A5
B5
CFLY–
C5
D5
E5
A6
B6
GND
C6
D6
E6
IND_SNS
F6
AI
Output Inductor Sense Input – Kelvin connect as close as possible to the output of the
switched inductor.
INT
E3
DO
Open-Drain Interrupt Output – Connect INT to the logic rail via a 10-kΩ resistor. The INT
pin sends active low, 256-μs pulse to the host to report charger device status and fault.
A2
PMID
B2
C2
P
Reverse Blocking MOSFET and QHSA MOSFET Connection – Given the total input
capacitance, place 1 μF on VBUS, and the rest on PMID, as close to the device as possible.
Typical value: 10-μF, 25-V ceramic capacitor
D2
REGN
F3
P
Gate Drive Supply – Bias supply for internal MOSFETs driver and device. Bypass REGN to
GND with a 4.7-μF, 10-V ceramic capacitor.
SCL
F1
DI
I2C Interface Open-Drain Clock Line – Connect SCL to the logic rail through a 10-kΩ
resistor.
SDA
E2
DIO
I2C Interface Open-Drain Data Line – Connect SDA to the logic rail through a 10-kΩ
resistor.
A4
B4
SW
C4
P
Inductor Connection – Connect to the switched side of the external inductor
(Recommended: 330 nH for up to 9-V applications or 470 nH for up to 12-V applications).
Refer to Application and Implementation section for more information on selecting inductor.
P
Input Supply – VBUS is connected to the external DC supply. Bypass VBUS to GND with at
least 1-μF, 25-V ceramic capacitor, placed as close to the device as possible.
D4
E4
A1
VBUS
B1
C1
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage range (with
respect to GND)
MIN
MAX
UNIT
VBUS (converter not switching)
–2
20
V
PMID (converter not switching)
–0.3
20
V
CDRV+, CDRV-
–0.3
20
V
CFLY+
–0.3
16 (2)
V
DC
–0.3
7
V
Pulse < 30ns
CFLY+ to SW, SW to
CFLY–, CFLY– to GND,
CAUX to GND
–0.3
11
V
BATP, BATN, IND_SNS
–0.3
6
V
REGN
–0.3
6
V
Voltage range (with
respect to GND)
SDA, SCL, /INT
–0.3
6
V
Output sink current
/INT
6
mA
Junction Temperature, TJ
–40
150
°C
Storage temperature, Tstg
–40
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This condition is contingent on the fact that 0V < VCFLY < 8V
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
Charged device model (CDM), per JEDEC
specification JESD22-C101 (2)
±250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VVBUS
Input voltage
IVBUS
Average input current (VBUS)
ISW
Average output current (SW)
VBAT
Battery voltage (BATP - BATN)
TA
Operating free-air temperature
(1)
NOM
MAX
3.9
V
3.3
A
6
A
4.775
V
85
°C
14
–40
UNIT
(1)
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either CFLY+, SW, or CFLY- pins. A
tight layout minimizes switching noise.
6.4 Thermal Information
bq25910
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
36-PINS
RΘJA
Junction-to-ambient thermal resistance
52.8
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
0.3
°C/W
RΘJB
Junction-to-board thermal resistance
11.1
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
11.1
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
QUIESCENT CURRENTS
IBAT
Battery discharge current (BATP,
BATN, SW)
IVBUS_HIZ
Input supply current (VBUS) in HIZ
IVBUS
VBAT = 4.5V, VBUS = 0 - 5V, SCL, SDA =
0V or 1.8V, TJ < 85°C, EN_CHG = 0
Input supply current (VBUS)
6.5
10
μA
VBUS = 5V, High-Z Mode, no battery
30
μA
VBUS < VVBUS_OV, High-Z Mode, no
battery
50
μA
VBUS > VSLEEPZ, VBAT = 3.8V, ICHG = 0A,
converter not switching
20
μA
VBUS > VSLEEPZ, VBAT = 3.8V, converter
switching, IOUT = 0A
13
mA
VBUS / VBAT POWER UP
VVBUS_OP
VBUS operating range
3.9
VVBUS_UVLOZ
VBUS rising for active I2C, no battery VBUS rising
14
3.6
V
V
VSLEEP
Enter sleep mode threshold
VBUS falling, VBUS - VBAT,
VBAT = 4V, TJ = 0°C - 85°C
VSLEEPZ
Exit sleep mode threshold
VBUS rising, VBUS - VBAT,
VBAT = 4V, TJ = 0°C - 85°C
VBUS over-voltage rising threshold
VBUS rising
14
14.3
14.7
V
VBUS over-voltage falling threshold
VBUS falling
13.3
13.65
14
V
VVBUS_OV
15
60
110
mV
115
220
275
mV
VBAT_UVLOZ
Battery for active I2C, no VBUS
2.3
V
VPOORSRC
Bad adapter detection threshold
3.7
V
IPOORSRC
Bad adapter detection current source
20
mA
POWER-PATH
RON_QBLK (QBLK)
Top reverse blocking MOSFET onresistance between VBUS and PMID
(QBLK)
TJ = –40°C - 125°C
14
22
mΩ
RON_QHSA (Q1)
Outer, high-side switching MOSFET
on-resistance between PMID and
CFLY+ (Q1)
TJ = –40°C - 125°C
22
40
mΩ
RON_QHSB (Q3)
Inner, high-side switching MOSFET
on-resistance between CFLY+ and
SW (Q3)
TJ = –40°C - 125°C
12
20
mΩ
RON_QLSB (Q4)
Inner, low-side switching MOSFET
on-resistance between SW and
CFLY- (Q4)
TJ = –40°C - 125°C
8
13
mΩ
RON_QLSA (Q2)
Outer, low-side switching MOSFET
on-resistance between CFLY- and
GND (Q2)
TJ = –40°C - 125°C
8
13
mΩ
BATTERY CHARGER
VREG_RANGE
Typical charge voltage regulation
range
VREG_STEP
Typical charge voltage regulation
step
VREG_ACC
Charge voltage regulation accuracy
ICHG_RANGE
Typical charge current regulation
range
ICHG_STEP
Typical charge current regulation
step
ICHG_ACC
Charge current regulation accuracy
3.5
4.775
5
VREG = 4.2V or 4.35V or 4.4V,
TJ = –40°C - 85°C
mV
-0.4
0.4
%
1000
6000
mA
50
ICHG = 2A, 3A, 4A, 5A, 6A,
TJ = –40°C - 85°C
-10
mA
10
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%
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Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VBUS = 9V, ICHG = 4A, ITERM = 1.0A,
TJ = 0°C - 85°C
ITERM_ACC
Termination current regulation
accuracy
VBAT_SHORT
Short battery voltage falling threshold VBAT falling
MIN
TYP
MAX UNIT
0.9
1
1.1
A
1.85
2.00
2.15
V
VBAT LOWV Rising threshold to
start fast-charging
VBAT rising, VBATLOW = 3.2V
3.1
3.2
3.3
V
VBAT LOWV Falling threshold to
stop fast-charging
VBAT falling, VBATLOW = 3.2V
2.9
3
3.1
V
VBAT LOWV Rising threshold to
start fast-charging
VBAT rising, VBATLOW = 3.5V
3.4
3.5
3.6
V
VBAT LOWV Falling threshold to
stop fast-charging
VBAT falling, VBATLOW = 3.5V
3.2
3.3
3.4
V
RBATP
BATP Input resistance
VBAT = 4V, VBUS = 5V, EN_CHG = 0
0.6
MΩ
RBATN
BATN Input resistance
VBAT = 4V, VBUS = 5V, EN_CHG = 0
0.6
MΩ
VBAT_LOWV
VBAT_LOWV
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE
Input voltage regulation range
VINDPM_STEP
Input voltage regulation step
VINDPM_ACC
Input voltage regulation accuracy
IINDPM_RANGE
Input current regulation range
IINDPM_STEP
Input current regulation step
IINDPM_ACC
3.9
14
100
VINDPM = 4.3V
4.121
4.3
4.447
V
VINDPM = 7.8V
7.566
7.8
8.034
V
VINDPM = 10.8V
10.476
10.8
11.124
500
3600
100
Input current regulation accuracy
V
mV
V
mA
mA
IINDPM = 500mA, TJ = –40°C - 85°C
410
500
mA
IINDPM = 1500mA, TJ = –40°C - 85°C
1275
1500
mA
IINDPM = 2500mA, TJ = –40°C - 85°C
2125
2500
mA
IINDPM = 3000mA, TJ = –40°C - 85°C
2540
3000
mA
BATTERY OVER-VOLTAGE PROTECTION
VBAT_OVP
Battery over-voltage rising threshold
VBAT rising, as percentage of VREG
102
104
106
%
Battery over-voltage falling threshold
VBAT falling, as percentage of VREG
100
102
103
%
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG
TSHUT
Junction temperature regulation
accuracy
TREG = 80°C
80
°C
TREG = 120°C
120
°C
Thermal Shutdown Rising threshold
Temperature Increasing
150
°C
Thermal Shutdown Falling threshold
Temperature Decreasing
120
°C
BUCK MODE OPERATION
FSW
PWM switching frequency
DMAX
Maximum PWM Duty Cycle
Switching-node frequency
1.35
1.5
1.65 MHz
97
%
V
REGN LDO
VREGN
REGN LDO output voltage
IREGN
REGN LDO current limit
8
VVBUS = 12V, IREGN = 40mA
4.85
5
VVBUS = 5V, IREGN = 20mA
4.7
4.8
VVBUS = 5V, VREGN = 3.8V
50
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Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
I2C INTERFACE (SCL, SDA)
VIH
Input high threshold level, SDA and
SCL
Pull-up rail 1.8V
VIL
Input low threshold level, SDA and
SCL
Pull-up rail 1.8V
0.4
V
VOL
Output low threshold level, SDA
Sink current = 5mA
0.4
V
IBIAS
High level leakage current, SDA and
SCL
Pull-up rail 1.8V
1
μA
1.3
V
LOGIC OUTPUT PIN (/INT)
VOL
Output low threshold level
Sink current = 5mA
IOUT_BIAS
High level leakage current
Pull-up rail 1.8V
0.4
V
1
μA
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6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBUS/BAT POWER UP
tVBUS_OV
VBUS OVP reaction time
tPOORSRC
Bad adapter detection duration
VBUS rising above VBUS_OV threshold to
converter turn off
200
ns
30
ms
20
ms
250
ms
1
µs
BATTERY CHARGER
tBAT_LOWV_DGL
Deglitchg time for BAT_LOWV
comparator
VBAT crossing VBAT_LOWV threshold
(rising and falling)
tTERM_DGL
Deglitch time for charge termination
Charge current falling below ITERM
tBATOVP_DGL
Deglitch time for battery over-voltage
to disable charge
tSAFETY
Charge Safety Timer Accuracy
CHG_TIMER[1:0] = 12 hours
10.8
12
13.2
hr
1000
kHz
I2C INTERFACE
fSCL
SCL clock frequency
DIGITAL CLOCK AND WATCHDOG TIMER
fDIG
tWDT
10
Digital clock
REGN LDO enabled
1.35
1.5
1.65 MHz
Watchdog Reset time
WATCHDOG[1:0] = 160s, REGN LDO
enabled
136
160
sec
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96
3
95
2.7
95
2.7
94
2.4
94
2.4
93
2.1
93
2.1
92
1.8
92
1.8
91
1.5
91
1.5
90
1.2
90
1.2
89
0.9
89
0.9
88
0.6
88
0.3
87
0
86
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
87
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
86
0
1
2
3
4
Change Current (A)
5
6
0.6
VBUS = 5 V
VBUS = 9 V
1
2
D001
0.3
3
4
Charge Current (A)
5
6
D002
VBAT = 3.8 V, Inductor = HMLQ25201B-R33 (330 nH, 17 mΩ
max)
Figure 2. Charge Efficiency vs Charge Current
Figure 1. Charge Efficiency vs Charge Current
15
15
VBUS = 5 V, ICHG = 2.5 A
VBUS = 9 V, ICHG = 2.5 A
VBUS = 12 V, ICHG = 2.5 A
10
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
10
5
Accuracy (%)
Accuracy (%)
VBUS = 5 V
VBUS = 9 V
0
0
VBAT = 3.8 V, Inductor = DFE252012F-R47 (470 nH, 23 mΩ max)
Power Loss (W)
3
Efficiency (%)
96
Power Loss (W)
Efficiency (%)
6.7 Typical Characteristics
0
-5
-10
5
0
-5
-10
-15
2.9
-15
3.1
3.3
3.5
3.7
3.9
VBAT (V)
4.1
4.3
4.5
1
2
D010
3
4
ICHG Setting (A)
5
6
D003
VBAT = 3.8 V
Figure 3. Charge Current Accuracy vs Battery Voltage
Figure 4. Charge Current Accuracy vs I2C ICHG Setting
15
0.5
ICHG = 1.5 A
ICHG = 2.5 A
ICHG = 3.5 A
0.4
0.3
0.2
5
Accuracy (%)
Accuracy (%)
10
0
-5
0.1
0
-0.1
-0.2
-0.3
-10
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
-0.4
-15
-40
-20
0
20
40
Temperature (qC)
60
80
100
-0.5
3.5
D011
3.7
3.9
4.1
4.3
VREG Setting (V)
4.5
4.7
D004
VBUS = 5 V, VBAT = 3.8 V
Figure 5. Charge Current Accuracy vs Temperature
Figure 6. Battery Voltage Regulation Accuracy vs I2C VREG
Setting
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Typical Characteristics (continued)
1300
0.5
VBAT = 4.1 V
VBAT = 4.2 V
VBAT = 4.35 V
VBAT = 4.4 V
0.3
1200
Termination Current (mA)
0.4
Accuracy (%)
0.2
0.1
0
-0.1
-0.2
-0.3
1100
1000
900
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
800
-0.4
700
-0.5
-40
-20
0
20
40
Temperature (qC)
60
0
80 90
10
VBUS = 9 V
30
40
50
60
Temperature (qC)
70
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
90
D005
Figure 8. Termination Current vs Temperature
10
IINDPM = 500 mA
IINDPM = 900 mA
IINDPM = 1.5 A
IINDPM = 2.0 A
IINDPM = 3.0 A
Accuracy (%)
5
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
0
0.5
1
1.5
2
2.5
IINDPM Setting (A)
3
0
-5
-10
-15
-20
-40
3.5
-20
0
D007
VBAT = 3.8 V
20
40
Temperature (qC)
60
80
100
D013
VBUS = 5 V, VBAT = 3.8 V
Figure 9. Input Current Limit Accuracy vs I2C IINDPM
Setting
Figure 10. Input Current Limit Accuracy vs Temperature
3
2
1.8
2
TREG = 60qC
TREG = 80qC
TREG = 100qC
TREG = 120qC
1.6
Charge Current (A)
Accuracy (%)
80
VREG = 4.35 V
Figure 7. Battery Voltage Regulation Accuracy vs
Temperature
Accuracy (%)
20
D012
1
0
-1
1.4
1.2
1
0.8
0.6
0.4
0.2
-2
0
-3
3
4
5
6
7
8
9
10
VINDPM Setting (V)
11
12
13
-0.2
40
60
80
D008
100
120
Temperature (qC)
140
160
180
D009
ICHG = 1.9 A
Figure 11. Input Voltage Limit Accuracy vs I2C VINDPM
Setting
12
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Figure 12. Charge Current vs Temperature
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7 Detailed Description
7.1 Overview
The bq25910 is an integrated three-level switch-mode parallel battery charge management device for single cell
Li-ion and Li-polymer batteries. Utilization of the three-level converter maintains highest switch-mode operation
efficiency while reducing solution footprint and increasing power density. The device supports fast charging with
high input voltage for a wide range of portable devices. The solution integrates reverse-blocking FET (QBLK), and
four switching FETs (QHSA, QHSB, QLSB, QLSA). The I2C serial interface with charging and system settings makes
the device a truly flexible solution.
The device supports a wide range of input sources, including standard USB host port, USB charging port, and
USB compliant adjustable high voltage adapter. The device is compliant with USB 2.0 and USB 3.0 power
specifications with input current and voltage regulation.
After initiating a charging cycle with host control, the device completes a charging cycle without software control.
It automatically detects battery voltage and charges the battery in two-phases: constant current and constant
voltage. At the end of the charging cycle, the charger automatically terminates when the charge current is below
a preset limit (termination current) in the constant voltage phase.
The device provides various safety features for battery charging, including charging safety timer, battery overvoltage, and over-current protections. Thermal regulation reduces charge current when the device junction
temperature exceeds 120°C (programmable via I2C). The INT output immediately notifies the host when the
charger changes state or a fault occurs.
The bq25910 is available in space-saving 36-bump 2.41 x 2.44 mm2 WCSP.
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7.2 Functional Block Diagram
The device is a highly integrated 6-A three-level switch-mode parallel battery charger for single-cell Li-ion and Lipolymer batteries. It integrates a reverse-blocking FET (QBLK), four switching FETs for three-level operation
(QHSA – QLSA), and bootstrap cap control to drive HS gates.
VBUS
PMID
VVBUS_UVLO
1 F
VSLEEP
REGN
QBLK
+
UVLO
+
BLKFET
CONTROL
10 F
QHSA
BATLOWV
SLEEP
REGN
LDO
EN_CHG
4.7 F
REGN
REGN
CFLY+
+
VBUS _ OVP
VVBUS_OV
VO,REF
QHSB
D0
2x 10 F
SR 0
VVBUS
IIN
VBAT
+
IINDPM
D180
BAT_OVP
SR180
VSW
GATE DRIVERS,
CURRENT SENSE,
CFLY PRE-CHARGE
AND MONITOR
QLSB
DC-DC
CONTROL
VBAT
VBAT_REG
330nH/
470nH
OCP
+
IC_TJ
+
VBAT_OVP
+
+
VINDPM
+
TREG
ICHG
ICHG
ICHG_REG
CFLY±
QLSA
EN_CHARGE
GND
GND
CFLY_FAULT
REF
DAC
POORSRC
CONVERTER
CONTROL
STATE
MACHINE
+
VPOORSRC
IND_SNS
VVBUS
IC_TJ
TSHUTDOWN
+
TSHUT
BATP
20 F
VBAT
TERMINATION
CHARGE
CONTROL
STATE
MACHINE
INT
+
BATLOWV
BATSNS
BATN
ICHG
ITERM
+
CAUX
FETS &
CONTROL
VBAT_LOWV
VBAT
CAUX
4.7 F
BATSHORT
+
VBAT_SHORT
VBAT
I2C
INTERFACE
bq25910
BOOTSTRAP
CAP CONTROL
CDRV+
220 nF
SCL
SDA
CDRV±
Copyright © 2017, Texas Instruments Incorporated
Figure 13. bq25910 I2C Controlled Functional Block Diagram
14
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7.3 Feature Description
7.3.1 Device Power-On-Reset (POR)
The internal bias circuits are powered from the higher voltage of VBUS and VBAT. When VVBUS rises above
VVBUS_UVLOZ, or VBAT rises above VBAT_UVLOZ, the sleep comparator and battery depletion comparator are active.
I2C interface is ready for communication and all the registers are reset to default value. The host can access all
the registers after POR.
7.3.2 Device Power Up from Battery without Input Source
If only battery is present, the device consumes up to IBAT quiescent current. The REGN LDO stays off to
minimize the current draw. I2C interface is ready for communication as long as VBAT is above VBAT_UVLOZ.
7.3.3 Device Power Up from Input Source
When an input source is plugged in, and the EN_CHG bit is set to 1, the device checks the input source voltage
and battery voltage to turn on REGN LDO, all the bias circuits and begin charging. The startup sequence from
input source is as listed:
1. Power up REGN LDO
2. Poor source qualification
3. CFLY and CAUX pre-charging routine
4. Converter Power-up
7.3.4 Power Up REGN LDO
The REGN LDO supplies internal bias circuits and power FET gate drivers. The pull-up rail of INT can be
connected to REGN as well. The REGN LDO is enabled when all the following conditions are met:
1. VBUS above VBUS_UVLOZ
2. VBUS above VBAT + VSLEEPZ
3. VBUS below VVBUS_OV
4. VBAT above VBAT_LOWV
5. EN_CHG bit = 1
6. ICHG ≠ 0 A
If one of the above conditions is not met, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than IVBUS_HIZ from VBUS in this state.
7.3.5 Poor Source Qualification
After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements in order to operate the buck converter:
1. VBUS voltage below VVBUS_OV
2. VBUS voltage above VPOORSRC when pulling IPOORSRC (typical 20 mA)
Once the conditions are met, the status register bit PG_STAT is set high and the INT pin is pulsed to signal the
host. If VBUS_OV is detected (condition 1 above), the device automatically retries detection once the overvoltage fault goes away. If a poor source is detected (condition 2 above), the device repeats poor source
qualification routine every 2 seconds. After 7 consecutive failures, the device sets POORSRC_STAT, sends an
INT pulse to notify the host, goes to HIZ mode and resets EN_CHG bit. Adapter re-plugin and/or EN_CHG toggle
is required to restart device operation.
7.3.6 Converter Power-Up
Prior to converter switching, the flying and auxiliary capacitors, CFLY, and CAUX are charged to VBUS/2. After
the capacitors have been pre-charged, the converter is enabled and the switching FETs QHSA – QLSB start
switching. As a battery charger, the device deploys a highly-efficient 750-kHz three-level step-down switching
regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of
input voltage, battery voltage, charge current and temperature, simplifying output filter design.
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Feature Description (continued)
The charge current is soft-started into the desired value by starting from 300 mA and increasing the current up to
ICHG programmed value over time. This "soft-start" also applies when increasing the ICHG register value while
charging.
7.3.7 Three-Level Buck Converter Theory of Operation
The three-level converter is a combination of a switched capacitor and a switched inductor circuit. Assuming the
flying capacitor, CFLY, remains balanced at VIN/2, the VSW node can be presented with three different voltages:
VIN, VIN/2, and GND. The gate driving scheme is similar to a two-phase buck converter. The outer FETs (QHSA
and QLSA) are driven with a complimentary signal with duty cycle D = VOUT/VIN. The inner FETs (QHSB and
QLSB) are driven with a second complimentary signal of equal duty cycle, but phase shifted by 180°. By
employing this driving scheme, there is a smooth transition around 50% duty ratio, where the VSW node moves
from presenting GND and VIN/2 to presenting VIN and VIN/2.
The three-level can achieve higher efficiency which cannot be easily obtained using traditional buck converter.
The high efficiency is due to reduced inductor ripple (volt-seconds), reduced switching loss, and use of a
compact inductor with lower DCR. The device integrates low RDSON FETs to optimize conduction loss. It also
integrates control circuit to monitor CFLY stability and pre-conditioning.
D < 0.50
L
VSW
VIN
QHSA
VIN
QHSB
+
+
±
VSW
VIN/2
QLSB
±
CO
CFLY
VO
+
VO
±
t
VSW
VIN
QLSA
D > 0.50
VO
VIN/2
t
Figure 14. (a) Three-Level Buck Converter Circuit, (b) Time-Domain VSW and VO Waveforms, and (c)
Inductor Current Ripple Comparison Across Duty Ratio
D < 0.50
VSW
QHSA
L
VSW
QHSB
QHSA
VIN
+
QHSA
QHSB
QLSB
±
CO
CFLY
+
VO VIN
±
+
+
±
QLSB
±
CO
CFLY
+
VO VIN
±
+
+
±
±
CO
CFLY
QLSA
QLSA
L
VSW
QHSB
QLSB
+
±
L
+
VO
±
QLSA
Figure 15. Three-Level Buck Converter States for Duty Ratios < 0.50
D > 0.50
VSW
QHSA
L
VSW
QHSB
QHSA
VIN
+
CO
CFLY
QHSA
QHSB
QLSB
±
QLSA
+
VO
±
VIN
+
±
+
QLSB
±
CO
CFLY
L
VSW
QHSB
QLSB
+
±
L
+
VO VIN
±
+
±
+
±
CO
CFLY
QLSA
+
VO
±
QLSA
Figure 16. Three-Level Buck Converter States for Duty Ratios > 0.50
16
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Feature Description (continued)
7.3.8 Host Mode and Default Mode
7.3.8.1 Host Mode and Default Mode in bq25910
The bq25910 is a host controlled charger, and will automatically shut off when the I2C watchdog timer is not reset
within the timer period. In default (HIZ) mode, the device automatically disables charging until the host writes the
EN_CHG bit high again and resets the watchdog timer via the WD_RST bit. When the charger is in default
mode, WD_STAT bit is HIGH. When the charger is in host mode, WD_STAT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired. All the registers are in the
default settings. In default mode, the device remains in HIZ mode and will not charge the battery.
Writing a 1 to the WD_RST bit forces the charger out of default mode and into host mode. All the device
parameters can be programmed by the host. To keep the device in host mode, the host has to reset the
watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set), or disable
watchdog timer by setting WATCHDOG bits = 00.
When the watchdog timer is expired (WD_STAT bit = 1), the device returns to default mode and registers are
reset to default values except as detailed in the I2C register section. As long as the watchdog timer is expired
(WD_STAT bit = 1), the device remains in Default Mode without charging the battery, regardless of the EN_CHG
bit state. In order to enable charge after watchdog expired, write WD_RST = 1, and EN_CHG = 1.
POR
Watchdog timer expired
Reset registers
I2C interface enabled
Default Mode
Watchdog timer expired
Reset selective registers
N
Y
Watchdog Timer
Expired?
WD_RST bit = 1?
N
Y
Host Mode
Start Watchdog timer
Host programs registers
WD_RST bit = 1?
N
Y
Figure 17. Watchdog Timer Flow Chart
The REG_RST bit can be used to reset all of the registers (except STATUS registers) to their default value at
any time.
7.3.9 Battery Charging Management
The device charges single-cell Li-Ion battery with up to 6-A charge current for high-capacity battery.
7.3.9.1 Autonomous Charging Cycle
When battery charging is enabled (EN_CHG bit = 1) and the battery is above VBAT_LOWV, the device
autonomously completes a charging cycle. The device default charging parameters are listed in Table 1. The
host can always control the charging operations and optimize the charging parameters by writing to the
corresponding registers through I2C.
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Feature Description (continued)
Table 1. Charging Parameter Default Settings
PARAMETER
A
•
•
•
•
VALUE
VBAT to start fast charge (VBATLOWV)
3.5 V
Charging voltage (VREG)
4.350 V
Charging current (ICHG)
3.500 A
Termination current (ITERM)
1.000 A
Safety timer (CHG_TIMER)
12 hours
new charge cycle starts when the following conditions are valid:
Converter starts
Battery charging is enabled by EN_CHG bit, and ICHG register is not 0 mA
Battery voltage above VBAT_LOWV
No safety timer fault
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, and device not in DPM mode or thermal regulation. Once termination is detected, an INT is asserted
to the host and the EN_CHG bit gets reset to zero. After the charge is done, EN_CHG bit can initiate a new
charging cycle.
Once a charging cycle is complete, an INT pulse is asserted to notify the host. In addition the status register
(CHRG_STAT) indicates the different charging phases (any change in CHRG_STAT will generate an INT to
notify the host):
• 000: Charging disable
• 001: Reserved
• 010: Reserved
• 011: Fast charge (constant current mode)
• 100: Taper charge (constant voltage mode)
• 101: Reserved
• 110: Reserved
• 111: Reserved
7.3.10 Master Charger and Parallel Charger Interactions
A master charger is required in the system to manage pre-charging and full termination of the battery. The
bq25910 monitors the battery voltage and compares it to VBAT_LOWV to ensure battery can safely take fast-charge
current. Once the bq25910 turns on and begins fast-charging, the host has two options: disable (HIZ) the master
charger, or continue running the master charger along with the parallel charger.
For the first option, once battery voltage reaches VBAT_LOWV, the master charger maintains the BATFET on to
supply system from battery (EN_HIZ = 1 on master charger), and the bq25910 provides both the charge current
and system current if required. It is recommended to select VBAT_LOWV equal to minimum system voltage in order
to maintain system operation during transition. The bq25910 will then fast-charge the battery up to VREG and
continue to regulate voltage while battery current tapers down. After the bq25910 detects termination, the host
can re-enable the master charger to regulate battery voltage in CV mode down to lower termination currents.
The second mode of operation requires both chargers to stay on. In order to maximize efficiency, it is
recommended to run the master charger at lower charge current than the bq25910. For example, the master
charger might be set at 1 A and the bq25910 at 3.5 A to achieve total charge current of 4.5 A. In this mode of
operation, the master charger provides mostly system current, while the bq25910 provides mostly charge current.
In this mode of operation, the bq25910 can select VBAT_LOWV as low as the battery dictates for fast-charge, since
the master charger can maintain system voltage regulation and ensure system continues to operate through the
transition. After the bq25910 detects termination, the master charger automatically continues to regulate battery
voltage in CV mode down to lower termination current.
Figure 18 shows both options with charge current for each device as well as battery voltage.
18
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Voltage
4.35V
BATP - BATN
SYS_MIN
3.5V
BATP - BATN
Time
Current
4.5A
bq2591x
ICHG
Master Charger
ICHG
2A
Time
Master Charger:
Pre-charges BAT
Master Charger:
HIZ or
,&+* ” 1A
Master Charger:
HIZ or
,&+* ” 1A
Master Charger:
ITERM << 0.5A
bq25910:
Off
bq25910:
ICHG = 4.5A
bq25910:
ITERM = 1A
bq25910:
Off
Figure 18. Master Charger and bq25910 Handoff
7.3.11 Battery Charging Profile
The device charges the battery in two phases: constant current, and constant voltage. At the beginning of a
charging cycle, the device checks the battery voltage and regulates current / voltage as needed. If the battery
voltage is below VBAT_LOWV, it is the master charger responsibility to increase VBAT up to VBAT_LOWV so the
parallel charger can initiate fast charging. As BAT increases to VBAT_LOWV, the master charger can stay in HIZ
and the bq25910 can start fast-charging the battery with up-to 6-A ICHG. Alternatively, the master charger can
remain on to maintain the system load from adapter, while the bq25910 charges the battery. The default charging
settings can be found in Table 2.
Table 2. Battery Charger Setting
VBAT
CHARGING CURRENT
REG DEFAULT SETTING
CHRG_STAT
<2V
Master controlled (IBATSHORT )
bq25910 off
000
2 V – VBAT_LOWV
Master controlled (IPRECHG )
bq25910 off
000
> VBAT_LOWV
ICHG
3.500 A
011
VREG
TAPER down to ITERM
4.350 V
100
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If the charger device is in DPM regulation or thermal regulation during charging, the charging current can be less
than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is
counted at half the clock rate.
bq25910 Charge Cycle
Fast Charge
ICHG
bq25910 on
VREG
Battery Current
Battery Voltage
VBATLOWV
ITERM
3.0V
0A
Pre-Charge
Master
Charger
CHRG_STAT[2:0]
CC
Master
Charger
CC
bq25910
CV
bq25910
CV
Master
Charger
000
011
100
000
Figure 19. Battery Charging Profile Highlighting Parallel Charger Region of Operation
After the device signals charge termination done (CHRG_TERM_FLAG = 1), the master charger may choose to
continue charging in CV mode or finish the charging cycle completely. The bq25910 will not start a re-charge
cycle automatically, and a toggle on EN_CHG bit is required to restart a charge cycle.
7.3.11.1 Charging Termination
The device terminates a charge cycle when the battery voltage is at VREG, and the current is below termination
current (ITERM). After the charging cycle is completed, the converter turns off and enters HIZ mode. At this
point, the master charger can continue charging the battery down to a lower termination current, or just provide
the system load from the adapter through its buck converter.
When termination occurs, the status register CHRG_STAT is set to 000, the CHRG_TERM_FLAG is set to 1,
and an INT pulse is asserted to the host. The CHRG_TERM_FLAG should be used to determine if termination
was detected. Termination is temporarily disabled when the charger device is in input current, input voltage or
thermal regulation.
Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination. In this case, the device will
continue regulating the battery voltage to VREG value until the safety timer runs out or until the EN_CHG bit is
cleared.
7.3.11.2 Differential Battery Voltage Remote Sensing
For high current charging systems, resistance between the charger output and battery cell terminal such as
board routing, connector, MOSFETs and sense resistor can force the charging process to move from constant
current to constant voltage too early, thereby increasing charge time. To speed up the charging cycle, the device
provides differential remote sensing terminals for battery positive and negative terminals, which can extend the
constant current charge time to deliver maximum power to the battery.
The device regulates BATP – BATN = VBAT to the programmed VREG voltage. By connecting the sense
terminals as close the battery as possible, the charger can deliver maximum charging power to battery. The
kelvin connections to the battery can be made via a 100-Ω resistor.
20
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7.3.11.3 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the
TMR_FLAG bit is set to 1, and an INT pulse is asserted to the host. The safety timer feature can be disabled via
I2C using EN_TIMER bit.
During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the register setting. For example, if the charger is in input current regulation
(IINDPM_STAT = 1) throughout the whole charging cycle, and the safety timer is set to 5 hours, then the timer
will expire in 10 hours. This half clock rate feature can be disabled by setting TMR2X_EN = 0. Changing the
TMR2X_EN bit while the device is running has no effect on the safety timer count, other than forcing the timer to
count at half the rate under the conditions dictated above.
7.4 Device Functional Modes
7.4.1 Lossless Current Sensing
In high current charging systems, extra resistance between the charger output and the battery contribute to
power loss and temperature rise. The bq25910 regulates the output current without the need of a sense resistor,
thereby reducing system power loss and operating temperature. Switching FET current information is used in
conjunction to inductor DCR sensing to regulate output current accurately. For optimal operation, the voltage
drop across the DCR should be below 180 mV. For example, to achieve 6-A charging, the DCR should be below
30 mΩ. In addition to lossless current regulation, the switching FET current is monitored on a cycle-by-cycle
basis to ensure safe operation.
7.4.2 Dynamic Power Management
To meet maximum current limit in USB spec and avoid over-loading the adapter, the device features Dynamic
Power Management (DPM), which continuously monitors the input current and input voltage. When input source
is over-loaded, either the current exceeds the input current limit (IINDPM) or the voltage falls below the input
voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input
current limit and the input voltage rises above the input voltage limit.
During DPM mode, the status register bits VINDPM_STAT (VINDPM) and/or IINDPM_STAT (IINDPM) is/are set
to 1. Figure 20 shows the IINDPM response with 9-V/1.33-A (12-W) adapter, 4.0-V battery, 3.5-A charge current,
and bq25910 in CV mode.
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Device Functional Modes (continued)
SYSTEM
LOAD
ISYS
VBUS
SYS
VBUS
bq25898
(Hi-Z Mode)
BAT
IOUT,910
IBUS
SW2
VBUS
IBAT
+
VBAT
GND
bq25910
VBUS
9.0V
8.5V
4A
3A
2A
1A
0A
IOUT
IBAT
IBUS
ISYS
-1A
CV
IINDPM
CV
Figure 20. DPM Response
7.4.3 Interrupt to Host (INT)
In some applications, the host does not always monitor the charger operation. The INT pin notifies the system
host on the device operation. By default, the following events will generate an active-low, 256-μs INT pulse.
1. Good input source detected (three conditions below met)
– VVBUS > VBAT (not in sleep)
– VVBUS < VVBUS_OV
– VVBUS > VVPOORSRC (typ 3.7 V) when IPOORSRC (typ 20 mA) current is applied (not a poor source)
2. Good input source removed
3. POORSRC routine failed 7 consecutive times (connected adaptor was found to be a poor source)
4. Capacitor pre-charge routine failed (CFLY / CAUX failed to pre-charge)
5. Entering IINDPM regulation
6. Entering VINDPM regulation
7. Entering device Junction Temperature Regulation
22
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Device Functional Modes (continued)
8. I2C Watchdog timer expired
– At initial power-up, this INT gets asserted to signal I2C is ready for communication
9. Charger changes state (CHRG_STAT value change)
10. VBUS over-voltage detected
11. Junction temperature shutdown (TSHUT)
12. Battery over-voltage detected (BATOVP)
13. CFLY fault detected
14. Charge Safety Timer Expired
Each one of these INT sources can be masked off to prevent INT pulses from being sent out when they occur.
Three bits exist for each one of these events:
• The STAT bit holds the current status of each INT source
• The FLAG bit holds information on which source produced an INT, regardless of current status.
• The MASK bit is used to prevent the device from sending out INT for each particular event.
When one of the above conditions occurs, the device sends out an INT pulse and keeps track of which source
generated the INT via the FLAG registers. The FLAG register bits are automatically reset to zero after the host
reads them, and a new edge on STAT bit is required to re-assert the FLAG.
IINDPM_STAT
IINDPM_FLAG
TREG_STAT
TREG_FLAG
INT
I2C Flag Read
Figure 21. INT Generation Behavior Example
7.4.4 Protections
7.4.4.1 Voltage and Current Monitoring
The device closely monitors the input and output voltage, as well as switching FET currents for safe buck mode
operation.
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Device Functional Modes (continued)
7.4.4.1.1 Input Over-Voltage (VVBUS_OV)
The valid input voltage range for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VVBUS_OV, the
device stops switching immediately to protect the power FETs. During input over-voltage, an INT pulse is
asserted to signal the host, and the VBUS_OVP_STAT and VBUS_OVP_FLAG fault register bits get set. The
device automatically starts switching again when the over-voltage condition goes away.
7.4.4.1.2 Input Under-Voltage (VPOORSRC)
The valid input voltage range for buck mode operation is VVBUS_OP. If VBUS voltage falls below VPOORSRC, the
device stops switching. During input under-voltage, an INT pulse is asserted to signal the host, and the
PG_STAT bit gets cleared. The PG_FLAG bit will get set to signal this event. The device automatically attempts
to restart switching when the under-voltage condition goes away.
7.4.4.1.3 Flying Capacitor Over- or Under-Voltage Protection (VCFLY_OVP and VCFLY_UVP)
Under normal operating conditions the flying capacitor is balanced by the converter. However, during line
transients or other failures, capacitor mis-balance is possible. The device constantly monitors the flying capacitor
voltage. If VCFLY exceeds the protection limits, the device stops switching immediately. When this fault is
detected, an INT pulse is asserted to notify the host, and the CFLY_STAT and CFLY_FLAG fault register bits get
set. The device automatically attempts to re-balance the cap and resumes charging if successful. If the device
fails to re-balance CFLY, the CAP_COND_STAT and CAP_COND_FLAG fault register bits get set, and an
EN_CHG toggle is required to re-attempt charging.
7.4.4.1.4 Over Current Protection
The device monitors the outer switching FET current on a cycle-by-cycle basis . If an over-current is detected,
the device responds by forcing the switching FETs to immediately discharge the inductor current and attempt
current ramp-up once again.
7.4.4.2 Thermal Regulation and Thermal Shutdown
The device monitors internal junction temperature TJ to avoid overheating the chip and limits the device surface
temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit
(TREG bits), the device reduces charge current. A wide thermal regulation range from 60°C to 120°C allows the
user to optimize the system thermal performance.
During thermal regulation, the actual charging current is usually below the programmed value in ICHG registers.
Therefore, termination is disabled, the safety timer runs at half the clock rate, the status register TREG_STAT bit
goes high, and an INT is asserted to the host.
Additionally, the device has thermal shutdown to turn off the converter when device surface temperature exceeds
TSHUT. The fault register TSHUT_STAT is set and an INT pulse is asserted to the host. The converter turns back
on when device temperature is below TSHUT_HYS.
7.4.4.3 Battery Protection
7.4.4.3.1 Battery Over-Voltage Protection (BATOVP)
The battery over-voltage limit is clamped at 4% above the battery regulation voltage. When battery over-voltage
occurs, the charger device immediately disables charge. The fault register BATOVP_STAT bit goes high and an
INT pulse is asserted to signal the host.
7.5 Programming
7.5.1 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial
data line (SDA), and a serial clock line (SCL). Devices can be considered as masters or slaves when performing
data transfers. A master is a device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave.
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Programming (continued)
The device operates as a slave device with address 4BH, receiving control inputs from the master device like
micro-controller or digital signal processor through REG00-REG0D. Register read beyond REG0D (0x0D) returns
0xFF. The I2C interface supports both standard mode (up to 100 kbits/s), and fast mode (up to 400 kbits/s).
When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the
positive supply voltage via a current source or pull-up resistor.
7.5.2 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on SCL line is LOW. One clock pulse is generated for each data
bit transferred.
SDA
SCL
Data line stable;
Data valid
Change of
data allowed
Figure 22. Bit Transfers on the I2C Bus
7.5.3 START and STOP Conditions
All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The
bus is considered busy after the START condition, and free after the STOP condition.
SDA
SDA
SCL
SCL
STOP (P)
START (S)
Figure 23. START and STOP Conditions on the I2C Bus
7.5.4 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the Most
Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has
performed some other function, it can hold the SCL line low to force the master into a wait state (clock
stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL
line.
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Programming (continued)
Acknowledgement
signal from receiver
Acknowledgement
signal from slave
MSB
SDA
SCL
S or Sr
1
2
8
7
2
1
9
8
P or Sr
9
ACK
ACK
START or
Repeated
START
STOP or
Repeated
START
Figure 24. Data Transfer on the I2C Bus
7.5.5 Acknowledge (ACK) and Not Acknowledge (NACK)
The ACK signaling takes place after byte. The ACK bit allows the receiver to signal the transmitter that the byte
was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock
pulse, are generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse
so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this 9th clock
pulse. A NACK is signaled when the SDA line remains HIGH during the 9th clock pulse. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
7.5.6 Slave Address and Data Direction Bit
After the START signal, a slave address is sent. This address is 7 bits long, followed by the 8 bit as a data
direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
The device 7-bit address is defined as 1001 011’ (0x4BH) by default. The address bit arrangement for 4BH is
shown in Figure 25.
Slave Address
1
0
0
1
0
1
1
R/W
Figure 25. 14: 7-Bit Addressing (4BH)
SDA
SCL
S
1-7
START
ADDRESS
8
R/W
9
ACK
1-7
8
DATA
9
1-7
ACK
8
DATA
9
ACK
P
STOP
2
Figure 26. Complete Data Transfer on I C Bus
7.5.7 Single Read and Write
Figure 27. Single Write
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Programming (continued)
Figure 28. Single Read
If the register address is not defined, the charger device sends back NACK and returns to the idle state.
7.5.8 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write of all registers.
Figure 29. Multi-Write
Figure 30. Multi-Read
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7.6 Register Maps
7.6.1 I2C Registers
Table 3 lists the memory-mapped registers for the I2C. All register offset addresses not listed in Table 3 should
be considered as reserved locations and the register contents should not be modified.
Table 3. I2C Register Summary Table
Address
Access Type
Acronym
Register Name
0h
R/W
REG00
Battery Voltage Limit
Section
Go
1h
R/W
REG01
Charge Current Limit
Go
2h
R/W
REG02
Input Voltage Limit
Go
3h
R/W
REG03
Input Current Limit
Go
4h
R/W
REG04
RESERVED
Go
5h
R/W
REG05
Charger Control 1
Go
6h
R/W
REG06
Charger Control 2
Go
7h
R
REG07
INT Status
Go
8h
R
REG08
FAULT Status
Go
9h
R
REG09
INT Flag
Go
Ah
R
REG0A
FAULT Flag
Go
Bh
R/W
REG0h
INT Mask
Go
Ch
R/W
REG0C
FAULT Mask
Go
Dh
R/W
REG0D
Part Information
Go
Complex bit access types are encoded to fit into small table cells. Table 4 shows the codes that are used for
access types in this section.
Table 4. I2C Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset Value
28
-n
Value after reset
-X
Undefined value
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7.6.1.1 Battery Voltage Regulation Limit Register (Address = 0h) [reset = AAh]
REG00 is shown in Figure 31 and described in Table 5.
Return to Summary Table.
Figure 31. REG00 Register
7
6
5
4
3
2
1
0
VREG[7:0]
R/W-AAh
Table 5. REG00 Register Field Descriptions
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
Description
7
VREG[7]
R/W
Yes
Yes
640 mV
6
VREG[6]
R/W
Yes
Yes
320 mV
5
VREG[5]
R/W
Yes
Yes
160 mV
4
VREG[4]
R/W
Yes
Yes
80 mV
3
VREG[3]
R/W
Yes
Yes
40 mV
2
VREG[2]
R/W
Yes
Yes
20 mV
1
VREG[1]
R/W
Yes
Yes
10 mV
0
VREG[0]
R/W
Yes
Yes
5 mV
Bit
Charge voltage limit:
Offset: 3.5 V
Range: 3.5 V to 4.775 V
Default 4.35 V
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7.6.1.2 Charger Current Limit Register (Address = 1h) [reset = 46h]
REG01 is shown in Figure 32 and described in Table 6.
Return to Summary Table.
Figure 32. REG01 Register
7
RESERVED
R/W-0h
6
5
4
3
ICHG[6:0]
R/W-46h
2
1
0
Table 6. REG01 Register Field Descriptions
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
7
RESERVED
R/W
Yes
Yes
Reserved bit always reads 0h
6
ICHG[6]
R/W
Yes
Yes
3200 mA
5
ICHG[5]
R/W
Yes
Yes
1600 mA
4
ICHG[4]
R/W
Yes
Yes
800 mA
3
ICHG[3]
R/W
Yes
Yes
400 mA
2
ICHG[2]
R/W
Yes
Yes
200 mA
1
ICHG[1]
R/W
Yes
Yes
100 mA
0
ICHG[0]
R/W
Yes
Yes
50 mA
Bit
30
Description
Fast charge current limit
Offset: 0 mA
Range: 0 mA to 6000 mA
Default: 3500 mA
NOTE: ICHG > 6 A (78h) clamped to 6 A
ICHG < 300 mA (06h) clamped to 0 A
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7.6.1.3 Input Voltage Limit Register (Address = 2h) [reset = 04h]
REG02 is shown in Figure 33 and described in Table 7.
Return to Summary Table.
Figure 33. REG02 Register
7
RESERVED
R/W-0h
6
5
4
3
VINDPM[6:0]
R/W-04h
2
1
0
Table 7. REG02 Register Field Descriptions
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
7
RESERVED
R/W
Yes
No
Reserved bit always reads 0h
6
VINDPM[6]
R/W
Yes
No
6400 mV
5
VINDPM[5]
R/W
Yes
No
3200 mV
4
VINDPM[4]
R/W
Yes
No
1600 mV
3
VINDPM[3]
R/W
Yes
No
800 mV
2
VINDPM[2]
R/W
Yes
No
400 mV
1
VINDPM[1]
R/W
Yes
No
200 mV
0
VINDPM[0]
R/W
Yes
No
100 mV
Bit
Description
Absolute input-voltage limit
Offset: 3.9 V
Range: 3.9 V to 14 V
Default: 4.3 V
NOTE: VINDPM > 14 V (65h) clamped to 14 V
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7.6.1.4 Input Current Limit Register (Address = 3h) [reset = 13h]
REG03 is shown in Figure 34 and described in Table 8.
Return to Summary Table.
Figure 34. REG03 Register
7
6
5
4
3
RESERVED
R/W-0h
2
1
0
INDPM[5:0]
R/W-13h
Table 8. REG03 Register Field Descriptions
Bit
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
7-6
RESERVED
R/W
Yes
No
Reserved bit always reads 0h
5
INDPM[5]
R/W
Yes
No
3200 mA
4
INDPM[4]
R/W
Yes
No
1600 mA
3
INDPM[3]
R/W
Yes
No
800 mA
2
INDPM[2]
R/W
Yes
No
400 mA
1
INDPM[1]
R/W
Yes
No
200 mA
0
INDPM[0]
R/W
Yes
No
100 mA
32
Description
Input current limit
Offset: 500 mA
Range: 500 mA to 3600 mA
Default: 2400 mA
NOTE: INDPM > 3600 mA (1Fh) clamped to 3600mA
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7.6.1.5 Reserved Register (Address = 4h) [reset = 03h]
REG04 is shown in Figure 35 and described in Table 9.
Return to Summary Table.
Figure 35. REG04 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
R/W-3h
Table 9. REG04 Register Field Descriptions
Bit
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
7-0
RESERVED
R/W
Yes
Yes
Description
Reserved bit always reads 03h
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7.6.1.6 Charger Control 1 Register (Address = 5h) [reset = 9Dh]
REG05 is shown in Figure 36 and described in Table 10.
Return to Summary Table.
When the WATCHDOG[1:0] bits change (writing the same value does not change these bits), the internal
counter is reset. The same applies for the CHG_TIMER bits (changing the value in the register will reset the
CHG_TIMER).
Figure 36. REG05 Register
7
EN_TERM
R/W-1h
6
WD_RST
R/W-0h
5
4
WATCHDOG[1:0]
R/W-1h
3
EN_TIMER
R/W-1h
2
1
CHG_TIMER[1:0]
R/W-2h
0
TMR2X_EN
R/W-1h
Table 10. REG05 Register Field Descriptions
Bit
7
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
EN_TERM
R/W
Yes
Yes
Description
Termination control
0h = Disable termination
1h = Enable termination
6
WD_RST
R/W
Yes
Yes
I2C watchdog-timer reset
0h = Normal
1h = Reset (bit returns to 0 after time reset)
5-4
WATCHDOG[1:0]
R/W
Yes
Yes
I2C watchdog-timer settings
0h = Disable watchdog timer
1h = 40 s
2h = 80 s
3h = 160 s
3
EN_TIMER
R/W
Yes
Yes
Charging safety-timer enable
0h = Disable
1h = Enable
2-1
CHG_TIMER[1:0]
R/W
Yes
Yes
Fast-charge safety timer setting
0h = 5 hours
1h = 8 hours
2h = 12 hours
3h = 20 hours
0
TMR2X_EN
R/W
Yes
Yes
Safety timer behavior during DPM or TREG
0h = Safety timer always counts normally
1h = Safety timer count slowed by 2x during input DPM or
TREG
34
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7.6.1.7 Charger Control 2 Register (Address = 6h) [reset = 33h]
REG06 is shown in Figure 37 and described in Table 11.
Return to Summary Table.
When the watchdog timer expires (WD_STAT = 1h), the EN_CHG bit is held in reset. To enable the charger after
the watchdog expires, write a value of 1h to the WD_RST bit and a value of 1h to the EN_CHG bit.
Figure 37. REG06 Register
7
6
5
RESERVED
R/W-0h
4
TREG[1:0]
R/W-3h
3
EN_CHG
R/W-0h
2
RESERVED
R/W-0h
1
0
VBATLOWV[1:0]
R/W-3h
Table 11. REG06 Register Field Descriptions
Bit
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
7-6
RESERVED
R/W
Yes
Yes
Reserved bit always reads 0h
5-4
TREG[1:0]
R/W
Yes
Yes
Thermal regulation threshold
Description
0h = 60°C
1h = 80°C
2h = 100°C
3h = 120°C
3
EN_CHG
R/W
Yes
Yes
Charger enable configuration
0h = Charger disabled
1h = Charger enabled
2
1-0
RESERVED
R/W
Yes
Yes
Reserved bit always reads 0h
VBATLOWV[1:0]
R/W
Yes
No
VBAT_LOWV threshold to start charging at ICHG programmed
setting:
0h = 2.6 V
1h = 2.9 V
2h = 3.2 V
3h = 3.5 V
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7.6.1.8 INT Status Register (Address = 7h) [reset = X]
REG07 is shown in Figure 38 and described in Table 12.
Return to Summary Table.
Figure 38. REG07 Register
7
PG_STAT
R-X
6
INDPM_STAT
R-X
5
VINDPM_STAT
R-X
4
TREG_STAT
R-X
3
WD_STAT
R-X
2
1
CHRG_STAT[2:0]
R-X
0
Table 12. REG07 Register Field Descriptions
Bit
7
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
PG_STAT
R
Yes
Yes
Description
Power-good status
0h = Not power good
1h = Power good
6
INDPM_STAT
R
Yes
Yes
INDPM status
0h = Normal
1h = In INDPM regulation
5
VINDPM_STAT
R
Yes
Yes
VINDPM status
0h = Normal
1h = In VINDPM regulation
4
TREG_STAT
R
Yes
Yes
Device thermal-regulation status
0h = Normal
1h = In thermal regulation
3
WD_STAT
R
Yes
No
I2C watchdog-timer status
0h = Normal
1h = Watchdog timer expired
2-0
CHRG_STAT[2:0]
R
Yes
Yes
Charge status
0h = Not charging
1h = Reserved
2h = Reserved
3h = Fast charging (CC mode)
4h = Taper charging (CV mode)
5h = Reserved
6h = Reserved
7h = Reserved
36
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7.6.1.9 FAULT Status Register (Address = 8h) [reset = X]
REG08 is shown in Figure 39 and described in Table 13.
Return to Summary Table.
When the watchdog timer expires (WD_STAT = 1h), the VBUS_OVP_STAT, TSHUT_STAT, BATOVP_STAT,
and CFLY_STAT bits are held in reset until the watchdog fault is cleared (WD_RST bit = 1h, or changing the
WATCHDOG[1:0] bits).
Figure 39. REG08 Register
7
VBUS_OVP_S
TAT
R-X
6
TSHUT_STAT
5
BATOVP_STA
T
R-X
R-X
4
CFLY_STAT
3
RESERVED
R-X
R-0h
2
CAP_COND_S
TAT
R-X
1
POORSRC_ST
AT
R-X
0
RESERVED
R-0h
Table 13. REG08 Register Field Descriptions
Bit
7
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
VBUS_OVP_STAT
R
Yes
Yes
Description
Input-overvoltage status
0h = Normal
1h = Device in overvoltage protection
6
TSHUT_STAT
R
Yes
Yes
Device temperature-shutdown status
0h = Normal
1h = Device in thermal-shutdown protection
5
BATOVP_STAT
R
Yes
Yes
Battery overvoltage status
0h = Normal
1h = BATOVP (VBAT > VBATOVP)
4
CFLY_STAT
R
Yes
Yes
Flying capacitor status
0h = Normal
1h = Flying capacitor fault (VCFLY_UVP or OVP)
3
Reserved
R
Yes
Yes
Reserved bit always reads 0
2
CAP_COND_STAT
R
Yes
Yes
Capacitor precondition status
0h = Normal
1h = CFLY or CAUX precondition failed
1
POORSRC_STAT
R
Yes
Yes
Poor-source-detection status
0h = Normal
1h = POORSRC routine failed 7 consecutive times
0
RESERVED
R
Yes
Yes
Reserved bit always reads 0
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7.6.1.10 INT Flag Status Register (Address = 9h) [reset = 00h]
REG09 is shown in Figure 40 and described in Table 14.
Return to Summary Table.
All bits in REG09 are automatically cleared after a read.
Figure 40. REG09 Register
7
PG_FLAG
6
INDPM_FLAG
5
VINDPM_FLAG
4
TREG_FLAG
3
WD_FLAG
R-0h
R-0h
R-0h
R-0h
R-0h
2
CHRG_TERM_
FLAG
R-0h
1
RESERVED
0
CHRG_FLAG
R-0h
R-0h
Table 14. REG09 Register Field Descriptions
Bit
7
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
PG_FLAG
R
Yes
No
Description
Power-good INT flag
0h = Normal
1h = PG-signal toggle detected
6
INDPM_FLAG
R
Yes
No
INDPM-regulation INT flag
0h = Normal
1h = INDPM-signal rising edge detected
5
VINDPM_FLAG
R
Yes
No
VINDPM-regulation INT flag
0h = Normal
1h = VINDPM-signal rising edge detected
4
TREG_FLAG
R
Yes
No
Device temperature-regulation INT flag
0h = Normal
1h = TREG-signal rising edge detected
3
WD_FLAG
R
Yes
No
I2C-watchdog INT flag
0h = Normal
1h = WD_STAT-signal rising edge detected
2
CHRG_TERM_FLAG
R
Yes
No
Charger-termination INT flag
0h = Normal
1h = Charger-termination signal rising edge detected
1
RESERVED
R
Yes
No
Reserved bit always reads 0
0
CHRG_FLAG
R
Yes
No
Charger status INT flag
0h = Normal
1h = CHRG_STAT[2:0] bits changed (transition to any state)
38
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7.6.1.11 FAULT Flag Register (Address = Ah) [reset = 00h]
REG0A is shown in Figure 41 and described in Table 15.
Return to Summary Table.
All bits in REG0A are automatically cleared after a read.
Figure 41. REG0A Register
7
VBUS_OVP_FL
AG
R-0h
6
TSHUT_FLAG
5
BATOVP_FLA
G
R-0h
R-0h
4
CFLY_FLAG
3
TMR_FLAG
R-0h
R-0h
2
CAP_COND_F
LAG
R-0h
1
POORSRC_FL
AG
R-0h
0
RESERVED
R-0h
Table 15. REG0A Register Field Descriptions
Bit
7
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
VBUS_OVP_FLAG
R
Yes
No
Description
Input-overvoltage INT flag
0h = Normal
1h = VBUS_OVP signal rising edge detected
6
TSHUT_FLAG
R
Yes
No
Thermal-shutdown INT flag
0h = Normal
1h = TSHUT signal rising edge detected
5
BATOVP_FLAG
R
Yes
No
Battery-overvoltage INT flag
0h = Normal
1h = BATOVP signal rising edge detected
4
CFLY_FLAG
R
Yes
No
Flying capacitor fault INT flag
0h = Normal
1h = Flying capacitor fault signal rising edge detected
3
TMR_FLAG
R
Yes
No
Charger safety-timer fault INT flag
0h = Normal
1h = Charger safety-timer expired rising edge
2
CAP_COND_FLAG
R
Yes
No
Capacitor precondition fault INT flag
0h = Normal
1h = CAP_COND_STAT signal rising edge detected
1
POORSRC_FLAG
R
Yes
No
Poor-source-fault INT flag
0h = Normal
1h = POORSRC_STAT signal rising edge detected
0
RESERVED
R
Yes
No
Reserved bit always reads 0
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7.6.1.12 INT Mask Register (Address = Bh) [reset = 00h]
REG0h is shown in Figure 42 and described in Table 16.
Return to Summary Table.
Figure 42. REG0h Register
7
PG_MASK
6
INDPM_MASK
R/W-0h
R/W-0h
5
VINDPM_MAS
K
R/W-0h
4
TREG_MASK
3
WD_MASK
R/W-0h
R/W-0h
2
CHRG_TERM_
MASK
R/W-0h
1
RESERVED
0
CHRG_MASK
R/W-0h
R/W-0h
Table 16. REG0h Register Field Descriptions
Bit
7
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
PG_MASK
R/W
Yes
No
Description
Power-good INT mask
0h = PG toggle produces INT pulse
1h = PG toggle does not produce INT pulse
6
INDPM_MASK
R/W
Yes
No
INDPM-regulation INT mask
0h = INDPM entry produces INT pulse
1h = INDPM entry does not produce INT pulse
5
VINDPM_MASK
R/W
Yes
No
VINDPM-regulation INT mask
0h = VINDPM entry produces INT pulse
1h = VINDPM entry does not produce INT pulse
4
TREG_MASK
R/W
Yes
No
Device temperature-regulation INT mask
0h = TREG entry produces INT pulse
1h = TREG entry does not produce INT pulse
3
WD_MASK
R/W
Yes
No
I2C watchdog-timer INT mask
0h = WD_STAT rising edge produces INT pulse
1h = WD_STAT rising edge does not produce INT pulse
2
CHRG_TERM_MASK
R/W
Yes
No
Charger-termination INT mask
0h = CHRG-termination detection produces INT pulse
1h = CHRG-termination detection does not produce INT pulse
1
RESERVED
R/W
Yes
No
Reserved bit always reads 0
0
CHRG_MASK
R/W
Yes
No
Charger-status INT mask
0h = CHRG_STAT[2:0] bit change produces INT pulse
1h = CHRG_STAT[2:0] bit change does not produce INT pulse
40
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7.6.1.13 FAULT Mask Register (Address = Ch) [reset = 00h]
REG0C is shown in Figure 43 and described in Table 17.
Return to Summary Table.
Figure 43. REG0C Register
7
VBUS_OVP_M
ASK
R/W-0h
6
TSHUT_MASK
R/W-0h
5
BATOVP_MAS
K
R/W-0h
4
CFLY_MASK
3
TMR_MASK
R/W-0h
R/W-0h
2
1
CAP_COND_M POORSRC_MA
ASK
SK
R/W-0h
R/W-0h
0
RESERVED
R/W-0h
Table 17. REG0C Register Field Descriptions
Bit
7
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
VBUS_OVP_MASK
R/W
Yes
No
Description
Input overvoltage INT mask
0h = VBUS_OVP rising edge produces INT pulse
1h = VBUS_OVP rising edge does not produce INT pulse
6
TSHUT_MASK
R/W
Yes
No
Thermal-shutdown INT mask
0h = TSHUT rising edge produces INT pulse
1h = TSHUT rising edge does not produce INT pulse
5
BATOVP_MASK
R/W
Yes
No
Battery-overvoltage INT mask
0h = BATOVP rising edge produces INT pulse
1h = BATOVP rising edge does not produce INT pulse
4
CFLY_MASK
R/W
Yes
No
Flying capacitor fault INT mask
0h = CFLY-fault rising edge produces INT pulse
1h = CFLY-fault rising edge does not produce INT pulse
3
TMR_MASK
R/W
Yes
No
Charger safety-timer fault INT mask
0h = Timer expired rising edge produces INT pulse
1h = Timer expired rising edge does not produce INT pulse
2
CAP_COND_MASK
R/W
Yes
No
Capacitor precondition-fault INT mask
0h = CAP_COND_FLAG rising edge produces INT pulse
1h = CAP_COND_FLAG rising edge does not produce INT
pulse
1
POORSRC_MASK
R/W
Yes
No
Poor-source-fault INT mask
0h = POORSRC_FLAG rising edge produces INT pulse
1h = POORSRC_FLAG rising edge does not produce INT pulse
0
RESERVED
R/W
Yes
No
Reserved bit always reads 0
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7.6.1.14 Part Information Register (Address = Dh) [reset = 09h]
REG0D is shown in Figure 44 and described in Table 18.
Return to Summary Table.
Figure 44. REG0D Register
7
REG_RST
R/W-0h
6
5
4
3
2
PN[3:0]
R-1h
1
DEV_REV[2:0]
R-1h
0
Table 18. REG0D Register Field Descriptions
Bit
7
Field
Type
Reset by
REG_RST
Reset by
WATCHDOG
REG_RST
R/W
No
No
Description
Register preset
0h = Keep the current register settings
1h = Reset to default register values and reset the safety timer
NOTE: This bit resets to 0 after the register reset is complete.
6-3
PN[3:0]
R
No
No
2-0
DEV_REV[2:0]
R
No
No
Part number
1h = bq25910
42
Device revision: 001
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A typical application consists of the device configured as an I2C controlled single cell, parallel battery charger for
Li-Ion and Li-polymer batteries used in a wide range of smartphones and other portable devices. It integrates an
input reverse-block FET (QBLK), four switching FETs for three-level operation (QHSA – QLSA), and a bootstrap
cap control to drive HS gates.
8.2 Typical Application
VBUS
SYSTEM
LOAD
SW
1 PF
20 PF
GND
PMID1
10 PF
I2C Bus
SYS
bq25600 /
bq25898 /
PMIC
BAT
10 PF
VBUS
CFLY +
1 PF
10 PF
10 PF
ICHG1
PMID2
SW2
470nH /
330nH
10 PF
CDRV+
CFLY -
CDRV-
IND_
SNS
220 nF
20 PF
100
VDD
+
BATP
VBAT
100
-
10k
10k
10k
BATN
GND
SDA
Host
REGN
SCL
INT
4.7 PF
CAUX
bq25910
4.7 PF
Figure 45. bq25910 Application Test Configuration
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 19.
Table 19. Design Parameters
PARAMETER
VALUE
Input Voltage Range
3.9 V to 14 V
Input Current Limit
2.4 A
Fast Charge Current
3.5 A
Battery Regulation Voltage
4.35 V
8.2.2 Detailed Design Procedure
8.2.2.1 External Passive Recommendation
The following part numbers are recommended for correct operation of bq25910.
Table 20. Recommended External Components
PASSIVE
Inductor
UP TO 9VBUS ±10%
UP TO 12VBUS ±10%
HMLQ25201B-R33
DFE252012F-R47
MPIM252010E-R33
DFE252010F-R47
CFLY (10 μF, X5R, 16 V)
2x GRM188R61C106MAALD
CAUX (4.7 μF, X5R, 16 V)
1x GRM155R61A475MEAAD
8.2.2.2 Inductor Selection
The bq25910 is a three-level converter with a fixed switching frequency of 750 kHz, allowing the use of small
inductor and capacitor values. The inductor saturation current should be higher than the output current (ICHG)
plus half the ripple current (IRIPPLE):
I
ISAT t ICHG RIPPLE
2
(1)
The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VBUS), switching frequency (fsw)
and inductance (L):
VBUS 0.5 u D 0.5
IRIPPLE
D 0.5
2
Lfsw
(2)
The maximum inductor ripple current happens with D = 1/3 or D = 2/3. The recommended value of inductance is
330 nH for 9-V applications or 470 nH for 12-V applications (750 kHz).
44
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Figure 46. Inductor Current Ripple as function of VBUS with Fixed VBAT
Table 21. Recommended Inductor values
VBUS
INDUCTOR VALUE
3.9 V < VBUS < 10 V
330 nH
3.9 V < VBUS < 14 V
470 nH
8.2.2.3 Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS current occurs when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst
case capacitor RMS current ICIN occurs where the duty cycle is closest to 50% and can be estimated by the
following equation:
ICIN
ICHG D 1 D
(3)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed as close as possible to PMID and GND pins. Voltage rating of the capacitor must be higher than normal
input voltage level. 25-V rating or higher capacitor is preferred for 12-V input voltage. 10-μF capacitance is
suggested for up-to 6-A charging current.
8.2.2.4 Flying Capacitor
Flying capacitor selection must meet criteria related to current ripple and voltage ripple. Just as the input
capacitor, the flying capacitor should also have enough ripple current rating to absorb the RMS current through it:
ICFLY
2 0.5
§
D 0.5 ¨ I2CHG
¨
©
I2RIPPLE ·
¸
12 ¸¹
(4)
This function becomes maximum when D = 0.5, because at that point the capacitor is in series with the inductor
for a complete switching cycle, and their RMS currents are the same. The flying capacitor should be sized to
handle the full charge current in the scenario where D = 0.5.
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Figure 47. Flying Capacitor RMS Current vs. VBUS with Fixed VBAT and ICHG
Additionally, the flying capacitor voltage ripple should be kept under 10% of VBUS/2 to ensure loop stability. This
quantity is given by the following equation:
'VCFLY
ICHG 0.5
D 0.5
CFLY fSW
(5)
It is recommended to use at least two 16-V, 10-μF, low ESR ceramic capacitors in parallel to achieve both RMS
current rating and maintain voltage ripple <10% in the flying capacitor for up-to 6-A charge current application.
The following curve shows what the ripple voltage of CFLY might look like for such a configuration by taking into
account voltage derating of the capacitor and plugging the effective capacitance value into equation above at
different charge currents and VBUS voltages.
Figure 48. Flying Capacitor Ripple Voltage vs. VBUS with Fixed VBAT
Table 22. Recommended CFLY Values
46
CHARGE CURRENT
CFLY CONFIGURATION
ICHG < 3.5 A
1 x 0603 (10 μF, X5R, 16 V)
ICHG > 3.5 A
2 x 0603 (10 μF, X5R, 16 V)
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8.2.2.5 Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given:
I
ICOUT RIPPLE | 0.29 u IRIPPLE
2 3
(6)
The output capacitor voltage ripple can be calculated as follows:
IRIPPLE
'VSYS
16CO fSW
(7)
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC. The preferred ceramic capacitor is 20 μF, 6.3 V or higher rating, X7R or X5R.
8.2.3 Application Curves
CBUS = 1 µF, CPMID = 10 µF, CBAT = 20 µF, CFLY = 20 µF, L = DFE252012F-R47 (470 nH) (unless otherwise noted)
VBUS = 5 V, VBAT = 3.8 V
VBUS = 12 V, VBAT = 3.8 V
Figure 49. Adapter Power Up with Charge Enabled
VBUS = 5 V, VBAT = 3.5 V, ICHG = 3 A
Figure 50. HV Adapter Power Up with Charge Enabled
VBUS = 12 V, VBAT = 3.5 V, ICHG = 4 A
Figure 51. Charge Disable
Figure 52. HV Adapter Charge Disable
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CBUS = 1 µF, CPMID = 10 µF, CBAT = 20 µF, CFLY = 20 µF, L = DFE252012F-R47 (470 nH) (unless otherwise noted)
VBUS = 5 V -> 12 V -> 5 V, VBAT = 4 V, ICHG = 1 A
CH 1 = VBUS, CH2 = SW, CH3 = CFLY differential, CH4 =
VBAT
Figure 53. Line Transient Response in CC Mode
VBUS = 12 V, VBAT = 4.35 V, ICHG = 4 A, IBAT = 1 A -> 4 A ->
1A
CH 1 = VBUS, CH2 = ILOAD, CH3 = CFLY differential, CH4 =
VBAT
Figure 54. Load Transient Response in CV Mode
VBUS = 5 V, VBAT = 3.8 V, ICHG = 2 A, (D > 50%)
VBAT = 4.1 V, VINDPM = 4.3 V
Figure 56. PWM Switching Waveform
Figure 55. VINDPM Response
VBUS = 8 V, VBAT = 3.8 V, ICHG = 2 A, (D approx. 50%)
VBUS = 12 V, VBAT = 3.8 V, ICHG = 2 A (D < 50%)
Figure 57. PWM Switching Waveform
48
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Figure 58. PWM Switching Waveform
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CBUS = 1 µF, CPMID = 10 µF, CBAT = 20 µF, CFLY = 20 µF, L = DFE252012F-R47 (470 nH) (unless otherwise noted)
VBUS = 5 V, VBAT = 3.8 V
VBUS = 12 V, VBAT = 3.8 V
Figure 60. Adapter Removal
Figure 59. Adapter Removal
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9 Power Supply Recommendations
In order to charge single-cell Li-Ion battery, the device requires a power supply between 3.9 V and 14 V with at
least 500-mA current rating connected to VBUS. Additionally, a single-cell Li-Ion battery with voltage > VBAT_LOWV
should be connected between at the output of the switched inductor, between BATP and BATN terminals.
50
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10 Layout
10.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loops is important to prevent electrical and magnetic field
radiation and high-frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB
according to this specific order is essential.
1. Utilize at least four-layer board for optimal layout, and assign one layer as solid ground plane near the IC to
minimize high-frequency current path
2. Place flying capacitor as close to CLFY+ and CLFY– bumps as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging
current. Do not use multiple layers in parallel for this connection.
3. Place input capacitor as close as possible to PMID bumps and PGND bumps and use solid GND plane
underneath the IC. Use plenty of vias close to PMID capacitor GND terminal and IC PGND bumps to ensure
low parasitic connection to GND plane.
4. Place inductor input terminal as close to SW bumps as possible. Minimize the copper area of this trace to
lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current.
5. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the device
ground with a short copper trace connection or GND plane.
6. Decoupling capacitors should be placed next to the device and make trace connection as short as possible.
7. Ensure that there are sufficient thermal vias directly under bumps of the power FETs, connecting to copper
on other layers.
8. The via size and number should be enough for a given current path.
9. Route BATP and BATN away from switching nodes such as SW and CFLY+, CFLY–.
Refer to the EVM design and Figure 61 for the recommended component placement with trace and via
locations.
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10.2 Layout Example
0603
0603
0603
GND
SW
1008
0603
PMID
VBUS
VBUS
C+
PMID
C+
C-
SW
C-
GND
BAT
GND
VBUS
PMID
C+
SW
C-
GND
VBUS
PMID
C+
SW
C-
GND
CDRV+ CDRV+
PMID
C+
SW
C-
GND
CDRV- CDRV-
SDA
INT
SW
C-
GND
CAUX
REGN
BATN
BATP
IND_
SNS
CAUX
REGN
0201
0603
SCL
0603
GND
GND
0402
0402
GND
SCL
SDA
/INT
BATN
BATP
Figure 61. bq25910 PCB Layout Example
52
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
11.1.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
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Product Folder Links: bq25910
53
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ25910YFFR
ACTIVE
DSBGA
YFF
36
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ25910
BQ25910YFFT
ACTIVE
DSBGA
YFF
36
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ25910
PQ25910YFFT
ACTIVE
DSBGA
YFF
36
250
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
YFF0036
DSBGA - 0.625 mm max height
SCALE 4.500
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
BALL TYP
0.30
0.12
0.05 C
2 TYP
SYMM
F
D: Max = 2.472 mm, Min =2.412 mm
E
D
2
TYP
C
B
36X
A
0.4 TYP
E: Max = 2.444 mm, Min =2.384 mm
SYMM
1
2
3
4
5
6
0.3
0.2
0.015
C A
B
0.4 TYP
4222008/A 03/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0036
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
36X ( 0.23)
1
2
3
4
5
6
A
(0.4) TYP
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
( 0.23)
METAL
0.05 MAX
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222008/A 03/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0036
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
36X ( 0.25)
1
2
4
3
5
6
A
(0.4)
TYP
METAL
TYP
B
C
SYMM
D
E
F
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222008/A 03/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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