ICS558-01 PECL/CMOS TO CMOS CLOCK DIVIDER Description Features The ICS558-01 accepts a high speed input of either PECL or CMOS, integrates a divider of 1, 2, 3, or 4, and provides four CMOS low skew outputs. The chip also has output enables so that one, three, or all four outputs can be tri-stated. • • • • • • • • • • The ICS558-01 is a member of the ICS Clock Blocks™ family of clock generation, synchronization, and distribution devices. 16-pin TSSOP package Available in Pb (lead) free package Selectable PECL or CMOS inputs Operates up to 250 MHz Works as a voltage translator Four low skew (<250 ps) outputs Selectable internal divider Operating input voltages of 3.3 V or 5.0 V Operating output voltages of 2.5 V, 3.3 V or 5.0 V Ideal for IA64 designs Block Diagram VDDP OE0 VDDC PECLIN CLK1 PECLIN 1 CMOSIN 0 CLK2 Output Divide CLK3 SELPECL CLK4 2 S0, S1 GND OE1 1 MDS 558-01 C I n t e gra te d C i r c u i t S y s t e m s GND ● 525 Race Stre et, San Jo se, CA 9 5126 Revision 122105 ● te l (40 8) 2 97-12 01 ● w w w. i c st . c o m ICS558-01 PECL/CMOS TO CMOS CLOCK DIVIDER Pin Assignment Input Clock Selection SELPECL Input S0 1 16 SELPECL 0 CMOSIN S1 2 15 VDDC 1 PECLIN VDDP 3 14 CLK1 PECLIN 4 13 CLK2 PECLIN 5 12 CLK3 OE1 OE0 CLK 1 CLK 2, 3, 4 GND 6 11 CLK4 0 0 Tri-state Tri-state CMOSIN 7 10 GND 0 1 Clock ON Tri-state OE0 8 9 OE1 1 0 Tri-state Clock ON 1 1 Clock ON Clock ON Tri-State Table 16-pin 173 Mil (0.65mm) TSSOP Output Divide Selection S1 S0 Output Divide 0 0 /1 0 1 /2 1 0 /3 1 1 /4 Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name S0 S1 VDDP PECLIN PECLIN GND CMOSIN OE0 OE1 GND CLK4 CLK3 CLK2 CLK1 VDDC SELPECL Pin Type Pin Description Input Input Power Clock Input Clock Input Power Clock Input Input Input Power Output Output Output Output Power Input Select 0 for output divider. See table above. Internal pull-up to VDDP. Select 1 for output divider. See table above. Internal pull-up to VDDP. Connect to +3.3 V or +5 V. Decouple to pin 6. PECL input. Connect to ground if not used. Complimentary PECL input. Connect to ground if not used. Connect to ground. CMOS input. Connect to ground if not used. Output Enable 0. See table above. Internal pull-up to VDDP. Output Enable 1. See table above. Internal pull-up to VDDP. Connect to ground. Low skew clock output. Low skew clock output. Low skew clock output. Low skew clock output. Connect to +2.5 V, +3.3 V, or +5 V. Decouple to pin 10. Selects PECL or CMOS input. See table above. Internal pull-up to VDDP. 2 MDS 558-01 C In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 122105 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS558-01 PECL/CMOS TO CMOS CLOCK DIVIDER External Components The ICS558-01 requires two 0.01 µF capacitors between VDDP and GND, and VDDC and GND—one on each side of the chip. These must be close to the chip to minimize lead inductance. Series termination resistors of 33Ω can be used on the outputs (these also must be close to the chip). Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS558-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage; VDDP, VDDC (referenced to ground) 7.0 V Inputs and Clock Outputs (referenced to ground) -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70 °C Storage Temperature -65 to +150 °C Soldering Temperature (maximum of 10 seconds) 260 °C DC Electrical Characteristics VDDP = VDDC = 3.3V (unless stated otherwise), Ambient temperature 0 to +70 °C Parameter Symbol Operating Voltage, VDDP Conditions Min. ≥ VDDC VDDP ≥ VDDC VDDP Operating Voltage, VDDC Input High Voltage, CMOSIN VIH Input Low Voltage, CMOSIN VIL Input High Voltage VIH non-clock pins Input Low Voltage VIL non-clock pins Typ. Max. Units 3.0 5.5 V 2.375 VDDP V (VDDP/2)+1 V (VDDP/2)-1 V VDDP V 0.5 V VDDP-0.5 Common Mode Range, PECLIN VDDP=5 V VDDP-3.7 VDDP-0.6 V Common Mode Range, PECLIN VDDP=3.3 V VDDP-2.0 VDDP-0.6 V 0.3 1.0 V Peak-to-Peak Input Voltage, PECLIN Output High Voltage VOH VDDC = 5 V, IOH = -24 mA Output Low Voltage VOL VDDC = 5 V, IOL = 24 mA Output High Voltage VOH VDDC = 3.3 V, IOH = -18 mA V 0.4 VDDC-0.4 ● 525 Ra ce Street, San Jose, CA 9512 6 V V 3 MDS 558-01 C In te grated Circuit Systems VDDC-0.4 Revision 122105 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS558-01 PECL/CMOS TO CMOS CLOCK DIVIDER Parameter Symbol Conditions Output Low Voltage VOL VDDC = 3.3 V, IOL = 18 mA Output High Voltage VOH VDDC = 2.5 V, IOH = -8 mA Output Low Voltage VOL VDDC = 2.5 V IOL = 8 mA Min. Typ. Max. Units 0.4 V VDDC-0.4 V 0.4 V Operating Supply Current IDDP No load, 100 MHz input 22 mA Operating Supply Current IDDC No load, 100 MHz input 18 mA +70 mA Short Circuit Current On-chip pull-up resistor RPU 250 kΩ Input Capacitance CIN 4 pF AC Electrical Characteristics VDDP = VDDC = 3.3 V (unless stated otherwise), Ambient Temperature 0 to +70 °C Parameter Symbol Conditions Min. Input Frequency Typ. 0 Max. Units 250 MHz Output Rise Time tOR 800 ns Output Fall Time tOF 750 ns 250 ps 0 Skew, between any output clocks (Assumes identically loaded outputs with identical rise times, measured at VDDC/2) Propagation Delay /1 5.0 ns /2 6.0 ns /3 ns /4 7.0 ns Output Clock Duty Cycle for /2 and /4 45 50 55 % Output Clock Duty Cycle for /1 and /3 45 50 55 % Min. Typ. Thermal Characteristics (16-pin TSSOP) Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Max. Units θJA Still air 78 °C/W θJA 1 m/s air flow 70 °C/W θJA 3 m/s air flow 68 °C/W 37 °C/W θJC 4 MDS 558-01 C In te grated Circuit Systems Symbol ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 122105 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS558-01 PECL/CMOS TO CMOS CLOCK DIVIDER Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters 16 Symbol E1 Min A A1 A2 b C D E E1 e L α aaa E INDEX AREA 1 2 D Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A2 A1 c -Ce SEATING PLANE b L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS558G-01 ICS558G-01T ICS558G-01LF ICS558G-01LFT ICS558G-01 ICS558G-01 558G-01LF 558G-01LF Tubes Tape and Reel Tubes Tape and Reel 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 5 MDS 558-01 C In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 122105 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m