CS51021/22/23/24 CS51021/CS51023 CS51022/CS51024 Enhanced Current Mode PWM Controller Features Description The CS51021/22/23/24 Fixed Frequency PWM Current Mode Controller family provides all necessary features required for AC-DC or DC-DC primary side control. Several features are included eliminating the additional components needed to implement them externally. In addition to low start-up current (75µA) and high frequency operation capability, the CS51021/ 22/23/24 family includes overvoltage and undervoltage monitoring, externally programmable dual Device threshold overcurrent protection, current sense leading edge blanking, current slope compensation, accurate duty cycle control and an externally available 5V reference. The CS51021 and CS51023 feature bidirectional synchronization capability, while the CS51022 and CS51024 offer a sleep mode with 100µA maximum IC current consumption. The CS51021/22/23/24 family is available in a 16 lead narrow body SO package. Sleep/Synch VCC Start/Stop CS51021 Synch 8.25V/7.7V CS51022 Sleep 8.25V/7.7V CS51023 Synch 13V/7.7V CS51024 Sleep 13V/7.7V Typical Application Diagram 100 VIN (36V to 72V) PGND 1µF BAS21 51k SYNC/SLEEP 18V 22µF 11V 100:1 0.1µF FZT688 200K,1% 24.3K 1% 10 10K 4700pF 22K 51K VC VREF COMP VFB RTCT SYNC/ SLEEP CSS 330pF LGnd U1 PGnd VOUT (5V/5A) 100µF 100µF 680pF OV BA521 SGND 100pF ISET 0.01µF 2:5 2.49K,1% UV SLOPE GATE ISENSE MBRB2060CT 10 VCC CS51021/51022 0.01µF 4:1 10K 6.98k, 6.98k, 100 1% 1% 100p Package Options 16 Lead SO Narrow IRF6345 10 ■ 75µA Max. Startup Current ■ Fixed Frequency Current Mode Control ■ 1MHz Switching Frequency ■ Undervoltage Protection Monitor ■ Overvoltage Protection Monitor with Programmable Hysteresis ■ Programmable Dual Threshold Overcurrent Protection with Delayed Restart ■ Programmable Soft Start ■ Accurate Maximum Duty Cycle Limit ■ Programmable Slope Compensation ■ Leading Edge Current Sense Blanking ■ 1A Sink/Source Gate Drive ■ Bidirectional Synchronization (CS51021/23) ■ 50ns PWM Propagation Delay ■ 100µA Max Sleep Current (CS51022/24) 62 GATE ISENSE 10 470pF TL431 VCC VREF 2K, 1% 1000pF 1K PGnd SLEEP or SYNC SLOPE 0.1µF 5.1K 180 VC 1 2K,1% 10K UV LGnd OV SS RTCT ISET MOC81025 1K COMP VFB Consult factory for other package options. 36-72V to 5V, 5A DC-DC Convertor Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 2/22/99 1 A ® Company CS51021/22/23/24 Absolute Maximum Ratings Power Supply Voltage, VCC ............................................................................................................................................-0.3V, 20V Driver Supply Voltage, VC ..............................................................................................................................................-0.3V, 20V SYNC, SLEEP, RTCT, SOFT START, VFB, SLOPE, ISENSE, UV, OV, ISET (Logic Pins).......................................-0.25V to VREF Peak GATE Output Current.........................................................................................................................................................1A Steady State Output Current..................................................................................................................................................± 0.2A Operating Junction Temperature, TJ ..................................................................................................................................... 150°C Storage Temperature Range, TS ...................................................................................................................................-65 to 150°C ESD (Human Body Model).........................................................................................................................................................2kV Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183°C, 230°C peak Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < TA < 85°C, -40°C < TJ < 150°C, 3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8.8 13.4 8.2 1.00 6 75 V V V V V µA ■ Under Voltage Lockout START Threshold (CS51021/22) START Threshold (CS51023/24) STOP Threshold Hysteresis (CS51021/22) Hysteresis (CS51023/24) ICC @ Startup (CS51021/22) VCC < UVSTART Threshold 8.25 13 7.7 0.75 5 40 ICC @ Startup (CS51023/24) VCC < UVSTART Threshold 45 75 µA ICC Operating (CS51021/23) 7 9 mA ICC Operating (CS51022/24) 6 8 mA Includes 1nF Load 7 12 mA Initial Accuracy TA = 25C, IREF = 2mA, VCC = 14V (Note1) 4.95 5 5.05 V Total Accuracy 1mA<IREF<10mA 5 5.15 V Line Regulation 8.2V < VCC < 18V, IREF = 2mA 6 20 mV Load Regulation 1mA < IREF < 10mA 6 15 mV NOISE Voltage OP Life Shift FAULT Voltage (Note 1) T=1000 Hours (Note 1) Force VREF .92 × VREF OK Voltage Force VREF .94 × VREF .96 × VREF .98 × VREF OK Hysteresis Force VREF 50 Current Limit Force VREF -20 IC Operating 7.95 12.4 7.4 0.50 4 ■ Voltage Reference 4.9 50 4 20 .95 × VREF .97 × VREF 105 160 uV mV V V mV mA ■ Error Amplifier Initial Accuracy TA=25°C, IREF = 2mA, VCC = 14V, VFB = COMP (Note 1) 2.465 2.515 2.565 V Reference Voltage VFB = COMP 2.440 2.515 2.590 V VFB Leakage Current VFB = 0V -0.2 -2 µA Open Loop Gain Unity Gain Bandwidth COMP Sink Current 1.4V < COMP < 4V (Note 1) (Note 1) COMP = 1.5V, VFB = 2.7V 60 1.5 2 90 2.5 6 dB MHz mA COMP Source Current COMP = 1.5V, VFB = 2.3V -0.2 -0.5 mA 2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ■ Error Amplifier continued COMP High Voltage VFB = 2.3V 4.35 4.8 5 V COMP Low Voltage VFB = 2.7V 0.4 0.8 1.2 V PS Ripple Rejection SS Clamp, VCOMP FREQ = 120Hz (Note 1) VSS=2.5V, VFB = 0V, ISET = 2V 60 2.4 85 2.5 2.6 dB V ILIM(SET) Clamp (Note 1) 0.95 1 1.15 V Accuracy RT = 12k, CT = 390pF 230 255 280 kHz Voltage Stability Delta Frequency 8.2V < VCC < 20V 2 3 % Temperature Stability TMIN < TA < TMAX (Note1) 8 Min Charge & Discharge Time Duty Cycle Accuracy (Note1) RT = 12k, CT = 390pF Peak Voltage Valley Voltage Valley Clamp Voltage (Note 1) (Note 1) 10k Resistor to ground on RTCT Discharge Current Discharge Current TA=25°C (Note 1) ■ Oscillator 0.333 70 77 % 83 µs % 1.2 3 1.5 1.4 1.6 V V V 0.8 0.925 1 1 1.2 1.075 mA mA 1.5 260 4.3 2.7 360 4.8 V ns V ■ Synchronization (CS51021/23) Input Threshold Output Pulsewidth Output High Voltage ISYNC = 100µA 1.0 160 3.5 Input Resistance Drive Delay Output Drive Current (Note 1) SYNC to GATE RESET 1k Load 35 80 1.25 70 120 2 140 150 3.5 kΩ ns mA SLEEP Input Threshold SLEEP Input Current Active High VSLEEP = 4V 1.0 11 1.5 25 2.7 46 V µA ICC @ SLEEP VCC ≤ 15V 50 100 µA HIGH Voltage Measure VC-GATE, VC = 10V, 150mA Load 1.5 2.2 V LOW Voltage HIGH Voltage Clamp Measure GATE-PGnd, 150mA SINK VC = 20V, 1nF 1.2 13.5 1.5 16 V V LOW Voltage Clamp Peak Current Measured at 10mA Output Current VC = 20V, 1nF (Note 1) 0.6 1 0.8 V A UVL Leakage VC = 20V, measured at 0V -1 -50 µA RISE Time Load = 1nF, 1V < GATE < 9V, VC = 20V, TA = 25˚C 60 100 ns FALL Time Load = 1nF, 9V > GATE > 1V, VC = 20V 15 40 ns ■ SLEEP (CS51022/24) ■ GATE Driver 3 11 CS51021/22/23/24 Electrical Characteristics: -40°C < TA < 85°C, -40°C < TJ < 150°C, 3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF, unless otherwise stated CS51021/22/23/24 Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < TA < 85°C, -40°C < TJ < 150°C, 3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ■ SLOPE Compensation Charge Current SLOPE = 2V COMP Gain Fraction of slope voltage added to ISENSE (Note 1) Discharge Voltage SYNC = 0V -63 -53 -43 µA 0.095 0.100 0.105 V/V 0.1 0.2 V 0.10 0.11 V 55 160 ns 1.8 2 2.2 V 1.21 1.33 1.45 V/V ■ Current Sense OFFSET Voltage (Note 1) 0.09 Blanking Time Blanking Disable Voltage Adjust VFB Second Current Threshold Gain ISENSE Input Resistance 5 Minimum On Time GATE High to Low Gain (Note 1) kΩ 30 70 110 ns 0.78 0.80 0.82 V/V 2.4 2.5 2.6 V OV Hysteresis Current -10 -12.5 -15 µA UV Monitor Threshold 1.38 1.45 1.52 V UV Monitor Hysteresis 25 75 100 mV -40 µA ■ OV & UV Voltage Monitors OV Monitor Threshold ■ SOFT START (SS) Charge Current SS = 2V -70 -55 Discharge Current SS = 2V 250 1000 µA Charge Voltage, VSS 4.4 4.7 5 V Discharge Voltage, VSS 0.25 0.27 0.30 V Note 1: Guaranteed by Design, not 100% tested in production. Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION 16L PDIP & SO Narrow 1 GATE External power switch driver with 1.0A peak capability. 2 ISENSE Current sense amplifier input. 3 SYNC (CS51021/23) Bi-directional synchronization. Locks to the highest frequency. 3 SLEEP (CS51022/24) Active high chip disable. In sleep mode, VREF and GATE are turned off. 4 SLOPE Additional slope to the current sense signal. Internal current source charges the external capacitor. 5 UV Undervoltage protection monitor. 6 OV Overvoltage protection monitor. 4 PACKAGE PIN # PIN SYMBOL FUNCTION 16L PDIP & SO Narrow 7 RTCT Timing resistor RT and capacitor CT determine oscillator frequency and maximum duty cycle, DMAX. 8 ISET Voltage at this pin sets pulse-by-pulse overcurrent threshold, and second threshold (1.33 times higher) with Soft Start retrigger (hiccup mode). 9 VFB Feedback voltage input. Connected to the error amplifier inverting input. 10 COMP Error amplifier output. Frequency compensation network is usually connected between COMP and VFB pins. 11 SS Charging external capacitor restricts error amplifier output voltage during the start or fault conditions (hiccup). 12 LGnd Logic ground. 13 VREF 5.0V reference voltage output. 14 VCC Logic supply voltage. 15 PGnd Output power stage ground connection. 16 VC Output power stage supply voltage. Block Diagram VCC - LGnd VREF Vcc_OK START STOP + VREF = 5V VREF_OK VC + SLEEP 4.75V 200ns 4.3V SYNC OSC RTCT Q S G2 D4 F1 SS Clamp G1 D2 ZD1 13.5V R ISET Clamp COMP PGnd D3 + 2.5V 20k E/A - D1 VFB VREF 53µA 55µA + × 0.1 × ISENSE Q2 – ∑ 0.1V + SS SS Monitor G4 2V DISABLE SLOPE VREF PWM Comp 10k VFB Monitor – + 4.7V 55ns Blank – VISense 0.8 2nd Threshold 1.33 ISET GATE × VREF G3 FAULT Discharge Latch 12.5µA OV UV UV Monitor OV Monitor + + 1.45V 2.5V – – Figure 1: CS51021/22/23/24 Block Diagram 5 CS51021/22/23/24 Package Pin Description: continued CS51021/22/23/24 Circuit Description Blanking is disabled when VFB is less than 2V so that the minimum on-time of the controller does not have an additional 55ns of delay time during fault conditions. For the remaining portion of the switching period, the current sense signal, combined with a fraction of the slope compensation voltage, is applied to the positive input of the PWM comparator where it is compared with the divided by three error amplifier output voltage. The pulse-bypulse overcurrent protection threshold is set by the voltage at the ISET pin. This voltage is passed through the ISET Clamp and appears at the non-inverting input of the PWM comparator, limiting its dynamic range according to the following formula: Overcurrent Threshold= 0.8 × VI(SENSE) +0.1V + 0.1 VSLOPE 200ns 4.3V SYNC RTCT TCH TDIS 0V VSLOPE SLOPE 0V IS 0V IS + 0.1 SLOPE IS 55ns Blanking 0V where VCOMP VI(SENSE) is voltage at the ISENSE pin PWM COMP and VSLOPE is voltage at the SLOPE pin. During extreme overcurrent or short circuit conditions, the slope of the current sense signal will become much steeper than during normal operation. Due to loop propagation delay, the sensed signal will overshoot the pulseby-pulse threshold eventually reaching the second overcurrent protection threshold which is 1.33 times higher than the first threshold and is described by the following equation: GATE 0V VDS VIN 0V 2nd Threshold = 1.33 × VI(SET) Figure 2: Typical Waveforms Exceeding the second threshold will reset the Soft Start capacitor CSS and reinitiate the Soft Start sequence, repeating for as long as the fault condition persists. Theory of Operation Powering the IC The IC has two supply and two ground pins. VC and PGnd pins provide high speed power drive for the external power switch. VCC and LGnd pins power the control portion of the IC. The internal logic monitors the supply voltage, VCC. During abnormal operating conditions, the output is held low. The CS51021/22/23/24 requires only 75µA of startup current. Soft Start During power up, when the output filter capacitor is discharged and the output voltage is low, the voltage across the Soft Start capacitor (VSS) controls the duty cycle. An internal current source of 55µA charges CSS. The maximum error amplifier output voltage is clamped by the SS Clamp. When the Soft Start capacitor voltage exceeds the error amplifier output voltage, the feedback loop takes over the duty cycle control. The Soft Start time can be estimated with the following formula: Voltage Feedback The output voltage is monitored via the VFB pin and is compared with the internal 2.5V reference. The error amplifier output minus one diode drop is divided by 3 and connected to the negative input of the PWM comparator. The positive input of the PWM comparator is connected to the modified current sense signal. The oscillator turns the external power switch on at the beginning of each cycle. When current sense ramp voltage exceeds the reference side of PWM comparator, the output stage latches off. It is turned on again at the beginning of the next oscillator cycle. tSS = 9 × 104 × CSS The Soft Start voltage, VSS, charges and discharges between 0.25V and 4.7V. Slope Compensation DC-DC converters with current mode control require a current sense signal with slope compensation to avoid instability at duty cycles greater than 50%. Slope capacitor CS is charged by an internal 53µA current source and is discharged during the oscillator discharge time. The slope compensation voltage is divided by 10 and is added to the current sense voltage, VI(SENSE). The signal applied to the Current Sense and Protection The current is monitored at the ISENSE pin. The CS51021/22/23/24 has leading edge blanking circuitry that ignores the first 55ns of each switching period. 6 input of the PWM comparator is a combination of these dVSLOPE two voltages. The slope compensation, , is calcudt lated using the following formula: VIN R2 VUV dVSLOPE 53µA = 0.1 × C dt S R3 VOV Figure 4: UV/OV Monitor Divider To calculate the OV/UV resistor divider: 1. Solve for R3, based on OV hysteresis requirements. It should be noted that internal capacitance of the IC will cause an error when determining slope compensation capacitance CS. This error is typically small for large values of CS, but increases as CS becomes small and comparable to the internal capacitance. The effect is apparent as a reduction in charging current due to the need to charge the internal capacitance in parallel with CS. Figure 3 shows a typical curve indicating this decrease in available charging current. VOV(HYST) × 2.5V ’ R3 = V MAX × 12.5µA where VOV(HYST) is the desired amount of overvoltage hysteresis, and VMAX is the input voltage at which the supply will shut down. 2. Find the total impedance of the divider. VMAX × R3 RTOT = R1 + R2 + R3 = 2.5 60 Charging Current (µA) R1 55 50 3. Determine the value of R2 from the UV threshold conditions. 1.45 × RTOT R2 = − R3, VMIN 45 40 35 where VMIN is the UV voltage at which the supply will shut down. 30 25 20 10 100 4. Calculate R1. 1000 R1 = RTOT − R2 − R3 Compensation Cap (pF) 5. The undervoltage hysteresis is given by: Figure 3: The slope compensation pin charge current reduces when a small capacitor is used. VUV(HYST) = Undervoltage (UV) and Overvoltage (OV) Monitor Two independent comparators monitor OV and UV conditions. A string of three resistors is connected in series between the monitored voltage (usually the input voltage) and ground (see Figure 4). When voltage at the OV pin exceeds 2.5V, an overvoltage condition is detected and GATE shuts down. An internal 12.5µA current source turns on and feeds current into the external resistor, R3, creating a hysteresis determined by the value of this resistor (the higher the value, the greater the hysteresis). The hysteresis voltage of the OV monitor is determined by the following formula: VMIN × 0.075 1.45 Synchronization A bi-directional synchronization is provided to synchronize several controllers. When SYNC pins are connected together, the converters will lock to the highest switching frequency. The fastest controller becomes the master, producing a 4.3V, 200ns pulse train. Only one, the highest frequency SYNC signal, will appear on the SYNC line. Sleep The sleep input is an active high input. The CS51022/51024 is placed in sleep mode when SLEEP is driven high. In sleep mode, the controller and MOSFET are turned off. Connect to Gnd for normal operation. The sleep mode operates at VCC ≤ 15V. VOV(HYST) = 12.5µA × R3 where R3 is a resistor connected from the OV pin to ground. When the monitored voltage is low and the UV pin is less than 1.45V, GATE shuts down. The UV pin has fixed 75mV hysteresis. Both OV and UV conditions are latched until the Soft Start capacitor is discharged. This way, every time a fault condition is detected the controller goes through the power up sequence. Oscillator and Duty Cycle Limit The switching frequency is set by RT and CT connected to the RTCT pin. CT charges and discharges between 3V and 1.5V. The maximum duty cycle is set by the ratio of the on time, tON, and the whole period, T = tON + tOFF. Because the 7 CS51021/22/23/24 Circuit Description: continued timing capacitor’s discharge current is trimmed, the maximum duty cycle is well defined. It is determined by the ratio between the timing resistor RT and the timing capacitor CT. Refer to figures 5 and 6 to select appropriate values for RT and CT. 1 fSW = T ; TSW = tCH + tDIS SW 100 8 7 6 5 90 4 Duty Cycle (%) 80 2500 3 2 70 1. CT = 47pF 2. CT = 100pF 3. CT = 150pF 4. CT = 220pF 5. CT = 390pF 6. CT = 470pF 7. CT = 560pF 8. CT = 680pF 1 60 1 2000 Frequency (kHz) CS51021/22/23/24 Circuit Description: continued 50 1. CT = 47pF 2. CT = 100pF 3. CT = 150pF 4. CT = 220pF 5. CT = 390pF 6. CT = 470pF 7. CT = 560pF 8. CT = 680pF 1500 2 40 5 4 500 5 6 5 7 10 15 20 25 30 35 40 20 25 30 35 40 45 50 Figure 6: Duty Cycle vs. RT for Discrete Capacitor Values. 3 0 15 RT (kΩ) 1000 8 10 45 50 RT (kΩ) Figure 5: Frequency vs. RT for Discrete Capacitor Values. 8 55 PACKAGE THERMAL DATA PACKAGE DIMENSIONS IN mm (INCHES) D Lead Count 16L SO Narrow Metric Max Min 10.00 9.80 Thermal Data English Max Min .394 .386 16L SO Narrow RΘJC typ 28 ˚C/W RΘJA typ 115 ˚C/W Surface Mount Narrow Body (D); 150 mil wide 4.00 (.157) 3.80 (.150) 6.20 (.244) 5.80 (.228) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 1.75 (.069) MAX 1.57 (.062) 1.37 (.054) 1.27 (.050) 0.40 (.016) 0.25 (.010) 0.19 (.008) D 0.25 (0.10) 0.10 (.004) REF: JEDEC MS-012 Ordering Information Part Number CS51021ED16 CS51021EDR16 CS51022ED16 CS51022EDR16 CS51023ED16 CS51023EDR16 CS51024ED16 CS51024EDR16 Rev. 2/22/99 Description 16L SO Narrow 16L SO Narrow (tape & reel) 16L SO Narrow 16L SO Narrow (tape & reel) 16L SO Narrow 16L SO Narrow (tape & reel) 16L SO Narrow 16L SO Narrow (tape & reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 9 © 1999 Cherry Semiconductor Corporation CS51021/22/23/24 Package Specification