Data Sheet, Rev. 1.0, Mar. 2004 HYS64D32020[H/G]DL–5–C HYS64D[32020/16000][H/G]DL–6–C 2 0 0 - P i n S m a l l O u t l i n e D u a l- I n - L i n e M e m o r y M o d u l e s SO-DIMM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g . Edition 2004-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, Rev. 1.0, Mar. 2004 HYS64D32020[H/G]DL–5–C HYS64D[32020/16000][H/G]DL–6–C 2 0 0 - P i n S m a l l O u t l i n e D u a l- I n - L i n e M e m o r y M o d u l e s SO-DIMM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g . HYS64D32020[H/G]DL–5–C,HYS64D[32020/16000][H/G]DL–6–C Revision History: Rev. 1.0 2004-03 Previous Version: Rev. 0.5 2003-11 Page Subjects (major changes since last revision) 6,7 Added DDR400 18 Updated Idd Currents and added DDR400 Idd Currents 24 Updated SPD Code Bytes 99 - 127 to FF and added SPD Codes for DDR400 13,14 editorial changes We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Template: mp_a4_v2.0_2003-06-06.fm HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Table of Contents 1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 4.1 4.2 4.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Data Sheet 5 15 15 17 19 Rev. 1.0, 2004-03 200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM 1 Overview 1.1 Features • • • • • • • • • • • • HYS64D32020[H/G]DL–5–C HYS64D[32020/16000][H/G]DL–6–C Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules One rank 16M ×64 and two ranks 32M ×64 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5 V (± 0.2 V) power supply Built with 256 Mbit DDR SDRAMs organised as ×16 in P–TSOPII–66–1 packages Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM Jedec standard form factor: 67.60 mm × 31.75 mm × 2.4 / 3.80 mm Jedec standard reference layout Raw Cards A and C Gold plated contacts Table 1 Performance Part Number Speed Code Speed Grade max. Clock Frequency –5 –6 Unit Component DDR400B DDR333B — Module PC3200–3033 PC2700–2533 — 200 166 MHz 166 166 MHz 133 133 MHz @CL3 @CL2.5 @CL2 2 fCK3 fCK2.5 fCK2 Description The HYS64D32020[H/G]DL–5–C and HYS64D[32020/16000][H/G]DL–6–C are industry standard 200-Pin Small Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 32M × 64 and 16M × 64. The memory array is designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. Data Sheet 6 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Description Table 2 Ordering Information Type Compliance Code Description SDRAM Technology PC3200S–3033–1–A1 two ranks 256 MB SO-DIMM 256 MBit (×16) HYS64D16000GDL–6–C PC2700S–2533–0–C1 one rank 128 MB SO-DIMM 256 MBit (×16) HYS64D32020GDL–6–C PC2700S–2533–0–A1 two ranks 256 MB SO-DIMM 256 MBit (×16) PC3200S–3033–1–A1 two ranks 256 MB SO-DIMM 256 MBit (×16) HYS64D16000HDL–6–C PC2700S–2533–0–C1 one rank 128 MB SO-DIMM 256 MBit (×16) HYS64D32020HDL–6–C PC2700S–2533–0–A1 two ranks 256 MB SO-DIMM 256 MBit (×16) PC3200 (CL=3.0) HYS64D32020GDL–5–C PC2700 (CL=2.5) PC3200 (CL=3.0) HYS64D32020HDL–5–C PC2700 (CL=2.5) Notes 1. All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components. 2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module. 1) RCD: Row-Column-Delay Data Sheet 7 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Pin Configuration 3 Pin Configuration Table 3 The pin configuration of the Unbuffered Small Outline DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 respectively. The pin numbering is depicted in Figure 1. Table 3 Pin# Pin Configuration of SO-DIMM Name Pin Buffer Function Type Type Clock Signals 35 CK0 I SSTL Clock Signal 160 CK1 I SSTL Clock Signal 89 CK2 I SSTL Clock Signal Note: ECC type module NC NC – Pin# Name Pin Buffer Function Type Type 112 A0 I SSTL 111 A1 I SSTL 110 A2 I SSTL 109 A3 I SSTL 108 A4 I SSTL 107 A5 I SSTL 106 A6 I SSTL 105 A7 I SSTL 102 A8 I SSTL 101 A9 I SSTL 115 A10 I SSTL AP I SSTL Note: non-ECC type module 100 A11 I SSTL 99 A12 I SSTL 37 CK0 I SSTL Complement Clock 158 CK1 I SSTL Complement Clock 91 CK2 I SSTL Complement Clock NC NC – Note: non-ECC type module 96 CKE0 I SSTL Clock Enable Rank 0 95 CKE1 I SSTL Clock Enable Rank 1 123 – NC NC – Note: 128 Mbit based module A13 I SSTL Address Signal 13 NC NC – Note: Module based on 512 Mbit or smaller dies Data Bus 63:0 Note: 1-rank module Data Signals Control Signals 121 S0 I SSTL Chip Select Rank 0 5 DQ0 I/O SSTL 122 S1 I SSTL Chip Select Rank 1 7 DQ1 I/O SSTL Note: 2-ranks module 13 DQ2 I/O SSTL NC NC – Note: 1-rank module 17 DQ3 I/O SSTL 118 RAS I SSTL Row Address Strobe 6 DQ4 I/O SSTL 8 DQ5 I/O SSTL 120 CAS I SSTL Column Address Strobe 14 DQ6 I/O SSTL 119 WE I SSTL Write Enable 18 DQ7 I/O SSTL 19 DQ8 I/O SSTL Bank Address Bus 1:0 23 DQ9 I/O SSTL 29 DQ10 I/O SSTL 31 DQ11 I/O SSTL 20 DQ12 I/O SSTL 24 DQ13 I/O SSTL Address Signals 117 BA0 I SSTL 116 BA1 I SSTL Data Sheet Address Signal 12 Note: 1 Gbit based module Note: 2-rank module NC Address Bus 11:0 Note: Module based on 256 Mbit or larger dies Note: ECC type module NC Pin Configuration of SO-DIMM (cont’d) 8 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Pin Configuration Table 3 Table 3 Pin Configuration of SO-DIMM (cont’d) Pin Configuration of SO-DIMM (cont’d) Pin# Name Pin Buffer Function Type Type Pin# Name Pin Buffer Function Type Type 30 DQ14 I/O SSTL 172 DQ54 I/O SSTL 32 DQ15 I/O SSTL 176 DQ55 I/O SSTL 41 DQ16 I/O SSTL 177 DQ56 I/O SSTL 43 DQ17 I/O SSTL 181 DQ57 I/O SSTL 49 DQ18 I/O SSTL 187 DQ58 I/O SSTL 53 DQ19 I/O SSTL 189 DQ59 I/O SSTL 42 DQ20 I/O SSTL 178 DQ60 I/O SSTL 44 DQ21 I/O SSTL 182 DQ61 I/O SSTL 50 DQ22 I/O SSTL 188 DQ62 I/O SSTL 54 DQ23 I/O SSTL 190 DQ63 I/O SSTL 55 DQ24 I/O SSTL 71 CB0 I/O SSTL 59 DQ25 I/O SSTL 65 DQ26 I/O SSTL 67 DQ27 I/O SSTL 56 DQ28 I/O SSTL 60 DQ29 I/O SSTL 66 DQ30 I/O SSTL 68 DQ31 I/O SSTL 127 DQ32 I/O SSTL 129 DQ33 I/O SSTL 135 DQ34 I/O SSTL 139 DQ35 I/O SSTL 128 DQ36 I/O SSTL 130 DQ37 I/O SSTL 136 DQ38 I/O SSTL 140 DQ39 I/O SSTL 141 DQ40 I/O SSTL 145 DQ41 I/O SSTL 151 DQ42 I/O SSTL 153 DQ43 I/O SSTL 142 DQ44 I/O SSTL 146 DQ45 I/O SSTL 152 DQ46 I/O SSTL 154 DQ47 I/O SSTL 163 DQ48 I/O SSTL 165 DQ49 I/O SSTL 171 DQ50 I/O SSTL 175 DQ51 I/O SSTL 164 DQ52 I/O SSTL 166 DQ53 I/O SSTL Data Sheet Data Bus 63:0 Data Bus 63:0 Check Bit 0 Note: ECC type module 73 NC NC – Note: Non-ECC module CB1 I/O SSTL Check Bit 1 Note: ECC type module 79 NC NC – Note: Non-ECC module CB2 I/O SSTL Check Bit 2 Note: ECC type module 83 NC NC – Note: Non-ECC module CB3 I/O SSTL Check Bit 3 Note: ECC type module 72 NC NC – Note: Non-ECC module CB4 I/O SSTL Check Bit 4 Note: ECC type module 74 NC NC – Note: Non-ECC module CB5 I/O SSTL Check Bit 5 Note: ECC type module NC 9 NC – Note: Non-ECC module Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Pin Configuration Table 3 Pin Configuration of SO-DIMM (cont’d) Table 3 Pin Configuration of SO-DIMM (cont’d) Pin# Name Pin Buffer Function Type Type Pin# 80 CB6 I/O Check Bit 6 Power Supplies Note: ECC type module 1,2 VREF 84 SSTL Name Pin Buffer Function Type Type AI – I/O Reference Voltage NC NC – Note: Non-ECC module 197 VDDSPD PWR – EEPROM Power Supply CB7 I/O SSTL Check Bit 7 9,10, 21, 22, 33, 34, 36, 45, 46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192 VDD Power Supply Note: ECC type module NC NC – Note: Non-ECC module 11 DQS0 I/O SSTL Data Strobes 7:0 25 DQS1 I/O SSTL 47 DQS2 I/O SSTL 61 DQS3 I/O SSTL Note: See block diagram for corresponding DQ signals 133 DQS4 I/O SSTL 147 DQS5 I/O SSTL 169 DQS6 I/O SSTL 183 DQS7 I/O SSTL 77 DQS8 I/O SSTL Data Strobe 8 Note: ECC type module NC NC – Note: Non-ECC module 12 DM0 I SSTL Data Mask 7:0 26 DM1 I SSTL 48 DM2 I SSTL 62 DM3 I SSTL 134 DM4 I SSTL 148 DM5 I SSTL 170 DM6 I SSTL 184 DM7 I SSTL 78 DM8 I SSTL PWR – Data Mask 8 Note: ECC type module NC NC – Note: Non-ECC module EEPROM 195 SCL I CMOS Serial Bus Clock 193 SDA I/O OD 194 SA0 I 196 SA1 I CMOS Slave Address CMOS Select Bus 2:0 198 SA2 I CMOS Data Sheet Serial Bus Data 10 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Pin Configuration Table 3 Pin Configuration of SO-DIMM (cont’d) Table 3 Pin Configuration of SO-DIMM (cont’d) Pin# Name Pin Buffer Function Type Type Pin# Name Pin Buffer Function Type Type 3,4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186 VSS GND – 85, 86, 97, 98, 124, 200 NC NC Ground Plane Table 4 – Not connected Note: Pins not connected on Infineon SO DIMMs Abbreviations for Pin Type Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected (JEDEC Standard) Table 5 Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminalted Logic (SSTL2) LV-CMOS Low Voltage CMOS CMOS CMOS Levels OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Other Pins 199 VDDID O OD VDD Identification Note: Pin in tristate, indicating VDD and VDDQ nets connected on PCB Data Sheet 11 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Pin Configuration DQ16 VDD DQ18 DQ19 VDD DQS3 DQ26 VDD CB1/NC DQS8/NC VDD NC CK2/NC VDD NC A9 A7 A3 VDD BA0 S0 VSS DQ33 DQS4 VSS DQ40 DQ41 VSS DQ43 VDD VSS DQ49 DQS6 VSS DQ56 DQ57 VSS DQ59 SDA VDDSPD - Pin 041 Pin 045 Pin 049 Pin 053 Pin 057 Pin 061 Pin 065 Pin 069 Pin 073 Pin 077 Pin 081 Pin 085 Pin 089 Pin 093 Pin 097 Pin 101 Pin 105 Pin 109 Pin 113 Pin 117 Pin 121 Pin 125 Pin 129 Pin 133 Pin 137 Pin 141 Pin 145 Pin 149 Pin 153 Pin 157 Pin 161 Pin 165 Pin 169 Pin 173 Pin 177 Pin 181 Pin 185 Pin 189 Pin 193 Pin 197 VSS DQ1 DQS0 VSS DQ8 DQ09 VSS DQ11 CK0 VSS - Pin 003 Pin 007 Pin 011 Pin 015 Pin 019 Pin 023 Pin 027 Pin 031 Pin 035 Pin 039 DQ17 - Pin 043 DQS2 - Pin 047 VSS - Pin 051 DQ33 - Pin 055 DQ25 - Pin 059 VSS - Pin 063 DQ27 - Pin 067 CB0/NC - Pin 071 VSS - Pin 075 CB2/NC - Pin 079 CB3/NC - Pin 083 VSS - Pin 087 CK2/NC - Pin 091 CKE1/NC - Pin 095 A12/NC - Pin 099 VSS - Pin 103 A5 - Pin 107 A1 - Pin 111 A10/AP - Pin 115 WE - Pin 119 A13/NC - Pin 123 DQ32 - Pin 127 VDD - Pin 131 DQ34 - Pin 135 DQ35 - Pin 139 VDD - Pin 143 DQS5 - Pin 147 DQ42 - Pin 151 VDD - Pin 155 VSS - Pin 159 DQ48 - Pin 163 VDD - Pin 167 DQ50 - Pin 171 DQ51 - Pin 175 VDD - Pin 179 DQS7 - Pin 183 DQ58 - Pin 187 VDD - Pin 191 SCL - Pin 195 VDDID - Pin 199 Pin 004 Pin 008 Pin 012 Pin 016 Pin 020 Pin 024 Pin 028 Pin 032 Pin 036 Pin 040 - VSS - DQ6 - DM0 - VSS - DQ12 - DQ13 - VSS - DQ15 - VDD - VSS Pin 044 Pin 048 Pin 052 Pin 056 Pin 060 Pin 064 Pin 068 Pin 072 Pin 076 Pin 080 Pin 084 Pin 088 Pin 092 Pin 096 Pin 100 Pin 104 Pin 108 Pin 112 Pin 116 Pin 120 Pin 124 Pin 128 Pin 132 Pin 136 Pin 140 Pin 144 Pin 148 Pin 152 Pin 156 Pin 160 Pin 164 Pin 168 Pin 172 Pin 176 Pin 180 Pin 184 Pin 188 Pin 192 Pin 196 Pin 200 - BACKSIDE Pin 001 Pin 005 Pin 009 Pin 013 Pin 017 Pin 021 Pin 025 Pin 029 Pin 033 Pin 037 FRONTSIDE VREF DQ0 VDD DQ2 DQ3 VDD DQS1 DQ10 VDD CK0 - DQ21 DM2 VSS DQ28 DQ29 VSS DQ31 CB4/NC VSS CB6/NC CB7/NC VSS VDD CKE0 A11 VSS A4 A0 BA1 CAS NC DQ36 VDD DQ38 DQ39 VDD DM5 DQ46 VDD CK1 DQ52 VDD DQ54 DQ55 VDD DM7 DQ62 VDD SA1 NC Pin 002 Pin 006 Pin 010 Pin 014 Pin 018 Pin 022 Pin 026 Pin 030 Pin 034 Pin 038 - VREF DQ4 VDD DQ6 DQ7 VDD DM1 DQ14 VDD VSS Pin 042 Pin 046 Pin 050 Pin 054 Pin 058 Pin 062 Pin 066 Pin 070 Pin 074 Pin 078 Pin 082 Pin 086 Pin 090 Pin 094 Pin 098 Pin 102 Pin 106 Pin 110 Pin 114 Pin 118 Pin 122 Pin 126 Pin 130 Pin 134 Pin 138 Pin 142 Pin 146 Pin 150 Pin 154 Pin 158 Pin 162 Pin 166 Pin 170 Pin 174 Pin 178 Pin 182 Pin 186 Pin 190 Pin 194 Pin 198 - DQ20 VDD DQ22 DQ23 VDD DM3 DQ30 VDD CB5/NC DM8/NC VDD NC VSS VDD NC A8 A6 A2 VDD RAS S1/NC VSS DQ37 DM4 VSS DQ44 DQ45 VSS DQ47 CK1 VSS DQ53 DM6 VSS DQ60 DQ61 VSS DQ63 SA0 SA2 MPPD0040 Figure 1 Pin Configuration Diagram 200-Pin SO-DIMM Table 6 Density Organization Memory Ranks SDRAMs # of SDRAMs # of row/bank/ columns bits Refresh Period Interval 128MB 16M ×64 1 16M ×16 4 13/2/9 8K 64 ms 7.8 µs 256MB 32M ×64 2 16M ×16 8 13/2/9 8K 64 ms 7.8 µs Data Sheet 12 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Pin Configuration BA0 - BA1 A0 - An RAS CAS WE CKE0 VDDSPD VDD/VDDQ VREF VSS VDDID BA0 - BA1: SDRAMs D0 - D3 A0 - An: SDRAMs D0 - D3 RAS: SDRAMs D0 - D3 CAS: SDRAMs D0 - D3 WE: SDRAMs D0 - D3 CKE: SDRAMs D0 - D3 VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D3 VREF: SDRAMs D0 - D3 VSS: SDRAMs D0 - D3 Strap: see Note 1 S0 DM1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDM CS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D0 DM3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDM CS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 SCL SAD SA0 SA1 SA2 VSS SCL SAD A0 A1 A2 WP D1 E0 DM5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDM CS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 DM7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDM CS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D2 D3 MPBD1051 Figure 2 Block Diagram Raw Card C ×64 1 Rank ×16 Notes 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 Ω ±5 % 3. BAn, An, RAS, CAS, WE resistors are 7.5 Ω ±5 % Data Sheet Table 7 13 Clock Signal Loads Clock Input Number of SDRAMs Note CK0, CK0 NC — CK1, CK1 2 SDRAMs — CK2, CK2 2 SDRAMs — Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Pin Configuration BA0 - BA1 A0 - An RAS CAS WE CKE0 CKE1 CK0 CK0 CK1 CK1 CK2 CK2 VDD,SPD VDD/VDDQ VREF VSS VDDID BA0 - BA1: SDRAMs D0 - D3 A0 - An: SDRAMs D0 - D3 RAS: SDRAMs D0 - D3 CAS: SDRAMs D0 - D3 WE: SDRAMs D0 - D3 CKE: SDRAMs D0 - D3 CKE: SDRAMs D4 - D7 4 loads VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D7 VREF: SDRAMs D0 - D7 VSS: SDRAMs D0 - D7 Strap: see Note 1 SCL SAD A0 A1 A2 WP SCL SAD SA0 SA1 SA2 VSS 4 loads 0 loads E0 S0 S1 DM0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS LDM LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 DM2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS LDM LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D0 D1 CS LDM LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS LDM LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D4 DM4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS LDM LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 DM6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CS LDM LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D5 D2 D3 CS LDM LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS LDM LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D6 D7 MPBD1091 Figure 3 Block Diagram Raw Card A ×64 2 Ranks ×8 3. BAn, An, RAS, CAS, WE resistors are 22 ohms +/5% Notes 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 18 ohms +/-5% Data Sheet 14 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Electrical Characteristics 4 Electrical Characteristics 4.1 Operating Conditions Table 8 Absolute Maximum Ratings Parameter Symbol Values Unit Note/ Test Condition min. typ. max. Voltage on I/O pins relative to VSS VIN, VOUT Voltage on inputs relative to VSS VIN Voltage on VDD supply relative to VSS VDD Voltage on VDDQ supply relative to VSS VDDQ Operating temperature (ambient) TA Storage temperature (plastic) TSTG Power dissipation (per SDRAM component) PD Short circuit output current IOUT –0.5 – VDDQ +0.5 V – –1 – +3.6 V – –1 – +3.6 V – –1 – +3.6 V – 0 – +70 °C – -55 – +150 °C – – 1 – W – – 50 – mA – Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 9 Electrical Characteristics and DC Operating Conditions Unit Note/Test Condition 1) Parameter Symbol Min. Typ. Max. Device Supply Voltage VDD 2.3 2.5 2.7 V Device Supply Voltage VDD VDDQ 2.5 2.6 2.7 V 2.3 2.5 2.7 V Output Supply Voltage 2.5 2.6 2.7 V fCK ≤ 166 MHz fCK > 166 MHz 2) fCK ≤ 166 MHz fCK > 166 MHz 2) EEPROM supply voltage 2.3 2.5 3.6 V — 0 V — 0.51 × V 3) VDDQ VDDQ VREF – 0.04 VDDQ VREF + 0.04 V 4) VREF + 0.15 7) Output Supply Voltage VDDQ VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ VREF Input Reference Voltage I/O Termination Voltage (System) VTT Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Values 0 0.49 × 0.5 × Input Voltage Level, CK and CK Inputs VIN(DC) –0.3 VDDQ + 0.3 V VREF – 0.15 V VDDQ + 0.3 V Input Differential Voltage, CK and CK Inputs VID(DC) 0.36 VDDQ + 0.6 V 7)5) VI-Matching Pull-up Current to Pull-down Current VIRatio 0.71 1.4 6) Data Sheet –0.3 15 — 7) 7) Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Electrical Characteristics Table 9 Electrical Characteristics and DC Operating Conditions (cont’d) Parameter Symbol Unit Note/Test Condition 1) Values Min. Typ. Max. Input Leakage Current II –2 2 µA Any input 0 V ≤ VIN ≤ VDD; All other pins not under test = 0 V 7)8) Output Leakage Current IOZ –5 5 µA DQs are disabled; 0 V ≤ VOUT ≤ VDDQ 7) Output High Current, Normal Strength Driver IOH — –16.2 mA VOUT = 1.95 V 7) Output Low Current, Normal Strength Driver IOL 16.2 — mA VOUT = 0.35 V 7) 1) 0 °C ≤ TA ≤ 70 °C 2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 5) VID is the magnitude of the difference between the input level on CK and the input level on CK. 6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 7) Inputs are not recognized as valid until VREF stabilizes. 8) Values are shown per DDR SDRAM component Data Sheet 16 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Electrical Characteristics 4.2 Current Specification and Conditions Table 10 IDD Conditions Parameter Symbol Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. IDD0 Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. IDD1 Precharge Power-Down Standby Current all banks idle; power-down mode; CKE ≤ VIL,MAX IDD2P Precharge Floating Standby Current CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. IDD2F Precharge Quiet Standby Current CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX. IDD2Q Active Power-Down Standby Current one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM. IDD3P Active Standby Current one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. IDD3N Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA IDD4R Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B IDD4W Auto-Refresh Current tRC = tRFCMIN, burst refresh IDD5 Self-Refresh Current CKE ≤ 0.2 V; external clock on IDD6 Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. IDD7 Data Sheet 17 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Electrical Characteristics HYS64D32020HDL–5–C HYS64D32020GDL–5–C HYS64D16000HDL–6–C HYS64D16000GDL–6–C HYS64D32020HDL–6–C HYS64D32020GDL–6–C IDD Specification for HYS64D[32020/16000][H/G]DL–[5/6]–C HYS64D16000HDL–5–C HYS64D16000GDL–5–C Part Number & Organization Table 11 128MB 256MB 128MB 256MB ×64 ×64 ×64 ×64 1 Ranks 2 Ranks 1 Ranks 2 Ranks –5 –5 –6 Unit Note 1)2) –6 Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 300 360 472 576 260 300 404 480 mA 3) 380 440 552 656 320 380 464 560 mA 3)4) 16 20 32 40 16 20 32 40 mA 5) 120 144 240 288 100 120 200 240 mA 5) 80 112 160 224 68 96 136 192 mA 5) 52 72 104 144 44 60 88 120 mA 5) 172 216 344 432 144 180 288 360 mA 5) 400 480 572 696 340 400 484 580 mA 3)4) 400 520 572 736 360 440 504 620 mA 3) 560 760 732 976 480 640 624 820 mA 3) 5.6 11.2 11.2 22.4 6 11 11 22 mA 5) 840 1000 1012 1216 720 860 864 1040 mA 3)4) 1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity. 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C 3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows: m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1) 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component] Data Sheet 18 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Electrical Characteristics 4.3 AC Characteristics Table 12 AC Timing - Absolute Specifications for DDR400B and DDR333 Parameter Symbol –5 –6 DDR400B DQ output access time from CK/ tAC CK Unit Note/ Test Condition 1) DDR333 Min. Max. Min. Max. –0.5 +0.5 –0.7 +0.7 ns 2)3)4)5) DQS output access time from CK/CK tDQSCK –0.6 +0.6 –0.6 +0.6 ns 2)3)4)5) CK high-level width tCH tCL tHP tCK 0.45 0.55 0.45 0.55 2)3)4)5) 0.45 0.55 0.45 0.55 tCK tCK min. (tCL, tCH) ns 2)3)4)5) CK low-level width Clock Half Period min. (tCL, tCH) 2)3)4)5) 5 8 6 12 ns CL = 3.0 2)3)4)5) 6 12 6 12 ns CL = 2.5 2)3)4)5) 7.5 12 7.5 12 ns CL = 2.0 2)3)4)5) tDH tDS tIPW 0.4 — 0.45 — ns 2)3)4)5) 0.4 — 0.45 — ns 2)3)4)5) 2.2 — 2.2 — ns 2)3)4)5)6) DQ and DM input pulse width (each input) tDIPW 1.75 — 1.75 — ns 2)3)4)5)6) Data-out high-impedance time from CK/CK tHZ — +0.7 –0.7 +0.7 ns 2)3)4)5)7) Data-out low-impedance time from CK/CK tLZ –0.7 +0.7 –0.7 +0.7 ns 2)3)4)5)7) Write command to 1st DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK 2)3)4)5) DQS-DQ skew (DQS and associated DQ signals) tDQSQ — +0.40 — +0.45 ns TSOPII 2)3)4)5) — +0.50 — +0.55 ns TSOPII 2)3)4)5) Clock cycle time DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) tQHS DQ/DQS output hold time tQH DQS input low (high) pulse width tDQSL,H Data hold skew factor tHP – tQHS tHP – tQHS ns 2)3)4)5) 0.35 — 0.35 — tCK 2)3)4)5) (write cycle) DQS falling edge to CK setup time (write cycle) tDSS 0.2 — 0.2 — tCK 2)3)4)5) DQS falling edge hold time from CK (write cycle) tDSH 0.2 — 0.2 — tCK 2)3)4)5) Mode register set command cycle time tMRD 2 — 2 — tCK 2)3)4)5) Write preamble setup time tWPRES tWPST tWPRE tIS 0 — 0 — ns 2)3)4)5)8) 2)3)4)5)9) Write postamble Write preamble Address and control input setup time 0.40 0.60 0.40 0.60 0.25 — 0.25 — tCK tCK 0.6 — 0.75 — ns 2)3)4)5) fast slew rate 3)4)5)6)10) 0.7 — 0.8 — ns slow slew rate 3)4)5)6)10) Data Sheet 19 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Electrical Characteristics Table 12 AC Timing - Absolute Specifications for DDR400B and DDR333 (cont’d) Parameter Address and control input hold time Symbol tIH –5 –6 Unit DDR400B DDR333 Min. Max. Min. Max. 0.6 — 0.75 — ns Note/ Test Condition 1) fast slew rate 3)4)5)6)10) 0.7 — 0.8 — ns slow slew rate 3)4)5)6)10) 2)3)4)5) 0.60 tCK tCK 42 70E+3 ns 2)3)4)5) — 60 — ns 2)3)4)5) 65 — 72 — ns 2)3)4)5) tRCD tRP tRAP 15 — 18 — ns 2)3)4)5) 15 — 18 — ns 2)3)4)5) tRCD or tRASmin tRCD or tRASmin ns 2)3)4)5) tRRD 10 — 12 — ns 2)3)4)5) tWR Auto precharge write recovery + tDAL 15 — 15 — ns 2)3)4)5) tCK 2)3)4)5)11) tRPRE tRPST tRAS tRC 0.9 1.1 0.9 1.1 0.40 0.60 0.40 40 70E+3 55 Auto-refresh to Active/Autorefresh command period tRFC Active to Read or Write delay Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time — precharge time — — — 2)3)4)5) Internal write to read command delay tWTR 2 — 1 — tCK 2)3)4)5) Exit self-refresh to non-read command tXSNR 75 — 75 — ns 2)3)4)5) Exit self-refresh to read command tXSRD 200 — 200 — tCK 2)3)4)5) Average Periodic Refresh Interval tREFI — 7.8 — 7.8 µs 2)3)4)5)12) 1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400) 2) Input slew rate ≥ 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. Data Sheet 20 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Electrical Characteristics 10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ ns, measured between VOH(ac) and VOL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Data Sheet 21 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules SPD Contents 5 SPD Contents Table 13 SPD Codes for HYS64D32020[H/G]DL–5–C Product Type & Organization HYS64D32020GDL–5–C HYS64D32020HDL–5–C 256 MB 256 MB ×64 ×64 2 Ranks 2 Ranks Label Code PC3200S–3033–1 PC3200S–3033–1 Jedec SPD Revision Rev 1.0 Rev 1.0 Byte# Description HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 1 Total number of Bytes in E2PROM 08 08 2 Memory Type (DDR = 07h) 07 07 3 Number of Row Addresses 0D 0D 4 Number of Column Addresses 09 09 5 Number of DIMM Ranks 02 02 6 Data Width (LSB) 40 40 7 Data Width (MSB) 00 00 8 Interface Voltage Levels 04 04 9 tCK @ CLmax (Byte 18) [ns] 50 50 10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 11 Error Correction Support 00 00 12 Refresh Rate 82 82 13 Primary SDRAM Width 10 10 14 Error Checking SDRAM Width 00 00 15 tCCD [cycles] 01 01 16 Burst Length Supported 0E 0E 17 Number of Banks on SDRAM Device 04 04 18 CAS Latency 1C 1C 19 CS Latency 01 01 20 Write Latency 02 02 21 DIMM Attributes 20 20 22 Component Attributes C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60 24 tAC SDRAM @ CLmax -0.5 [ns] 50 50 25 tCK @ CLmax -1 (Byte 18) [ns] 75 75 26 tAC SDRAM @ CLmax -1 [ns] 50 50 27 tRPmin [ns] 3C 3C 28 tRRDmin [ns] 28 28 29 tRCDmin [ns] 3C 3C 30 tRASmin [ns] 28 28 31 Module Density per Rank 20 20 32 tAS, tCS [ns] 60 60 Data Sheet 22 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules SPD Contents Table 13 SPD Codes for HYS64D32020[H/G]DL–5–C Product Type & Organization HYS64D32020GDL–5–C HYS64D32020HDL–5–C 256 MB 256 MB ×64 ×64 2 Ranks 2 Ranks Label Code PC3200S–3033–1 PC3200S–3033–1 Jedec SPD Revision Rev 1.0 Rev 1.0 Byte# Description HEX HEX 33 tAH, TCH [ns] 60 60 34 tDS [ns] 40 40 35 tDH [ns] 40 40 36 - 40 not used 00 00 41 tRCmin [ns] 37 37 42 tRFCmin [ns] 41 41 43 tCKmax [ns] 28 28 44 tDQSQmax [ns] 28 28 45 tQHSmax [ns] 50 50 46 not used 00 00 47 DIMM PCB Height 01 01 48 - 61 not used 00 00 62 SPD Revision 10 10 63 Checksum of Byte 0-62 F6 F6 64 JEDEC ID Code of Infineon (1) C1 C1 65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 72 Module Manufacturer Location xx xx 73 Part Number, Char 1 36 36 74 Part Number, Char 2 34 34 75 Part Number, Char 3 44 44 76 Part Number, Char 4 33 33 77 Part Number, Char 5 32 32 78 Part Number, Char 6 30 30 79 Part Number, Char 7 32 32 80 Part Number, Char 8 30 30 81 Part Number, Char 9 47 48 82 Part Number, Char 10 44 44 83 Part Number, Char 11 4C 4C 84 Part Number, Char 12 35 35 85 Part Number, Char 13 43 43 86 Part Number, Char 14 20 20 87 Part Number, Char 15 20 20 88 Part Number, Char 16 20 20 89 Part Number, Char 17 20 20 90 Part Number, Char 18 20 20 Data Sheet 23 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules SPD Contents Table 13 SPD Codes for HYS64D32020[H/G]DL–5–C Product Type & Organization HYS64D32020GDL–5–C HYS64D32020HDL–5–C 256 MB 256 MB ×64 ×64 2 Ranks 2 Ranks Label Code PC3200S–3033–1 PC3200S–3033–1 Jedec SPD Revision Rev 1.0 Rev 1.0 Byte# Description HEX HEX 91 Module Revision Code 0x 0x 92 Test Program Revision Code xx xx 93 Module Manufacturing Date Year xx xx 94 Module Manufacturing Date Week xx xx 95 - 98 Module Serial Number (1 - 4) xx xx FF FF 99 - 127 Blank HYS64D16000HDL–6–C HYS64D32020GDL–6–C HYS64D32020HDL–6–C SPD Codes for HYS64D[32020/16000][H/G]DL–6–C HYS64D16000GDL–6–C Table 14 128MB 128MB 256MB 256MB ×64 ×64 ×64 ×64 1 Rank 1 Rank 2 Ranks 2 Ranks –6 –6 –6 –6 Label Code PC2700S– 2533–0 PC2700S– 2533–0 PC2700S– 2533–0 PC2700S– 2533–0 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Part Number & Organization Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 08 2 Memory Type DDR = 07h 07 07 07 07 3 # of Row Addresses 0D 0D 0D 0D 4 # Number of Column Addresses 09 09 09 09 5 # of DIMM Ranks 01 01 02 02 6 Data Width (LSB) 40 40 40 40 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 tCK @ CLmax (Byte 18) [ns] 60 60 60 60 10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70 Data Sheet 24 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules SPD Contents HYS64D16000HDL–6–C HYS64D32020GDL–6–C HYS64D32020HDL–6–C SPD Codes for HYS64D[32020/16000][H/G]DL–6–C HYS64D16000GDL–6–C Table 14 128MB 128MB 256MB 256MB ×64 ×64 ×64 ×64 1 Rank 1 Rank 2 Ranks 2 Ranks –6 –6 –6 –6 Label Code PC2700S– 2533–0 PC2700S– 2533–0 PC2700S– 2533–0 PC2700S– 2533–0 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX HEX 11 DIMM Configuration Type (non- / ECC) 00 00 00 00 12 Refresh Rate 82 82 82 82 13 Primary SDRAM width 10 10 10 10 14 Error Checking SDRAM width 00 00 00 00 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM 04 04 04 04 18 CAS Latency 0C 0C 0C 0C 19 CS Latency 01 01 01 01 20 WE (Write) Latency 02 02 02 02 Part Number & Organization 21 DIMM Attributes 20 20 20 20 22 Component Attributes C1 C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75 75 24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70 25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00 00 26 tAC SDRAM @ CLmax -1 [ns] 00 00 00 00 27 tRPmin (ns) 48 48 48 48 28 tRRDmin [ns] 30 30 30 30 29 tRCDmin [ns] 48 48 48 48 30 tRASmin [ns] 2A 2A 2A 2A 31 Module Density per Rank 20 20 20 20 32 tAS, tCS [ns] 75 75 75 75 33 tAH, TCH [ns] 75 75 75 75 34 tDS [ns] 45 45 45 45 35 tDH [ns] 45 45 45 45 36 - 40 not used 00 00 00 00 Data Sheet 25 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules SPD Contents HYS64D16000HDL–6–C HYS64D32020GDL–6–C HYS64D32020HDL–6–C SPD Codes for HYS64D[32020/16000][H/G]DL–6–C HYS64D16000GDL–6–C Table 14 128MB 128MB 256MB 256MB ×64 ×64 ×64 ×64 1 Rank 1 Rank 2 Ranks 2 Ranks –6 –6 –6 –6 Label Code PC2700S– 2533–0 PC2700S– 2533–0 PC2700S– 2533–0 PC2700S– 2533–0 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX HEX 41 tRCmin [ns] 3C 3C 3C 3C 42 tRFCmin [ns] 48 48 48 48 43 tCKmax [ns] 30 30 30 30 44 tDQSQmax [ns] 2D 2D 2D 2D 45 tQHSmax [ns] 55 55 55 55 46 - 61 not used 00 00 00 00 62 SPD Revision 00 00 00 00 63 Checksum of Byte 0-62 (LSB only) E8 E8 E9 E9 64 JEDEC ID Code for Infineon(1) C1 C1 C1 C1 65 - 71 JEDEC ID Code for Infineon(2 -8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 36 36 36 36 74 Part Number, Char 2 34 34 34 34 75 Part Number, Char 3 44 44 44 44 76 Part Number, Char 4 31 31 33 33 77 Part Number, Char 5 36 36 32 32 78 Part Number, Char 6 30 30 30 30 79 Part Number, Char 7 30 30 32 32 80 Part Number, Char 8 30 30 30 30 81 Part Number, Char 9 47 48 47 48 82 Part Number, Char 10 44 44 44 44 83 Part Number, Char 11 4C 4C 4C 4C 84 Part Number, Char 12 36 36 36 36 85 Part Number, Char 13 43 43 43 43 86 Part Number, Char 14 20 20 20 20 87 Part Number, Char 15 20 20 20 20 Part Number & Organization Data Sheet 26 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules SPD Contents HYS64D16000HDL–6–C HYS64D32020GDL–6–C HYS64D32020HDL–6–C SPD Codes for HYS64D[32020/16000][H/G]DL–6–C HYS64D16000GDL–6–C Table 14 128MB 128MB 256MB 256MB ×64 ×64 ×64 ×64 1 Rank 1 Rank 2 Ranks 2 Ranks –6 –6 –6 –6 Label Code PC2700S– 2533–0 PC2700S– 2533–0 PC2700S– 2533–0 PC2700S– 2533–0 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX HEX 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 Part Number & Organization 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code xx xx xx xx 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx xx 99 -127 not used FF FF FF FF Data Sheet 27 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Package Outlines 6 Package Outlines 67.6 2.4 MAX. 31.75 4 ±0.1 1.8 ±0.05 63.6 (2.15) 1 (2.45) 18.45 ±0.1 100 1±0.1 1.8 ±0.1 0.15 (2.4) 11.4 ±0.1 47.4 ±0.1 (2.7) (2.45) (2.15) 1.5 ±0.1 200 20 101 6 4 ±0.1 1±0.1 2 MIN. 2.55 0.25 -0.18 Detail of contacts 0.45 ±0.03 0.6 ±0.1 Burnished, no burr allowed L-DIM-200-011 Figure 4 Data Sheet Package Outlines – Raw Card C DDR-SDRAM SO-DIMM HYS64D16000[G/H]DL–6–C 28 Rev. 1.0, 2004-03 HYS64D[32020/16000][H/G]DL–[5/6]–C Small Outline DDR SDRAM Modules Package Outlines 67.6 3.8 MAX. 31.75 4 ±0.1 1.8 ±0.05 63.6 ±0.1 (2.15) 1 (2.45) 18.45 ±0.1 100 1±0.1 1.8 ±0.1 0.15 (2.4) 11.4 ±0.1 47.4 ±0.1 (2.7) (2.15) 1.5 ±0.1 4 ±0.1 1±0.1 200 20 ±0.1 101 6 ±0.1 (2.45) 2 MIN. 2.55 0.25 -0.18 Detail of contacts 0.45 ±0.03 0.6 ±0.1 Burnished, no burr allowed L-DIM-200-006 Figure 5 Data Sheet Package Outlines – Raw Card A DDR SDRAM SO-DIMM HYS64D32020[G/H]DL–5/6]–C 29 Rev. 1.0, 2004-03 www.infineon.com Published by Infineon Technologies AG