TI1 LM25118 Lm25118/lm25118q wide voltage range buck-boost controller Datasheet

LM25118
LM25118/LM25118Q Wide Voltage Range Buck-Boost Controller
Literature Number: SNVS726A
LM25118/LM25118Q
Wide Voltage Range Buck-Boost Controller
General Description
Features
The LM25118 wide voltage range Buck-Boost switching regulator controller features all of the functions necessary to
implement a high performance, cost efficient Buck-Boost regulator using a minimum of external components. The BuckBoost topology maintains output voltage regulation when the
input voltage is either less than or greater than the output
voltage making it especially suitable for automotive applications. The LM25118 operates as a buck regulator while the
input voltage is sufficiently greater than the regulated output
voltage and gradually transitions to the buck-boost mode as
the input voltage approaches the output. This dual mode approach maintains regulation over a wide range of input voltages with optimal conversion efficiency in the buck mode and
a glitch-free output during mode transitions. This easy to use
controller includes drivers for the high side buck MOSFET and
the low side boost MOSFET. The regulator’s control method
is based upon current mode control utilizing an emulated current ramp. Emulated current mode control reduces noise
sensitivity of the pulse-width modulation circuit, allowing reliable control of the very small duty cycles necessary in high
input voltage applications. Additional protection features include current limit, thermal shutdown and an enable input.
The device is available in a power enhanced TSSOP-20
package featuring an exposed die attach pad to aid thermal
dissipation.
■ LM25118Q1 is an Automotive Grade product that is AEC■
■
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■
■
■
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Q100 Grade 1 qualified (-40°C to 125°C operating junction
temperature)
Input voltage operating range from 3V to 42V
Emulated peak current mode control
Smooth transition between step-down and step- up modes
Switching frequency programmable to 500KHz
Oscillator synchronization capability
Internal high voltage bias regulator
Integrated high and low-side gate drivers
Programmable soft-start time
Ultra low shutdown current
Enable input
Wide bandwidth error amplifier
1.5% feedback reference accuracy
Thermal shutdown
Package
TSSOP-20EP (Exposed pad)
Typical Application Circuit
30165101
© 2011 Texas Instruments Incorporated
301651
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LM25118/LM25118Q Wide Voltage Range Buck-Boost Controller
November 28, 2011
LM25118/LM25118Q
Connection Diagram
30165102
Top View
20-Lead TSSOP with Exposed Pad
See NS Package Number MXA20A
Ordering Information
Ordering Number
Grade
Package Type
NSC Package
Drawing
Supplied As
LM25118MH
Standard
TSSOP-20EP
MXA20A
Rail of 73 Units
Reel of 2500 Units
LM25118MHX
Standard
TSSOP-20EP
MXA20A
LM25118Q1MH
Automotive (*)
TSSOP-20EP
MXA20A
Rail of 73 Units
LM25118Q1MHX
Automotive (*)
TSSOP-20EP
MXA20A
Reel of 2500 Units
* Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.
Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identified
with the letter Q. For more information go to http://www.national.com/automotive.
Pin Descriptions
Pin
Name
1
VIN
Description
Input supply voltage.
If the UVLO pin is below 1.23V, the regulator will be in standby mode (VCC regulator running, switching
regulator disabled). When the UVLO pin exceeds 1.23V, the regulator enters the normal operating mode. An
external voltage divider can be used to set an under-voltage shutdown threshold. A fixed 5 µA current is sourced
out of the UVLO pin. If a current limit condition exists for 256 consecutive switching cycles, an internal switch
pulls the UVLO pin to ground and then releases.
2
UVLO
3
RT
The internal oscillator frequency is set with a single resistor between this pin and the AGND pin. The
recommended frequency range is 50 kHz to 500 kHz.
4
EN
If the EN pin is below 0.5V, the regulator will be in a low power state drawing less than 10 µA from VIN. EN
must be raised above 3V for normal operation.
5
RAMP
Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope
used for emulated current mode control.
6
AGND
Analog ground.
7
SS
Soft-Start. An external capacitor and an internal 10 µA current source set the rise time of the error amp
reference. The SS pin is held low when VCC is less than the VCC under-voltage threshold (< 3.7V), when the
UVLO pin is low (< 1.23V), when EN is low (< 0.5V) or when thermal shutdown is active.
8
FB
Feedback signal from the regulated output. Connect to the inverting input of the internal error amplifier.
9
COMP
Output of the internal error amplifier. The loop compensation network should be connected between COMP
and the FB pin.
10
VOUT
Output voltage monitor for emulated current mode control. Connect this pin directly to the regulated output.
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2
Name
Description
11
SYNC
Sync input for switching regulator synchronization to an external clock.
12
CS
13
CSG
14
PGND
15
LO
16
VCC
17
VCCX
Optional input for an externally supplied bias supply. If the voltage at the VCCX pin is greater than 3.9V, the
internal VCC regulator is disabled and the VCC pin is internally connected to VCCX pin supply. If VCCX is not
used, connect to AGND.
18
HB
High side gate driver supply used in bootstrap operation. The bootstrap capacitor supplies current to charge
the high side MOSFET gate. This capacitor should be placed as close to the controller as possible and
connected between HB and HS.
19
HO
Buck MOSFET gate drive output. Connect to the gate of the high side buck MOSFET through a short, low
inductance path.
20
HS
Buck MOSFET source pin. Connect to the source terminal of the high side buck MOSFET and the bootstrap
capacitor.
EP
Exposed thermal pad. Solder to the ground plane under the IC to aid in heat dissipation.
Current sense input. Connect to the diode side of the current sense resistor.
Current sense ground input. Connect to the ground side of the current sense resistor.
Power Ground.
Boost MOSFET gate drive output. Connect to the gate of the external boost MOSFET.
Output of the bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as close to
the controller as possible.
3
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LM25118/LM25118Q
Pin
LM25118/LM25118Q
ESD Rating
HBM (Note 2)
Storage Temperature Range
Junction Temperature
Absolute Maximum Ratings (Note 1)
VIN, EN, VOUT to GND
-0.3V to 45V
VCC, LO, VCCX, UVLO to GND (Note 3)
-0.3V to 16V
HB to HS
-0.3V to 16V
HO to HS
-0.3 to HB+0.3V
HS to GND
-4V to 45V
CSG, CS to GND
-0.3V to +0.3V
RAMP, SS, COMP, FB, SYNC, RT to GND
-0.3V to 7V
Operating Ratings
2 kV
-55°C to +150°C
+150°C
(Note 1)
VIN (Note 4)
VCC, VCCX
Junction Temperature
3V to 42V
4.75V to 14V
-40°C to +125°C
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
operating junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design,
or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 24V, VCCX = 0V, EN = 5V, RT = 29.11 kΩ, No load
on LO and HO.
Symbol
Parameter
Conditions
IBIAS
VIN Operating Current
IBIASX
ISTDBY
Min
Typ
Max
Units
VCCX = 0V
4.5
5.5
mA
VIN Operating Current
VCCX = 5V
1
1.85
mA
VIN Shutdown Current
EN = 0V
1
10
µA
6.8
7
7.2
V
5.5
VIN SUPPLY
VCC REGULATOR
VCC(REG)
VCC Regulation
VCCX = 0V
VCC(REG)
VCC Regulation
VCCX = 0V, VIN = 6V
5
5.25
VCC Sourcing Current Limit
VCC = 0
21
35
VCCX Switch threshold
VCCX Rising
3.68
3.85
VCCX Switch hysterisis
ICCX = 10 mA
VCCX Switch Leakage
VCCX = 0V
VCCCX Pull-down Resistance
VCCX = 3V
VCC Under-Voltage Lockout Voltage
VCC Rising
V
5
12
0.5
1
Ω
µA
V
70
3.52
VCC Under-Voltage Hysterisis
HB DC Bias current
4.02
0.2
VCCX Switch RDS(ON)
3.7
kΩ
3.86
V
260
µA
0.21
HB-HS = 15V
205
VC LDO Mode Turn-off
V
mA
V
10
V
EN INPUT
VEN(OFF)
EN Input Low Threshold
VEN Falling
VEN(ON)
EN Input High Threshold
VEN Rising
EN Input Bias Current
VEN = 3V
-1
1
µA
EN Input Bias Current
VEN = 0.5V
-1
1
µA
EN Input Bias Current
VEN = 42V
0.5
V
V
3.00
50
µA
UVLO THRESHOLDS
UVLO
ΔUVLO
UVLO Standby Threshold
UVLO Rising
1.191
UVLO Threshold Hysteresis
UVLO Pull-up Current Source
UVLO = 0V
UVLO Pull-down RDS(ON)
1.231
1.271
V
0.105
V
5
µA
100
200
10.5
13.5
Ω
SOFT-START
SS Current Source
SS = 0V
SS to FB Offset
FB = 1.23V
SS Output Low Voltage
Sinking 100 µA, UVLO = 0V
7.5
µA
150
mV
7
mV
ERROR AMPLIFIER
VREF
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FB Reference Voltage
Measured at FB pin,
FB = COMP
FB Input Bias Current
FB = 2V
4
1.212
1.230
1.248
V
20
200
nA
Parameter
Conditions
COMP Sink/Source Current
Min
Typ
Max
Units
mA
3
AOL
DC Gain
80
dB
fBW
Unity Bain Bandwidth
3
MHz
PWM COMPARATORS
tHO(OFF)
Forced HO Off-time
TON(MIN)
Minimum HO On-time
70
ns
COMP to Comparator Offset
200
mV
305
400
495
ns
OSCILLATOR (RT PIN)
fSW1
Frequency 1
RT = 29.11 kΩ
178
200
224
kHz
fSW2
Frequency 2
RT = 9.525 kΩ
450
515
575
kHz
SYNC
Sync threshold falling
1.3
V
CURRENT LIMIT
VCS(TH)
Cycle-by-cycle Sense Voltage
Threshold (CS-CSG)
RAMP = 0 Buck Mode
-103
-125
-147
mV
VCS(THX)
Cycle-by-cycle Sense Voltage
Threshold (CS-CSG)
RAMP = 0 Buck-Boost Mode
-218
-255
-300
mV
CS Bias Current
CS = 0V
45
60
µA
CSG Bias Current
CSG = 0V
45
60
Current Limit Fault Timer
256
µA
cycles
RAMP GENERATOR
IR2
RAMP Current 2
VIN = 12V, VOUT = 12V
95
115
135
µA
IR3
RAMP Current 3
VIN = 5V, VOUT = 12V
65
80
95
µA
VOUT Bias Current
VOUT = 42V
245
µA
LOW SIDE (LO) GATE DRIVER
VOLL
LO Low-state Output Voltage
ILO = 100 mA
VOHL
LO High-state Output Voltage
ILO = -100 mA
VOHL = VCC-VLO
LO Rise Time
LO Fall Time
IOHL
IOLL
0.095
0.14
0.23
V
0.25
V
C-load = 1 nF, VCC = 8V
16
ns
C-load = 1 nF, VCC = 8V
14
ns
Peak LO Source Current
VLO = 0V, VCC = 8V
2.2
A
Peak LO Sink Current
VLO = VCC = 8V
2.7
A
HIGH SIDE (HO) GATE DRIVER
VOLH
HO Low-state Output Voltage
IHO = 100 mA
VOHH
HO High-state Output Voltage
IHO = -100 mA,
VOHH = VHB-VOH
HO Rise Time
HO Fall Time
IOHH
IOLH
0.1
0.135
0.21
V
0.25
V
C-load = 1 nF, VCC = 8V
14
ns
C-load = 1 nF, VCC = 8V
12
ns
Peak HO Source Current
VHO = 0V, VCC = 8V
2.2
A
Peak HO Sink Current
VHO = VCC = 8V
3.5
A
3
V
HB-HS Under Voltage Lock-out
BUCK-BOOST CHARACTERISTICS
Buck-Boost Mode
Buck Duty Cycle (Note 5)
69
75
80
%
THERMAL
TSD
ΔTSD
Thermal Shutdown Junction
Temperature
165
°C
Thermal Shutdown Hysterisis
25
°C
5
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LM25118/LM25118Q
Symbol
LM25118/LM25118Q
Symbol
Parameter
Conditions
Junction to Case, θJC
(Note 6)
4
(Note 7)
110
(Note 8)
40
(Note 9)
35
Thermal
Resistance Junction to Ambient, θ
JA
Min
Typ
Max
Units
°C/W
°C/W
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should
not be operated beyond such conditions. For guaranteed specifications and conditions, see the Electrical Characteristics table.
Note 2: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Applicable standard is JESD-22-A114-C.
Note 3: If VIN ≥ 15.7V, the AbsMax Rating for VCC, LO, VCCX, and UVLO to GND is: -0.3V to 16V. If VIN < 15.7V, the AbsMax Rating for VCC, LO, VCCX,
and UVLO to GND is: -0.3V to VIN+0.3V
Note 4: VIN ≥ 5.0V is required to initially start the controller.
Note 5: When the duty cycle exceeds 75%, the LM25118 controller gradually phases into the Buck-Boost mode.
Note 6: θJC refers to center of the Exposed Pad on the bottom of the package as the Case.
Note 7: JEDEC 2-Layer test board (JESD51-3)
Note 8: JEDEC 4-Layer test board (JESD 51-7) with 4 thermal vias under the Exposed Pad.
Note 9: JEDEC 4-Layer test board (JESD 51-7) with 12 thermal vias under the Exposed Pad.
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6
LM25118/LM25118Q
Typical Performance Characteristics
Efficiency vs VIN and IOUT
VOUT = 12V
Current Limit Threshold vs VOUT/VIN
VOUT = 12V
30165103
30165104
VCC vs VIN
VCC vs IVCC
30165105
30165106
LO and HO Peak Gate Current vs Output Voltage
VCC = 8V
Error Amplifier Gain/Phase
30165107
30165108
7
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LM25118/LM25118Q
Oscillator Frequency vs RT
30165109
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8
LM25118/LM25118Q
FIGURE 1.
30165110
Block Diagram and Typical Application Circuit
9
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LM25118/LM25118Q
state at the enable pin will put the regulator into an extremely
low current shutdown state. The device is available in the
TSSOP-20EP package featuring an exposed pad to aid in
thermal dissipation.
A buck-boost regulator can maintain regulation for input voltages either higher or lower than the output voltage. The
challenge is that buck-boost power converters are not as efficient as buck regulators. The LM25118 has been designed
as a dual mode controller whereby the power converter acts
as a buck regulator while the input voltage is above the output.
As the input voltage approaches the output voltage, a gradual
transition to the buck-boost mode occurs. The dual mode approach maintains regulation over a wide range of input voltages, while maintaining the optimal conversion efficiency in
the normal buck mode. The gradual transition between
modes eliminates disturbances at the output during transitions. Figure 2 shows the basic operation of the LM25118
regulator in the buck mode. In buck mode, transistor Q1 is
active and Q2 is disabled. The inductor current ramps in proportion to the Vin - Vout voltage difference when Q1 is active
and ramps down through the re-circulating diode D1 when Q1
is off. The first order buck mode transfer function is VOUT/
VIN = D, where D is the duty cycle of the buck switch, Q1.
Detailed Operating Description
The LM25118 high voltage switching regulator features all of
the functions necessary to implement an efficient high voltage
buck or buck-boost regulator using a minimum of external
components. The regulator switches smoothly from buck to
buck-boost operation as the input voltage approaches the
output voltage, allowing operation with the input greater than
or less than the output voltage. This easy to use regulator
integrates high-side and low-side MOSFET drivers capable
of supplying peak currents of 2 Amps. The regulator control
method is based on current mode control utilizing an emulated current ramp. Peak current mode control provides inherent
line feed-forward, cycle-by-cycle current limiting and ease of
loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit,
allowing reliable processing of very small duty cycles necessary in high input voltage applications. The operating frequency is user programmable from 50 kHz to 500 kHz. An
oscillator synchronization pin allows multiple LM25118 regulators to self synchronize or be synchronized to an external
clock. Fault protection features include current limiting, thermal shutdown and remote shutdown capability. An undervoltage lockout input allows regulator shutdown when the
input voltage is below a user selected threshold, and a low
30165111
FIGURE 2. Buck Mode Operation
Figure 3 shows the basic operation of buck-boost mode. In
buck-boost mode both Q1 and Q2 are active for the same time
interval each cycle. The inductor current ramps up (proportional to VIN) when Q1 and Q2 are active and ramps down
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through the re-circulating diode during the off time. The first
order buck-boost transfer function is VOUT/VIN = D/(1-D),
where D is the duty cycle of Q1 and Q2.
10
LM25118/LM25118Q
30165112
FIGURE 3. Buck-Boost Mode Operation
30165113
FIGURE 4. Mode Dependence on Duty Cycle (VOUT =12V)
Buck-Boost Mode Operation: VIN ≊ VOUT
When VIN decreases relative to VOUT, the duty cycle of the
buck switch will increase to maintain regulation. Once the duty
cycle reaches 75%, the boost switch starts to operate with a
very small duty cycle. As VIN is further decreased, the boost
switch duty cycle increases until it is the same as the buck
switch. As VIN is further decreased below VOUT, the buck
and boost switch operate together with the same duty cycle
and the regulator is in full buck-boost mode. This feature allows the regulator to transition smoothly from buck to buckboost mode. It should be noted that the regulator can be
designed to operate with VIN less than 4 volts, but VIN must
be at least 5 volts during start-up. Figure 5 presents a timing
illustration of the gradual transition from buck to buck-boost
mode when the input voltage ramps downward over a few
switching cycles.
Operation Modes
Figure 4 illustrates how duty cycle affects the operational
mode and is useful for reference in the following discussions.
Initially, only the buck switch is active and the buck duty cycle
increases to maintain output regulation as VIN decreases.
When VIN is approximately equal to 15.5V, the boost switch
begins to operate with a low duty cycle. If VIN continues to
fall, the boost switch duty cycle increases and the buck switch
duty cycle decreases until they become equal at VIN = 13.2V.
Buck Mode Operation: VIN > VOUT
The LM25118 buck-boost regulator operates as a conventional buck regulator with emulated current mode control
while VIN is greater than VOUT and the buck mode duty cycle
is less than 75%. In buck mode, the LO gate drive output to
the boost switch remains low.
11
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LM25118/LM25118Q
30165155
FIGURE 5. Buck (HO) and Boost (LO) Switch Duty Cycle vs. Time,
Illustrating Gradual Mode Change with Decreasing Input Voltage
imum voltage rating of 45V. During line or load transients,
voltage ringing on the VIN line that exceeds the absolute
maximum rating can damage the IC. Both careful PC board
layout and the use of quality bypass capacitors located close
to the VIN and GND pins are essential.
High Voltage Start-Up Regulator
The LM25118 contains a dual mode, high voltage linear regulator that provides the VCC bias supply for the PWM controller and the MOSFET gate driver. The VIN input pin can be
connected directly to input voltages as high as 42V. For input
voltages below 10V, an internal low dropout switch connects
VCC directly to VIN. In this supply range, VCC is approximately equal to VIN. For VIN voltages greater than 10V, the
low dropout switch is disabled and the VCC regulator is enabled to maintain VCC at approximately 7V. A wide operating
range of 4V to 42V (with a startup requirement of at least 5
volts) is achieved through the use of this dual mode regulator.
The output of the VCC regulator is current limited to 35 mA,
typical. Upon power up, the regulator sources current into the
capacitor connected to the VCC pin. When the voltage at the
VCC pin exceeds the VCC under-voltage threshold of 3.7V
and the UVLO input pin voltage is greater than 1.23V, the gate
driver outputs are enabled and a soft-start sequence begins.
The gate driver outputs remain enabled until VCC falls below
3.5V or the voltage at the UVLO pin falls below 1.13V.
In many applications the regulated output voltage or an auxiliary supply voltage can be applied to the VCCX pin to reduce
the IC power dissipation. For output voltages between 4V and
15V, VOUT can be connected directly to VCCX. When the
voltage at the VCCX pin is greater than 3.85V, the internal
VCC regulator is disabled and an internal switch connects
VCCX to VCC, reducing the internal power dissipation.
In high voltage applications extra care should be taken to ensure the VIN pin voltage does not exceed the absolute max-
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30165116
FIGURE 6. VIN and VCC Sequencing
Enable
The LM25118 contains an enable function which provides a
very low input current shutdown mode. If the EN pin is pulled
below 0.5V, the regulator enters shutdown mode, drawing
less than 10 µA from the VIN pin. Raising the EN input above
12
UVLO
An under-voltage lockout pin is provided to disable the regulator when the input is below the desired operating range. If
the UVLO pin is below 1.13V, the regulator enters a standby
mode with the outputs disabled, but with VCC regulator operating. If the UVLO input exceeds 1.23V, the regulator will
resume normal operation. A voltage divider from the input to
ground can be used to set a VIN threshold to disable the regulator in brown-out conditions or for low input faults.
If a current limit fault exists for more than 256 clock cycles,
the regulator will enter a “hiccup” mode of current limiting and
the UVLO pin will be pulled low by an internal switch. This
switch turns off when the UVLO pin approaches ground potential allowing the UVLO pin to rise. A capacitor connected
to the UVLO pin will delay the return to a normal operating
level and thereby set the off-time of the hiccup mode fault
protection. An internal 5 µA pull-up current pulls the UVLO pin
to a high state to ensure normal operation when the VIN
UVLO function is not required and the pin is left floating.
30165118
FIGURE 7. Sync from Multiple Devices
Multiple LM25118 devices can be synchronized together simply by connecting the SYNC pins together. In this configuration all of the devices will be synchronized to the highest
frequency device. The diagram in Figure 7 illustrates the
SYNC input/output features of the LM25118. The internal oscillator circuit drives the SYNC pin with a strong pull-down/
weak pull-up inverter. When the SYNC pin is pulled low, either
by the internal oscillator or an external clock, the ramp cycle
of the oscillator is terminated and forced 400 ns off-time is
initiated before a new oscillator cycle begins. If the SYNC pins
of several LM25118 IC’s are connected together, the IC with
the highest internal clock frequency will pull all the connected
SYNC pins low and terminate the oscillator ramp cycles of the
other IC’s. The LM25118 with the highest programmed clock
frequency will serve as the master and control the switching
frequency of all the devices with lower oscillator frequencies.
Oscillator and Sync Capability
The LM25118 oscillator frequency is set by a single external
resistor connected between the RT pin and the AGND pin.
The RT resistor should be located very close to the device and
connected directly to the pins of the IC. To set a desired oscillator frequency (f), the necessary value for the RT resistor
can be calculated from the following equation:
The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be of higher
30165119
FIGURE 8. Simplified Oscillator and Block Diagram with Sync I/O Circuit
13
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LM25118/LM25118Q
frequency than the free-running frequency set by the RT resistor. A clock circuit with an open drain output is the recommended interface from the external clock to the SYNC pin.
The clock pulse duration should be greater than 15 ns.
3V returns the regulator to normal operation. The EN pin can
be tied directly to the VIN pin if this function is not needed. It
must not be left floating. A 1 MΩ pull-up resistor to VIN can
be used to interface with an open collector or open drain control signal.
LM25118/LM25118Q
trated in Figure 1 are connected between the COMP and FB
pins. This network creates a low frequency pole, a zero, and
a noise reducing high frequency pole. The PWM comparator
compares the emulated current sense signal from the RAMP
generator to the error amplifier output voltage at the COMP
pin. The same error amplifier is used for operation in buck and
buck-boost mode.
Error Amplifier and PWM
Comparator
The internal high gain error amplifier generates an error signal
proportional to the difference between the regulated output
voltage and an internal precision reference (1.23V). The output of the error amplifier is connected to the COMP pin. Loop
compensation components, typically a type II network illus-
30165125
FIGURE 9. Composition of Emulated Current Signal
and CSG pins should be Kelvin connected directly to the
sense resistor. The voltage level across the sense resistor is
sampled and held just prior to the onset of the next conduction
interval of the buck switch. The current sensing and sampleand-hold provide the DC level of the reconstructed current
signal. The sample and hold of the re-circulating diode current
is valid for both buck and buck-boost modes. The positive
slope inductor current ramp is emulated by an external capacitor connected from the RAMP pin to the AGND and an
internal voltage controlled current source. In buck mode, the
ramp current source that emulates the inductor current is a
function of the VIN and VOUT voltages per the following
equation:
Ramp Generator
The ramp signal of a pulse-width modulator with current mode
control is typically derived directly from the buck switch drain
current. This switch current corresponds to the positive slope
portion of the inductor current signal. Using this signal for the
PWM ramp simplifies the control loop transfer function to a
single pole response and provides inherent input voltage
feed-forward compensation. The disadvantage of using the
buck switch current signal for PWM control is the large leading
edge spike due to circuit parasitics. The leading edge spike
must be filtered or blanked to avoid early termination of the
PWM pulse. Also, the current measurement may introduce
significant propagation delays. The filtering, blanking time
and propagation delay limit the minimal achievable pulse
width. In applications where the input voltage may be relatively large in comparison to the output voltage, controlling a
small pulse width is necessary for regulation. The LM25118
utilizes a unique ramp generator which does not actually
measure the buck switch current but instead creates a signal
representing or emulating the inductor current. The emulated
ramp provides signal to the PWM comparator that is free of
leading edge spikes and measurement or filtering delays. The
current reconstruction is comprised of two elements, a sample-and-hold pedestal level and a ramp capacitor which is
charged by a controlled current source. Refer to Figure 9 for
details.
The sample-and-hold pedestal level is derived from a measurement of the re-circulating current through a current sense
resistor in series with the re-circulating diode of the buck regulator stage. A small value current sensing resistor is required
between the re-circulating diode anode and ground. The CS
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In buck-boost mode, the ramp current source is a function of
the input voltage VIN, per the following equation:
Proper selection of the RAMP capacitor (CRAMP) depends upon the value of the output inductor (L) and the current sense
resistor (RS). For proper current emulation, the sample and
hold pedestal value and the ramp amplitude must have the
same relative relationship to the actual inductor current. That
is:
14
In the buck mode the average inductor current is equal to the
output current (Iout). In buck-boost mode the average inductor current is approximately equal to:
Where gm is the ramp generator transconductance (5 µA/V)
and A is the current sense amplifier gain (10V/V). The ramp
capacitor should be located very close to the device and connected directly to the RAMP and AGND pins.
The relationship between the average inductor current and
the pedestal value of the sampled inductor current can cause
instability in certain operating conditions. This instability is
known as sub-harmonic oscillation, which occurs when the
inductor ripple current does not return to its initial value by the
start of the next switching cycle. Sub-harmonic oscillation is
normally characterized by observing alternating wide and narrow pulses at the switch node. Adding a fixed slope voltage
ramp (slope compensation) to the current sense signal prevents this oscillation. The 50µA of offset current provided from
the emulated current source adds enough slope compensation to the ramp signal for output voltages less than or equal
to 12V. For higher output voltages, additional slope compensation may be required. In such applications, the ramp capacitor can be decreased from the nominal calculated value
to increase the ramp slope compensation.
The pedestal current sample is obtained from the current
sense resistor (Rs) connected to the CS and CSG pins. It is
sometimes helpful to adjust the internal current sense amplifier gain (A) to a lower value in order to obtain the higher
current limit threshold. Adding a pair of external resistors RG
in a series with CS and CSG as shown in Figure 10 reduces
the current sense amplifier gain A according to the following
equation:
Consequently, the inductor current in buck-boost mode is
much larger especially when VOUT is large relative to VIN.
The LM25118 provides a current monitoring scheme to protect the circuit from possible over-current conditions. When
set correctly, the emulated current sense signal is proportional to the buck switch current with a scale factor determined by
the current sense resistor. The emulated ramp signal is applied to the current limit comparator. If the peak of the emulated ramp signal exceeds 1.25V when operating in the buck
mode, the PWM cycle is immediately terminated (cycle-bycycle current limiting). In buck-boost mode the current limit
threshold is increased to 2.50V to allow higher peak inductor
current. To further protect the external switches during prolonged overload conditions, an internal counter detects consecutive cycles of current limiting. If the counter detects 256
consecutive current limited PWM cycles, the LM25118 enters
a low power dissipation hiccup mode. In the hiccup mode, the
output drivers are disabled, the UVLO pin is momentarily
pulled low, and the soft-start capacitor is discharged. The
regulator is restarted with a normal soft-start sequence once
the UVLO pin charges back to 1.23V. The hiccup mode offtime can be programmed by an external capacitor connected
from UVLO pin to ground. This hiccup cycle will repeat until
the output overload condition is removed.
In applications with low output inductance and high input voltage, the switch current may overshoot due to the propagation
delay of the current limit comparator and control circuitry. If
an overshoot should occur, the sample-and-hold circuit will
detect the excess re-circulating diode current. If the sampleand-hold pedestal level exceeds the internal current limit
threshold, the buck switch will be disabled and will skip PWM
cycles until the inductor current has decayed below the current limit threshold. This approach prevents current runaway
conditions due to propagation delays or inductor saturation
since the inductor current is forced to decay before the buck
switch is turned on again.
30165123
FIGURE 10. Current Limit and Ramp Circuit
15
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LM25118/LM25118Q
Current Limit
LM25118/LM25118Q
Various sequencing and tracking schemes can be implemented using external circuits that limit or clamp the voltage
level of the SS pin. The SS pin acts as a non-inverting input
to the error amplifier anytime SS voltage is less than the 1.23V
reference. In the event a fault is detected (over-temperature,
VCC under-voltage, hiccup current limit), the soft-start capacitor will be discharged. When the fault condition is no
longer present, a new soft-start sequence will begin.
Maximum Duty Cycle
Each conduction cycle of the buck switch is followed by a
forced minimum off-time of 400ns to allow sufficient time for
the re-circulating diode current to be sampled. This forced offtime limits the maximum duty cycle of the controller. The
actual maximum duty cycle will vary with the operating frequency as follows:
DMAX = 1 - f x 400 x 10-9
HO Output
where f is the oscillator frequency in Hz
The LM25118 contains a high side, high current gate driver
and associated high voltage level shift. This gate driver circuit
works in conjunction with an internal diode and an external
bootstrap capacitor. A 0.1 µF ceramic capacitor, connected
with short traces between the HB pin and HS pin is recommended for most circuit configurations. The size of the bootstrap capacitor depends on the gate charge of the external
FET. During the off time of the buck switch, the HS pin voltage
is approximately -0.5V and the bootstrap capacitor is charged
from VCC through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck switch will be
forced off each cycle for 400ns to ensure that the bootstrap
capacitor is recharged.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 165°C, the
controller is forced into a low power reset state, disabling the
output driver and the bias regulator. This protection is provided to prevent catastrophic failures from accidental device
overheating.
30165126
FIGURE 11. Maximum Duty Cycle vs Frequency
Limiting the maximum duty cycle will limit the maximum boost
ratio (VOUT/VIN) while operating in buck-boost mode. For
example, from Figure 11, at an operating frequency of 500
kHz, DMAX is 80%. Using the buck-boost transfer function.
Application Information
The procedure for calculating the external components is illustrated with the following design example. The designations
used in the design example correlate to the final schematic
shown in Figure 18. The design specifications are:
• VOUT = 12V
• VIN = 4V to 42V
• F = 300 kHz
• Minimum load current (CCM operation) = 600 mA
• Maximum load current = 3A
With D= 80%, solving for VOUT results in,
VOUT = 4 x VIN
With a minimum input voltage of 5 volts, the maximum possible output voltage is 20 volts at f = 500 kHz. The buck-boost
step-up ratio can be increased by reducing the operating frequency which increases the maximum duty cycle.
R7 = RT
RT sets the oscillator switching frequency. Generally speaking, higher operating frequency applications will use smaller
components, but have higher switching losses. An operating
frequency of 300 kHz was selected for this example as a reasonable compromise for both component size and efficiency.
The value of RT can be calculated as follows:
Soft-Start
The soft-start feature allows the regulator to gradually reach
the initial steady state operating point, thus reducing start-up
stresses and surges. The internal 10 µA soft-start current
source gradually charges an external soft-start capacitor connected to the SS pin. The SS pin is connected to the positive
input of the internal error amplifier. The error amplifier controls
the pulse-width modulator such that the FB pin approximately
equals the SS pin as the SS capacitor is charged. Once the
SS pin voltage exceeds the internal 1.23V reference voltage,
the error amp is controlled by the reference instead of the SS
pin. The SS pin voltage is clamped by an internal amplifier at
a level of 150 mV above the FB pin voltage. This feature provides a soft-start controlled recovery in the event a severe
overload pulls the output voltage (and FB pin) well below normal regulation but doesn’t persist for 256 clock cycles.
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therefore, R7 = 18.3 kΩ
16
30165129
FIGURE 12. Inductor Current Waveform
For this example, the two equations yield:
I1(PEAK) = 5.43A
I2(PEAK) = 13.34A
An acceptable current limit setting would be 6.7A for buck
mode since the LM25118 automatically doubles the current
limit threshold in buck-boost mode. The selected inductor
must have a saturation current rating at least as high as the
buck-boost mode cycle-by-cycle current limit threshold, in this
case at least 13.5A. A 10 µH 15 amp inductor was chosen for
this application.
INDUCTOR SELECTION
L1
The inductor value is determined based upon the operating
frequency, load current, ripple current and the input and output voltages. Refer to Figure 12 for details.
To keep the circuit in continuous conduction mode (CCM), the
maximum ripple current IRIPPLE should be less than twice
the minimum load current. For the specified minimum load of
0.6A, the maximum ripple current is 1.2A p-p. Also, the minimum value of L must be calculated both for a buck and buckboost configurations. The final value of inductance will
generally be a compromise between the two modes. It is desirable to have a larger value inductor for buck mode, but the
saturation current rating for the inductor must be large for
buck-boost mode, resulting in a physically large inductor. Additionally, large value inductors present buck-boost mode
loop compensation challenges which will be discussed in error amplifier configuration section. For the design example,
the inductor values in both modes are calculated as:
R13 = RSENSE
To select the current sense resistor value, begin by calculating the value of RSENSE for both modes of operation.
R13(BUCK) = 23 mΩ
For the buck-boost mode, RSENSE is given by:
R13(BUCK-BOOST) = 18.7 mΩ
A RSENSE value of no more than 18.7 mΩ must be used to
guarantee the required maximum output current in the buckboost mode. A value of 15 mΩ was selected for component
tolerances and is a standard value.
R13 = 15 mΩ
Where:
VOUT is the output voltage
VIN1 is the maximum input voltage
f is the switching frequency
IRIPPLE is the selected inductor peak to peak ripple current
(1.2 A selected for this example)
VIN2 is the minimum input voltage
The resulting inductor values are:
L1 = 28 µH, Buck Mode
L1 = 9.8 µH Buck-Boost mode
A 10 µH inductor was selected which is a compromise between these values, while favoring the buck-boost mode. As
will be illustrated in the compensation section below, the inductor value should be as low as possible to move the buckboost right-half-plane zero to a higher frequency. The ripple
current is then rechecked with the selected inductor value using the equations above,
IRIPPLE(BUCK) = 3.36A
IRIPPLE(BUCK-BOOST) = 1.17A
C15 = CRAMP
With the inductor value selected, the value of C3 necessary
for the emulation ramp circuit is:
With the inductance value (L1) selected as 10 µH, the calculated value for CRAMP is 333 pF. A standard value of 330 pF
was selected.
C9 - C12 = OUTPUT CAPACITORS
In buck-boost mode, the output capacitors C9 - C12 must
supply the entire output current during the switch on-time. For
this reason, the output capacitors are chosen for operation in
buck-boost mode, the demands being much less in buck operation. Both bulk capacitance and ESR must be considered
17
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LM25118/LM25118Q
Because the inductor selected is lower than calculated for the
Buck mode, the minimum load current for CCM in buck mode
is 1.68 A at maximum VIN.
With a 10 µH inductor, the worst case peak inductor currents
can be estimated for each case, assuming a 20% inductor
value tolerance.
LM25118/LM25118Q
to guarantee a given output ripple voltage. Buck-boost mode
capacitance can be estimated from:
a worst case 0.6V drop across the diode, the maximum diode
power dissipation can be high. The diode should have a voltage rating of VIN and a current rating of IOUT. A conservative
design would at least double the advertised diode rating since
specifications between manufacturers vary. For the reference
design a 100V, 10A Schottky in a D2PAK package was selected.
ESR requirements can be estimated from:
C1 - C5 = INPUT CAPACITORS
A typical regulator supply voltage has a large source
impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN
pin while supplying most of the switch current during the buck
switch on-time. When the buck switch turns on, the current
into the buck switch steps from zero to the lower peak of the
inductor current waveform, then ramps up to the peak value,
and then drops to the zero at turn-off. The RMS current rating
of the input capacitors depends on which mode of operation
is most critical.
For our example, with a ΔVOUT (output ripple) of 50 mV,
CMIN = 141 µF
ESRMAX = 3.8 mΩ
If hold-up times are a consideration, the values of input/output
capacitors must be increased appropriately. Note that it is
usually advantageous to use multiple capacitors in parallel to
achieve the ESR value required. Also, it is good practice to
put a .1 µF - .47 µF ceramic capacitor directly on the output
pins of the supply to reduce high frequency noise. Ceramic
capacitors have good ESR characteristics, and are a good
choice for input and output capacitors. It should be noted that
the effective capacitance of ceramic capacitors decreases
with dc bias. For larger bulk values of capacitance, a low ESR
electrolytic is usually used. However, electrolytic capacitors
have poor tolerance, especially over temperature, and the
selected value should be selected larger than the calculated
value to allow for temperature variation. Allowing for component tolerances, the following values of Cout were chosen for
this design example:
Two 180 µF Oscon electrolytic capacitors for bulk capacitance
Two 47 µF ceramic capacitors to reduce ESR
Two 0.47 µF ceramic capacitors to reduce spikes at the output .
The RMS current demand on the input capacitor(s) is at the
maximum value when the duty cycle is at 50%.
Checking both modes of operation we find:
IRMS(BUCK) = 1.5 Amps
IRMS(BUCK-BOOST) = 4.7 Amps
Therefore C1 - C5 should be sized to handle 4.7A of ripple
current. Quality ceramic capacitors with a low ESR should be
selected. To allow for capacitor tolerances, four 2.2 µF, 100V
ceramic capacitors will be used. If step input voltage transients are expected near the maximum rating of the LM25118,
a careful evaluation of the ringing and possible spikes at the
device VIN pin should be completed. An additional damping
network or input voltage clamp may be required in these cases.
D1
Reverse recovery currents degrade performance and decrease efficiency. For these reasons, a Schottky diode of
appropriate ratings should be used for D1. The voltage rating
of the boost diode should be equal to VOUT plus some margin. Since D1 only conducts during the buck switch off time in
either mode, the current rating required is:
C20
The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value of C20
should be no smaller than 0.1 µF, and should be a good quality, low ESR, ceramic capacitor. A value of 1 µF was selected
for this design. C20 should be 10 x C8.
If operating without VCCX, then
IDIODE = IOUT x (1-D) Buck Mode
IDIODE = IOUT Buck-Boost Mode
D4
A Schottky type re-circulating diode is required for all
LM25118 applications. The near ideal reverse recovery characteristics and low forward voltage drop are particularly important diode characteristics for high input voltage and low
output voltage applications. The reverse recovery characteristic determines how long the current surge lasts each cycle
when the buck switch is turned on. The reverse recovery
characteristics of Schottky diodes minimize the peak instantaneous power in the buck switch during the turn-on transition.
The reverse breakdown rating of the diode should be selected
for the maximum VIN plus some safety margin.
The forward voltage drop has a significant impact on the conversion efficiency, especially for applications with a low output
voltage. “Rated” current for diodes vary widely from various
manufacturers. For the LM25118 this current is user selectable through the current sense resistor value. Assuming
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fOSC x (QCBuck + Boost) + ILOAD(INTERNAL)
must be less than the VCC current limit.
C8
The bootstrap capacitor between the HB and HS pins supplies the gate current to charge the buck switch gate at turnon. The recommended value of C8 is 0.1 µF to 0.47 µF, and
should be a good quality, low ESR, ceramic capacitor. A value
of 0.1 µF was chosen for this design.
C16 = CSS
The capacitor at the SS pin determines the soft-start time, i.e.
the time for the reference voltage and the output voltage, to
reach the final regulated value. The time is determined from:
18
and assumes a current limit>Iload + ICout
For this application, a C16 value of 0.1 µF was chosen which
corresponds to a soft-start time of about 12 ms.
R8, R9
R8 and R9 set the output voltage level, the ratio of these resistors is calculated from:
For a 12V output, the R8/R9 ratio calculates to 9.76. The resistors should be chosen from standard value resistors and a
good starting point is to select resistors within power ratings
appropriate for the output voltage. Values of 309Ω for R9 and
2.67 kΩ for R8 were selected.
Error Amplifier Configuration
R4, C18, C17
These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current mode control is the ability to close the loop with
only three feedback components, R4, C18 and C17. The
overall loop gain is the product of the modulator gain and the
error amplifier gain. The DC modulator gain of the LM25118
is as follows:
R1, R3, C21
A voltage divider can be connected to the UVLO pin to set a
minimum operating voltage VIN(UVLO) for the regulator. If this
feature is required, the easiest approach to select the divider
resistor values is to choose a value for R1 between 10 kΩ and
100 kΩ, while observing the minimum value of R1 necessary
to allow the UVLO switch to pull the UVLO pin low. This value
is:
R1 ≥ 1000 x VIN(MAX)
R1 ≥ 75k in our example
R3 is then calculated from
The dominant, low frequency pole of the modulator is determined by the load resistance (RLOAD) and output capacitance
(COUT). The corner frequency of this pole is:
Since VIN(MIN) for our example is 5V, set VIN(UVLO) to 4.0V for
some margin in component tolerances and input ripple.
R1 = 75k is chosen since it is a standard value
R3 = 29.332k is calculated from the equation above. 29.4k
was used since it is a standard value.
Capacitor C21 provides filtering for the divider and the off time
of the “hiccup” duty cycle during current limit. The voltage at
the UVLO pin should never exceed 15V when using an external set-point divider. It may be necessary to clamp the
UVLO pin at high input voltages.
Knowing the desired off time during “hiccup” current limit, the
value of C21 is given by:
For this example, RLOAD = 4Ω, DMIN = 0.294, and COUT = 454
µF, therefore:
fP(MOD) = 149 Hz
DC Gain(MOD) =3.63 = 11.2 dB
Additionally, there is a right-half plane (RHP) zero associated
with the modulator. The frequency of the RHP zero is:
fRHPzero = 7.8 kHz
The output capacitor ESR produces a zero given by:
Notice that tOFF varies with VIN
In this example, C21 was chosen to be 0.1 µF. This will set
the tOFF time to 956 µs with VIN = 12V.
ESRZERO = 70 kHz
The RHP zero complicates compensation. The best design
approach is to reduce the loop gain to cross zero at about
30% of the calculated RHP zero frequency. The Type ll error
amplifier compensation provided by R4, C18 and C17 places
one pole at the origin for high DC gain. The 2nd pole should
R2
A 1M pull-up resistor connected from the EN pin to the VIN
pin is sufficient to keep enable in a high state if on-off control
is not used.
19
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LM25118/LM25118Q
SNUBBER
A snubber network across the buck re-circulating diode reduces ringing and spikes at the switching node. Excessive
ringing and spikes can cause erratic operation and increase
noise at the regulator output. In the limit, spikes beyond the
maximum voltage rating of the LM25118 or the re-circulating
diode can damage these devices. Selecting the values for the
snubber is best accomplished through empirical methods.
First, make sure the lead lengths for the snubber connections
are very short. Start with a resistor value between 5 and 20
Ohms. Increasing the value of the snubber capacitor results
in more damping, however the snubber losses increase. Select a minimum value of the capacitor that provides adequate
clamping of the diode waveform at maximum load. A snubber
may be required for the boost diode as well. The same empirical procedure applies. Snubbers were not necessary in
this example.
LM25118/LM25118Q
half-plane zero frequency). The error amplifier zero (fz)
should be selected at a frequency near that of the modulator
pole and much less than the target crossover frequency. This
constrains the product of R4 and C18 for a desired compensation network zero to be less than 2 kHz. Increasing R4,
while proportionally decreasing C18 increases the error amp
gain. Conversely, decreasing R4 while proportionally increasing C18 decreases the error amp gain. For the design example C18 was selected for 4.7 nF and R4 was selected to be
10 kΩ. These values set the compensation network zero at
149 Hz. The overall loop gain can be predicted as the sum (in
dB) of the modulator gain and the error amp gain.
If a network analyzer is available, the modulator gain can be
measured and the error amplifier gain can be configured for
the desired loop transfer function. If a network analyzer is not
available, the error amplifier compensation components can
be designed with the guidelines given. Step load transient
tests can be performed to verify acceptable performance. The
step load goal is minimal overshoot with a damped response.
be located close to the RHP zero. The error amplifier zero
(see below) should be placed near the dominate modulator
pole. This is a good starting point for compensation.
Components R4 and C18 configure the error amplifier as a
Type II configuration which has a DC pole and a zero at
C17 introduces an additional pole used to cancel high frequency switching noise. The error amplifier zero cancels the
modulator pole leaving a single pose response at the
crossover frequency of the loop gain if the crossover frequency is much lower than the right half plane zero frequency. A
single pole response at the crossover frequency yields a very
stable loop with 90 degrees of phase margin.
For the design example, a target loop bandwidth (crossover
frequency) of 2.0 kHz was selected (about 30% of the right-
30165148
FIGURE 13. Modulator Gain and Phase
30165149
FIGURE 14. Error Amplifier Gain and Phase
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20
LM25118/LM25118Q
30165150
FIGURE 15. Overall Loop Gain and Phase
The plots shown in Figures 13, 14 and 15 illustrate the gain
and phase diagrams of the design example. The overall bandwidth is lower in a buck-boost application due the compensation challenges associated with the right-half-plane zero.
For a pure buck application, the bandwidth could be much
higher. The LM5116 datasheet is a good reference for compensation design of a pure buck mode regulator.
translates into high power dissipation in the VCC regulator.
There are several techniques that can significantly reduce this
bias regulator power dissipation. Figures 16 and 17 depict two
methods to bias the IC, one from the output voltage and one
from a separate bias supply. In the first case, the internal VCC
regulator is used to initially bias the VCC pin. After the output
voltage is established, the VCC pin bias current is supplied
through the VCCX pin, which effectively disables the internal
VCC regulator. Any voltage greater than 4.0V can supply
VCC bias through the VCCX pin. However, the voltage applied to the VCCX pin should never exceed 15V. The voltage
supplied through VCCX must be large enough to drive the
switching MOSFETs into full saturation.
Bias Power Dissipation Reduction
Buck or Buck-boost regulators operating with high input voltage can dissipate an appreciable amount of power while
supplying the required bias current of the IC. The VCC regulator must step-down the input voltage VIN to a nominal VCC
level of 7V. The large voltage drop across the VCC regulator
30165151
FIGURE 16. VCC Bias from VOUT 4V < VOUT < 15V
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LM25118/LM25118Q
30165152
FIGURE 17. VCC Bias with Additional Bias Supply
easiest way to determine the power dissipated in the MOSFETs is to measure the total conversion losses (PIN - POUT),
then subtract the power losses in the Schottky diodes, output
inductor and any snubber resistors. An approximation for the
re-circulating Schottky diode loss is:
P = (1-D) x IOUT x VFWD.
The boost diode loss is:
P = IOUT x VFWD.
If a snubber is used, the power loss can be estimated with an
oscilloscope by observation of the resistor voltage drop at
both turn-on and turn-off transitions. The LM25118 package
has an exposed thermal pad to aid power dissipation. Selecting diodes with exposed pads will aid the power dissipation of
the diodes as well. When selecting the MOSFETs, pay careful
attention to RDS(ON) at high temperature. Also, selecting MOSFETs with low gate charge will result in lower switching losses.
See Application Notes AN-1520 and AN-2020 for thermal
management techniques for use with surface mount components.
PCB Layout and Thermal
Considerations
In a buck-boost regulator, there are two loops where currents
are switched very fast. The first loop starts from the input capacitors, and then to the buck switch, the inductor, the boost
switch then back to the input capacitor. The second loop starts
from the inductor, and then to the output diode, the output
capacitor, the re-circulating diode, and back to the inductor.
Minimizing the PC board area of these two loops reduces the
stray inductance and minimizes noise and the possibility of
erratic operation. A ground plane in the PC board is recommended as a means to connect the input filter capacitors to
the output filter capacitors and the PGND pins of the
LM25118. Connect all of the low current ground connections
(CSS, RT, CRAMP) directly to the regulator AGND pin. Connect
the AGND and PGND pins together through topside copper
area covering the entire underside of the device. Place several vias in this underside copper area to the ground plane of
the input capacitors.
The highest power dissipating components are the two power
MOSFETs, the re-circulating diode, and the output diode. The
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FIGURE 18. 12V, 3A Typical Application Schematic
30165153
LM25118/LM25118Q
23
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LM25118/LM25118Q
Physical Dimensions inches (millimeters) unless otherwise noted
TSSOP-20EP Outline Drawing
NS Package Number MXA20A
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24
LM25118/LM25118Q
Notes
25
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LM25118/LM25118Q Wide Voltage Range Buck-Boost Controller
Notes
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www.ti.com/audio
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amplifier.ti.com
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www.ti.com/computers
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dataconverter.ti.com
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www.dlp.com
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www.ti.com/energy
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dsp.ti.com
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logic.ti.com
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power.ti.com
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Microcontrollers
microcontroller.ti.com
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www.ti-rfid.com
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www.ti.com/omap
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www.ti.com/wirelessconnectivity
TI E2E Community Home Page
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e2e.ti.com
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