TI BQ24087DRCT 750 ma single-chip li-ion/li-pol charge management ic Datasheet

bq24085, bq24086
bq24087, bq24088
www.ti.com............................................................................................................................................. SLUS784D – DECEMBER 2007 – REVISED AUGUST 2009
750 mA SINGLE-CHIP Li-Ion/Li-Pol CHARGE MANAGEMENT IC
WITH THERMAL REGULATION
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Ideal for Low-Dropout Designs for Single-Cell
Li-Ion or Li-Pol Packs in Space Limited
Applications
Integrated Power FET and Current Sensor for
up to 750-mA Charge Applications
Reverse Leakage Protection Prevents Battery
Drainage
±0.5% Voltage Regulation Accuracy
Thermal Regulation Maximizes Charge Rate
Charge Termination by Minimum Current and
Time
Precharge Conditioning With Safety Timer
Status Outputs for LED or System Interface
Indicate Charge, Fault, and Power Good
Outputs
Short-Circuit and Thermal Protection
Automatic Sleep Mode for Low Power
Consumption
Small 3×3 mm MLP Package
Selectable Battery Insertion and Battery
Absent Detection
Input Overvoltage Protection
– 6.5 V and 10.5 V Options
The bq24085/6/7/8 series are highly integrated Li-Ion
and Li-Pol linear chargers, targeted at space-limited
portable applications. The bq24085/6/7/8 series offers
a variety of safety features and functional options,
while still implementing a complete charging system
in a small package. The battery is charged in three
phases: conditioning, constant or thermally regulated
current, and constant voltage. Charge is terminated
based
on
minimum
current.
An
internal
programmable charge timer provides a backup safety
feature for charge termination and is dynamically
adjusted during the thermal regulation phase. The
bq24085/6/7/8 automatically restarts the charge if the
battery voltage falls below an internal threshold; sleep
mode is set when the external input supply is
removed. Multiple versions of this device family
enable easy design of the bq24085/6/7/8 in cradle
chargers or in the end equipment, while using low
cost or high-end AC adapters.
Pin Out
(Top View)
bq24085
IN
1
10
OUT
TMR
2
9
BAT
APPLICATIONS
STAT1
3
8
CE
•
•
STAT2
4
7
PG
VSS
5
6
ISET
PDA, MP3 Players, Digital Cameras
Internet Appliances and Handheld Devices
TYPICAL APPLICATION CIRCUIT
Li-Ion or Li-Pol
Battery Pack
bq24085
Input Power
1
RTMR
C3
4.7 mF
R1
1.5 kW
R2
1.5 kW
2
IN
TMR
49.9 kW
RED
GREEN
3
4
5
OUT
BAT
STAT 1
CE
STAT 2
PG
Vss
ISET
10
9
Pack+
C2
+
1 mF
Pack-
8
7
6
RSET
1.13 kW
Charge Enable
and Power Good
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
bq24085, bq24086
bq24087, bq24088
SLUS784D – DECEMBER 2007 – REVISED AUGUST 2009............................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
Charge Input Over
Voltage
Voltage
Termination
Enable
Safety
Timer
Enable
Power
Good
Status
IC
Enable
Pack
Temp
Pack Voltage
Detection
(Absent)
Devices (1)
(2) (3)
4.2 V
6.5 V
TMR pin
TMR pin
PG pin
No
TS pin
With timer
enabled
bq24086DRCR
4.2 V
6.5 V
TMR pin
TMR pin
PG pin
CE pin
No
With timer
enabled
bq24085DRCR
4.2 V
6.5 V
TE pin
TMR pin
No
CE pin
No
With termination
enabled
bq24087DRCR
4.2 V
10.5 V
TMR pin
TMR pin
PG pin
No
TS pin
With timer
enabled
bq24088DRCR
(1)
(2)
(3)
Marking
CDW
bq24086DRCT
CDV
bq24085DRCT
CDX
bq24087DRCT
CHE
bq24088DRCT
The bq24085/6/7/8 are only available taped and reeled. Add suffix R to the part number for quantities of 3,000 devices per reel (e.g.,
bq24085DRCR). Add suffix T to the part number for quantities of 250 devices per reel (e.g., bq24085/6/7DRCT).
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
bq24085/6/7/8
–0.3 V to 20 V (2)
Supply voltage (IN with respect to Vss)
Input voltage on IN, STATx, PG, TS, CE, TMR (all with respect to Vss)
–0.3 V to V(IN)
Input voltage on OUT, BAT, ISET (all with respect to Vss)
–0.3 V to 7 V
Output sink current (STATx) + PG
15 mA
Output current (OUT pin)
2A
TA
Operating free-air temperature range
–40°C to 155°C
Tstg
Storage temperature range
–65°C to 150°C
TJ
Junction temperature range
–40°C to 150°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
The bq24085/6/7/8 family can withstand up to 18 V maximum continuously, 20 V for maximum of 2000hrs and 26 V for a maximum for
87 hours.
RECOMMENDED OPERATING CONDITIONS
MIN
V(IN)
Supply voltage range
Battery absent detection not functional
V(IN)
Supply voltage range
Battery absent detection functional
TJ
Junction temperature
R(TMR)
33K ≤ R(TMR) ≤ 100K
MAX
UNIT
3.5
TYP
4.35
V
4.35
6.5
V
0
125
°C
DISSIPATION RATINGS (1)
(1)
2
PACKAGE
θJC (°C/W)
θJA (°C/W)
10-pin DRC
3.21
46.87
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a
copper pad on the board. This is connected to the ground plane by a 2×3 via matrix.
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24085, bq24086 bq24087, bq24088
bq24085, bq24086
bq24087, bq24088
www.ti.com............................................................................................................................................. SLUS784D – DECEMBER 2007 – REVISED AUGUST 2009
ELECTRICAL CHARACTERISTICS
over recommended operating range, TJ = 0 –125°C range, See the Application Circuits section, typical values at TJ = 25°C
(unless otherwise noted), RTMR = 49.9KΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER DOWN THRESHOLD – UNDERVOLTAGE LOCKOUT
UVLO
Power down threshold
V(IN) = 0 V, increase V(OUT): 0 → 3 V OR
V(OUT) = 0 V, increase V(IN): 0 → 3 V,
CE = LO (1)
tDGL(PG)
Deglitch time on power good
V(IN) = 0 V → 5 V in 1 µs to
PG:HI → LO
1.5
3
2
V
ms
INPUT POWER DETECTION, CE = HI or LOW, V(IN) > 3.5 V
VIN(DT)
Input power detection threshold
V(IN) detected at [V(IN) – V(OUT)] > VIN(DT)
VHYS(INDT)
Input power detection hysteresis
Input power not detected at
[V(IN) – V(OUT)] < [VIN(DT) – VHYS(INDT)]
tDGL(NOIN)
Delay time, input power not detected
status (1)
PG: LO →HI after tDGL(NOIN)
tDLY(CHGOFF)
Charger off delay
Charger turned off after tDLY(CHGOFF), Measured
from PG: LO → HI; Timer reset after tDLY(CHGOFF)
130
30
mV
mV
10
25
µs
ms
INPUT OVERVOLTAGE PROTECTION
bq24088
10.2
10.5
11.7
6.2
6.5
7
V(OVP)
Input overvoltage detection threshold
V(IN) increasing
VHYS(OVP)
Input overvoltage hysteresis
V(IN) decreasing
tDGL(OVDET)
Input overvoltage detection delay
CE = HI or LO, Measured from V(IN) > V(OVP) to
PG: LO → HI; VIN increasing
100
µs
tDGL(OVNDET)
Input overvoltage not detected delay (1)
CE = HI or LO, Measured from V(IN) < V(OVP)
to PG: HI → LO; V(IN) decreasing
100
µs
bq24085/6/7
bq24088
0.5
bq24085/6/7
0.2
V
V
QUIESCENT CURRENT
V(IN) = 6 V
100
V(IN) = 16.5 V
350
ICC(CHGOFF)
IN pin quiescent current, charger off
Input power detected,
CE = HI
ICC(CHGON)
IN pin quiescent current, charger on
Input power detected, CE = LO, VBAT = 4.5 V
IBAT(DONE)
IBAT(CHGOFF)
200
µA
4
6
mA
Battery leakage current after termination Input power detected, charge terminated,
into IC
CE = LO
1
5
µA
Battery leakage current into IC, charger
off
1
5
µA
Input power detected, CE = HI OR
input power not detected, CE = LO
TS PIN COMPARATOR
V(TS1)
Lower voltage temperature threshold
Hot detected at V(TS) < V(TS1); NTC thermistor
29
30
31 %V(IN)
V(TS2)
Upper voltage temperature threshold
Cold detected at V(TS) > V(TS2); NTC thermistor
60
61
62 %V(IN)
VHYS(TS)
Hysteresis
Temp OK at V(TS) > [ V(TS1) + VHYS(TS) ] OR
V(TS) < [ V(TS2) – VHYS(TS) ]
2
%V(IN)
VIL
Input (low) voltage
V(/CE)
0
VIH
Input (high) voltage
V(/CE)
2
CE INPUT
1
V
V
STAT1, STAT2 AND PG OUTPUTS , V(IN) ≥ VO(REG) + V(DO-MAX)
VOL
Output (low) saturation voltage
Iout = 1 mA (sink)
200
mV
THERMAL SHUTDOWN
T(SHUT)
Temperature trip
Junction temperature, temp rising
T(SHUTHYS)
Thermal hysteresis
Junction temperature
(1)
155
°C
20
°C
Specified by design, not production tested.
Copyright © 2007–2009, Texas Instruments Incorporated
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bq24085, bq24086
bq24087, bq24088
SLUS784D – DECEMBER 2007 – REVISED AUGUST 2009............................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating, TJ = 0°C–125°C range, See the Application Circuits section, typical values at TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REGULATION, V(IN) ≥ VO(REG) + V(DO-MAX), I(TERM) < I(OUT) < IO(OUT), CHARGER ENABLED, NO FAULT CONDITIONS
DETECTED
VO(REG)
Output voltage
4.20
VO(TOL)
Voltage regulation accuracy
V(DO)
Dropout voltage, V(IN) – V(OUT)
TA = 25°C
–0.5%
V
0.5%
–1%
1%
I(OUT) = 750 mA
600
mV
750
mA
V
CURRENT REGULATION , V(IN) > V(OUT) > V(DO-MAX), CHARGER ENABLED, NO FAULT CONDITIONS DETECTED
IO(OUT)
Output current range
V(BAT) > V(LOWV), IO(OUT) = I(OUT) = K(SET) ×
V(SET)/R(SET)
50
V(SET)
Output current set voltage
V(ISET) = V(SET), V(LOWV) < V(BAT) ≤ VO(REG)
2.45
2.5
2.55
K(SET)
Output current set factor
100 mA ≤ IO(OUT) ≤ 750 mA
175
182
190
180
215
250
RISET
External resistor range
mA kW
Volts
10 mA ≤ IO(OUT) < 100 mA
Resistor connected to ISET pin
0.6
10
kΩ
VOLTAGE AND CURRENT REGULATION TIMING, V(IN) > V(OUT) + V(DO-MAX), CHARGER ENABLED, NO FAULT CONDITIONS
DETECTED, RTMR = 50K or V(TMR) = OPEN; Thermal regulation loop not active
tPWRUP(CHG)
Input power detection to full
charge current time delay
Measured from PG:HI → LO to I(OUT) > 100 mA,
CE = LO, IO(OUT) = 750 mA, V(BAT) = 3.5 V
25
ms
tPWRUP(EN)
Charge enable to full charge
current delay
Measured from CE:HI → LO to I(OUT) >100 mA,
IO(OUT) = 750 mA, V(BAT)= 3.5 V, V(IN) = 4.5 V, Input
power detected
25
ms
tPWRUP(LDO)
Input power detection to voltage
regulation delay, LDO mode set,
no battery or load connected
Measured from PG:HI → LO to V(OUT) > 90% of
charge voltage regulation;
V(TMR) = OPEN, LDO mode set, no battery and no
load at OUT pin, CE = LO
25
ms
PRECHARGE AND OUTPUT SHORT-CIRCUIT CURRENT REGULATION, V(IN)–V(OUT) > V(DO-MAX) , V(IN) ≥ 4.5V, CHARGER
ENABLED, NO FAULT CONDITIONS DETECTED, RTMR = 50K or V(TMR)=OPEN; Thermal regulation loop not active
V(LOWV)
Precharge to fast-charge
transition threshold
V(BAT) increasing
V(SC)
Precharge to short-circuit
transition threshold
V(BAT) decreasing
V(SCIND)
Short-circuit indication
V(BAT) decreasing
IO(PRECHG)
Precharge current range
V(SC) < VI(BAT) < V(LOWV), t < t(PRECHG)
IO(PRECHG) = K(SET) × V(PRECHG)/R(ISET)
V(PRECHG)
Precharge set voltage
V(ISET) = V(PRECHG), V(SC) < VI(BAT) < V(LOWV),
t < t(PRECHG)
IO(SHORT)
Output shorted regulation current
VSS ≤ V(BAT) ≤ V(SCI),
IO(SHORT) = I(OUT), V(BAT)=
VSS, Internal pullup resistor,
TJ = 25°C
2.8
2.95
3.15
1
1.6
1.8
5
VPOR < VIN < 6.0 V
V
2
75
mA
mV
225
250
280
7
15
24
6.0 V < VIN < VOVP
V
mA
15
TEMPERATURE REGULATION (Thermal regulation™), CHARGER ENABLED, NO FAULT CONDITIONS DETECTED
TJ(REG)
Temperature regulation limit
V(IN) = 5.5 V, V(BAT) = 3.2 V, Fast charge current
set to 1A
I(MIN_TJ(REG))
Minimum current in thermal
regulation
V(LOWV) < V(BAT) < VO(REG),
0.7kΩ < R(ISET) < 1.18kΩ
4
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101
112
125
°C
105
125
mA
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24085, bq24086 bq24087, bq24088
bq24085, bq24086
bq24087, bq24088
www.ti.com............................................................................................................................................. SLUS784D – DECEMBER 2007 – REVISED AUGUST 2009
ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating, TJ = 0–125°C range, See the Application Circuits section, typical values at TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGE TERMINATION DETECTION, VO(REG) = 4.2 V, CHARGER ENABLED, NO FAULT CONDITIONS DETECTED, Thermal
regulation LOOP NOT ACTIVE, RTMR = 50K or TMR pin OPEN
I(TERM)
Termination detection current
range
V(BAT) > V(RCH), I(TERM) = K(SET) × V(TERM)/R(ISET)
V(TERM)
Charge termination detection
set voltage (1)
V(BAT) > V(RCH)
tDGL(TERM)
Deglitch time, termination
detected
V(ISET) decreasing
5
225
250
75
mA
275
mV
50
ms
BATTERY RECHARGE THRESHOLD
V(RCH)
Recharge threshold detection
[VO(REG)–V(BAT) ] > V(RCH)
tDGL(RCH)
Deglitch time, recharge
detection
V(BAT) decreasing
75
100
135
350
mV
ms
TIMERS, CE = LO, CHARGER ENABLED, NO FAULT CONDITIONS DETECTED, V(TMR) < 3 V, TIMERS ENABLED
t(CHG)
Charge safety timer range
t(CHG) = K(CHG) × RTMR ; thermal loop not active
K(CHG)
Charge safety timer constant
V(BAT) > V(LOWV)
0.08
t(PCHG)
Pre-charge safety timer range
t(PCHG) = K(PCHG) × t(CHG) ; Thermal regulation loop
not active
1080
K(PCHG)
Pre-charge safety timer
constant
V(BAT) < V(LOWV)
0.08
0.1
0.12
Charge timer and termination
enable threshold
Charge timer AND termination
disabled at: V(TMR) >
bq24085/86/88
VTMR(OFF)
2.5
3
3.5
V
Charge timer enable threshold
Charge timer disabled at:
V(TMR) > VTMR(OFF)
1
2
3.2
mA
VTMR(OFF)
3
0.1
10
hours
0.12
hr/kΩ
3600
sec
bq24087
BATTERY DETECTION THRESHOLDS
IDET(DOWN)
Battery detection current (sink)
2 V < V(BAT) < VO(REG)
IDET(UP)
Battery detection current
(source)
2 V < V(BAT) < VO(REG)
t(DETECT)
Battery detection time
2 V < V(BAT) < VO(REG), Thermal regulation loop not
active; RTMR = 50 kΩ, IDET(down) or IDET (UP)
125
V(OUT) < V(RCH)
0.8
IO(PRECHG)
ms
TIMER FAULT RECOVERY
I(FAULT)
Fault Current (source)
1.1
mA
OUTPUT CURRENT SAFETY LIMIT, V(IN) ≥ 4.5 V, CHARGER ENABLED, ISET SHORTED TO GND
I(SETSC)
(1)
Charge overcurrent safety
V(ISET) = VSS
1.5
A
The voltage on the ISET pin is compared to the V(TERM) voltage to determine when the termination should occur.
Copyright © 2007–2009, Texas Instruments Incorporated
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SLUS784D – DECEMBER 2007 – REVISED AUGUST 2009............................................................................................................................................. www.ti.com
DEVICE INFORMATION
PIN ASSIGNMENT
VSS
STAT 2
STAT 1
TMR
IN
VSS
STAT 2
STAT 1
TMR
IN
VSS
STAT 2
STAT 1
TMR
IN
5
4
3
2
1
5
4
3
2
1
5
4
3
2
1
bq24086 DRC
bq24088 DRC
(TOP VIEW)
bq24085 DRC
(TOP VIEW)
bq24087 DRC
(TOP VIEW)
6
7
8
9
10
6
7
8
9
10
6
7
8
9
10
ISET
PG
TS
BAT
OUT
ISET
PG
CE
BAT
OUT
ISET
CE
TE
BAT
OUT
TERMINAL FUNCTIONS, REQUIRED COMPONENTS
TERMINAL NO.
NAME
I/O
DESCRIPTION AND REQUIRED COMPONENTS
bq24086/8
bq24085
bq24087
IN
1
1
1
I
Charge Input Voltage and internal supply. Connect a 1- µF (minimum)
capacitor from IN to VSS. CIN ≥ COUT
TMR
2
2
2
I
Safety Timer Program Input, timer disabled if floating. Connect a resistor to
VSS pin to program safety timer timeout value
STAT1
3
3
3
O
Charge Status Output 1 (open-collector, seeTable 3)
STAT2
4
4
4
O
Charge Status Output 2 (open-collector, see Table 3)
VSS
5
5
5
I
Ground
ISET
6
6
6
O
Charge current set point, resistor connected from ISET to VSS sets charge
current value. Connect a 0.1-µF capacitor from BAT to ISET for I(OUT) < 200
mA.
PG
7
7
—
O
Power Good status output (open-collector), active low
CE
—
8
7
I
Charge enable Input. CE = LO enables charger. CE = HI disables charger.
TE
—
—
8
I
Termination enable Input. TE = LO enables termination detection and battery
absent detection. TE = HI disables termination detection and battery absent
detection.
TS
8
—
—
I
Temperature Sense Input, connect to battery pack thermistor. Connect an
external resistive divider to program temperature thresholds.
BAT
9
9
9
I
Battery Voltage Sense Input. Connect to the battery positive terminal.
Connect a 390-Ω resistor from BAT to OUT for I(OUT) < 200 mA..
OUT
10
10
10
O
Charge current output. Connect to the battery positive terminal. Connect a 1µF (minimum) capacitor from OUT to VSS.
Exposed
Thermal
Pad
6
Pad
Pad
Pad
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There is an internal electrical connection between the exposed thermal pad
and Vss pin of the IC. The exposed thermal pad must be connected to the
same potential as the VSS pin on the printed circuit board. Do not use the
thermal pad as the primary ground input for the IC. VSS pin must be
connected to ground at all times.
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24085, bq24086 bq24087, bq24088
bq24085, bq24086
bq24087, bq24088
www.ti.com............................................................................................................................................. SLUS784D – DECEMBER 2007 – REVISED AUGUST 2009
TYPICAL OPERATING CHARACTERISTICS
Measured using the typical application circuit shown previously.
THERMAL REGULATION
DTC OPERATION
25
450
Safety Timer Duration
Charge Current - mA
400
350
300
250
200
150
100
20
15
10
5
50
0
0
0
80
40
120
0
160
Actual Charge Current
due to thermal regulation - mA
Figure 1.
Figure 2.
800
7
700
600
VIN
6
5
500
4
400
IBAT
3
300
200
2
PG DEGLITCH TIME
Voltage - V
8
Charge Current - mA
INPUT OVP RECOVERY TRANSIENTS
Voltage - V
50 100 150 200 250 300 350 400 450
Die Temperature (oC)
VIN
PG
VPG
100
1
0
0
0
5
10 15
20 25 30 35
40 45 50
t - Time - ms
Figure 3.
Figure 4.
PRE-CHARGE CURRENT
vs
BATTERY VOLTAGE
FAST-CHARGE CURRENT
vs
BATTERY VOLTAGE
40.5
405
40.45
404
Charge Current - mA
Charge Current - mA
t - Time - mS
40.4
40.35
40.3
85°C
40.25
25°C
40.2
40.15
0°C
403
402
0°C
400
399
85°C
398
40.1
397
40.05
396
40
2
25°C
401
395
2.20
2.40
2.60
2.80
3
3
3.20
Figure 5.
Copyright © 2007–2009, Texas Instruments Incorporated
3.40
3.60
3.80
4
Battery Voltage - V
Battery Voltage - V
Figure 6.
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SLUS784D – DECEMBER 2007 – REVISED AUGUST 2009............................................................................................................................................. www.ti.com
TYPICAL OPERATING CHARACTERISTICS (continued)
Measured using the typical application circuit shown previously.
KSET LINEARITY
vs
FAST-CHARGE CURRENT
KSET LINEARITY
vs
PRE-CHARGE CURRENT
230
195
V(BAT) = 2.5 V
220
KSET - mA/mA
KSET - mA/mA
V(BAT) = 4.1 V
190
185
V(BAT) = 3.5 V
210
200
190
180
180
0
200
400
600
800
0
Fast-Charge Current - mA
20
40
60
80
Pre-Charge Current - mA
Figure 7.
Figure 8.
DROPOUT VOLTAGE
vs
TEMPERATURE
V(DO) - Droput Voltage - V
600
IO = 750 mA
400
200
0
0
50
100
150
TA - Temperature - °C
Figure 9.
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FUNCTIONAL DESCRIPTION
The charge current is programmable using external components (RISET resistor). The charge process starts when
an external input power is connected to the system, the charger is enabled by CE = LO and the battery voltage is
below the recharge threshold, V(BAT) < V(RCH). When the charge cycle starts a safety timer is activated, if the
safety timer function is enabled. The safety timer timeout value is set by an external resistor connected to TMR
pin.
When the charger is enabled two control loops modulate the battery switch drain to source impedance to limit the
BAT pin current to the programmed charge current value (charge current loop) or to regulate the BAT pin voltage
to the programmed charge voltage value (charge voltage loop). If V(BAT) < V(LOWV) (3 V typical) the BAT pin
current is internally set to 10% of the programmed charge current value.
A typical charge profile is shown below, for an operation condition that does not cause the IC junction
temperature to exceed TJ(REG), (112°C typical).
VO(REG)
PreConditioning
Phase
Voltage Regulation and
Charge Termination
Phase
Current
Regulation
Phase
DONE
IO(OUT)
FAST-CHARGE
CURRENT
Battery Current,
I(BAT)
Battery Voltage,
V(BAT)
v(LOWV)
Charge
Complete
Status,
Charger
Off
IO(PRECHG), I(TERM)
PRE-CHARGE
CURRENT AND
TERMINATION
THRESHOLD
T(PRECHG)
T(CHG)
DONE
Figure 10. Charging Profile With TJ(REG)
If the operating conditions cause the IC junction temperature to exceed TJ(REG), the charge cycle is modified, with
the activation of the integrated thermal control loop. The thermal control loop is activated when an internal
voltage reference, which is inversely proportional to the IC junction temperature, is lower than a fixed,
temperature stable internal voltage. The thermal loop overrides the other charger control loops and reduces the
charge current until the IC junction temperature returns to TJ(REG), effectively regulating the IC junction
temperature.
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IN
VREF
VTJ
Thermal
Loop
BATTERY
SWITCH
I(BAT)
OUT
I(BAT) / K(SET)
ISET
V(BAT)
VO(REG)
System Voltage
Regulation Loop
BAT
Figure 11. Thermal Regulation Circuit
A modified charge cycle, with the thermal loop active, is shown in Figure 12.
VO(REG)
PreConditioning
Phase
Thermal
Regulation
Phase
Current
Regulation
Phase
Voltage Regulation and
Charge Termination
Phase
DONE
IO(OUT)
Battery Current,
I(BAT)
FAST-CHARGE
CURRENT
PRE-CHARGE
CURRENT AND
TERMINATION
THRESHOLD
Battery
Voltage,
V(BAT)
Charge
Complete
Status,
Charger
Off
VO(LOWV)
IO(PRECHG),I(TERM)
T(THREG)
temperature , Tj
T(PRECHG)
T(CHG)
DONE
Figure 12. Charge Profile, Thermal Loop Active
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FUNCTIONAL BLOCK DIAGRAM
BACKGATE BIAS
V(IN)
I(OUT)
OUT
IN
V(OUT)
PRE_CHARGE
IOUT) / K(SET)
ISET
VO(REG)
V(ISET)
I(DETECT)
V(IN)
V(SET)
V(PRECHG)
I(FAULT )
TJ
BATTERY ABSENT DETECTION
AND SHORT RECOVERY
T J(REG)
CHG ENABLE
V(IN)
Dynamically
Controlled
Oscillator
V(SET) , V(PRECHG)
+
- V
OC
TDGL(CHOVC)
Deglitch
TMR
+
V(IN)
VTMR(OFF)
TDGL(INDT)
Deglitch
Over_current
+
+
V(IN)
-
V(OUT)+VIN(DT )
Input Power
Detected
TS
Timer
Fault
+
V(IN)
Timer
V(IN)
Disable
+
V(OVP)
BAT
+
V (RCH)
-
TDGL(OVP)
Deglitch
Input Over-Voltage
TDGL(RCH)
Deglitch
Recharge
Precharge
+
V(LOW)
V (TERM )
V(ISET)
POR
Suspend
Thermal
Shutdown
REFERENCE
AND
BIAS
Internal
Voltage
References
CE
CHARGE
CONTROL,
TIMER and
DISPLAY LOGIC
PG
+
-
STAT1
TDGL(TERM)
Deglitch
Terminate
STAT2
VSS
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APPLICATION CIRCUITS
The typical application diagrams shown here are configured for 400 mA fast charge current, 40 mA pre-charge
current, 5 hour safety timer and 30 min pre-charge timer.
Li-Ion or Li-Pol
Battery Pack
bq24086/8
Input Power
1
RTMR
C3
4.7 mF
R1
R2
1.5 kW 1.5 kW
2
OUT 10
IN
TMR
BAT 9
STAT 1
TS 8
STAT 2
PG
49.9 kW
RED
3
GREEN
4
5
Pack+
+
C2
R8
2.2 mF
RT1
10 kW
7
ISET 6
Vss
R ISET
1.13 kW
Pack-
RT2
33.2 kW
Power
Good
Li-Ion or Li-Pol
Battery Pack
bq24085
Input Power
1
RTMR
C3
4.7 mF
R1
1.5 kW
R2
1.5 kW
2
IN
OUT
TMR
49.9 kW
3
RED
GREEN
4
5
BAT
STAT 1
CE
STAT 2
PG
Vss
TEMP
ISET
10
Pack+
+
C2
9
1 mF
Pack-
8
7
6
RSET
1.13 kW
Charge Enable
and Power Good
Li-Ion or Li-Pol
Battery Pack
bq24087
Input Power
1
RTMR
C3
4.7 mF
R1
1.5 kW
R2
1.5 kW
2
IN
TMR
49.9 kW
RED
GREEN
3
4
5
OUT
BAT
STAT 1
TE
STAT 2
CE
Vss
ISET
10
Pack+
C2
9
+
1 mF
Pack-
8
7
6
RSET
1.13 kW
Charge and
Termination Enable
Figure 13. Application Circuits
OPERATING MODES
Power Down
The bq24085/6/7/8 family is in a power-down mode when the input power voltage (IN) is below the power-down
threshold V(PDWN). During the power down mode all IC functions are off, and the host commands at the control
pins are not interpreted. The integrated power mosfet connected between IN and OUT pins is off, the status
output pins STAT1 and STAT2 are set to high impedance mode and PG output is set to the high impedance
state.
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Sleep Mode
The bq24085/6/7/8 enters the sleep mode when the input power voltage (IN) is above the power down threshold
V(PDWN) but still lower than the input power detection threshold, V(IN) < V(OUT) + VIN(DT).
During the sleep mode the charger is off, and the host commands at the control pins are not interpreted. The
integrated power mosfet connected between IN and OUT pins is off, the status output pins STAT1 and STAT2
are set to the high impedance state and the PG output indicates input power not detected.
The sleep mode is entered from any other state, if the input power (IN) is not detected.
Overvoltage Lockout
The input power is detected when the input voltage V(IN) > V(OUT) + VIN(DT). When the input power is detected
the bq24085/6/7/8 transitions from the sleep mode to the power-on-reset mode. In this mode of operation, an
internal timer T(POR) is started and internal blocks are reset (power-on-reset). Until the timer expires, the STAT1
and STAT2 outputs indicate charger OFF, and the PG output indicates the input power status as not detected.
At the end of the power-on-reset delay, the internal comparators are enabled, and the STAT1, STAT2 and PG
pins are active.
Stand-By Mode
In the bq24085/6/7/8, the stand-by mode is started at the end of the power-on-reset phase, if the input power is
detected and CE = HI. In the stand-by mode, selected blocks in the IC are operational, and the control logic
monitors system status and control pins to define if the charger will set to on or off mode. The quiescent current
required in stand-by mode is 100 µA typical.
If the CE pin is not available the bq24085/6/7/8 enters the begin charge mode at the end of the power-on-reset
phase.
Begin Charge Mode
All blocks in the IC are powered up, and the bq24085/6/7/8 is ready to start charging the battery pack. A new
charge cycle is started when the control logic decides that all conditions required to enable a new charge cycle
are met. During the begin charge phase all timers are reset, after that the IC enters the charging mode.
Charging Mode
When the charging mode is active, the bq24085/6/7/8 executes the charging algorithm, as described in the
operational flow chart, Figure 14.
Suspend Mode
The suspend mode is entered when the pack temperature is not within the valid temperature range. During the
suspend mode the charger is set to off, but the timers are not reset.
The normal charging mode resumes when the pack temperature is within range.
LDO Mode Operation
The LDO Mode (TMR pin open circuit) disables the charging termination circuit, disables the battery detect
routine and holds the safety timer clock in reset. This is often used for operation without a battery or in
production testing. This mode is different than a typical LDO since it has different modes of operation, and
delivers less current at lower output voltages. See Figure 20 for the output current versus the output voltage.
Note that a load on the output prior to powering the device may keep the part in short-circuit mode. Also, during
normal operation, exceeding the programmed fast charge level causes the output to drop, further restricting the
output power, and soon ends up in short-circuit mode. Operation with a battery or keeping the average load
current below the programmed current level prevents this type of latch up. The out pin current can be monitored
via the ISET pin. If in LDO mode without a battery present, It is recommended that a 350-Ω feedback resistor be
used between the BAT and OUT pins.
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STATE MACHINE DIAGRAM
CHARGING
RECHARGE
DETECTION
No
V(TS) >V(TS2) OR
V(TS) < V( TS1)
VI(BAT ) < V(RCH )
Yes
Suspend
Set Charge Off,
Stop timers,
Keep timer count,
STATn=Hi-Z
V(TS) < V(TS2) AND
V(TS) > V( TS1)
V(OUT) <V(SC)
Enable IO(SHORT)
current
T (PRCH) OFF
ANY
STATE
Reset T(CHG)
Regulate
IO(PRECHG)
T(PRCH) ON
Indicate ChargeIn-Progress
No
VDETECT
ENABLED
ANY
STATE
Yes
V(OUT)
<V(LOWV)
Yes
No
Enable I(DETECT) for
t(DETECT)
No
Yes
Reset T(PRCH)
T (CHG) ON
Battery Present
VI(BAT) <V(LOWV)
GO TO
Begin Charge
No
Indicate ChargeIn-Progress
Yes
BATTERY
DETECTION
No OR
Timers disabled
Regulate Current
or Voltage
Apply IO(PRECHG) for
t(DETECT)
No
Yes
Yes
No
T(CHG) Expired?
T (PRCH)
Expired?
VI(BAT ) > V(RCH )
No OR
timers disabled
Yes
ANY
STATE
V(OUT)
<V( LOWV)
Yes AND
timers enabled
Yes AND
Timers enabled
Battery Absent
Charge Off
T(DETECT) Fault
Yes
V(OUT)
<V(LOWV)
Fault Condition
V(TS) >V (TS2) OR
V(TS) < V (TS1)
Suspend
Set Charge Off,
Stop timers,
Keep timer count,
STATn=Hi-Z
V(TS) >V(TS2) OR
V(TS) < V(TS1)
No
OR
termination
disabled
ANY
STATE
V(TS) < V(TS2) AND
V(TS) > V(TS1)
Indicate Fault
No
ITERM
detection?
V(OUT)
> V(RCH)?
Stand-by
/CE=HI OR
V(IN)>V( OVP)
STATn set to HI-Z,
update /PG status,
enable control logic
Yes AND
termination
enabled
Yes
/CE=LO AND
[V(BAT)+V(INDT) ]
< V(IN) <
V( OVP)
No
Enable IFAULT
current
Termination
No
Indicate
Termination
Yes
T (POR)
Expired?
V(OUT)
> V(RCH )?
Yes
No
Power-on-reset
Turn off charger ,
STATn and PG
set to HI-Z,
reset timers
Begin Charge
Disable IFAULT
current
Reset ALL TImers
V(IN) > V(POR) AND
V(IN) > V(OUT)+VIN(DT)
FAULT
RECOVERY
Sleep
[V(IN) -V(OUT)] <
[VIN(DT) - VHYS(INDT) ]
Turn off charger ,
STATn , /PG set to
HI-Z , monitor
input power
Done
Turn off charger ,
Indicate
Charge done
Reset timers
V(IN) > V(POR)
V(IN) < V (POR)
Power down
All IC functions off
STATn and PG
set to HI-Z
START -UP
ANY
STATE
Figure 14. Operational Flow Chart
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CONTROL LOGIC OVERVIEW
An external host can enable or disable the charging process using a dedicated control pin, CE. A low-level signal
on this pin enables the charge, and a high-level signal disables the charge. The bq24085/6/7/8 is in stand-by
mode with CE = HI. When the charger function is enabled (CE = LO) a new charge is initiated.
Table 1 describes the charger control logic operation, in bq24085/6/7/8 versions without the TS pin the pack
temp status is internally set to OK.
Table 1. Control Logic Functionality
bq24085/6/7/8
OPERATION
MODE
CE
INPUT
POWER
TIMER
FAULT
(latched)
OUTPUT
SHORT
CIRCUIT
TERMINATION
(latched)
PACK
TEMP
THERMAL
SHUTDOWN
POWER
DOWN
CHARGER
POWER
STAGE
POWER
DOWN
LO
Low
X
X
X
X
X
Yes
OFF
SLEEP
X
Not
Detected
X
X
X
X
X
No
OFF
OFF
STANDBY
SEE STATE
DIAGRAM
CHARGING
HI
Detected
X
X
X
X
X
No
LO
Detected
X
Yes
X
X
X
No
LO
Detected
No
No
Yes
X
X
No
LO
Detected
Yes
No
No
X
X
No
IFAULT
LO
Detected
No
No
Yes
Absent
TJ < TSHUT
No
IDETECT
LO
Detected
No
No
No
Hot or
Cold
TJ < TSHUT
No
OFF
LO
Detected
No
No
No
Ok
TJ < TSHUT
No
OFF
LO
Over
Voltage
No
No
No
Ok
TJ < TSHUT
No
OFF
LO
Detected
No
No
No
Ok
TJ < TSHUT
No
ON
OFF
In both STANDBY and SUSPEND modes the charge process is disabled. In the STANDBY mode all timers are
reset; in SUSPEND mode the timers are held at the count stored when the suspend mode was set.
The timer fault, termination and output short circuit variables shown in the control logic table are latched in the
detection circuits, outside the control logic. Refer to the timers, termination and short circuit protection sections
for additional details on how those latched variables are reset.
TEMPERATURE QUALIFICATION (Applies only to versions with TS pin option)
The bq24085/6/7/8 devices continuously monitor the battery temperature by measuring the voltage between the
TS and VSS pins. The IC compares the voltage on the TS pin against the internal V(TS1) and V(TS2) thresholds to
determine if charging is allowed. Once a temperature outside the V(TS1) and V(TS2) thresholds is detected the IC
immediately suspends the charge. The IC suspends charge by turning off the power FET and holding the timer
value (i.e., timers are NOT reset). Charge is resumed when the temperature returns to the normal range.
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VIN
Charge Suspend
VC(TS2)
0.6 x VIN
Normal Temperature
Charge Range
VC(TS1)
0.3 x VIN
Charge Suspend
Figure 15. Battery Temperature Qualification With NTC Thermistor
The external resistors RT1 and RT2 (see Figure 13) enable selecting a temperature window. If RTC and RTH are
the thermistor impedances for the Cold and Hot thresholds the values for RT1 and RT2 can be calculated as
follows, for a NTC (negative temperature coefficient) thermistor. Solve for RT2 first and substitute into RT1
equation.
2.5 R TCRTH
R T2 +
RTC * 3.5 RTH
(1)
R T1 +
7 R THRT2
3 ƪRTH ) RT2ƫ
(2)
Applying a fixed voltage, 1/2 Vin (50% resistor divider from Vin to ground), to the TS pin to disable the
temperature sensing feature.
INPUT OVERVOLTAGE DETECTION, POWER GOOD STATUS OUTPUT
The input power detection status for pin IN is shown at the open collector output pin PG.
Table 2. Input Power Detection Status
INPUT POWER DETECTION (IN)
PG STATE
NOT DETECTED
High impedance
DETECTED, NO OVERVOLTAGE
LO
DETECTED, OVERVOLTAGE
High impedance
The bq24085/6/7/8 detects an input overvoltage when V(IN) > V(OVP). When an overvoltage protection is detected
the charger function is turned off and the bq24085/6/7/8 is set to standby mode of operation. The OVP detection
is not latched, and the IC returns to normal operation when the fault condition is removed.
CHARGE STATUS OUTPUTS
The open-collector STAT1 and STAT2 outputs indicate various charger operations as shown in Table 3. These
status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the
open-collector transistor is turned off. When termination is disabled (TMR pin floating, or TE = Hi for bq24087)
the Done state is not available; the status LEDs indicate fast charge if V(BAT) > V(LOWV) and precharge if V(BAT) <
V(LOWV). The available output current is a function of the OUT pin voltage, See Figure 20.
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Table 3. Charge Status (1)
Charge State
STAT1
STAT2
Precharge in progress
ON
ON
Fast charge in progress
ON
OFF
Done (termination enabled only)
OFF
ON
OFF
OFF
Charge Suspend (temperature)
Timer Fault
Charger off
Selected Input power overvoltage detected
Battery absent
Batteryshort
(1)
Pulse loading on the OUT pin may cause the IC to cycle between Done and charging states (LEDs
Flashing)
BATTERY CHARGING: CONSTANT CURRENT PHASE
The bq24085/6/7/8 family offers on-chip current regulation. The current regulation is defined by the value of the
resistor connected to ISET pin.
During a charge cycle the fast charge current IO(OUT) is applied to the battery if the battery voltage is above the
V(LOWV) threshold (2.95 V typical):
V(SET) KSET)
I(OUT) + I O(OUT) +
RISET
(3)
Where K(SET) is the output current set factor and V(SET) is the output current set voltage.
During a charge cycle if the battery voltage is below the V(LOWV) threshold a pre-charge current I(PRECHG) is
applied to the battery. This feature revives deeply discharged cells.
V(PRECHG) KSET)
I O(OUT)
I(OUT) + I (PRECHG) +
X
10
RISET
(4)
Where K(SET) is the output current set factor and V(PRECHG) is the precharge set voltage.
At low constant current charge currents, less than 200 mA, it is recommended that a 0.1-µF capacitor be placed
between the ISET and BAT pins to insure stability.
CHARGE CURRENT TRANSLATOR
When the charge function is enabled, internal circuits generate a current proportional to the charge current at the
ISET pin. This current, when applied to the external charge current programming resistor RISET generates an
analog voltage that can be monitored by an external host to calculate the current sourced from the OUT pin.
R ISET
V(ISET) + I(OUT)
K(SET)
(5)
BATTERY VOLTAGE REGULATION
The battery pack voltage is sensed through the BAT pin, which is tied directly to the positive side of the battery
pack. The bq24085/6/7/8 monitors the battery pack voltage between the BAT and VSS pins. When the battery
voltage rises to VO(REG) threshold, the voltage regulation phase begins and the charging current begins to taper
down. The voltage regulation threshold VO(REG) is fixed by an internal IC voltage reference.
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PRE-CHARGE TIMER
The bq24085/6/7/8 family activates an internal safety timer during the battery pre-conditioning phase. The charge
safety timer time-out value is set by the external resistor connected to TMR pin, RTMR and the timeout constants
K(PCHG) and t(CHG) :
t(PCHG) = K(PCHG) × t(CHG)
The pre-charge timer operation is detailed in Table 4.
Table 4. Pre-Charge Timer Operational Modes
bq24085/6/7/8 MODE
STANDBY (CE = Hi)
V(OUT) > V(LOWV)
PRE-CHARGE TIMER MODE
X
RESET
CHARGING
Yes
RESET
SUSPEND (TS out of range)
Yes
RESET
SUSPEND (TS out of range)
No
Hold
CHARGING, TMR PIN NOT OPEN
No
COUNTING, EXTERNAL PROGRAMMED RATE
X
RESET
CHARGING, TMR PIN OPEN
In SUSPEND mode the pre-charge timer is put on hold (i.e., pre-charge timer is not reset), normal operation
resumes when the timer returns to the normal operating mode (COUNTING). If V(BAT) does not reach the internal
voltage threshold V(LOWV) within the pre-charge timer period a fault condition is detected, the charger is turned off
and the pre-charge safety timer fault condition is latched.
When the pre-charge timer fault latch is set the charger is turned off. Under those conditions a small current
IFAULT is applied to the OUT pin, as long as input power (IN) is detected AND V(OUT) < V(LOWV), as part of a timer
fault recovery protocol. This current allows the output voltage to rise above the pre-charge threshold V(LOWV),
resetting the pre-charge timer fault latch when the pack is removed. Table 5 further details the pre-charge timer
fault latch operation.
Table 5. Pre-Charge Timer Latch Functionality
PRE-CHARGE TIMER FAULT ENTERED WHEN
PRE-CHARGE TIMER FAULT LATCH RESET AT
CE rising edge or OVP detected
Pre-charge timer timeout AND V(OUT) < V(LOW
V)
Input power removed (not detected)
Timer function disabled
THERMAL PROTECTION LOOP
An internal control loop monitors the bq24085/6/7/8 junction temperature (TJ) to ensure safe operation during
high power dissipations and or increased ambient temperatures. This loop monitors the bq24085/6/7/8 junction
temperature and reduces the charge current as necessary to keep the junction temperature from exceeding,
TJ(REG), (112°C, typical).
The bq24085/6/7/8's thermal loop control can reduce the charging current down to ~105 mA if needed. If the
junction temperature continues to rise, the IC will enter thermal shutdown.
THERMAL SHUTDOWN AND PROTECTION
Internal circuits monitor the junction temperature, TJ, of the die and suspends charging if TJ exceeds an internal
threshold T(SHUT) (155°C typical). Charging resumes when TJ falls below the internal threshold T(SHUT) by
approximately 20°C.
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bq24085, bq24086
bq24087, bq24088
www.ti.com............................................................................................................................................. SLUS784D – DECEMBER 2007 – REVISED AUGUST 2009
DYNAMIC TIMER FUNCTION
The charge and pre-charge safety timers are programmed by the user to detect a fault condition if the charge
cycle duration exceeds the total time expected under normal conditions. The expected charge time is usually
calculated based on the fast charge current rate.
When the thermal loop is activated the charge current is reduced, and bq24085/6/7/8 activates the dynamic timer
control, an internal circuit that slows down the safety timer's clock frequency. The dynamic timer control circuit
effectively extends the safety time duration for either the precharge or fast charge timer modes. This minimizes
the chance of a safety timer fault due to thermal regulation.
The bq24085/6/7/8 dynamic timer control (DTC) monitors the voltage at pin ISET during pre-charge and fast
charge, and if in thermal regulation slows the clock frequency proportionately to the change in charge current.
The time duration is based on a 224 ripple counter, so slowing the clock frequency is a real time correction. The
DTC circuit changes the safety timers clock period based on the V(SET)/V(ISET) ratio (fast charge) or
V(PRECHG)/V(SET) ratio (pre-charge). Typical safety timer multiplier values relative to the V(SET)/V(ISET) ratio is shown
in Figure 16 and Figure 17.
The device deglitch timers are set by the same oscillators as the safety and precharge timers. In thermal
regulation, the timers are scaled appropriately, see Figure 2.
CHARGE TIMER INTERNAL CLOCK
PERIOD MULTIPLICATION FACTOR
5
4
3
2
1
0
0
1
3
2
V(SET)/V(ISET) - V
4
5
Figure 16. Safety Timer Linearity
Internal Clock Period Multiplication Factor
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45
RTMR = 70 kW
T(CHG) - Safety Timer - Hours
40
35
30
RTMR = 50 kW
25
20
RTMR = 30 kW
15
10
5
0
0
1
2
3
VSET/VISET - V
4
5
6
Figure 17. bq24085/6/78 Safety Timer Linearity for RTMR Values
160
Core Oscillator Frequency - kHz
140
120
100
80
60
40
20
0
20
30
40
60
50
ITMR Current - mA
70
80
90
Figure 18. bq24085/6/7/8 Oscillator Linearity vs ITMR
RTMR 30 KΩ – 100 KΩ
20
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CHARGE TERMINATION DETECTION AND RECHARGE
The charging current is monitored the during the voltage regulation phase. Charge termination is indicated at the
STATx pins (STAT1 = Hi-Z; STAT2 = Low ) once the charge current falls below the termination current threshold
I(TERM). A deglitch period tDGL(TERM) is added to avoid false termination indication during transient events.
Charge termination is not detected if the charge current falls below the termination threshold as a result of the
thermal loop activation. Termination is also not detected when charger enters the suspend mode, due to
detection of invalid pack temperature or internal thermal shutdown.
Table 6 describes the termination latch functionality.
Table 6. Termination Latch Functionality
TERMINATION DETECTED LATCHED WHEN
TERMINATION LATCH RESET AT
CE rising edge or OVP detected
I(OUT) < I(TERM) AND t > tDGL(TERM) AND V(OUT) > V(RCH)
New charging cycle started; see state diagram
Termination disabled
The termination function is DISABLED:
1. In bq24085/6/7/8 the termination is disabled when the TMR pin is left open (floating).
2. In bq24087, leaving the TMR pin open (floating) does not disable the termination. The only way to disabled
termination in bq24087 is to have TE = high.
BATTERY ABSENT DETECTION – VOLTAGE MODE ALGORITHM
The bq24085/6/7/8 provides a battery absent detection scheme to reliably detect insertion and/or removal of
battery packs. The detection circuit applies an internal current to the battery terminal, and detects battery
presence based on the terminal voltage behavior. Figure 19 has a typical waveform of the output voltage when
the battery absent detection is enabled and no battery is connected:
5
VO - Output Voltage - V
4.50
4
3.50
3
2.50
2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
t - Time - s
Figure 19. Battery-Absent Detection Waveforms
The battery absent detection function is disabled if the voltage at the BAT pin is held above the battery recharge
threshold, V(RCH), after termination detection. When the voltage at the BAT pin falls to the recharge threshold,
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either by connection of a load to the battery or due to battery removal, the bq24085/6/7/8 begins a battery absent
detection test. This test involves enabling a detection current, IDET(DOWN), for a period of t(DETECT) and checking to
see if the battery voltage is below the pre-charge threshold, V(LOWV). Following this, the precharge current,
IDET(UP) is applied for a period of t(DETECT) and the battery voltage checked again to be above the recharge
threshold.
Passing both of the discharge and charging tests (battery terminal voltage being below the pre-charge and above
the recharge thresholds on the battery detection test) indicates a battery absent fault at the STAT1 and STAT2
pins. Failure of either test starts a new charge cycle. For the absent battery condition, the voltage on the BAT pin
rises and falls between the V(LOWV) and VO(REG) thresholds indefinitely. See the operation flowchart for more
details on this algorithm. If it is desired to power a system load without a battery, it is recommended to float the
TMR pin which puts the charger in LDO mode (disables termination).
The battery absent detection function is disabled when the termination is disabled.
The bq24085/6/7/8 provides a small battery leakage current, IBAT(DONE) (1 µA typical), after termination to pull
down the BAT pin voltage in the event of battery removal. If the leakage on the OUT pin is higher than this
pulldown current, then the voltage at the pin remains above termination and a battery-absent state will not be
detected. This problem is fixed with the addition of a pulldown resistor of 2 MΩ to 4 MΩ from the OUT pin to
VSS. A resistor too large (< 2 MΩ) can cause the OUT pin voltage to drop below the V(LOWV) threshold before the
recharge deglitch (typical 25 ms) expires, causing a fault condition. In this case, the bq24085/6/7/8 provides a
fault current (typical 750 µA) to pull the pin above the termination threshold.
CHARGE SAFETY TIMER
As a safety mechanism, the bq24085/6/7/8 has a user-programmable timer that monitors the total fast charge
time. This timer (charge safety timer) is started at the beginning of the fast charge period. The safety charge
timeout value is set by the value of an external resistor connected to the TMR pin (RTMR); if pin TMR is left open
(floating) the charge safety timer is disabled.
The charge safety timer time-out value is calculated as follows:
t(CHG) = [K(CHG) × R(TMR)]
The safety timer operation modes are shown in Table 7
Table 7. Charge Safety Timer Operational Modes
V(OUT) > V(LOWV)
CHARGE SAFETY TIMER MODE
STANDBY
bq24085/6/7/8
X
RESET
CHARGING
No
RESET
SUSPEND
No
RESET
SUSPEND
Yes
SUSPEND
CHARGING, TMR PIN NOT OPEN
Yes
COUNTING
X
RESET
CHARGING, TMR PIN OPEN
In SUSPEND mode, the charge safety timer is put on hold (i.e., charge safety timer is not reset), normal
operation resumes when the TS fault is removed and the timer returns to the normal operating mode
(COUNTING). If charge termination is not reached within the timer period, a fault condition is detected. Under
those circumstances, the LED status is updated to indicate a fault condition and the charger is turned off.
When the charge safety timer fault latch is set and the charger is turned off, a small current IFAULT is applied to
the OUT pin, as long as input power (IN) is detected AND V(OUT) < V(RCHG), as part of a timer fault recovery
protocol. This current allows the output voltage to rise above the recharge threshold V(RCHG) if the pack is
removed, and assures that the charge safety timer fault latch is reset if the pack is removed and re-inserted.
Table 8 further details the charge safety timer fault latch operation.
22
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Table 8. Charge Safety Timer Latch Functionality
CHARGE SAFETY TIMER FAULT ENTERED
CHARGE SAFETY TIMER FAULT LATCH RESET AT
CE rising edge, or OVP detected
V(OUT) > V(LOW V)
Input power removed (not detected)
New charging cycle started; see state diagram
SHORT-CIRCUIT PROTECTION
The internal comparators monitor the battery voltage and detect when a short circuit is applied to the battery
terminal. If the voltage at the BAT pin is less than the internal threshold V(scind) (1.8 V typical), the STAT pins
indicate a fault condition (STAT1 = STAT2 = Hi-Z). When the voltage at the BAT pin falls below a second internal
threshold V(sc) (1.4 V typical), the charger power stage is turned off. A recovery current, I(short) (22 mA typical),
is applied to the BAT pin, enabling detection of the short circuit removal. The battery output current versus
battery voltage is shown in the graph, Figure 20
1200
RISET at 840 W
Battery Current - mA
1000
800
600
400
200
0
4
3.5
3
2.5
2
1.5
1
0.5
0
Battery Voltage - V
Figure 20. bq24085/6/7/8 Short Circuit Behavior
See the application section for additional details on start-up operation with V(BAT) < V(SC).
STARTUP WITH DEEPLY DEPLETED BATTERY CONNECTED
The bq24085/6/7/8 charger furnishes the programmed charge current if a battery is detected. If no battery is
connected the bq24085/6/7/8 operates as follows:
• The output current is limited to 22 mA (typical), if the voltage at BAT pin is below the short circuit detection
threshold V(SC), 1.8 V typical.
• The output current is regulated to the programmed pre-charge current if V(SC) < V(BAT) < V(LOWV).
• The output current is regulated to the programmed fast charge current If V(BAT) > V(LOWV) AND voltage
regulation is not reached.
The output voltage collapses if no battery is present and the end equipment requires a bias current larger that
the available charge current.
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APPLICATION INFORMATION
SELECTING INPUT AND OUTPUT CAPACITOR
In most applications, all that is needed is a high-frequency decoupling capacitor on the input power pin. A 1-µF
ceramic capacitor, placed in close proximity to the IN pin and GND pad, works fine. In some applications,
depending on the power supply characteristics and cable length, it may be necessary to increase the input filter
capacitor to avoid exceeding the IN pin maximum voltage rating during adapter hot plug events.
The bq2408x, at low charge currents, requires a small output capacitor for loop stability. A 0.1 µF ceramic
capacitor placed between the BAT and ISET pad is typically sufficient.
bq2408x CHARGER DESIGN EXAMPLE
Requirements
• Supply voltage = 5 V
• Safety timer duration of 5 hours for fast charge
• Fast charge current of approximately 400 mA
• Battery temp sense is not used
Calculations
Program the charge current for 400 mA:
R(ISET) = [V(SET) × K(SET) / I(OUT)]
from electrical characteristics table. . . V(SET) = 2.5 V
from electrical characteristics table. . . K(SET) = 182
R(ISET) = [2.5 V × 187 / 0.4 A] = 1137 Ω
Selecting the closest standard value, use a 1.13 kΩ resistor connected between ISET (pin 6) and ground.
Program 5-hour safety timer timeout:
R(TMR) = [T(CHG) / K(CHG)]
from the electrical characteristics table. . . K(CHG) = 0.1 hr / kΩ
K(TMR) = [5 hrs / (0.1 hr / kΩ)] = 50 kΩ
Selecting the closest standard value, use a 49.9 kΩ resistor connected between TMR (pin 2) and ground.
Disable the temp sense function:
A constant voltage between VTS1 and VTS2 on the TS input disables the temp sense function.
from electrical characteristics table. . . V(TS1) = 30% × VIN
from electrical characteristics table. . . V(TS2) = 61% × VIN
A constant voltage of 50% × Vin disables the temp sense function, so a divide-by-2 resistor divider
connected between Vin and ground can be used. Two 1-MΩ resistors keeps the power dissipated in this
divider to a minimum.
For a 0–45°C range with a Semitec 103AT thermistor, the thermistor values are 4912 at 45°C and 27.28k at 0°C.
RT1 (top resistor) and RT2 (bottom resistor) are calculated as follows:
2.5 RTCRTH
2.5 (27.28k) (4.912k)
RT2 =
=
= 33.2k
RTC - 3.5RTH
27.28k - 3.5(4.912k)
RT1 =
24
7 RTHRT2
7 (4.921k) (33.2k)
=
= 10k
3 (RTH + RT2 ) 3 (4.921k + 33.2k)
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PIN
COMPONENTS
IN
In most applications, the minimum input capacitance needed is a 0.1 µF ceramic decoupling
capacitor near the input pin connected to ground (preferably to a ground plane through vias).
The recommended amount of input capacitance is 1 µF or at least as much as on the output
pin. This added capacitance helps with hot plug transients, input inductance and initial
charge transients.
OUT
There is no minimum value for capacitance for this output, but it is recommended to connect
a 1 µF ceramic capacitor between OUT and ground. This capacitance helps with
termination, and cycling frequency between charge done and refresh charge when no
battery is present. It also helps cancel out any battery lead inductance for long leaded
battery packs. It is recommended to put as much ceramic capacitance on the input as the
output so as not to cause a drop out of the input when charging is initiated.
ISET/BAT
For stability reasons, it may be necessary to put a 0.1-µF capacitor between the ISET and
BAT pin..
STAT1/2 and PG Optional (LED STATUS – See below, Processor Monitored; or no status)
STAT1
Connect the cathode of a red LED to the open-collector STAT1 output, and connect the
anode of the red LED to the input supply through a 1.5 kΩ resistor that limits the current.
STAT2
Connect the cathode of a green LED to the open-collector STAT2 output, and connect the
anode of the green LED to the input supply through a 1.5 kΩ resistor that limits the current.
PG
Connect the cathode of an LED to the open-collector PG output, and connect the anode of
the LED to the input supply through a 1.5 kΩ resistor to limit the current.
THERMAL CONSIDERATIONS
The bq2408x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the IC and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment Application
Note (SLUA271).
The most common measure of package thermal performance is thermal impedance (θJA ) measured (or modeled)
from the chip junction to the air surrounding the package surface (ambient). The mathematical expression for θJA
is:
T - TA
q(JA) = J
P
(7)
Where:
TJ = chip junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested
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The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal
PowerFET. It can be calculated from the following equation when a battery pack is being charged :
P = [V(IN) – V(OUT)] × I(OUT)
Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See the charging profile, Figure 10 .
If the board thermal design is not adequate the programmed fast charge rate current may not be achieved under
maximum input voltage and minimum battery voltage, as the thermal loop can be active effectively reducing the
charge current to avoid excessive IC junction temperature.
USING ADAPTERS WITH LARGE OUTPUT VOLTAGE RIPPLE
Some low cost adapters implement a half rectifier topology, which causes the adapter output voltage to fall below
the battery voltage during part of the cycle. To enable operation with low cost adapters under those conditions
the bq2408x family keeps the charger on for at least 25 msec (typical) after the input power puts the part in sleep
mode. This feature enables use of external low cost adapters using 50 Hz networks.
The backgate control circuit prevents any reverse current flowing from the battery to the adapter terminal during
the charger off delay time.
Note that the PG pin is not deglitched, and it indicates input power loss immediately after the input voltage falls
below the output voltage. If the input source frequently drops below the output voltage and recovers, a small
capacitor can be used from PG to VSS to prevent PG flashing events.
PCB LAYOUT CONSIDERATIONS
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter
capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq2408x, with short
trace runs to both IN, OUT and GND (thermal pad).
• All low-current GND connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
• The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces.
• The bq2408x family are packaged in a thermally enhanced MLP package. The package includes a thermal
pad to provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal
pad is also the main ground connection for the device. Connect the thermal pad to the PCB ground
connection. Full PCB design guidelines for this package are provided in the application note entitled:
QFN/SON PCB Attachment Application Note (SLUA271).
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24085DRCR
ACTIVE
SON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDV
BQ24085DRCRG4
ACTIVE
SON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDV
BQ24085DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDV
BQ24085DRCTG4
ACTIVE
SON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDV
BQ24086DRCR
ACTIVE
SON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
0 to 125
CDW
BQ24086DRCRG4
ACTIVE
SON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDW
BQ24086DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDW
BQ24086DRCTG4
ACTIVE
SON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDW
BQ24087DRCR
ACTIVE
SON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDX
BQ24087DRCRG4
ACTIVE
SON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDX
BQ24087DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDX
BQ24087DRCTG4
ACTIVE
SON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CDX
BQ24088DRCR
ACTIVE
SON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CHE
BQ24088DRCRG4
ACTIVE
SON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CHE
BQ24088DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CHE
BQ24088DRCTG4
ACTIVE
SON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 125
CHE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
BQ24085DRCR
SON
DRC
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ24085DRCT
SON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ24086DRCR
SON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ24087DRCR
SON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ24087DRCT
SON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ24088DRCR
SON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ24088DRCT
SON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24085DRCR
SON
DRC
10
3000
367.0
367.0
35.0
BQ24085DRCT
SON
DRC
10
250
210.0
185.0
35.0
BQ24086DRCR
SON
DRC
10
3000
367.0
367.0
35.0
BQ24087DRCR
SON
DRC
10
3000
367.0
367.0
35.0
BQ24087DRCT
SON
DRC
10
250
210.0
185.0
35.0
BQ24088DRCR
SON
DRC
10
3000
367.0
367.0
35.0
BQ24088DRCT
SON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
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