TI1 OPA1678 Low-distortion audio operational amplifier Datasheet

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OPA1678, OPA1679
SBOS855A – FEBRUARY 2017 – REVISED MAY 2018
OPA167x Low-Distortion Audio Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
The OPA1678 (dual-channel) and OPA1679 (quadchannel) operational amplifiers offer higher systemlevel performance over legacy op amps commonly
used in audio circuitry. The OPA167x amplifiers
achieve a low 4.5-nV/√Hz noise density and low
distortion of 0.0001% at 1 kHz which improves audio
signal fidelity. They also offer rail-to-rail output swing
to within 800 mV with a 2-kΩ load, which increases
headroom and maximizes dynamic range.
1
•
•
•
•
•
•
•
•
Low Noise: 4.5 nV/√Hz at 1 kHz
Low Distortion: 0.0001% at 1 kHz
High Open-Loop Gain: 114dB
High Common-Mode Rejection: 110 dB
Low Quiescent Current:
– 2 mA Per Channel
Low Input Bias Current: 10 pA (Typical)
Slew Rate: 9 V/μs
Wide Gain Bandwidth: 16 MHz (G = 1)
Unity-Gain Stable
Rail-to-Rail Output
Wide Supply Range:
– ±2.25 V to ±18 V, or 4.5 V to 36 V
Dual-Channel and Quad-Channel Versions
Small Package Sizes:
– Dual-Channel: SO-8, MSOP-8, SON-8
– Quad-Channel: SO-14, TSSOP-14, QFN-16
The OPA167x amplifiers use completely independent
internal circuitry for lowest crosstalk and freedom
from interactions between channels, even when
overdriven or overloaded.
The OPA167x temperature ranges are specified from
–40°C to +85°C.
2 Applications
•
•
•
•
•
The OPA1678 and OPA1679 operate over a very
wide supply range of ±2.25 V to ±18 V or (4.5 V to 36
V) on only 2 mA of supply current to accommodate
the power supply constraints of many types of audio
products. These op amps are unity-gain stable and
provide excellent dynamic behavior over a wide range
of load conditions allowing them to be used in many
audio circuits.
Analog Signal Conditioning
Analog and Digital Mixers
Audio Effects Pedals
A/V Receivers
Car Audio Systems
Device Information(1)
PART NUMBER
OPA1678
OPA1679
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SON (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Internal Schematic
V
BIAS1
V +
IN
V
Class AB
Control
Circuitry
IN
V
V
BIAS2
V
O
Total Harmonic Distortion +Noise (%)
Tail
Current
0.1
-60
Gain = 10 V/V
Gain = 1 V/V
Gain = -1 V/V
0.01
-80
0.001
-100
0.0001
-120
Total Harmonic Distortion + Noise (dB)
THD+N vs Frequency (2-kΩ Load)
V+
-140
0.00001
10
100
1k
Frequency (Hz)
10k
C002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1678, OPA1679
SBOS855A – FEBRUARY 2017 – REVISED MAY 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
6
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: OPA1678 ................................
Thermal Information: OPA1679 ................................
Electrical Characteristics: VS = ±15 V.......................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
14
18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 27
10.3 Power Dissipation ................................................. 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
29
29
29
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2017) to Revision A
Page
•
Added SON-8 package to Features list.................................................................................................................................. 1
•
Added DRG (SON) 8-pin package to Device Information table ............................................................................................ 1
•
Added DRG (SON) 8-pin pinout drawing to Pin Configuration and Functions section .......................................................... 3
•
Added thermal pad information to Pin Functions: OPA1678 table......................................................................................... 3
•
Added DRG (SON) thermal information to Thermal Information: OPA1678 table ................................................................. 6
2
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5 Pin Configuration and Functions
OPA1678 D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OPA1678 DRG Package
8-Pin SON With Exposed Thermal Pad
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
OUT A
1
±IN A
2
+IN A
3
V±
4
Thermal
Pad
8
V+
7
OUT B
6
±IN B
5
+IN B
Not to scale
Not to scale
Pin Functions: OPA1678
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
Thermal pad
Exposed thermal die pad on underside; connect thermal die pad to V–. Soldering the thermal
pad improves heat dissipation and provides specified performance.
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OPA1679 D and PW Packages
14-Pin SOIC and TSSOP
Top View
OUT A
1
14
OUT D
±IN A
2
13
±IN D
+IN A
3
12
+IN D
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
Pin Functions: OPA1679
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
–IN C
9
I
Inverting input, channel C
+IN D
10
I
Noninverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V+
4
—
Positive (highest) power supply
V–
11
—
Negative (lowest) power supply
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage
Input
V
(V+) + 0.5
V
–10
10
mA
125
°C
200
°C
150
°C
Output short-circuit (2)
Continuous
Operating, TA
Temperature
–55
Junction, TJ
Storage, Tstg
(2)
UNIT
40
(V–) – 0.5
Input (all pins except power-supply pins)
Current
(1)
MAX
Supply voltage, VS = (V+) – (V–)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2 (ground in symmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
TA
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
85
°C
Operating temperature
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6.4 Thermal Information: OPA1678
OPA1678
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
DRG (SON)
8 PINS
8 PINS
8 PINS
UNIT
219
66.9
°C/W
RθJA
Junction-to-ambient thermal resistance
144
RθJC(top)
Junction-to-case (top) thermal resistance
77
79
54.5
°C/W
RθJB
Junction-to-board thermal resistance
62
104
40.4
°C/W
ψJT
Junction-to-top characterization parameter
28
15
1.9
°C/W
ψJB
Junction-to-board characterization parameter
61
102
40.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
10.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA1679
OPA1679
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
90
127
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55
47
°C/W
RθJB
Junction-to-board thermal resistance
44
59
°C/W
ψJT
Junction-to-top characterization parameter
20
5.5
°C/W
ψJB
Junction-to-board characterization parameter
44
58
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics: VS = ±15 V
at TA = 25°C, RL = 2 kΩ, and VCM = VOUT = midsupply, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.0001%
THD+N
IMD
Total harmonic distortion + noise
Intermodulation distortion
G=1
RL = 600 Ω
f = 1 kHz
VO = 3 VRMS
G=1
VO = 3 VRMS
–120
SMPTE/DIN Two-Tone, 4:1
(60 Hz and 7 kHz)
0.0001%
DIM 30 (3-kHz square wave
and 15-kHz sine wave)
0.0001%
CCIF Twin-Tone
(19 kHz and 20 kHz)
0.0001%
dB
–120
dB
–120
dB
–120
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
G=1
16
SR
Slew rate
G = –1
9
MHz
V/µs
Full power bandwidth (1)
VO = 1 VP
1.4
MHz
Overload recovery time
G = –10
Channel separation (dual and quad)
f = 1 kHz
1
µs
–130
dB
NOISE
en
Input voltage noise
In
f = 20 Hz to 20 kHz
5.4
f = 0.1 Hz to 10 Hz
1.74
µVPP
Input voltage noise density
f = 1 kHz
4.5
nV/√Hz
Input current noise density
f = 1 kHz
3
fA/√Hz
OFFSET VOLTAGE
VS = ±2.25 V to ±18 V
±0.5
VOS
Input offset voltage
VS = ±2.25 V to ±18 V
TA = –40°C to +85°C (2)
2
PSRR
Power-supply rejection ratio
VS = ±2.25 V to ±18 V
3
±2
mV
µV/°C
8
µV/V
INPUT BIAS CURRENT
IB
Input bias current
VCM = 0 V
±10
pA
IOS
Input offset current
VCM = 0 V
±10
pA
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
(V–) + 0.5
CMRR
Common-mode rejection ratio
100
(V+) – 2
V
110
dB
INPUT IMPEDANCE
Differential
Common-mode
100 || 6
MΩ || pF
6000 || 2
GΩ || pF
OPEN-LOOP GAIN
Open-loop voltage gain
(V–) + 0.8 V ≤ VO ≤ (V+) – 0.8 V
RL = 2 kΩ
VOUT
Voltage output
RL = 2 kΩ
IOUT
Output current
ZO
Open-loop output impedance
ISC
Short-circuit current (3)
CLOAD
Capacitive load drive
AOL
106
114
dB
OUTPUT
(1)
(2)
(3)
(V–) + 0.8
(V+) – 0.8
See Typical Characteristics curves
f = 1 MHz
See Typical Characteristics curves
V
mA
Ω
50/–50
mA
100
pF
Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
Specified by design and characterization
One channel at a time
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Electrical Characteristics: VS = ±15 V (continued)
at TA = 25°C, RL = 2 kΩ, and VCM = VOUT = midsupply, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
IQ
Specified voltage
Quiescent current
(per channel)
±2.25
IOUT = 0 A
2
IOUT = 0 A
TA = –40°C to +85°C (2)
±18
V
2.5
mA
2.8
mA
TEMPERATURE
8
Specified range
–40
85
°C
Operating range
–55
125
°C
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6.7 Typical Characteristics
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
Voltage (200nV/div)
9ROWDJH 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+]
1000
100
10
1
1
10
100
1k
10k
Time (1s/div)
100k
Frequency (Hz)
C003
C001
Figure 1. Input Voltage Noise Density vs Frequency
2XWSXW 9ROWDJH 1RLVH Q9 ¥+]
10000
Figure 2. 0.1-Hz to 10-Hz Noise
20
Resistor Noise Contribution
Voltage Noise Contribution
Current Noise Contribution
Total Noise
16
Output Voltage (V)
1000
100
10
14
12
10
8
6
4
1
2
0.1
0
10
100
1k
10k
100k
1M
10M
100M 1000M
Source Resistance (O)
10k
Gain
Phase
120
20
40
10
Gain (dB)
Phase (s)
90
0
±10
±20
45
20
±30
0
±20
100
1k
10k
100k
1M
10M
Frequency (Hz)
C015
Figure 4. Maximum Output Voltage vs Frequency
80
60
10M
30
180
135
100
1M
Frequency (Hz)
Figure 3. Voltage Noise vs Source Resistance
10
100k
C001
140
Gain (dB)
VS = +/- 18 V
VS = +/- 5 V
VS = +/- 2.25 V
18
0
100M
±40
100k
Gain = -1 V/V
Gain = 1 V/V
Gain = 10 V/V
1M
10M
Frequency (Hz)
C006
CL = 10 pF
100M
C002
CL = 10 pF
Figure 5. Open-Loop Gain and Phase vs Frequency
Figure 6. Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
0.01
-80
0.001
-100
0.0001
-120
-140
10
100
1k
0.01
-80
0.001
-100
0.0001
-120
-140
0.00001
10k
10
Frequency (Hz)
VOUT = 3 VRMS
100
Bandwidth = 80 kHz
0.001
-100
-120
0.01
-140
0.1
1
RL = 2 kΩ
-60
0.01
-80
0.001
-100
Gain = 1 V/V
Gain = -1 V/V
Gain = 10 V/V
0.01
-140
0.1
1
10
Output Amplitude (VRMS)
C002
Bandwidth = 80 kHz
f = 1 kHz
Figure 9. THD+N Ratio vs Output Amplitude
RL = 600 Ω
C002
Bandwidth = 80 kHz
Figure 10. THD+N Ratio vs Output Amplitude
140
±70
120
±80
CMRR, PSRR (dB)
Channel Separation (dB)
-120
0.0001
±60
±90
±100
±110
±120
±130
±140
100
80
60
40
CMRR
PSRR(+)
PSRR(-)
20
±150
0
±160
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
VOUT = 3 VRMS
10
100
1k
10k
100k
1M
Frequency (Hz)
C006
10M
C006
Gain = 1 V/V
Figure 11. Channel Separation vs Frequency
10
Bandwidth = 80 kHz
0.1
0.00001
0.001
10
Output Amplitude (VRMS)
f = 1 kHz
Total Harmonic Distortion +Noise (%)
-80
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion +Noise (%)
0.01
Gain = 1 V/V
Gain = -1 V/V
Gain = 10 V/V
C002
RL = 600 Ω
Figure 8. THD+N Ratio vs Frequency
-60
0.0001
10k
Frequency (Hz)
VOUT = 3 VRMS
Figure 7. THD+N Ratio vs Frequency
0.1
0.00001
0.001
1k
C002
RL = 2 kΩ
-60
Gain = 10 V/V
Gain = 1 V/V
Gain = -1 V/V
Total Harmonic Distortion + Noise (dB)
0.00001
0.1
Total Harmonic Distortion + Noise (dB)
-60
Gain = 10 V/V
Gain = 1 V/V
Gain = -1 V/V
Total Harmonic Distortion +Noise (%)
Total Harmonic Distortion +Noise (%)
0.1
Total Harmonic Distortion + Noise (dB)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
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Figure 12. CMRR and PSRR vs Frequency
(Referred to Input)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
Voltage (25 mV/div)
VIN
VOUT
Voltage (25 mV/div)
VIN
VOUT
Time (0.2 s/div)
Time (0.2 s/div)
C009
Gain = 1 V/V
CL = 100 pF
C009
Gain = –1 V/V
CL = 100 pF
VIN
VOUT
VIN
VOUT
Voltage (2.5 V/div)
Figure 14. Small-Signal Step Response (100 mV)
Voltage (2.5 V/div)
Figure 13. Small-Signal Step Response (100 mV)
Time (1 s/div)
Time (1 s/div)
C009
Gain = +1 V/V
RF = 2 kΩ
CL = 100 pF
C009
Gain = –1 V/V
Figure 15. Large-Signal Step Response
CL = 100 pF
Figure 16. Large-Signal Step Response
1000
145
140
Input Bias Current (pA)
Open-Loop Gain (dB)
500
135
130
125
120
115
110
0
-500
-1000
IB(N)
-1500
IB(P)
105
100
I(OS)
-2000
±40
±15
10
35
60
85
Temperature (ƒC)
110
±40
±15
Figure 17. Open-Loop Gain vs Temperature
10
35
60
85
Temperature (ƒC)
C008
110
C008
Figure 18. IB and IOS vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
8
3
6
2.8
2.6
Supply Current (mA)
Input Bias Current (pA)
4
2
0
-2
-4
-8
±18 ±15 ±12 ±9
±6
±3
0
3
6
9
12
15
Common-Mode Voltage (V)
2.2
2
1.8
1.6
1.4
IB(N)
IB(P)
I(OS)
-6
2.4
1.2
1
18
±40
10
±15
35
60
85
110
Temperature (ƒC)
C008
Figure 19. IB and IOS vs Common-Mode Voltage
C008
Figure 20. Supply Current vs Temperature
20
3
18
Output Voltage Swing (V)
Supply Current (mA)
2.5
2
1.5
1
0.5
0
5
10
15
20
25
30
35
Supply Voltage (V)
12
10
8
6
-40°C
4
0°C
2
25°C
85°C
0
40
0
85°C
20
25
30
35
40
45
50
55
60
C004
80
ISC (+)
Short-Circuit Current (mA)
25°C
-6
15
Figure 22. Output Voltage vs Output Current (Sourcing)
0°C
-4
10
C008
-40°C
-2
5
Output Current (mA)
Figure 21. Supply Current vs Supply Voltage
Output Voltage Swing (V)
14
0
0
-8
-10
-12
-14
-16
60
ISC (-)
40
20
0
±20
±40
-18
-20
±60
0
5
10
15
20
25
30
Output Current (mA)
35
40
45
50
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±40
±15
10
35
60
85
110
135
Temperature (sC)
C004
Figure 23. Output Voltage vs Output Current (Sinking)
12
16
C003
Figure 24. Short-Circuit Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
70
60
50
50
Overshoot (%)
Phase Margin (s)
60
40
30
20
40
30
20
10
10
0
VS = +/- 18 V
VS = +/- 2.25 V
0
0
100
200
300
400
500
600
Capacitive Load (pF)
0
100
300
400
500
600
Capacitive Load (pF)
C002
G=1
C001
G=1
Figure 25. Phase Margin vs Capacitive Load
Figure 26. Percent Overshoot vs Capacitive Load
10
20
5
15
0
10
Voltage (V)
Voltage (V)
200
-5
-10
5
0
-15
-5
VIN
VOUT
-20
VIN
VOUT
-10
Time (500 ns/div)
Time (500 ns/div)
C004
C004
Gain = –10 V/V
Gain = –10 V/V
Figure 27. Negative Overload Recovery
Figure 28. Positive Overload Recovery
10000
20
15
10
Voltage (V)
Impedance (O)
1000
100
10
5
0
-5
-10
-15
1
-20
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
VIN
VOUT
Time (125 s/div)
C015
C004
Gain = 1 V/V
Figure 29. Open-Loop Output Impedance vs Frequency
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Figure 30. No Phase Reversal
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7 Detailed Description
7.1 Overview
The OPA167x devices are unity-gain stable, dual– and quad-channel op amps with low noise and distortion. The
Functional Block Diagram shows a simplified schematic of the OPA167x (one channel shown). The device
consists of a low noise input stage with a folded cascode and a rail-to-rail output stage. This topology exhibits
superior noise and distortion performance across a wide range of supply voltages that are not delivered by
legacy commodity audio operational amplifiers.
7.2 Functional Block Diagram
V+
Tail
Current
V
BIAS1
V +
IN
V
Class AB
Control
Circuitry
V
O
IN
V
BIAS2
V
7.3 Feature Description
7.3.1 Phase Reversal Protection
The OPA167x family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPA167x prevents phase reversal with excessive common-mode
voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 31.
20
15
Voltage (V)
10
5
0
-5
-10
-15
-20
VIN
VOUT
Time (125 s/div)
C004
Figure 31. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
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Feature Description (continued)
7.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 32 illustrates the ESD circuits contained in the OPA167x (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
TVS
+
±
RF
+VS
R1
IN±
250 Ÿ
RS
IN+
250 Ÿ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
Figure 32. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA167x but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (see Figure 32), the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
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Feature Description (continued)
Figure 32 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 32. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
7.3.3 EMI Rejection Ratio (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this document provides the EMIRR IN+, which specifically describes the EMIRR performance
when the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the
noninverting input is tested for EMIRR for the following three reasons:
• Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
• The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
• EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can
be isolated on a printed-circuit-board (PCB). This isolation allows the RF signal to be applied directly to the
noninverting input pin with no complex interactions from other components or connecting PCB traces.
A more formal discussion of the EMIRR IN+ definition and test method is shown in the EMI Rejection Ratio of
Operational Amplifiers application report, available for download at www.ti.com.
The EMIRR IN+ of the OPA167x is plotted versus frequency in Figure 33. If available, any dual and quad
operational amplifier device versions have approximately identical EMIRR IN+ performance. The OPA167x unitygain bandwidth is 16 MHz. EMIRR performance below this frequency denotes interfering signals that fall within
the operational amplifier bandwidth.
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Feature Description (continued)
100
90
EMIRR IN+ (dB)
80
70
60
50
40
30
20
10
0
10
100
1000
10000
Frequency (MHz)
C001
Figure 33. OPA167x EMIRR vs Frequency
Table 1 lists the EMIRR IN+ values for the OPA167x at particular frequencies commonly encountered in realworld applications. Applications listed in Table 1 can be centered on or operated near the particular frequency
shown. This information can be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 1. OPA167x EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, UHF
36 dB
900 MHz
GSM, radio communication and navigation, GPS (to 1.6 GHz), ISM,
aeronautical mobile, UHF
42 dB
1.8 GHz
GSM, mobile personal comm. broadband, satellite, L-band
52 dB
2.4 GHz
802.11b/g/n, Bluetooth™, mobile personal comm., ISM, amateur radio and satellite, S-band
64 dB
3.6 GHz
Radiolocation, aero comm./nav., satellite, mobile, S-band
67 dB
5 GHz
802.11a/n, aero communication and navigation, mobile communication,
space and satellite operation, C-band
77 dB
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7.3.3.1 EMIRR IN+ Test Configuration
Figure 34 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
operational amplifier noninverting input pin using a transmission line. The operational amplifier is configured in a
unity-gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A
large impedance mismatch at the operational amplifier input causes a voltage reflection; however, this effect is
characterized and accounted for when determining the EMIRR IN+. The resulting dc offset voltage is sampled
and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that can interfere with
multimeter accuracy. See the EMI Rejection Ratio of Operational Amplifiers application report for more details.
Ambient temperature: 25Û&
+VS
±
50
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
-VS
Sample /
Averaging
Not shown: 0.1 µF and 10 µF
supply decoupling
Digital Multimeter
Figure 34. EMIRR IN+ Test Configuration Schematic
7.4 Device Functional Modes
7.4.1 Operating Voltage
The OPA167x series op amps operate from ±2.25 V to ±18 V supplies while maintaining excellent performance.
The OPA167x series can operate with as little as 4.5 V between the supplies and with up to 36 V between the
supplies. However, some applications do not require equal positive and negative output voltage swing. With the
OPA167x series, power-supply voltages are not required to be equal. For example, the positive supply can be
set to 25 V with the negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. In addition, key
parameters are ensured over the specified temperature range of TA = –40°C to +85°C. Parameters that vary
significantly with operating voltage or temperature are shown in the Typical Characteristics section.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Capacitive Loads
The dynamic characteristics of the OPA167x series are optimized for commonly encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (RS equal to 50 Ω,
for example) in series with the output.
This small series resistor also prevents excess power dissipation if the output of the device becomes shorted.
For more details about analysis techniques and application circuits, see the Feedback Plots Define Op Amp AC
Performance application report, available for download from the TI website (www.ti.com).
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8.2 Typical Application
Contact microphones are useful for amplifying the sound of musical instruments which do not contain electrical
pickups, such as acoustic guitars and violins. Most contact microphones use a piezo element to convert
vibrations in the body of the musical instrument to a voltage which may be amplified or recorded. The low noise
and low input bias current of the OPA1678 make the device an excellent choice for high impedance preamplifiers
for piezo elements. This preamplifier circuit provides high input impedance for the piezo element but has low
output impedance for driving long cable runs. The circuit is also designed to be powered from 48-V phantom
power which is commonly available in professional microphone preamplifiers and recording consoles.
A TINA-TI ™ simulation schematic of the circuit below is available in the Tools and Software section of the
OPA167x product folder.
R1
1.2 k
C2
0.1 F
R14
100
C1
22 F +
ZD1
24 V
½ OPA1678
+
±
VS+
VOUT
VS±
R7 2 k
C5
22 F
+
R10
100
R3
1M
R2
1.2 k
R12
100 k
R5
100 k
TPD1E1B04
Piezo
Contact
Microphone
R8
442
C3 390 pF
C4 390 pF
R6
100 k
R11
100
R15
100
+
R13
100 k
R9 2 k
R4
1M
To
Microphone
Preamplifier
C6
22 F
±
+
½ OPA1678
Figure 35. Phantom-Powered Preamplifier for Piezo Contact Microphones
8.2.1 Design Requirements
• –3-dB Bandwidth: 20 Hz to 20 kHz
• Gain: 20 dB (10 V/V)
• Piezo Element Capacitance: 8 nF (9-kHz resonance)
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Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Power Supply
In professional audio systems, phantom power is applied to the two signal lines that carry a differential audio
signal from the microphone. Figure 36 is a diagram of the system showing 48-V phantom power applied to the
differential signal lines between the piezo preamplifier output and the input of a professional microphone
preamplifier.
6.8 k
R1
R2
6.8 k
48 V
Phantom
Power
+
+
Piezo
Contact
Microphone
Differential
Signal Cable
±
±
Microphone
Preamplifier
Piezo
Preamplifier
Figure 36. System Diagram Showing the Application of Phantom Power to the Audio Signal Lines
A voltage divider is used to extract the common-mode phantom power from the differential audio signal in this
type of system. The voltage at center point of the voltage divider formed by R1 and R2 does not change when
audio signals are present on the signal lines (assuming R1 and R2 are matched). A Zener diode forces the
voltage at the center point of R1 and R2 to a regulated voltage. The values of R1 and R2 are determined by the
allowable voltage drop across these resistors from the current delivered to both op amp channels and the Zener
diode. There are two power supply current pathways in parallel, each sharing half the total current of the op amp
and Zener diode. Resistors R1 and R2 can be calculated using Equation 1:
R1 R2 RPS
VZD
I
§ OPA IZD ·
¨ 2
2 ¸¹
©
6.8 k:
RPS
(1)
A 24-V Zener diode is selected for this design, and 1 mA of current flows through the diode at idle conditions to
maintain the reverse-biased condition of the Zener. The maximum idle power supply current of both op amp
channels is 5 mA. Inserting these values into Equation 1 gives the values for R1 and R2 shown in Equation 2.
24V
24V
6.8 k:
6.8 k: 1.2 k: RPS
§ IOPA IZD ·
§ 5.0 mA 1.0 mA ·
¨
¸
¨ 2
2
2
2 ¸¹
©
¹
©
(2)
Using a value of 1.2 kΩ for resistors R1 and R2 establishes a 1-mA current through the Zener diode and properly
regulate the node to 24 V. Capacitor C1 forms a low-pass filter with resistors R1 and R2 to filter the Zener diode
noise and any residual differential audio signals. Mismatch in the values of R1 and R2 causes a portion of the
audio signal to appear at the voltage divider center point. The corner frequency of the low-pass filter must be set
below the audio band, as shown in Equation 3.
1
1
t
t 13 PF o 22 PF
C1 t
2 ˜ S ˜ R1 || R2 ˜ f 3dB 2 ˜ S ˜ 600 : ˜ 20 Hz
(3)
A 22-μF capacitor is selected because the capacitor meets the requirements for power supply filtering and is a
widely available denomination. A 0.1-µF capacitor (C2) is added in parallel with C1 as a high-frequency bypass
capacitor.
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Typical Application (continued)
8.2.2.2 Input Network
Resistors R3 and R4 provide a pathway for the input bias current of the OPA1678 while maintaining the high
input impedance of the circuit. The contact microphone capacitance and the required
low-frequency response determine the values of R3 and R4. The –3-dB frequency formed by the microphone
capacitance and amplifier input impedance is shown in Equation 4:
1
d 20 Hz
F 3dB
2 ˜ S ˜ (R3 R4 ) ˜ CMIC
(4)
A piezo element with 8 nF of capacitance was selected for this design because the 9-kHz resonance is towards
the upper end of the audible bandwidth, and is less likely to affect the frequency response of many musical
instruments. The minimum value for resistors R3 and R4 is then calculated with Equation 5:
R3 R 4 RIN
RIN t
1
4 ˜ S ˜F
t
3dB ˜ CMIC
1
t 497.4 k:
4 ˜ S ˜ 20 Hz ˜ 8 nF
(5)
1-MΩ resistors are selected for R3 and R4 to ensure the circuit meets the design requirements for –3-dB
bandwidth. The center point of resistors R3 and R4 is biased to half the supply voltage through the voltage
divider formed by R5 and R6. This sets the input common-mode voltage of the circuit to a value within the input
voltage range of the OPA1678. Piezo elements can produce very large voltages if the elements are struck with
sufficient force. To prevent damage, the input of the OPA1678 is protected by a transient voltage suppressor
(TVS) diode placed across the preamplifier inputs. The TPD1E1B04 TVS was selected due to low capacitance
and the 6.4-V clamping voltage does not clamp the desired low amplitude vibration signals. Resistors R14 and
R15 limit current flow into the amplifier inputs in the event that the internal protection diodes of the amplifier are
forward-biased.
8.2.2.3 Gain
R7, R8, and R9 determines the gain of the preamplifier circuit. The gain of the circuit is shown in Equation 6:
R7 R9
AV 1
10 V/V
R8
(6)
Resistors R7 and R9 are selected with a value of 2 kΩ to avoid loading the output of the OPA1678 and
producing distortion. The value of R8 is then calculated in Equation 7:
R7 R9 2 k: 2 k:
R8
444.4 : o 442 :
AV 1
10 1
(7)
Capacitors C3 and C4 limit the bandwidth of the circuit so that signals outside the audio bandwidth are not
amplified. The corner frequency produced by capacitors C3 and C4 is shown in Equation 8. This corner
frequency must be above the desired –3-dB bandwidth point to avoid attenuating high frequency audio signals.
C3 C4 CFB
CFB d
1
2 ˜ S ˜ F 3dB ˜ R7/9
d
1
d 3.98 nF
2 ˜ S ˜ 20 kHz ˜ 2 k:
(8)
390-pF capacitors are selected for C3 and C4, which places the corner frequency approximately 1 decade above
the desired –3-dB bandwidth point . Capacitors C3 and C4 must be NP0 or C0G type ceramic capacitors or film
capacitors. Other ceramic dielectrics, such as X7R, are not suitable for these capacitors and produces distortion.
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Typical Application (continued)
8.2.2.4 Output Network
The audio signal is AC-coupled onto the microphone signal lines through capacitors C5 and C6. The value of
capacitors C5 and C6 are determined by the low-frequency design requirements and the input impedance of the
microphone preamplifier that connect to the output of the circuit. Equation 9 shows an approximation of the
capacitor value requirements, and neglects the effects of R10, R11, R12, and R13 on the frequency response.
The microphone preamplifier input impedance (RIN_MIC) uses a typical value of 4.4 kΩ for the calculation.
C5 C6 COUT
COUT t
2
2 ˜ S ˜ RIN _ MIC ˜ 20 Hz
t
2
t 3.6 PF
2 ˜ S ˜ 4.4 k: ˜ 20 Hz
(9)
For simplicity, the same 22-μF capacitors selected for the power supply filtering are selected for C5 and C6 to
satisfy Equation 9. At least 50-V rated capacitors must be used for C5 and C6. If polarized capacitors are used,
the positive terminal must be oriented towards the microphone preamplifier. Resistors R10 and R11 isolate the
op amp outputs from the capacitances of long cables which may cause instability. R12 and R13 discharge ACcoupling capacitors C4 and C5 when phantom power is removed.
8.2.3 Application Curves
The frequency response of the preamplifier circuit is shown in Figure 37. The –3-dB frequencies are 15.87 Hz
and 181.1 kHz which meet the design requirements. The gain within the passband of the circuit is 18.9 dB,
slightly below the design goal of 20 dB. The reduction in gain is a result of the voltage division between the
output resistors of the piezo preamplifier circuit and the input impedance of the microphone preamplifier. The Aweighted noise of the circuit (referred to the input) is 842.2 nVRMS or –119.27 dBu.
20
19
18
17
Gain (dB)
16
15
14
13
12
11
10
10
100
1k
10k
100k
1M
Frequency (Hz)
C001
Figure 37. Frequency Response of the Preamplifier Circuit for a 8-nF Piezo Element
8.2.4 Other Applications
The low noise and distortion of the OPA167x series make the devices designed for a variety of applications in
professional and consumer audio products. The examples shown here are possible applications where the
OPA167x provides exceptional performance.
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Typical Application (continued)
8.2.4.1 Phono Preamplifier for Moving Magnet Cartridges
The noise and distortion performance of the OPA167x family of amplifiers is exceptional in applications with high
source impedances, which makes these devices a viable choice in preamplifier circuits for moving magnet (MM)
phono cartridges. Figure 38 shows a preamplifier circuit for MM cartridges with 40 dB of gain at 1 kHz.
15 V
MM Phono Input
R1
47 k
V+
C1
150 pF
V±
R2
118 k
R4
127
C2
27 nF
+
½ OPA1678
±
VOUT
-15 V
R3
10 k
R5
100
C5
100 F
Output
R6
100 k
C3
7.5 nF
C4
100 F
Figure 38. Phono Preamplifier for Moving Magnet Cartridges
(Single-Channel Shown)
8.2.4.2 Single-Supply Electret Microphone Preamplifier
The preamplifier circuit shown in Figure 39 operates the OPA1678 as a transimpedance amplifier that converts
the output current from the electret microphone's internal JFET into a voltage. Resistor R4 determines the gain of
the circuit. Resistors R2 and R3 bias the input voltage to half the power supply voltage for proper functionality on
a single-supply.
C3
9V
16 pF
R4
R1
13.7 k
61.9 k
9V
C1
0.1 F
2.2 F
Electret
Microphone
9V
R2
100 k
±
Output
+
R3
100 k
½ OPA1678
C2
2.2 F
Figure 39. Single-Supply Electret Microphone Preamplifier
8.2.4.3 Composite Headphone Amplifier
Figure 40 shows the BUF634 buffer inside the feedback loop of the OPA1678 to increase the available output
current for low-impedance headphones. If the BUF634 is used in wide-bandwidth mode, no additional
components besides the feedback resistors are required to maintain loop stability.
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Typical Application (continued)
12 V
100 F
0.1 F
0.1 F
+
Input
R1
100 k
½
OPA1678
BUF634
±
Output
0.1 F
RBW
0.1 F
100 F
-12 V
R3
R2
200
200
Figure 40. Composite Headphone Amplifier (Single-Channel Shown)
8.2.4.4 Differential Line Receiver With AC-Coupled Outputs
Figure 41 shows the OPA1678 used as an integrator that drives the reference pin of the INA1650, which forces
the output DC voltage to 0 V. This configuration is an alternative to large AC-coupling capacitors which can
distort at high output levels. The low input bias current and low input offset voltage of the OPA1678 make the
device designed for integrator applications.
18 V
-18 V
C5 1 F
C7 1 F
R7
1M
Input Differential
Audio Signals
C6 0.1 F
C1 10 F
C8 0.1 F
18 V
R2
100 k
XLR Connector
R4
100 k
3
2
1
2 IN+ A
OUT A 13
3 COM A
REF A 12
C2 10 F
4 IN- A
VMID(IN) 11
C3 10 F
5 IN- B
VMID(OUT) 10
6 COM B
REF B 9
7 IN+ B
OUT B 8
½
OPA1678
-18 V
R6 1 M
R5
100 k
INA1650
C9
100 nF
Output Single-Ended
Audio Signals
½
OPA1678
±
1
R3 1 M
+
3
VEE 14
±
2
1 VCC
+
R1
100 k
C10
100 nF
XLR Connector
C4 10 F
R8
1M
Figure 41. Differential Line Receiver With AC-Coupled Outputs
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9 Power Supply Recommendations
The OPA167x devices are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications
apply from –40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are shown in the Typical Characteristics section. Applications with noisy or high-impedance power
supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Physically
separate digital and analog grounds, observing the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to
in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 42, keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
+
VIN A
+
VIN B
VOUT A
RG
VOUT B
RG
RF
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors.
Output A
VS+
OUTPUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
V+
RF
Output B
GND
-IN A
OUTPUT B
+IN A
-IN B
RF
RG
VIN A
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VS±
+IN B
Ground (GND) plane on another layer
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible.
Figure 42. Operational Amplifier Board Layout for Noninverting Configuration
10.3 Power Dissipation
The OPA167x series op amps are capable of driving 2-kΩ loads with a power-supply voltage up to ±18 V and full
operating temperature range. Internal power dissipation increases when operating at high supply voltages.
Copper leadframe construction used in the OPA167x series op amps improves heat dissipation compared to
conventional materials. Circuit board layout can also help minimize junction temperature rise. Wide copper traces
help dissipate the heat by acting as an additional heat sink. Temperature rise can be further minimized by
soldering the devices to the circuit board rather than using a socket.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH ® Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount devices. The
evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT-23-6, SOT-235 and SOT-23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used
with terminal strips or may be wired directly to existing circuits.
11.1.1.3 Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of device package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own devices. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer allows the user to create optimized filter designs using a selection of TI operational amplifiers and
passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
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11.2 Documentation Support
11.2.1 Related Documentation
The following documents are relevant to using the OPA167x, and are recommended for reference. All are
available for download at www.ti.com unless otherwise noted.
• Texas Instruments, Source resistance and noise considerations in amplifiers
• Texas Instruments, Single-Supply Operation of Operational Amplifiers
• Texas Instruments, Op Amp Performance Analysis
• Texas Instruments, Compensate Transimpedance Amplifiers Intuitively
• Texas Instruments, Tuning in Amplifiers
• Texas Instruments, Feedback Plots Define Op Amp AC Performance
• Texas Instruments, Active Volume Control for Professional Audio
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA1678
Click here
Click here
Click here
Click here
Click here
OPA1679
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
is a trademark of ~ Texas Instruments.
is a registered trademark of ~ Texas Instruments.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA1678IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
1AW7
OPA1678IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
1AW7
OPA1678IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OP1678
OPA1678IDRGR
ACTIVE
SON
DRG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OP1678
OPA1678IDRGT
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OP1678
OPA1679IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA1679
OPA1679IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA1679
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA1678IDGKR
VSSOP
DGK
8
OPA1678IDGKT
VSSOP
DGK
OPA1678IDR
SOIC
D
OPA1678IDRGR
SON
OPA1678IDRGT
SON
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
DRG
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
DRG
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA1679IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
OPA1679IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA1678IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA1678IDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
OPA1678IDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA1678IDRGR
SON
DRG
8
3000
367.0
367.0
35.0
OPA1678IDRGT
SON
DRG
8
250
210.0
185.0
35.0
OPA1679IDR
SOIC
D
14
2500
367.0
367.0
38.0
OPA1679IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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