AKM AK5406 80msps triple adc for display Datasheet

ASAHI KASEI
[AK5406]
AK5406
80MSPS Triple ADC for Displays
General Description
The AK5406 is an RGB Graphic & D-terminal Signal Process Device in which
integrates 10-Bit 80Mhz AD Converters.
The Device has On-Chip 3 Channels ADCs, Voltage Reference circuit, Programmable
Gain Offset Amplifiers and Black Loop Function which automatically sustains
Clamp Level to an arbitrarily set value.
Features
•
•
•
•
•
•
ADCs 80 MSPS max. (Internally
•
Power Down function
10-bit, Output is reduced to 8-bit)
•
Low Power Dissipation
0.5V ~ 1.0V input signal range
•
3.3V ± 0.3V power supply
Black Loop (Automatic Offset adjust)
•
CMOS
function
•
-40℃ to 85℃
Low Clock Jitter
•
Package 80-LQFP
On-Chip SYNC Separation function
Pedestal Clamp and Mid-Point Clamp function
BIAS
AVDD AVSS PVDD
BYPASS
DVDD DVSS
VREF
RIN
CLAMP
PGA
10bit
ADC
10
BLACK
LOOP
8
ROUT7~0
8
GIN
The same as Rch
BIN
The same as Rch
CLAMP
COAST
SOGIN
VSYNC
HSYNC
GOUT7~0
8
BOUT7~0
DTCLK
SOGOUT
Sync Processing
VSYNCO
HSYNCO
TEST2
Control Serial I/F
TEST SDA SCL
FLT
A0
RESET
Fig. 1 Block Diagram
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ASAHI KASEI
[AK5406]
■ Functional Block Description
Table 1 : Block Description
block
Function
CLAMP
To Clamp Pedestal level of input signal during Clamp period.
PGA
Programmable Gain Amplifier.
It has 8-bit resolution. Full-scale input range of ADC can be
pre-set from 0.5V to 1V.
ADC
10-bit 80 MSPS AD Converter.
BLACK LOOP A loop to settle Pedestal level to the Black set value.
Can be disable by register setting.
VREF
To generate internal reference voltage.
Control Serial I/F Control register with I2C Interface (400KHz).
Sync Processing To generate timing signals such as ADC operating clock, from
Horizontal / Vertical SYNC signal inputs.
SLICER
Comparator to slice SYNC signal part in
SYNC-ON-Green signal.
PLL
PLL to generate Pixel Clock from Horizontal SYNC
signal
COAST
To generate Coast signal from VSYNC.
GEN
CLAMP
To generate Clamp signal from HSYNC.
GEN
CLP
To execute Coast processing on Clamp signal.
COAST
SYNC SEP To separate VSYNC from Slicer output.
CLAMP SEL
CLAMP
1
0
CLAMP GEN
SOGIN
To CLP
CLP COAST
1
0
SLICER
SOGOUT
SOGOUT SEL
HSYNC
HSYNC SEL
1
0
COAST GEN
PLL
1
COAST
HSYNCO
DTCLK
0
COAST
1
1
0
0
HSYNC SEL
COASTGEN
VSYNC
Sync
Separator
1
0
VSYNCO
VSYNC SEL
Fig. 2 Sync Processing
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ASAHI KASEI
[AK5406]
■ Pin Allocations
RESETN
VSYNCO
SOGOUT
HSYNCO
DTCLK
DVSS
DVDD
ROUT7
ROUT6
ROUT5
ROUT4
ROUT3
ROUT2
ROUT1
ROUT0
NC
NC
DVDD
DVSS
GOUT7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
GOUT6
GOUT5
GOUT4
GOUT3
GOUT2
GOUT1
GOUT0
NC
NC
DVSS
DVDD
BOUT7
BOUT6
BOUT5
BOUT4
BOUT3
BOUT2
BOUT1
BOUT0
NC
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
80 LQFP
51
11
（TOP VIEW）
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
AVSS
AVDD
BYPASS
SDA
SCL
A0
RIN
AVSS
AVDD
AVDD
AVSS
SOGIN
GIN
AVSS
AVDD
AVDD
AVSS
BIN
AVDD
AVSS
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AVSS
AVDD
TEST
BIAS
AVSS
PVDD
PVDD
FLT
AVSS
VSYNC
HSYNC
COAST
AVSS
PVDD
TEST2
AVSS
CLAMP
DVDD
DVSS
NC
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ASAHI KASEI
[AK5406]
■ Pin Functions
Table 2 : Pin Functions
Pin name
I/O
Output Pins
64
HSYNCO
DO
62
VSYNCO
DO
63
SOGOUT
DO
Serial Interface (I2C) Pins
57
SDA
DI/
DO
56
SCL
DI
55
AO
DI
61
RESETN
DI
Data Pins
68
ROUT7
DO
~75
~ROUT0
80,
GOUT7
1~7
~GOUT0
12
BOUT7
~19
~BOUT0
Data Clock Pins
65
DTCLK
Clock
Address
Register initialization signal input ( active low ).
RED channel ADC outputs
GREEN channel ADC outputs
BLUE channels ADC outputs
Bit 7 is the MSB. They are output in sync with DTCLK.
When DTCLK phase is modify by Clock Adjust register
setting, these output phases also change in sync with it.
AI
RED channel analog input.
GREEN channel analog input.
BLUE channel analog input.
0.5V~1.0V full scale input. Each input signal is AC-coupled
to each pin and clamp operation is executed.
Horizontal SYNC input.
Reference Clock input to generate DTCLK clock by the
on-chip PLL (it is also possible to input Sync-On-Green
signal on SOGIN pin as Reference Clock).
Active polarity of input signal is selectable by register
setting.
Leading edge is used for this and trailing edge is ignored.
Vertical SYNC input.
HSYNC
DI
31
VSYNC
DI
MS0592-E-01
Data I/O pins
Strobe clock for Data and HSYNCO. It is generated by PLL
and synchronized with internal ADC sampling clock.
Its phase changes in accordance with Clock Phase Adjust
register setting. It is phase-synchronized with HSYNCO and
Data.
30
SOGIN
Horizontal SYNC output.
HSYNC output which is re-configured HSYNC input signal
by internal timing.
It is phase-synchronized with DTCLK. When phase of
DTCLK is modified by Clock Phase Adjust register setting,
this output phase also changes in sync with it.
Vertical SYNC output.
Either VSYNC input or Sync Separator could be output.
Sync-On-Green Slice comparator output.
DO
Input Pins
RIN
54
GIN
48
BIN
43
49
Functions
AI
Sync-On-Green input.
Comparator input pin to extract SYNC signal from
Sync-On-Green signal.
Comparator threshold level is adjustable by register
setting (10 ~ 320mV / step).
When this pin is not used, connect to AVDD directly or
connect to AVSS via a 1nF capacitor.
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38
TEST
[AK5406]
Test pin.
Connect to AVSS. This pin has an on-chip pull-down
resistor.
29
COAST
DI
Clock control coast input.
Upon application of this Coast input, PLL stops to
synchronize with Horizontal SYNC signal and starts to
self-run the oscillation.
It is also possible to use internally generated timing from
VSYNC, without using this pin. Connect to AVSS when
not used.
24
CLAMP
DI
External Clamp input.
Input pin to select timing in order to clamp Video input to
an internal, pre-set value.
26
TEST2
DI
Test pin.
Connect to PVDD through MOS SW internally.
Decoupling capacitor etc. connection pins
58
BYPASS
AO
Bypass capacitor connection pin for Reference Voltage.
Connect a 0.1uF capacitor between this pin and AVSS.
37
BIAS
AO
Bias Current pin for internal Analog circuit.
Connect a 6.8kΩ ±1% resistor between this pin and AVSS.
33
FLT
AO
External Filter connection pin for PLL.
This pin is internally fixed to PVDD at power-down mode.
Power Supply pins
PWR Analog power supply pins.
39 42 AVDD
45 46
51 52
59
DVDD
PWR Digital power supply pins.
11
23 67
78
27
PVDD
PWR Power supply pins for PLL.
34 35
PWR Analog ground pins.
25 28 AVSS
32 36
40 41
44 47
50 53
60
10,22 DVSS
PWR Digital ground pins.
66,79
NC Pins
NC
NC
NC pins. Left open.
8,9,
20,21
76,77
AI : Analog Input pin,
AO : Analog Output pin
DI : Digital Input pin,
DO : Digital Output pin,
PWR : Power Supply /
Ground pin
DI pins be free from Hi-Z input.
DO pins set to be Hi-Z output state by register setting.
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ASAHI KASEI
[AK5406]
Absolute Maximum Ratings
Table 3 : Absolute Maximum Ratings (AVSS, DVSS = 0V : all voltages are referenced to
ground level)
Item
Symbol
Min
Max
Unit
Note
Power Supplies
V
4.5
-0.3
AVDD
Analog
V
4.5
-0.3
DVDD
Digital
V
4.5
-0.3
PVDD
PLL
Input Current
(excluding power
IIN
±10
mA
supply pins)
Analog Input
RIN, GIN, BIN,
VINＡ
AVSS-0.3
AVDD+0.3
V
Voltage
SOGIN
Digital Input
SDA, SCL, A0,
VINL
AVSS-0.3
AVDD+0.3
V
Voltage
RESETN
VSYNC, HSYNC,
Digital Input
VINL2
AVSS-0.3
PVDD+0.3
V
CLAMP, COAST,
Voltage
TEST, TEST2
ROUT,GOUT,BO
UT,
Input Voltage at
HSYNCO,
Hi-Z condition
VONL
DVSS-0.3
DVDD+0.3
V
VSYNCO,
(Data Output pin)
SOGOUT,
DTCLK
Storage
Tstg
-65
150
°C
Temperature
(note) Operation under a condition exceeding above limits may cause permanent damage
to the device. Normal operation is not guaranteed under the above, extreme conditions.
Recommended Operating Conditions
At the power-up, the AK5406 device must be reset using RESETN pin.
Table 4 : Recommended Operating Conditions
(AVSS, DVSS = 0V : all voltages are referenced to ground level)
Item
Symbol
Min
TYP
MAX
Unit
Note
Power Supplies
V
3.6
3.3
3.0
AVDD
Analog
V
3.6
3.3
3.0
DVDD
Digital
V
3.6
3.3
3.0
PVDD
PLL
Operating
Ta
-40
85
°C
Temperature Range
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ASAHI KASEI
[AK5406]
Electrical Characteristics
1) Analog Characteristics
(AVDD = DVDD = PVDD = 3.3V, Ta = 25°C, sampling frequency at 80 MSPS, input
signal frequency = 1MHz, input signal amplitude = -2 dBFS unless otherwise noted )
Table 5.
Item
Symbol
Conditions
MIN TYP
MAX
Unit
Input Range
at maximum gain IRNG1
0.5
V
at minimum gain IRNG2
1.0
V
Input Full Scale
IRNGM at minimum gain
10
%FS
Matching
Static Characteristics
±1.0
±0.5
LSB
Differential Non-Linearity
DNL
(note 1)
LSB
Integral Non-Linearity
INL
(note 1)
±3.0
±1.0
LSB
Offset
VOF
±47
Dynamic Characteristics
S/N
SNR
46
dB
Input Frequency = 7.5MHz
dBc
Cross-Talk
CT
55
PLL Jitter
TJ
(note 2)
300
ps rms
Power Dissipation
Analog
IA
180
mA
Digital
ID
(note 3)
24
mA
PLL
IP
15
mA
Total
IT
219
290
mA
At Power-Down
IPD
(note 4)
1.5
2.6
mA
(note 1) Measured at gain = 80H (Address : 08H, 09H, 0AH)
(note 2) VCO range = 2H, charged pump current = 3H (Address : 05H), PLL Div :
2200(897H), fH=33.75kHz, CLK=74.25MHz
(note 3) Capacitive loadings
CL = 15pF ( DTCLK pin )
CL = 5pF ( ROUT, GOUT, BOUT, HSYNCO, VSYNCO pins )
(note 4) During power-down, SOG Slicer & Slicer VREF and I2C Control circuits are active.
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ASAHI KASEI
[AK5406]
2) Digital Input / Output DC Characteristics
Table 6 : Digital DC Characteristics
(AVDD = DVDD = PVDD = 3.0 ~ 3.6V, AVSS = DVSS= 0v,
Symbo
TY
Item
Condition
MIN
l
P
High Level Input
VIH
A0, RESETN pins
0.7AVDD
Voltage
Low Level Input
VIL
A0, RESETN pins
Voltage
VSYNC, HSYNC,
High Level Input
VIHP COAST,
CLAMP 0.7PVDD
Voltage
pins
VSYNC, HSYNC,
Low Level Input
VILP COAST,
CLAMP
Voltage
pins
Input
Pin
HSYNC,VSYNC,CL
ILIKG
Leakage Current
AMP, COAST pins
ROUT,
GOUT,
BOUT, HSYNCO,
High
Level
VOH VSYNCO,
DVDD-0.5
Output Voltage
SOGOUT pins
IOH=-1mA
ROUT,
GOUT,
BOUT, HSYNCO,
Low Level Output
VOL VSYNCO,
Voltage
SOGOUT pins
IOL=1mA
DTCLK pin
DTCLK pin
High
Level VOHC
DVDD-0.5
IOH= -4mA
Output Voltage
DTCLK pin
DTCLK pin
Low Level Output VOLC
IOL= 4mA
Voltage
ROUT,
GOUT,
BOUT
Hi-Z
Leakage
HSYNCO,
IOZ
Current
VSYNCO,
SOGOUT, DTCLK
pins at Hi-Z output
I2C
High Level Input VIH2 SDA, SCL pins
0.7AVDD
Voltage
I2C
Low Level Input VIL2 SDA, SCL pins
Voltage
I2C
SDA pin,
Low Level Output VOL2
IOL=3mA
Voltage
MS0592-E-01
8
Ta = -40 ~ 85°C)
MAX
Unit
V
0.3AVDD
V
V
0.3PVDD
V
±10
uA
V
0.5
V
V
0.5
V
±10
uA
V
0.3AVDD
V
0.4
V
2008/07
ASAHI KASEI
[AK5406]
3) Switching Characteristics
Table 7 : Switching Characteristics
(AVDD = DVDD = PVDD = 3.0 ~ 3.6V, AVSS = DVSS = 0V, Ta = -40 ~ 85°C, CL of
DTCLK pin = 15pF, CL of ROUT, GOUT, BOUT, HSYNCO pins = 5pF)
Item
Symbol
Condition
MIN
TYP
MAX
Unit
Conversion Speed
maximum fsmax
80
MSPS
minimum fsmin
MSPS
9
DTCLK duty
42
50
58
%
Referenced to the
Falling edge of
Data Skew
tskw
-1.0
4.0
ns
DTCLK
output
(note 1)
HSYNC
Input
15
110
kHz
Frequency
Reset Timing
trst
After the power-up
1
us
(note 1) 1/2 of VDD referenced
DTCLK
ROUT7～0,
tskw
GOUT7～0,
BOUT7～0,
HSYNCO
Fig. 4 Output Timing
PWR
trst
RESETN
Fig. 5 Reset Timing
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ASAHI KASEI
[AK5406]
4) Serial I/F Switching Characteristics
Table 8 : Serial I/F Switching Characteristics
(AVDD = DVDD = PVDD = 3.0 ~ 3.6V, AVSS = DVSS = 0V, Ta = -40 ~ 85°C)
Item
Symbol
Condition
MIN
TYP
MAX
Unit
Bus Free Time
tBUF
1.3
us
Hold Time
0.6
us
tHD:STA
(Start Condition)
Clock Pulse
1.3
us
tLOW
Low Time
Input Signal
300
ns
tR
Rise Time
Input Signal
300
ns
tF
Fall Time
Setup Time
0.6
us
tSU:STA
(Start Condition)
Setup Time
tSU:STO
0.6
us
(Stop Condition)
The above I2C bus related timings are I2C Bus Specifications, and they are not the
device limits.
For details, refer to I2C Bus Specifications.
tBUF
tHD:STA
tR
tF
tSU:STO
SDA
tF
tR
SCL
tLOW
tSU:STA
Fig. 6 Serial Control Timing
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ASAHI KASEI
[AK5406]
Table 9.
(AVDD = DVDD = PVDD = 3.0 ~ 3.6V, AVSS = DVSS = 0V, Ta = -40 ~ 85°C)
Symbol
Condition
MIN
TYP
MAX
Unit
100
Data Setup Time tSU:DAT
ns
(note 1)
0.9
Data Hold Time
tHD:DAT
0.0
us
(note 2)
Clock Pulse
0.6
us
tHIGH
High Time
Item
(note 1) when to use in I2C Bus Standard mode, tSU:DAT≥250ns must be satisfied.
(note 2) when the AK5406 is used on non-extended tLOW bus (used at tLOW
minimum specification), this condition must be satisfied.
tHD:DAT
SDA
tHIGH
tSU:DAT
SCL
Fig. 7 Serial Control Timing (#2)
MS0592-E-01
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=
ASAHI KASEI
[AK5406]
Functional Description
ADC
10-bit 80 MSPS A/D Converter, output is reduced to 8-bit.
Reset Operation
Reset Operation must be executed after the power-up.
Reset pulse can be fed in asynchronous fashion, with a pulse width of longer than 1 us.
Right after the reset operation, registers are set to their default.
PLL Function
The Pixel Clock is re-produced by PLL based on HSYNC to be input.
The AK5406 is corresponds from 9MHz to 80MHz of frequency by adjusting Charged
Pump Current as PLL parameter.
The example of Charged Pump current calculation is shown below, and the closest value
is setting to register (Address 0x03 bit 5:3).
AK5406 PLL Cpcurrent (CPI) calculation :
CPI = ((2pi*fH)/NFRatio)^2*C*N*P / Kvco;
fH : PLL reference signal (Horizontal SYNC signalin [Hz] )
NFRatio : Set to each natural frequency
Reference signal is divided and set to 13.
C: 0.082uF
N: PLL divide ratio (Register Address 0x01, 0x02)
P: 4:<9-32MHz>, 2:<32-64MHz>, 1:<64-80MHz> Clock Frequency range.
Kvco: 130MHz
PLL Coast Funtion
The Pixel Clock is re-produced by PLL based on HSYNC to be input.
Coast mode is to cease its PLL tracking operation and to let VCO self-run.
There are 2 modes in Coast function –
One is HSYNC Pulse Duration Coast where the duration time is selected from
Pre-VSYNC timing as start point and Post-VSYNC timing as stop point, and the other is
to input directly on Coast pin a signal to notify its timing.
( refer to timing diagram 3 ) Coast Timing )
Clamp Function
This is a function to adjust reference level of AC-coupled input signal to match with the
AK5406 internal reference level. It is required to specify a specific period where
reference level of input signal is being input. It is selectable to specify the period by
external CLAMP pin or by register setting. If the clamp period is specified by register,
the position and the period from the trailing edge of HSYNC are set to the register.
( refer to timing diagram 4 ) Clamp Timing #1)
During the clamp period the Analog Clamp circuit (Clamp Block) and the Black Loop
circuit (Black Loop block) are operational at the same timing at the default setting. It is
possible to set the Analog Clamp at the first half of clamp period and Black Loop at the
other half during the clamp period by register setting. ((refer to timing diagram 5)
Clamp timing #2) Clamp function can be coasted as in the case of PLL (( refer to timing
diagram 6) Clamp Coast).
It is also possible by register setting to clamp the minimum value in accordance with
RGB signals or to clamp the center value in accordance with YUV signals (refer to
register address 10H).
Gain Adjust Function
ADC Full-Scale Input Range is adjustable within 0.5V ~ 1V by PGA (Programmable
Gain Amplifier). PGA has an 8-bit resolution.
SYNC Separation Function
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ASAHI KASEI
[AK5406]
VSYNC is extracted from the internal Slicer output.
Black Loop Function, Offset Adjust Function
With a help of Black Loop operation during the Clamp period, offset of internal circuit
can be eliminated and Clamp level is retained to the set value.
Black level is arbitrarily pre-settable for each of 3 channels independently, in the range
from –4 to +20 by Black Loop Setting Value setting register.
In addition to enabling Black Loop function always during the Clamp period, it is also
possible to control Black Loop function to operate or to hold the condition by register
setting.
Black Loop function can be completely disabled.
Only in this case, each of channel offset adjust registers is valid and external offset
adjustment is enabled.
Gain Offset Control diagram below shows its relation.
OFFSET = 1FFH
OFFSET = 0FFH
1.0
Input Voltage (V)
OFFSET = 000H
0.5
OFFSET = 1FFH
OFFSET = 0FFH
0.0
OFFSET = 000H
00H
Gain
FFH
Fig. 8 Gain Offset Control
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ASAHI KASEI
[AK5406]
Control Serial I/F
This is a control register with I2C Serial Interface.
An external pull-up resistor should be connected on SDA pin.
Data on SDA line is captured at the rising edge of SCL.
Make certain that Data on SDA line changes state only during SCL at low condition.
When SDA changes state while SCL is at high condition, it is interpreted to be a Start
condition if the change occurs at the falling transition, and it is to be a Stop condition
if it occurs at the rising transition.
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ASAHI KASEI
[AK5406]
[I2C Slave Address]
I2C Slave Address is selectable to be either 1001100 or 1001101 by AO pin setting.
Table 10 : I2C Address
A0 pin
LO
HI
I2C Slave Address
1001100
1001101
[I2C Write Sequence]
When the Slave Address of the AK5406 Write Mode is received at the First Byte,
Sub-Address at the Second Byte and Data at the Third & Succeeding Bytes are
received.
There are 2 operations in Write sequence –
(a) Single Byte Write Sequence
S
Slave W A
Sub
Address
Address
1b
8b
8b
A
Data
1b
8b
A Stp
1b
Fig. 9a Single Byte Write Sequence
(b) Multiple Byte (m bytes) Write Sequence ( Sequential Write operation )
S
Slave
Address
W
A
1b
8b
Sub
A
Address(n)
8b
Data(n)
1b
8b
A Data(n+1) A
1b
8b
Data(n+m) A Stp
1b
8b
1b
Fig. 9b Sequential Write
(c) Read Sequence
When the Slave Address of the AK5406 Read Mode is received at the First Byte,
Data at the second & Succeeding Bytes transmitted from the AK5406.
S
Slave
Address
8b
W
A
1b
Sub
A rS Slave
Address(n)
Address
8b
1b
8b
R A
1b
Data1
A
Data2
A
Data n
8b
1b
8b
1b
8b
A Stp
1b
Fig. 9c Read Sequence
Abbreviation terms listed above mean :
S,rS
Start Condition
A
0:Acknowledge
(SDA Low)
A
1:Not Acknowledge
(SDA High)
Stp
Stop Condition
R/W
1:Read, 0:Write
To be controlled by the Master device. To be output by micro-computer
normally.
To be controlled by the Slave device. To be output by the AK5406.
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ASAHI KASEI
[AK5406]
Reference register address
07H : (HSYNCO WIDTH)
0EH : HSYNC POL, HSYNCO POL
Timing Charts
1) Output Timing
leading edge
HSYNC
R(GB)IN
pipe-line delay (12 clocks )
PX0
PX1
PX2
(ADCLK)
DTCLK
R(G,B)OUT
D0
HSYNCO
D1
D2
D3
2 clocks
register set value (HSYNCO width) -1
Fig. 10 Output Timing
2) 4 : 2 : 2 Output Mode Timing
leading edge
HSYNC
R(GB)IN
pipe-line register ( 12 clocks )
PX0
PX1
PX2
(ADCLK)
DTCLK
GOUT
Y0
Y1
Y2
ROUT
U0
V1
U2
HSYNCO
2 clocks
U/V alternative output
register set value ( HSYNCO width ) -1
Fig. 11
MS0592-E-01
4 : 2 : 2 Output Mode Timing
16
Reference register address
15H : Output Format
2008/07
ASAHI KASEI
[AK5406]
Reference register address
0FH : COAST SEL, COAST POL
12H : PRE COAST
13H : POST COAST
3) Coast Timing
when COAST pin is not used
VSYNC
HSYNC
(CSYNC)
m m-1 m-2
3
2
1
1
2
3
n-2
n-1 n
8 pixels clock period
COAST
(internal)
register (PRE-COST) set value (m)
8 pixels clock period
register (POST-COAST) set value (n)
COAST period
Fig. 13 COAST Timing
(note) Since PRE-COAST time is counted, based on # of lines in the previous Field,
there is a case in the interlaced signal mode that COAST period may slightly differ
between Odd Field case and Even Field case.
*525i Mode COAST example
[Field 1]
Line No.
524
525
1
2
3
4
5
6
7
8
9
10
11
12
VSYNC
HSYNC
(CSYNC)
257
258
line # retained
259 260 261 262 263 264
1
2
265
3
4
5
6
7
8
272
273
274
264
(internal)
265-6=259
COAST
(internal)
[Field 2]
Line No.
261
262
263
264
265
266
267
268
269
270
271
VSYNC
HSYNC
(CSYNC)
258
line # retained
259 260 261 262 263 264 265
1
264
2
3
4
5
6
7
265
(internal)
COAST
264-6=258
(internal)
equivalent pulse period
vertical sync period
equivalent pulse period
（in case of register pre-coast = 6, register post-coast = 5）
Fig. 14 COAST Timing ( 525i Mode Coast example )
MS0592-E-01
17
2008/07
8
ASAHI KASEI
[AK5406]
when COAST pin is used
input signal fed on COAST pin is used as is, as internal coast signal.
normal leading edge without coast
leading edge to be coasted
HSYNC
COAST
Fig. 15 COAST Timing ( when COAST pin is used )
Reference register address
0FH : CLAMP SEL, CLAMP POL
05H : CLP PLACE
06H : CLP DURATION
4) Clamp Timing 1
when CLAMP pin is not used
trailing edge
HSYNC
ADCLK
(internal)
CLAMP
(internal)
Register (CLP PLACE) set value (m)
Register (CLP DURATION) set value (n)
Fig. 16 Clamp Timing
when CLAMP pin is used
Externally feds clamp timing pulse from CLAMP pin.
Clamp timing pulse be sampled by ADCLK then used internally.
CLAMP
ADCLK
(internal)
Internal CLAMP
Fig. 17 Clamp Timing
MS0592-E-01
18
2008/07
ASAHI KASEI
[AK5406]
5) CLAMP Timing 2
When register (LOOP DISABLE) is set to value (m) other than 0, the clamp period is
divided into 2 half where it is possible that the Clamp Circuit operational at First half
of the period (m pixels clock) and Black Loop at the other half.
When m = 0 (reset value), the Clamp Circuit and the Black Loop are operate at the
same timing.
CLAMP
(internal)
1
2
m-2
m-1
m
ADCLK
(internal)
Block Loop operation
Clamp Circuit operation
register (LOOP DISABLE) set value
Fig. 18 Clamp Timing (#2)
Reference register address
26H : PRE CLPCOAST
27H : POST CLPCOAST
6) COAST Timing for Clamp
VSYNC
HSYNC
(CSYNC)
m
m-1
3
2
1
1
2
3
n
COAST
(internal)
register（PRE-CLPCOAST）set value(m)
register（POST-CLPCOAST）set value(n)
CLAMP COAST Period
Fig. 19 Clamp Coast Timing
(note) Since PRE CLPCOAST time is counted, based on # of lines in the previous Field,
there is a case in the interlaced signal mode that COAST period may slightly differ
between Odd Field and Even Field case.
For details, refer to (3) COAST Timing section.
MS0592-E-01
19
2008/07
ASAHI KASEI
[AK5406]
Control Register
Table 11 : Register map
Sub
R/W
Default
Adrs
Or
Bits
Value
RO
00H
RO
7:0
10101110
01H
R/W
7:0
01101001
02H
R/W
7:4
1101****
03H
R/W
04H
05H
06H
R/W
R/W
R/W
7:6
5:3
7:3
7:0
7:0
01******
**001***
10000***
10000000
10000000
07H
R/W
7:0
00100000
08H
R/W
7:0
10000000
09H
R/W
7:0
10000000
0AH
R/W
7:0
10000000
0B-0DH
RO
7:0
00000000
0EH
R/W
6
*1******
5
**0*****
3
****0***
2
*****0**
0
*******0
7
0*******
6
5
*1******
**0*****
3
****1***
1
******1*
7:3
2
10111***
*****0**
1
******0*
0
*******0
0FH
10H
R/W
R/W
MS0592-E-01
Register
Name
Function
CHIPID
Device ID number
PLL
DIV Upper 8-bit PLL divider ratio[11:4]
（MSB）
PLL
DIV
（LSB）
PLL VCO
PLL CP
PHADJ
CLP PLACE
CLP
DURATION
HSYNCO
WIDTH
RED GAIN
GREEN
GAIN
BLUE GAIN
Lower 4-bit
PLL divider ratio[3:0]
Bit [7:6] PLL VCO range
Bit [5:3] PLL Charged Pump current
Clock phase adjust
(1LSB = T/32)
Clamp position
Clamp period
HSYNCO pulse width
Red channel gain adjust
Green channel gain adjust
Blue channel gain adjust
Reserved
HSYNC POL
Bit 6 : HSYNC input polarity setting
( 0 : Low 1 : Hi )
HSYNCO
Bit 5 : HSYNCO output polarity setting
POL
( 0 : Hi 1 : Low )
HSYNC SEL Bit 3 : Hsync select
( 0 : HSYNC 1: Sync-on-Green )
VSYNC POL Bit 2 : VSYNCO inversion
( 0 : INV 1 : No INV )
VSYNC SEL Bit 0 : VSYNC select
( 0 at power-down(PDN=0) )
(0 : VSYNC 1 : Sync Separator Signal )
CLAMP SEL Bit 7: Clamp signal select
( 0:HSYNC 1:CLAMP pin )
CLAMP POL Bit 6: Clamp polarity ( 0 : Hi 1 : Low )
COAST SEL Bit 5: Coast select
( 0 : COAST Pin 1 : VSYNC )
COAST POL Bit 3: Coast polarity setting
( 0 : Low 1 : Hi )
PDN
Bit 1: Power-down
( 0 : power-down 1 : normal operation )
SOGTH
Sync-on- Green threshold level setting
RED
CLP Bit 2: Red channel clamp level setting
LVL
( 0 : Minimum value 1 : Mid value )
GREEN CLP Bit 1: Green channel clamp level setting
LVL
( 0 : Minimum value 1 : Mid value )
BLUE CLP Bit 0: Blue channel clamp level setting
LVL
( 0 : Minimum value 1 : Mid value )
20
2008/07
ASAHI KASEI
[AK5406]
Sub
Adrs
11H
12H
13H
14H
15H
R/W
Or RO
R/W
R/W
R/W
RO
R/W
Bits
7:0
7:0
7:0
7:0
1
Default
Value
00100000
00000000
00000000
00000000
******1*
16H
17H
R/W
R/W
7:0
0
********
*******1
18H
R/W
7:0
00000000
19H
R/W
0
*******1
1AH
R/W
7:0
00000000
1BH
R/W
0
*******1
1CH
R/W
7:0
00000000
MS0592-E-01
Register
Name
SSEPTH
PRE COAST
POST COAST
RESERVE
OUTPUT
FORMAT
RED OFFSET
(MSB)
RED OFFSET
(LSB)
GREEN
OFFSET
(MSB)
GREEN
OFFSET
(LSB)
BLUE OFFSET
(MSB)
BLUE OFFSET
(LSB)
21
Function
Sync Separator threshold level setting
Pre-Coast
Post-Coast
Reserved
Bit1 : Output Format
(0: 4:2:2, 1:4:4:4)
Don’t care
Red channel offset adjust (MSB)
Red channel offset adjust (LSB)
Green channel offset adjust (MSB)
Green channel offset adjust (LSB)
Blue channel offset adjust (MSB)
Blue channel offset adjust (LSB)
2008/07
ASAHI KASEI
[AK5406]
Table 12 : Black Loop Registers
Sub
R/W
Default
Adrs
Or
Bits
Value
RO
1DH
R/W
0
*******0
Register
Name
RED BLK LVL
(MSB)
RED BLK LVL
(LSB)
GREEN
BLK
LVL
(MSB)
GREEN
BLK
LVL
(LSB)
BLUE BLK LVL
(MSB)
BLUE BLK LVL
(LSB)
LBW
LOOPOFFRNG
LOOPMODE
1EH
R/W
7:0
00000000
1FH
R/W
0
*******0
20H
R/W
7:0
00000000
21H
R/W
0
*******0
22H
R/W
7:0
00000000
23H
R/W
7:5
4:3
2
000*****
***00***
*****0**
1
0
******0*
*******0
LOOPHOLD
VSYNC
UPDATE
6
*0******
COASTGEN SEL
5
4:3
**0*****
***11***
CLPBW
Fixed Bit
2
*****0**
SOGOUT POL
1
******0*
SOGOUT SEL
0
*******0
DOFIX
24H
R/W
25H
26H
27H
R/W
R/W
R/W
7:0
7:0
7:0
00000000
00000000
00000000
28H
R/W
7:6
11******
LOOP DISABLE
PRE CLPCOAST
POST
CLPCOAST
DATA DRIVE
29H
R/W
5:4
7:6
5:3
2:1
0
**11****
10******
**101***
*****00*
*******0
CLOCK DRIVE
Reserved
IN RANGE
Reserved
Reserved
2AH
2BH
2CH
R/W
R/W
RO
6:0
3:0
7:0
*0111001
******00
00000000
Reserved
MS0592-E-01
22
Function
RED channel black loop setting value
(MSB)
RED channel black loop setting value
(LSB)
GREEN channel black loop setting value
(MSB)
GREEN channel black loop setting value
(LSB)
BLUE channel black loop setting value
(MSB)
BLUE channel black loop setting value
(LSB)
Black Loop bandwidth
Black Loop coring bandwidth control
Black Loop mode
(0 : loop enable 1 : loop disable)
retention of black loop condition
(0 : active 1 : condition retained)
limit black level update frequency to
every 64 VSYNC
COASTGEN input setting
(0: VSYNC 1 : SYNC SEP )
Clamp bandwidth setting
Used in fixed condition. Write “11” when
to write.
SOGOUT polarity
( 0 : normal 1 : inverted )
SOGOUT signal select
( 0 : SOG 1 : HSYNC )
Output level at power-down mode
( 0 : fixed low 1 : fixed high )
Black loop off period during Clamp period
Pre-Coast for clamp signal
Post-Coast for clamp signal
ROUT,GOUT,BOUT,HSYNCO,VSYNCO,
SOGOUT pin drivability
DTCLK pin drivability
reserved
accelerate range control of black loop
setting
Reserved
reserved
Do not write value other
than “0”
Reserved
Reserved
Reserved
2008/07
ASAHI KASEI
[AK5406]
TEST Register
AK5406 has test register address 0x20 ~ 0x30, which could be accessed in normal mode.
Do not write without default.
2DH
2EH
2FH
30H
R/W
R/W
R/W
R/W
7:0
7:0
7:0
7:0
00000000
00000000
00100000
00000000
TEST
TEST
TEST
TEST
Default value of AK5406
Adr
R/W
default
00H
RO
AEH
01H
R/W
69H
02H
R/W
D0H
03H
R/W
48H
04H
R/W
80H
05H
R/W
80H
06H
R/W
80H
07H
R/W
20H
08H
R/W
80H
09H
R/W
80H
0AH
R/W
80H
0BH
RO
00H
0CH
RO
00H
0DH
RO
00H
0EH
R/W
40H
0FH
R/W
4AH
10H
R/W
B8H
11H
R/W
20H
12H
R/W
00H
13H
R/W
00H
14H
RO
00H
15H
R/W
02H
16H
R/W
00H
17H
R/W
01H
18H
R/W
00H
19H
R/W
01H
1AH
R/W
00H
1BH
R/W
01H
1CH
R/W
00H
1DH
R/W
00H
1EH
R/W
00H
1FH
R/W
00H
MS0592-E-01
Default Value : 0x00
Default Value : 0x00
Default Value : 0x20
Default Value : 0x00
Adr
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
23
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
default
00H
00H
00H
00H
18H
00H
00H
00H
F0H
A8H
39H
00H
00H
2008/07
ASAHI KASEI
[AK5406]
Description of Register Contents
Default value is meshed
Sub Address 00H CHIP ID
When it is read, device ID number (ADH) is returned.
Default : 69DH
Sub Address 01H ~ 02H PLL DIV
01H
02H
Decimal
PLL multiplier ratio
[7:0]
[7:4]
notation of 01H
[7:0]&02H [7:4]
00H
0H
0
00H
1H
1
Inhibited
:
:
:
0DH
DH
221
0DH
EH
222
223
0DH
FH
223
224
0EH
0H
224
225
:
:
:
:
FFH
FH
4095
4096
“set-value plus one” becomes multiplier ratio of PLL.
Write operation of MSB side bits ( sub address 01H ) does not initiate PLL operation,
and after LSB side data ( sub address 02H ) is written, a multiplier ratio becomes
valid and PLL operation is executed.
Sub Address 03H
[7:6] PLL VCO
[7:6]
00
01
10
11
PLL VCO operating range
9~32MHz
32~64MHz
64~80MHz
Inhibited
[5:3] PLL CP
[5:3]
000
001
010
011
100
101
110
111
PLL charge pump current
50uA
100uA
150uA
250uA
350uA
500uA
750uA
Inhibited
MS0592-E-01
24
2008/07
ASAHI KASEI
[AK5406]
Sub Address 04H PHADJ
[7:3]
ADC sampling clock phase
00H
-180°
advances
01H
-168.75°
↑
:
:
0EH
-22.5°
0FH
-11.25°
10H
standard
11H
+11.25°
12H
+22.5°
↓
:
:
delayed
1EH
+157.5°
1FH
+168.75°
Each single step is equal to 11.25 degrees.
A larger number reflects direction of a bigger delay.
Sub Address 05H CLP PLACE
Default : 80H
Default : 80H
Sub Address 06H CLP DURATION
Clamp timing can be internally generated when CLAMP SEL is set to “0”.
The periods of clamping is start from trailing edge of HSYNC after the delayed of CLP
PLACE pixels and its continue according to the setting of CLP DURATION pixels
value. (refer to timing chart 4)
Do not set CLP DURATION to “0” when CLP PLACE is set to “0”,”1”,”2” value.
Default : 20H
Sub Address 07H HSYNCO WIDTH
This is to set the pulse width of Horizontal SYNC signal which is re-configured by PLL
and is output on HSYNCO pin ( refer to timing charts 1 & 2 ).
Do not write this register value to “0”.
RED (GREEN,BLUE) GAIN
Input range
Gain
[Vpp]
00H
0.377
High gain
01H
0.380
↑
02H
0.383
:
:
7FH
0.751
80H
0.754
81H
0.757
↓
:
:
Low gain
FDH
1.123
FEH
1.126
FFH
1.129
(note) PGA Gain is shown by 543/(128 + N) where (N = 0 ~ 255(DEC)).
PGA Gain is set until ADC input range becomes 1.6Vpp.
Sub Address 08H ~ 0AH
[7:0]
MS0592-E-01
25
2008/07
ASAHI KASEI
[AK5406]
Sub Address 0EH
[6] HSYNC POL
[6]
0
1
[5] HSYNCO POL
[5]
0
1
[3] HSYNC
SEL
[3]
0
1
[2] VSYNC
POL
[2]
0
1
HSYNC input pin polarity
Active low
( leading edge to fall )
Active high
( leading edge to rise )
HSYNCO output pin polarity
Active high
( leading edge to rise )
Active low
( leading edge to fall )
HSYNC signal to be input to
PLL
HSYNC pin
Sync-On-Green SLICER
output
Signal to be input to Sync
Separator
HSYNC pin
Sync-On-Green SLICER output
VSYNCO output pin polarity
Inverted VSYNC
Normal VSYNC
SEL
[0]
VSYNC select
0
VSYNC
1
Sync Separator signal
(note) Sync Separator circuit is in power down, when bit 1 of PDN register at Sub
Address 0FH is “0”.
[0] VSYNC
MS0592-E-01
26
2008/07
ASAHI KASEI
[AK5406]
Sub Address 0FH
[7] CLAMP SEL
[7]
0
1
[6] CLAMP
[5] COAST
[3] COAST
POL
[6]
0
1
SEL
[5]
0
1
Clamp signal to be used at CLP
Internally generated signal from
HSYNC
CLAMP pin
CLAMP input pin polarity
Active high
Active low
Signal to be used as PLL COAST
COAST pin
Internally generated signal from
VSYNC
POL
[3]
0
1
COAST input pin polarity
Active low
Active high
[1] PDN
[1]
Power-down control
0
Power-down
1
Normal operation
Sub Address 10H
[7:3] SOGTH
[7:3]
00H
01H
:
1EH
1FH
[2:0] RED(GREEN,BLUE)
0
1
MS0592-E-01
Operating functional blocks
VREF
Sync-On-Green SLICER
Total circuit
Default : 17H
SOG SLICER threshold level
(upward direction from SOG clamp level)
320mV
310mV
:
20mV
10mV
CLP
LVL
Input clamp level
Minimum level
Center level
27
2008/07
ASAHI KASEI
[AK5406]
Sub Address 11H SSEPTH
[7:0]
Sync Separator threshold level
Wider pulse width
FFH
↑
FEH
:
20H
Standard
:
↓
01H
Narrower pulse width
00H
Sub Address 12H PRE COAST
Sub Address 13H POST COAST
Parameters in order to internally generate PLL COAST signal from VSYNC are set.
It is valid only when the COAST SEL bit is “1”.
In the PRE-COAST register, # of preceding HSYNC periods to be coasted prior to
VSYNC signal, is set and in the POST COAST register, # of succeeding HSYNC
periods to be coasted after VSYNC signal, is set (refer to timing chart 3).
Sub Address 15H
[1] OUTFORMAT
[4]
0
1
Output Format
4:2:2
4:4:4
Input & Output signals vs Channel relation is listed in the following table when 4:2:2
output format is selected ( refer to timing chart 1 & 2 ).
Channel
Red
Green
Blue
MS0592-E-01
Input signal
V
Y
U
Output signal
U/V
Y
Hi-Z
28
2008/07
ASAHI KASEI
[AK5406]
Sub Address 17H ~ 1CH RED(GREEN, BLUE)OFFSET
[0],[7:0]
OFFSET adjust ( addition / subtraction ) values
1FFH
-64 LSB
1FEH
-63.75 LSB
:
:
100H
-0.25 LSB
0FFH
0 LSB
0FEH
+0.25 LSB
:
:
001H
+63.5 LSB
000H
+63.75 LSB
OFFSET of each channel is adjusted in 9-bit resolution.
Its center value is 0FFH and it is adjusted in 1/4 LSB per single step.
OFFSET adjust is valid only when black loop is disable ( LOOP MODE = 1 ).
Data Write of MSB bits does not affect the operation and Data value becomes valid
when Data write of LSB bits is made.
Sub Address 1DH ~ 22H RED (GREEN, BLUE) BLK LVL
BLKLVL
Black Loop setting values
[0], [7:0]
At minimum clamp level setting
At center clamp level setting
(CLP LVL = 0)
(CLP LVL=1)
011111111
Inhibited
Inhibited
011111110
Inhibited
Inhibited
:
:
:
001010001
Inhibited
:
001010000
20
:
001001111
19.75
:
:
:
000011101
7.25
Inhibited
000011100
7
135
000011011
6.75
134.75
:
:
000000010
0.5
128.5
000000001
0.25
128.25
000000000
0
128 (200H)
111111111
-0.25
127.75
111111110
-5
127.5
:
:
:
111110001
-3.75
124.25
111110000
-4
124
111101111
Inhibited
123.75
:
:
111100001
:
120.25
111100000
:
120
111011111
:
Inhibited
::
:
100000001
Inhibited
Inhibited
100000000
Inhibited
Inhibited
Data Write of MSB bits does not affect operation, and Data value becomes valid when
Data Write of LSB bits are made.
MS0592-E-01
29
2008/07
ASAHI KASEI
[AK5406]
Sub Address 23H
[7:5] LOOPBW
LOOPBW
011
010
:
001
000
111
:
101
100
[4:3] LOOPOFFRNG
LOOPOFFRNG
00
01
10
11
[2] LOOPMODE
LOOPMODE
0
1
[1] LOOPHOLD
LOOPHOLD
0
1
Black Loop bandwidth
FAST
↑
Standard
↓
SLOW
Black level coring control
No coring
±0.25 LSB
±1.5 LSB
±1.0 LSB
Black Loop mode
Black Loop enable
(BLK LVL register valid)
Black Loop disable
(OFFSET register valid)
Black Loop condition
Black Loop operation
Hold of Black Loop condition
[0] VSYNC UPDATE
VSYNC UPDATE
Update timing of the Black loop Offset
correction
0
Corrected value of Black Loop Offset is updated
at every HSYNC timing
1
Corrected value of Black Loop Offset is updated
at every 64 VSYNC timing
*OFFSET Integrator of the Black Loop is updated at every HSYNC timing,
regardless of this bit setting.
Only the update timing of the Offset Correction amounts which is added or
subtracted to/from the ADC output is altered by this bit.
MS0592-E-01
30
2008/07
ASAHI KASEI
[AK5406]
Sub Address 24H
[6] COASTGEN SEL
COASTGEN SEL
COASTGEN input setting
0
VSYNC pin
1
Sync Separator output
(note) when COASTGEN SEL is set to “1”, please select the Sync Separator signal for
VSYNC SEL at Sub Address 0EH bit “0”.
[5] CLPBW
CLP BW
0
1
Clamp input / output
current
600uA
150uA
Clamp bandwidth
Standard
SLOW
[4:3] “1” is written to each of these 2 bits.
[2] SOGOUT POL
SOGOUT POL
Signal polarity to be output on
SOGOUT pin
0
Non-inverted
1
Inverted
(note) Polarity of the selected signal by SOGOUT SEL register is altered when it is
output on SOGOUT pin.
[1] SOGOUT SEL
SOGOUT SEL
0
1
Signal to be output on SOGOUT pin
SOG SLICER output
Input signal on HSYNC pin
[0] DOFIX
DOFIX
Output level at power-down
0
Fixed low
1
Fixed high
(note) Compatible pins : ROUT7-0, GOUT7-0, BOUT7-0, , HSYNCO, VSYNCO,
SOGOUT, DTCLK.
MS0592-E-01
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ASAHI KASEI
[AK5406]
Sub Address 25H LOOP DISABLE
When this register value(m) is set to value other than “0”, it is possible to divide the
clamp period into two half, where the First half is Clamp circuit operational (m pixels
clock) and Black Loop operation in the other half. (refer to timing chart 5)
When set this register value, the value must be smaller than CLP DURATION value.
Default : 00H
Sub Address 26H PRE CLPCOAST
Default : 00H
Sub Address 27H POST CLPCOAST
Parameters to coast Clamp signal are set.
In the PRE COAST register, # of preceding HSYNC periods to be coasted after VSYNC
signal, is set in the POST CLPCOAST register, # of succeeding HSYNC periods to be
coasted after VSYNC signal, is set. (refer to timing chart 6)
Sub Address 28H
[7:6] DATA DRIVE
DATA DRIVE
00
01
10
11
ROUT, GOUT, BOUT, HSYNCO,
VSYNCO, SOGOUT pin drivability
Hi-Z
Hi-Z
MAX x 1/4
MAX
[5:4] CLOCK DRIVE
CLOCK DRIVE
00
01
10
11
Sub Address 29H
[3:1] IN RANGE
IN RANGE
000
001
010
011
100
101
110
111
DTCLK pin drivability
Hi-Z
Hi-Z
MAX x 1/4
MAX
Accelerate range control of black loop setting
No acceleration
Non-boosted bandwidth when it settles within ±0.25 LSB
Non-boosted bandwidth when it settles within ±0.5 LSB
Non-boosted bandwidth when it settles within ±0.75 LSB
Non-boosted bandwidth when it settles within ±1 LSB
Non-boosted bandwidth when it settles within ± 2 LSB
Non-boosted bandwidth when it settles within ±3 LSB
Non-boosted bandwidth when it settles within ±4 LSB
Sub Address 2AH [6:0] Reserve
Sub Address 2BH [3:0] Reserve
MS0592-E-01
1 Default : 39H
1 Default : 00H Reserved.
32
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ASAHI KASEI
[AK5406]
Recommended External Component Connection Examples ( part 1 )
Analog Power Supply
0.1uF
AVDD
AVSS
0.1uF
PVDD
AVSS
Analog Ground
Digital Power Supply
0.1uF
DVDD
DVSS
Digital Ground
Analog Power Supply
8.2nF
FLT
2.7kΩ
82nF
Fig. 17 Recommended External Component connection examples
MS0592-E-01
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ASAHI KASEI
[AK5406]
Recommended External Component Connection Examples ( part 2 )
RIN
GIN
BIN
0.1uF
0.1uF
0.1uF
1nF
SOGIN
BYPASS
0.1uF
Analog Ground
BIAS
6.8kΩ ±1%
Analog Ground
Fig. 18 Recommended External Component connection examples ( part 2 )
MS0592-E-01
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ASAHI KASEI
[AK5406]
Package Marking
AK 5 4 0 6 X Q
XXXXAAA
Contents of XXXXAAA
XXXX: Production date (numbers)
AAA : lot number (alphabet)
MS0592-E-01
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ASAHI KASEI
[AK5406]
Package Outline Dimensions
14.0±0.2
12.0±0.2
41
61
40
80
21
12.0±0.2
1
20
0゜～10゜
0.20±0.1
MS0592-E-01
0.08
0.50±0.2
0.10
36
M
+0.15
0.10 -0.10
+0.10
0.125-0.05
0.50
1.85MAX
1.25TYP
1.40±0.2
14.0±0.2
60
2008/07
ASAHI KASEI
[AK5406]
IMPORTANT NOTICE
These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the
sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to
current status of the products.
AKEMD assumes no liability for infringement of any patent, intellectual property, or
other rights in the application or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
AKEMD products are neither intended nor authorized for use as critical
componentsNote1) in any safety, life support, or other hazard related device or
systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As
used here:
Note1) A critical component is one whose failure to function or perform may
reasonably be expected to result, whether directly or indirectly, in the loss of the
safety or effectiveness of the device or system containing it, and which must
therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life
support or maintenance of safety or for applications in medicine, aerospace, nuclear
energy, or other fields, in which its failure to function or perform may reasonably
be expected to result in loss of life or in significant injury or damage to person or
property.
It is the responsibility of the buyer or distributor of AKEMD products, who distributes,
disposes of, or otherwise places the product with a third party, to notify such third
party in advance of the above content and conditions, and the buyer or distributor
agrees to assume any and all responsibility and liability for and hold AKEMD harmless
from any and all claims arising from the use of said product in the absence of such
notification.
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2008/07