Fairchild FQI4P40 400v p-channel mosfet Datasheet

FQB4P40 / FQI4P40
August 2000
QFET
TM
FQB4P40 / FQI4P40
400V P-Channel MOSFET
General Description
Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for electronic lamp ballast based on complimentary
half bridge.
•
•
•
•
•
•
-3.5A, -400V, RDS(on) = 3.1Ω @VGS = -10 V
Low gate charge ( typical 18 nC)
Low Crss ( typical 11 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
S
D
!
●
●
G!
▶ ▲
G
S
●
D2-PAK
G D S
FQB Series
I2-PAK
FQI Series
!
D
Absolute Maximum Ratings
Symbol
VDSS
ID
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
FQB4P40 / FQI4P40
-400
Units
V
-3.5
A
- Continuous (TC = 100°C)
IDM
Drain Current
- Pulsed
(Note 1)
-2.2
A
-14
A
VGSS
Gate-Source Voltage
± 30
V
EAS
Single Pulsed Avalanche Energy
(Note 2)
260
mJ
IAR
Avalanche Current
(Note 1)
-3.5
A
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C) *
(Note 1)
8.5
-4.5
3.13
mJ
V/ns
W
85
0.68
-55 to +150
W
W/°C
°C
300
°C
dv/dt
PD
TJ, TSTG
TL
(Note 3)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
--
Max
1.47
Units
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient *
--
40
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
--
62.5
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
-400
--
--
V
--
0.36
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = -250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
VDS = -400 V, VGS = 0 V
--
--
-1
µA
VDS = -320 V, TC = 125°C
--
--
-10
µA
Gate-Body Leakage Current, Forward
VGS = -30 V, VDS = 0 V
--
--
-100
nA
Gate-Body Leakage Current, Reverse
VGS = 30 V, VDS = 0 V
--
--
100
nA
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-3.0
--
-5.0
V
RDS(on)
Static Drain-Source
On-Resistance
VGS = -10 V, ID = -1.75 A
--
2.44
3.1
Ω
gFS
Forward Transconductance
VDS = -50 V, ID = -1.75 A
--
2.7
--
S
--
520
680
pF
--
80
105
pF
--
11
15
pF
--
13
35
ns
--
55
120
ns
--
35
80
ns
--
37
85
ns
--
18
23
nC
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = -200 V, ID = -3.5 A,
RG = 25 Ω
(Note 4, 5)
VDS = -320 V, ID = -3.5 A,
VGS = -10 V
(Note 4, 5)
--
3.8
--
nC
--
9.4
--
nC
A
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
-3.5
ISM
--
--
-14
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = -3.5 A
Drain-Source Diode Forward Voltage
--
--
-5.0
V
trr
Reverse Recovery Time
--
260
--
ns
Qrr
Reverse Recovery Charge
--
1.4
--
µC
VGS = 0 V, IS = -3.5 A,
dIF / dt = 100 A/µs
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 37mH, IAS = -3.5A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ -3.5A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, August 2000
FQB4P40 / FQI4P40
Elerical Characteristics
VGS
-15.0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V
Bottom : -5.5 V
1
1
10
Top :
0
10
-I D , Drain Current [A]
-I D, Drain Current [A]
10
-1
10
※ Notes :
1. 250μs Pulse Test
2. TC = 25℃
-2
0
10
150℃
25℃
-55℃
※ Notes :
1. VDS = -50V
2. 250μs Pulse Test
-1
10
-1
0
10
10
1
10
2
10
4
6
8
10
-VGS , Gate-Source Voltage [V]
-VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
8
1
VGS = - 10V
6
-I DR , Reverse Drain Current [A]
RDS(on) [ Ω ],
Drain-Source On-Resistance
10
VGS = - 20V
4
2
※ Note : TJ = 25℃
0
0
10
150℃
25℃
※ Notes :
1. VGS = 0V
2. 250μs Pulse Test
-1
0
3
6
9
12
10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-ID , Drain Current [A]
-VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
1200
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
800
Ciss
600
Coss
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
400
Crss
200
0
-1
10
10
-V GS , Gate-Source Voltage [V]
1000
Capacitance [pF]
FQB4P40 / FQI4P40
Typical Characteristics
VDS = -80V
VDS = -200V
8
VDS = -320V
6
4
2
※ Note : ID = -3.5 A
0
0
10
1
10
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
0
2
4
6
8
10
12
14
16
18
20
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A, August 2000
(Continued)
2.5
1.2
2.0
1.1
RDS(ON) , (Normalized)
Drain-Source On-Resistance
-BV DSS , (Normalized)
Drain-Source Breakdown Voltage
FQB4P40 / FQI4P40
Typical Characteristics
1.0
※ Notes :
1. VGS = 0 V
2. ID = -250 μA
0.9
0.8
-100
-50
0
50
100
150
1.5
1.0
※ Notes :
1. VGS = -10 V
2. ID = -1.75 A
0.5
0.0
-100
200
-50
o
0
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
2
4
10
Operation in This Area
is Limited by R DS(on)
1
3
100 µs
1 ms
-I D, Drain Current [A]
-I D, Drain Current [A]
10
10 ms
DC
0
10
-1
10
※ Notes :
2
1
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-2
10
0
1
10
2
10
0
25
3
10
10
50
100
125
150
Figure 10. Maximum Drain Current
vs. Case Temperature
0
D = 0 .5
※ N o te s :
1 . Z θ J C ( t ) = 1 . 4 7 ℃ /W M a x .
2 . D u ty F a c t o r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C( t )
0 .2
0 .1
10
-1
0 .0 5
PDM
0 .0 2
0 .0 1
θ JC
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature [℃]
-VDS, Drain-Source Voltage [V]
t1
t2
Z
s in g le p u ls e
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, August 2000
FQB4P40 / FQI4P40
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
-10V
300nF
VDS
VGS
Qgs
Qgd
DUT
-3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
t on
VDD
VGS
RG
td(on)
VGS
t off
tr
td(off)
tf
10%
DUT
-10V
VDS
90%
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
tp
ID
RG
VDD
DUT
-10V
tp
©2000 Fairchild Semiconductor International
VDD
Time
VDS (t)
ID (t)
IAS
BVDSS
Rev. A, August 2000
FQB4P40 / FQI4P40
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
VDS
DUT
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
I SD
( DUT )
Compliment of DUT
(N-Channel)
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
Body Diode Reverse Current
IRM
di/dt
IFM , Body Diode Forward Current
VDS
( DUT )
VSD
Body Diode
Forward Voltage Drop
VDD
Body Diode Recovery dv/dt
©2000 Fairchild Semiconductor International
Rev. A, August 2000
4.50 ±0.20
9.90 ±0.20
+0.10
2.00 ±0.10
2.54 TYP
(0.75)
°
~3
0°
0.80 ±0.10
1.27 ±0.10
2.54 ±0.30
15.30 ±0.30
0.10 ±0.15
2.40 ±0.20
4.90 ±0.20
9.20 ±0.20
1.30 –0.05
1.20 ±0.20
(0.40)
D2PAK
1.40 ±0.20
+0.10
0.50 –0.05
2.54 TYP
4.90 ±0.20
(2XR0.45)
9.20 ±0.20
10.00 ±0.20
(7.20)
(1.75)
10.00 ±0.20
(8.00)
(4.40)
15.30 ±0.30
FQB4P40 / FQI4P40
Package Dimensions
0.80 ±0.10
©2000 Fairchild Semiconductor International
Rev. A, August 2000
FQB4P40 / FQI4P40
Package Dimensions
(Continued)
I2PAK
4.50 ±0.20
(0.40)
9.90 ±0.20
+0.10
MAX13.40
9.20 ±0.20
(1.46)
1.20 ±0.20
1.30 –0.05
0.80 ±0.10
2.54 TYP
2.54 TYP
10.08 ±0.20
1.47 ±0.10
MAX 3.00
(0.94)
13.08 ±0.20
)
5°
(4
1.27 ±0.10
+0.10
0.50 –0.05
2.40 ±0.20
10.00 ±0.20
©2000 Fairchild Semiconductor International
Rev. A, August 2000
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Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
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This datasheet contains final specifications. Fairchild
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Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. F1