INTEGRATED CIRCUITS 74F821/822/823/824/825/826 Bus interface registers Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Product specification Bus interface registers 74F821 74F822 74F823 74F824 74F825 74F826 74F821/822/823/824/825/826 10-bit bus interface register, non-inverting (3-State) 10-bit bus interface register, inverting (3-State) 9-bit bus interface register, non-inverting (3-State) 9-bit bus interface register, inverting (3-State) 8-bit bus interface register, non-inverting (3-State) 8-bit bus interface register, inverting (3-State) FEATURES DESCRIPTION • High speed parallel registers with positive edge-triggered D-type The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. flip-flops • High performance bus interface buffering for wide data/address paths or busses carrying parity The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions. • High impedance PNP base inputs for reduced loading (20µA in high and low states) The 74F822 is the inverted output version of 74F821. • IIL is 20µA vs 1000µA for AM29821 series • Buffered control inputs to reduce AC effects • Ideal where high speed, light loading, or increased fan-in as The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The 74F824 is the inverted version of 74F823. required with MOS microprocessor • Positive and negative over-shoots are clamped to ground • 3-State outputs glitch free during power-up and power-down • Slim Dip 300 mil package • Broadside pinout compatible with AMD AM 29821-29826 series • Outputs sink 64mA and source 24mA • Industrial temperature range available (–40°C to +85°C) for The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) to allow multiuser control of the interface, e.g., CS, DMA, and RD/WR. They are ideal for uses as an output port requiring high IOL/IOH. The 74F826 is the inverted version of 74F825. TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 74F821, 74F822 180MHz 75mA 74F823, 74F824 180MHz 70mA 74F825, 74F826 180MHz 65mA TYPE 74F823 ORDERING INFORMATION ORDER CODE COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C PKG. DWG. # 24-pin plastic slim DIP (300mil) N74F821N, N74F822N, N74F823N, N74F824N, N74F825N, N74F826N I74F823N SOT222-1 24-pin plastic SOL N74F821D, N74F822D, N74F823D, N74F824D, N74F825D, N74F826D I74F823D SOT137-1 DESCRIPTION 1996 Jan 05 2 853-1304 16195 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dn Data inputs 1.0/1.0 20µA/0.6mA 74F821 CP Clock input 1.0/1.0 20µA/0.6mA 74F822 OE Output enable input (active low) 1.0/3.0 20µA/1.8mA Qn, Qn 1200/106.7 24mA/64mA Dn Data inputs 1.0/1.0 20µA/0.6mA CP Clock input 1.0/1.0 20µA/0.6mA 74F823 CE Clock enable input (active low) 1.0/3.0 20µA/1.8mA 74F824 MR Master reset input (active low) 1.0/3.0 20µA/1.8mA OE Output enable input (active low) 1.0/3.0 20µA/1.8mA Qn, Qn Data outputs 1200/106.7 24mA/64mA Dn Data inputs 1.0/1.0 20µA/0.6mA CP Clock input 1.0/1.0 20µA/0.6mA 74F825 CE Clock enable input (active low) 1.0/3.0 20µA/1.8mA 74F826 MR Master reset input (active low) 1.0/3.0 20µA/1.8mA OE Output enable input (active low) 1.0/3.0 20µA/1.8mA 1200/106.7 24mA/64mA Qn, Qn Data outputs Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION – 74F821 OE 1 24 VCC D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 D5 7 18 Q5 D6 8 17 Q6 D7 9 16 Q7 D8 10 15 Q8 D9 11 14 Q9 GND 12 13 CP LOGIC SYMBOL – 74F821 2 4 5 6 7 8 9 10 11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 13 CP 1 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 VCC = Pin 24 GND = Pin 12 SF00482 1996 Jan 05 3 3 23 22 21 20 19 18 17 16 15 14 SF00483 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 IEC/IEEE SYMBOL – 74F821 IEC/IEEE SYMBOL – 74F822 1 1 EN1 EN1 13 13 G2 G2 2 2D 2 23 1 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 2D 23 1 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 SF00484 SF00487 PIN CONFIGURATION – 74F823 PIN CONFIGURATION – 74F822 OE 1 24 VCC OE 1 24 VCC D0 2 23 Q0 D0 2 23 Q0 D1 3 22 Q1 D1 3 22 Q1 D2 4 21 Q2 D2 4 21 Q2 D3 5 20 Q3 D3 5 20 Q3 D4 6 19 Q4 D4 6 19 Q4 D5 7 18 Q5 D5 7 18 Q5 D6 8 17 Q6 D6 8 17 Q6 D7 9 16 Q7 D7 9 16 Q7 D8 10 15 Q8 D8 10 15 Q8 D9 11 14 Q9 MR 11 14 CE GND 12 13 CP GND 12 13 CP SF00488 SF00485 LOGIC SYMBOL – 74F823 LOGIC SYMBOL – 74F822 2 3 4 5 6 7 8 9 10 2 11 13 CP 13 CP 14 CE 1 OE 11 MR 1 OE 1996 Jan 05 22 21 20 19 18 17 16 15 5 6 7 8 9 10 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 23 4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VCC = Pin 24 GND = Pin 12 3 23 14 VCC = Pin 24 GND = Pin 12 SF00486 4 22 21 20 19 18 17 16 15 SF00489 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 IEC/IEEE SYMBOL – 74F823 IEC/IEEE SYMBOL – 74F824 1 1 EN1 EN1 11 11 R R 14 14 G1 G1 13 13 1G2 1G2 23 2 3 22 3 22 4 21 4 21 5 20 5 20 6 19 6 19 7 18 7 18 8 17 8 17 9 16 9 16 10 15 10 15 2 2D 1 2D 23 1 SF00493 SF00490 PIN CONFIGURATION – 74F824 PIN CONFIGURATION – 74F825 24 V CC OE0 1 24 VCC D0 2 23 Q0 OEI 2 23 OE2 D1 3 22 Q1 DO 3 22 QO D2 4 21 Q2 D1 4 21 Q1 D3 5 20 Q3 D2 5 20 Q2 D4 6 19 Q4 D3 6 19 Q3 D5 7 18 Q5 D4 7 18 Q4 D6 8 17 Q6 D5 8 17 Q5 D7 9 16 Q7 D6 9 16 Q6 D8 10 15 Q8 D7 10 15 Q7 MR 11 14 CE MR 11 14 CE GND 12 13 CP GND 12 13 CP OE 1 SF00491 SF00494 LOGIC SYMBOL – 74F824 2 3 4 5 LOGIC SYMBOL – 74F825 6 7 8 9 10 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 CP CP 14 CE 14 CE 11 MR 11 MR 1 OE0 1 OE 2 OE1 23 OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 23 1996 Jan 05 22 21 20 19 18 17 16 5 6 7 8 9 10 D0 D1 D2 D3 D4 D5 D6 D7 13 13 VCC = Pin 24 GND = Pin 12 4 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 VCC = Pin 24 GND = Pin 12 SF00492 5 22 21 20 19 18 17 16 15 SF00495 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 IEC/IEEE SYMBOL – 74F825 LOGIC SYMBOL – 74F826 & 1 2 3 4 5 6 7 8 9 10 EN 23 D0 D1 D2 D3 D4 D5 D6 D7 11 R 14 G1 13 1G2 3 2D 22 1 4 21 5 20 6 19 7 18 8 17 9 16 10 15 13 CP 14 CE 11 MR 1 OE0 2 OE1 23 OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 22 21 20 19 18 17 VCC = Pin 24 GND = Pin 12 16 15 SF00498 IEC/IEEE SYMBOL – 74F826 & 1 SF00496 2 EN 23 PIN CONFIGURATION – 74F826 11 R 14 G1 OE0 1 24 VCC OEI 2 23 OE2 DO 3 22 QO 3 D1 4 21 Q1 4 21 20 Q2 5 20 6 19 7 18 8 17 9 16 10 15 13 D2 5 19 Q3 D3 6 D4 7 18 Q4 D5 8 17 Q5 D6 9 16 Q6 D7 10 15 Q7 MR 11 14 CE GND 12 13 CP 1G2 2D 22 1 SF00499 SF00497 LOGIC DIAGRAM FOR 74F821 D0 2 D1 3 D CP Q CP OE D2 4 D CP Q D3 5 D CP Q D4 6 D CP Q D5 7 D CP Q D6 8 D CP Q D8 10 D7 9 D CP Q D9 11 D CP Q D CP Q D CP Q 13 1 23 Q0 22 Q1 21 Q2 20 19 Q3 Q4 VCC = Pin 24 GND = Pin 12 1996 Jan 05 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 SF00500 6 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 LOGIC DIAGRAM FOR 74F822 D0 2 D1 3 D CP Q CP D2 4 D CP Q D3 5 D4 6 D CP Q D CP Q D5 7 D6 8 D CP Q D CP Q D8 10 D7 9 D CP Q D9 11 D CP Q D CP Q D CP Q 13 1 OE 23 22 Q0 VCC = Pin 24 GND = Pin 12 21 Q1 20 Q2 19 Q3 18 Q4 17 Q5 15 16 Q6 14 Q8 Q7 Q9 SF00501 FUNCTION TABLE FOR 74F821 AND 74F822 OUTPUTS INPUTS H = h = L = l = NC= X = Z = ↑ = ↑ = 74F821 74F822 Q Q OE CP Dn L ↑ l L H L ↑ h H L L ↑ X NC NC H X X Z Z OPERATING MODE Load and read data Hold High impedance High-voltage level High state must be present one setup time before the low-to-high clock transition Low-voltage level Low state must be present one setup time before the low-to-high clock transition No change Don’t care High impedance “off” state Low-to-high clock transition Not low-to-high clock transition LOGIC DIAGRAM FOR 74F823 CE CP 14 13 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 D CP R Q MR OE D CP R Q 1996 Jan 05 D CP R Q D CP R Q D CP R Q D CP R Q 10 D CP R Q D CP R Q 11 1 23 VCC = Pin 24 GND = Pin 12 D CP R Q D8 Q0 22 Q1 21 20 Q2 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 SF00502A 7 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 LOGIC DIAGRAM FOR 74F824 CE CP D1 3 D0 2 14 D2 4 D3 5 D4 6 D5 7 D6 8 D8 10 D7 9 13 D CP R Q MR OE D CP R Q D CP R Q D CP R Q D CP R Q D CP R Q D CP R Q D CP R Q D CP R Q 11 1 23 22 21 Q1 Q0 VCC = Pin 24 GND = Pin 12 20 Q2 19 Q3 18 Q4 17 Q5 15 16 Q6 Q8 Q7 SF00503A FUNCTION TABLE for 74F823 and 74F824 OUTPUTS INPUTS OE 74F823 74F824 Q Q MR CE* CP Dn L L X X X L L L H L ↑ h H L L H L ↑ l L H L H H X X NC NC H X X X X Z Z OPERATING MODE Clear Load and read data Hold High impedance H = h = L = l = NC= X = Z = * = High-voltage level High state must be present one setup time before the low-to-high clock transition Low-voltage level Low state must be present one setup time before the low-to-high clock transition No change Don’t care High impedance “off” state Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders or other potentially glitch prone device on the CE input. ↑ = Low-to-high clock transition LOGIC DIAGRAM FOR 74F825 CE CP 14 13 D0 D1 D2 D3 D4 D5 D6 3 4 5 6 7 8 9 D CP R Q MR D CP R Q D CP R Q D CP R Q D CP R Q 10 D CP R Q D CP R Q 11 1 OE0 2 OE1 23 OE2 VCC = Pin 24 GND = Pin 12 D CP R Q D7 22 Q0 21 Q1 20 Q2 19 Q3 18 Q4 17 Q5 16 Q6 15 Q7 SF00504A 1996 Jan 05 8 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 LOGIC DIAGRAM FOR 74F826 CE D0 3 14 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 13 CP D CP R Q MR D CP R Q D CP R Q D CP R Q D CP R Q D CP R Q D CP R Q D CP R Q 11 1 OE0 2 OE1 23 OE2 22 21 Q0 VCC = Pin 24 GND = Pin 12 Q1 20 Q2 19 18 Q3 Q4 17 Q5 15 16 Q6 Q7 SF00505A FUNCTION TABLE FOR 74F825 AND 74F826 OUTPUTS INPUTS OEn 74F825 74F826 Q Q MR CE* CP Dn L L X X X L L L H L ↑ h H L L H L ↑ l L H L H H X X NC NC H X X X X Z Z OPERATING MODE Clear Load and read data Hold High impedance H = h = L = l = NC= X = Z = * = High-voltage level High state must be present one setup time before the low-to-high clock transition Low-voltage level Low state must be present one setup time before the low-to-high clock transition No change Don’t care High impedance “off” state Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders or other potentially glitch prone device on the CE input. ↑ = Low-to-high clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in low output state 128 mA Commercial range 0 to +70 Tamb Operating free-air free air temperature range °C Industrial range –40 to +85 °C Tstg Storage temperature range –65 to +150 °C 1996 Jan 05 9 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 RECOMMENDED OPERATING CONDITIONS LIMITS PARAMETER SYMBOL MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIk Input clamp current –18 mA IOH High–level output current –24 mA IOL Low–level output current Tambb Operating O erating free-air tem temperature erature range V V 64 mA Commercial range 0 +70 °C Industrial range –40 +85 °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH O TEST CONDITIONS1 PARAMETER VCC = MIN, VIL = MAX MAX, VIH = MIN High level output voltage High-level VCC = MIN, VIL = MAX MAX, VIH = MIN IOH 15mA O = –15mA IOH 24mA O = –24mA LIMITS MIN TYP2 MAX UNIT ±10%VCC 2.4 V ±5%VCC 2.4 V ±10%VCC 2.0 V ±5%VCC 2.0 V ±10%VCC 0.55 V 0.42 0.55 V –0.73 –1.2 V VCC = 0.0V, VI = 7.0V 100 µA VCC = MAX, VI = 2.7V 20 µA Low–level input current VCC = MAX, VI = 0.5V –20 µA Off–state output current, high–level voltage applied VCC = MAX, VO = 2.7V 50 µA IOZL Off–state output current, low–level voltage applied VCC = MAX, VO = 0.5V IOS Short–circuit output current3 VCC = MAX VOL O Low level output voltage Low-level VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage IIH High–level input current IIL IOZH ICCH 74F821, 74F822 ICCL VCC = MAX ICCZ ICCH ICC Supply current (total) 74F823, 74F824 ICCL VCC = MAX ICCZ ICCH 74F825, 74F826 ICCL VCC = MAX ICCZ IOL O = MAX ±5%VCC –50 µA -225 mA 75 105 mA 75 105 mA 75 115 mA 65 100 mA 70 105 mA 75 110 mA 60 85 mA 60 90 mA 65 95 mA -100 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1996 Jan 05 10 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 AC ELECTRICAL CHARACTERISTICS FOR 74F821/74F822/74F824/74F825/74F826 LIMITS SYMBOL TEST CONDITION PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN TYP Waveform 1 150 180 74F821, 74F825, 74F826 Waveform 1 4.0 4.0 6.5 6.0 8.5 8.5 4.0 3.5 9.5 9.0 ns Propagation delay CP to Qn 74F822, 74F824 Waveform 1 4.5 4.5 6.5 6.5 9.0 9.0 4.5 4.5 10.0 9.0 ns tPHL Propagation delay MR to Qn or Qn 74F824 74F825, 74F826 Waveform 2 3.0 5.0 8.0 3.0 8.0 ns tPZH tPZL Output enable time OEn to Qn or Qn Waveform 4 Waveform 5 2.0 3.0 4.5 5.0 8.0 8.0 2.0 2.5 9.0 9.0 ns tPHZ tPLZ Output disable time OEn to Qn or Qn Waveform 4 Waveform 5 1.5 1.5 3.5 3.5 6.5 6.5 1.5 1.5 7.5 7.5 ns fmax Maximum clock frequency tPLH tPHL Propagation delay CP to Qn or Qn tPLH tPHL MAX MIN UNIT MAX 140 ns AC SETUP REQUIREMENTS FOR 74F821/74F822/74F824/74F825/74F826 LIMITS SYMBOL TEST CONDITION PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω MIN TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX tsu (H) tsu (L) Setup time, high or low Dn to CP Waveform 3 1.0 1.0 1.0 1.0 ns th (H) th (L) Hold time, high or low Dn to CP Waveform 3 2.0 2.0 2.0 2.0 ns tw (H) tw (L) CP Pulse width, high or low Waveform 1 3.5 3.5 4.0 4.0 ns tsu (H) tsu (L) Setup time, high or low, CE to CP Waveform 3 0.0 2.0 0.0 2.0 ns th (H) th (L) Hold time, high or low CE to CP Waveform 3 0.0 3.0 0.0 3.5 ns tw (L) MR Pulse width, low Waveform 2 4.5 4.5 ns trec Recovery time, MR to CP Waveform 2 2.5 2.5 ns 1996 Jan 05 74F824, 74F825, 74F826 11 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 AC ELECTRICAL CHARACTERISTICS FOR 74F823 LIMITS Tamb = +25°C VCC = +5.0V CL = 50pF RL = 500Ω Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF RL = 500Ω Tamb = –40°C to +85°C VCC = +5.0V ± 10% CL = 50pF RL = 500Ω PARAMETER TEST CONDITION MIN TYP fmax Maximum clock frequency Waveform 1 150 180 tPLH tPHL Propagation delay CP to Qn or Qn Waveform 1 4.0 4.0 6.5 6.0 8.5 8.5 4.0 3.5 9.5 9.0 4.0 3.5 10.0 9.0 ns tPHL Propagation delay MR to Qn or Qn Waveform 2 3.0 5.0 8.0 3.0 8.0 3.0 8.5 ns tPZH tPZL Output enable time OEn to Qn or Qn Waveform 4 Waveform 5 2.0 3.0 4.5 5.0 8.0 8.0 2.0 2.5 9.0 9.0 2.0 2.5 11.0 9.0 ns tPHZ tPLZ Output disable time OEn to Qn or Qn Waveform 4 Waveform 5 1.5 1.5 3.5 3.5 6.5 6.5 1.5 1.5 7.5 7.5 1.5 1.5 8.5 8.5 ns SYMBOL MAX MIN MAX 140 MIN UNIT MAX 130 ns AC SETUP REQUIREMENTS FOR 74F823 LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V CL = 50pF RL = 500Ω MIN TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF RL = 500Ω MIN MAX Tamb = –40°C to +85°C VCC = +5.0V ± 10% CL = 50pF RL = 500Ω MIN UNIT MAX tsu (H) tsu (L) Setup time, high or low Dn to CP Waveform 3 1.0 1.0 1.0 1.0 2.0 1.5 ns th (H) th (L) Hold time, high or low Dn to CP Waveform 3 2.0 2.0 2.0 2.0 2.5 2.0 ns tw (H) tw (L) CP Pulse width, high or low Waveform 1 3.5 3.5 4.0 4.0 4.0 4.0 ns tsu (H) tsu (L) Setup time, high or low, CE to CP Waveform 3 0.0 2.0 0.0 2.0 0.0 2.0 ns th (H) th (L) Hold time, high or low CE to CP Waveform 3 0.0 3.0 0.0 3.5 1.5 4.0 ns tw (L) MR Pulse width, low Waveform 2 4.5 4.5 4.5 ns trec Recovery time, MR to CP Waveform 2 2.5 2.5 2.5 ns 1996 Jan 05 12 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax CP VM MR VM tw(H) VM Qn VM tPHL tPLH Qn trec CP VM tPHL VM tw(L) tPHL tw(L) tPLH VM VM VM Qn, Qn VM VM SF00507 Waveform 2. Master reset pulse width, master reset to output delay and master reset to clock recovery time SF00506 Waveform 1. Propagation delay for clock input to output, clock pulse width, and maximum clock frequency Dn, CE VM tsu(H) VM VM tsu(L) th(H) th(L) Qn, Qn VM CP OEn VM VM VM VM tPZH tPHZ VOH -0.3V VM 0V SF00508 SF00509 Waveform 3. OEn Data setup time and hold times VM VM tPZL Qn, Qn Waveform 4. 3-State output enable time to high level and output disable time from high level tPLZ 3.5V VM VOL +0.3V SF00510 Waveform 5. 3-State output enable time to low level and output disable time from low level 1996 Jan 05 13 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 TEST CIRCUIT AND WAVEFORMS VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for Open Collector Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00128 1996 Jan 05 14 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 DIP24: plastic dual in-line package; 24 leads (300 mil) 1996 Jan 05 15 SOT222-1 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 SO24: plastic small outline package; 24 leads; body width 7.5 mm 1996 Jan 05 16 SOT137-1 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 NOTES 1996 Jan 05 17 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05185