AD AD8370ARE Lf to 750 mhz digitally controlled vga Datasheet

LF to 750 MHz
Digitally Controlled VGA
AD8370
FUNCTIONAL BLOCK DIAGRAM
FEATURES
The AD8370 is a low cost, digitally controlled, variable gain
amplifier that provides precision gain control, high IP3, and low
noise figure. The excellent distortion performance and wide
bandwidth make the AD8370 a suitable gain control device for
modern receiver designs.
For wide input, dynamic range applications, the AD8370 provides two input ranges: high gain mode and low gain mode. A
vernier 7-bit transconductance (Gm) stage provides 28 dB of
gain range at better than 2 dB resolution, and 22 dB of gain
range at better than 1 dB resolution. A second gain range, 17 dB
higher than the first, can be selected to provide improved noise
performance.
The AD8370 is powered on by applying the appropriate logic
level to the PWUP pin. When powered down, the AD8370
consumes less than 4 mA and offers excellent input to output
isolation. The gain setting is preserved when operating in a
power-down mode.
VCCO
6
BIAS CELL
ICOM 2
INHI 1
PRE
AMP
OUTPUT
AMP
TRANSCONDUCTANCE
INLO 16
ICOM 15
5
VOCM
7
OCOM
8
OPHI
9
OPLO
10
OCOM
SHIFT REGISTER
AND LATCHES
13
03692-0-001
AD8370
14
12
DATA CLCK LTCH
Figure 1.
70
40
CODE = LAST 7 BITS OF GAIN CODE
(NO MSB)
60
30
50
20
LOW GAIN MODE
40
∆ GAIN ≅ 0.409
∆ CODE
HIGH GAIN MODE
30
10
0
20
–10
10
LOW GAIN MODE
0
0
10
20
30
40
50
60
70
80
∆ GAIN ≅ 0.059
∆ CODE
–20
–30
90 100 110 120 130
GAIN CODE
VOLTAGE GAIN (dB)
HIGH GAIN MODE
VOLTAGE GAIN (V/V)
GENERAL DESCRIPTION
11
PWUP 4
APPLICATIONS
Differential ADC drivers
IF sampling receivers
RF/IF gain stages
Cable and video applications
SAW filter interfacing
Single-ended-to-differential conversion
VCCO
3
03692-0-003
Programmable low and high gain (<2 dB resolution)
Low range: −11 dB to +17 dB
High range: +6 dB to +34 dB
Differential input and output:
200 Ω differential input
100 Ω differential output
7 dB noise figure @ maximum gain
Two-tone IP3 of +35 dBm @ 70 MHz
−3 dB bandwidth of 750 MHz
40 dB precision gain range
Serial 8-bit digital interface
Wide input dynamic range
Power-down feature
Single 3 V to 5 V supply
VCCI
Figure 2. Gain vs. Gain Code at 70 MHz
Gain control of the AD8370 is through a serial 8-bit gain control
word. The MSB selects between the two gain ranges, and the
remaining 7 bits adjust the overall gain in precise linear gain steps.
Fabricated on the ADI high speed XFCB process, the high bandwidth of the AD8370 provides high frequency and low distortion.
The quiescent current of the AD8370 is 78 mA typically. The
AD8370 amplifier comes in a compact, thermally enhanced
16-lead TSSOP package and operates over the temperature
range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD8370
TABLE OF CONTENTS
Specifications..................................................................................... 3
Choosing between Gain Ranges............................................... 15
Absolute Maximum Ratings............................................................ 5
Layout and Operating Considerations .................................... 16
ESD Caution.................................................................................. 5
Package Considerations............................................................. 17
Pin Configuration and Functional Descriptions.......................... 6
Single-Ended-to-Differential Conversion............................... 17
Typical Performance Characteristics ............................................. 7
DC-Coupled Operation............................................................. 18
Theory of Operation ...................................................................... 13
ADC Interfacing ......................................................................... 19
Block Architecture...................................................................... 13
3 V Operation ............................................................................. 20
Preamplifier................................................................................. 13
Evaluation Board and Software .................................................... 21
Transconductance Stage ............................................................ 13
Appendix ......................................................................................... 24
Output Amplifier ........................................................................ 14
Characterization Equipment..................................................... 24
Digital Interface and Timing .................................................... 14
Composite Waveform Assumption .......................................... 24
Applications..................................................................................... 15
Definitions of Selected Parameters.......................................... 24
Basic Connections ...................................................................... 15
Outline Dimensions ....................................................................... 28
Gain Codes .................................................................................. 15
Ordering Guide .......................................................................... 28
Power-Up Feature....................................................................... 15
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8370
SPECIFICATIONS
VS = 5 V, T = 25°C, ZS = 200 Ω, ZL = 100 Ω at Gain Code HG127, 70 MHz, 1 V p-p differential output, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
INPUT STAGE
Maximum Input
Input Resistance
Common-Mode Input Range
CMRR
Input Noise Spectral Density
GAIN
Maximum Voltage Gain
High Gain Mode
Conditions
Min
VOUT < 1 V p-p
Gain Code HG127, RL = 1 kΩ, AD8370 in
Compression
Gain Code LG127, RL = 1 kΩ, VOUT = 2 V p-p
Pins INHI and IHLO
Gain Code LG2, 1 dB Compression
Differential
3500
V/ns
3.2
200
3.2
77
1.9
V p-p
Ω
V p-p
dB
nV/√Hz
34
52
17
7.4
dB
Volts/Volt
dB
Volts/Volt
−8
0.4
−25
0.06
0.408
0.056
–2
20
dB
Volts/Volt
dB
Volts/Volt
(Volts/Volt)/Code
(Volts/Volt)/Code
RL ≥ 1 kΩ (1 dB compression)
Differential
VINHI = VINLO, over all gain codes
8.4
95
±60
V p-p
Ω
mV
Within ±10 MHz of 10 MHz
±0.01
7.2
−77
−77
35
17
dB
dB
dBc
dBc
dBm
dBm
Differential, f = 10 MHz, Gain Code LG127
Gain Code = HG127
Minimum Voltage Gain
High Gain Mode
Gain Code = HG1
Low Gain Mode
Gain Code = LG1
Gain Step Size
High Gain Mode
Low Gain Mode
Gain Code = HG127
For 6 dB gain step, settled to 10% of final value
NOISE/HARMONIC PERFORMANCE
10 MHz
Gain Flatness
Noise Figure
Second Harmonic1
Third Harmonic
Output IP3
Output 1 dB Compression Point
1
Unit
MHz
V/ns
Gain Code = LG127
OUTPUT INTERFACE
Output Voltage Swing
Output Resistance
Output Differential Offset
Max
750
5750
Low Gain Mode
Gain Temperature Sensitivity
Step Response
Typ
mdB/°C
ns
Pins OPHI and OPLO
VOUT = 2 V p-p
VOUT = 2 V p-p
See footnotes on next page.
Rev. 0 | Page 3 of 28
AD8370
Parameter
NOISE/HARMONIC PERFORMANCE (cont.)
70 MHz
Gain Flatness
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
140 MHz
Gain Flatness
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
190 MHz
Gain Flatness
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
240 MHz
Gain Flatness
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
380 MHz
Gain Flatness
Noise Figure
Output IP3
Output 1 dB Compression Point
POWER-INTERFACE
Supply Voltage
1
1
1
1
1
1
1
1
Quiescent Current3
vs. Temperature
4
Total Supply Current
Power Down Current
vs. Temperature4
POWER UP INTERFACE
Power-Up Threshold
Power-Down Threshold
PWUP Input Bias Current
GAIN CONTROL INTERFACE
VIH
VIL
Input Bias Current
4
4
4
4
Conditions
Min
Within ±10 MHz of 70 MHz
VOUT = 2 V p-p
VOUT = 2 V p-p
Within ±10 MHz of 140 MHz
VOUT = 2 V p-p
VOUT = 2 V p-p
Within ±10 MHz of 240 MHz
VOUT = 2 V p-p
VOUT = 2 V p-p
Within ±10 MHz of 240 MHz
VOUT = 2 V p-p
VOUT = 2 V p-p
Within ±10 MHz of 240 MHz
Typ
72.5
dB
dB
dBc
dBc
dBm
dBm
±0.03
7.2
−54
−50
33
17
dB
dB
dBc
dBc
dBm
dBm
±0.03
7.2
−43
−43
33
17
dB
dB
dBc
dBc
dBm
dBm
±0.04
7.4
–28
–33
32
17
dB
dB
dBc
dBc
dBm
dBm
±0.04
8.1
27
14
dB
dB
dBm
dBm
79
Refer to Figure 20 for performance into a lighter load.
See the 3 V Operation section for more information.
Minimum and maximum specified limits for this parameter are guaranteed by production test.
4
Minimum or maximum specified limit for this parameter is a 6-sigma value and not guaranteed by production test.
2
3
Rev. 0 | Page 4 of 28
5.5
V
85.5
mA
105
mA
mA
82
3.7
5
1.8
mA
mA
0.8
V
V
nA
0.8
V
V
nA
400
1.8
900
1
Unit
±0.02
7.2
−65
−62
35
17
3.02
PWUP High, GC = LG127, RL = ∞, 4 seconds after power-on,
thermal connection made to exposed paddle under device
−40°C ≤ TA ≤ +85°C
PWUP High, VOUT = 1 V p-p, ZL = 100 Ω reactive, GC = LG127
(includes load current)
PWUP Low
−40°C ≤TA ≤ +85°C
Pin PWUP
Voltage to enable the device
Voltage to disable the device
PWUP = 0 V
Pins CLCK, DATA, and LTCH
Voltage for a logic high
Voltage for a logic low
Max
AD8370
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage, VS
PWUP, DATA, CLCK, LTCH
Differential Input Voltage,
VINHI – VINLO
Common-Mode Input Voltage, VINHI or
VINLO, with respect to ICOM or OCOM
Internal Power Dissipation
θJA (Exposed paddle soldered down)
θJA (Exposed paddle not soldered down)
θJC (At exposed paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range
(Soldering 60 sec)
Rating
5.5 V
VS + 500 mV
2V
VS + 500 mV
(maximum),
VICOM – 500 mV,
VOCOM – 500 mV
(minimum)
575 mW
30°C/W
95°C/W
9°C/W
150°C
–40°C to +85°C
–65°C to +150°C
235°C
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those
listed in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 28
AD8370
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
INHI 1
16
INLO
ICOM 2
15
ICOM
VCCI 3
14
DATA
PWUP 4
13
CLCK
VOCM 5
AD8370
LTCH
TOP VIEW
VCCO 6 (Not to Scale) 11 VCCO
OCOM 7
10
OCOM
OPHI 8
9
OPLO
03692-0-002
12
Figure 3.16-Lead TSSOP
Table 3. Pin Function Descriptions
Pin No.
1
2, 15,
PADDLE
3
4
5
Mnemonic
INHI
ICOM
VCCI
PWUP
VOCM
6, 11
7, 10
8
9
12
VCCO
OCOM
OPHI
OPLO
LTCH
13
14
16
CLCK
DATA
INLO
Description
Balanced Differential Input. Internally biased.
Input Common. Connect to a low impedance ground. This node is also connected to the exposed pad on the
bottom of the device.
Input Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed.
Power Enable Pin. Device is operational when PWUP is pulled high.
Common-Mode Output Voltage Pin. The midsupply ((VVCCO − VOCOM)/2) common-mode voltage is delivered to
this pin for external bypassing for additional common-mode supply decoupling. This can be achieved with a
bypass capacitor to ground. This pin is an output only and is not to be driven externally.
Output Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed.
Output Common. Connect to a low impedance ground.
Balanced Differential Output. Biased to midsupply.
Balanced Differential Output. Biased to midsupply.
Serial Data Latch Pin. Serial data is clocked into the shift register via the DATA pin when LTCH is low. Data in
shift register is latched on the next high-going edge.
Serial Clock Input Pin.
Serial Data Input Pin.
Balanced Differential Input. Internally biased.
Rev. 0 | Page 6 of 28
AD8370
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, ZS = 200 Ω, ZL = 100 Ω, T = 25°C, unless otherwise noted.
40
40
CODE = LAST 7 BITS OF GAIN CODE
(NO MSB)
60
0
20
–10
0
0
10
20
30
40
50
60
70
80
LG90
15
LG36
5
HG3
–20
LOW GAIN CODES SHOWN WITH SOLID LINES
–10
10
100
Figure 7. Frequency Response vs. Gain Code
30
40
50
HIGH GAIN MODE
+25°C
25
15
20
10
15
5
SHADING INDICATES ±3σ FROM THE
MEAN. DATA BASED ON 30 PARTS
FROM TWO BATCH LOTS.
10
5
0
20
40
60
80
100
120
OUTPUT IP3 (dBm) +25°C
25
OUTPUT IP3 (dBVrms)
20
GAIN CODE
45
30
40
+85°C
25
35
20
30
–40°C
15
0
–5
140
UNIT CONVERSION NOTE FOR
100Ω LOAD: dBVrms = dBm–10dB
35
25
SHADING INDICATES ±3σ FROM THE
MEAN. DATA BASED ON 30 PARTS
FROM TWO BATCH LOTS.
10
03692-0-024
OUTPUT IP3 (dBm)
30
1000
FREQUENCY (MHz)
Figure 4. Gain vs. Gain Code at 70 MHz
LOW GAIN MODE
LG18
LG9
–5
GAIN CODE
35
HG18
HG9
10
0
–30
90 100 110 120 130
40
LG127
HG25
20
0
50
100
150
200
250
300
350
20
400
FREQUENCY (MHz)
OUTPUT IP3 (dBm) –40°C, +85°C
LOW GAIN MODE
25
03692-0-026
10
∆ GAIN ≅ 0.059
∆ CODE
VOLTAGE GAIN (dB)
∆ GAIN ≅ 0.409
∆ CODE
HIGH GAIN MODE
10
HG102
HG51
VOLTAGE GAIN (dB)
LOW GAIN MODE
30
HG77
30
20
03692-0-003
VOLTAGE GAIN (V/V)
HIGH GAIN MODE
50
40
HIGH GAIN CODES SHOWN WITH DASHED LINES
HG127
35
30
03692-0-072
70
Figure 8. Output Third-Order Intercept vs. Frequency at Maximum Gain
Figure 5. Output Third-Order Intercept vs. Gain Code at 70 MHz
45
25
40
20
NOISE FIGURE (dB)
30
380 MHz
25
LOW GAIN MODE
20
70 MHz
LG127
15
10
HG18
15
HG127
5
380 MHz
10
HIGH GAIN MODE
5
0
20
40
60
80
100
120
GAIN CODE
140
0
0
100
200
300
400
500
FREQUENCY (MHz)
Figure 9. Noise Figure vs. Frequency at Various Gains
Figure 6. Noise Figure vs. Gain Code at 70 MHz
Rev. 0 | Page 7 of 28
600
03692-0-011
70 MHz
03692-0-012
NOISE FIGURE (dB)
35
AD8370
20
1kΩ LOAD
HIGH GAIN MODE
8
4
UNIT CONVERSION NOTE:
FOR 100Ω LOAD: dBVrms = dBm–10dB
FOR 1kΩ LOAD: dBVrms = dBm
–4
SHADING INDICATES ±3σ FROM THE
MEAN. DATA BASED ON 30 PARTS
FROM TWO BATCH LOTS.
–8
0
20
40
60
80
100
120
140
GAIN CODE
14
16
UNIT CONVERSION NOTE:
RE 100Ω LOAD: dBVrms = dBm – 10dB
RE 1kΩ LOAD: dBVrms = dBm
–40°C, 100Ω LOAD
+25°C, 1kΩ LOAD
14
12
8
+85°C, 1kΩ LOAD
8 SHADING INDICATES ±3σ FROM
THE MEAN. DATA BASED ON 30
PARTS FROM TWO BATCH LOTS.
6
0
50
100
150
200
OUTPUT IMD (dBc) +25°C
OUTPUT IMD (dBc)
–80
80
100
120
140
GAIN CODE
–72
–82
–74
–84
–82
–92
–84
50
100
150
200
250
300
350
–86
400
Figure 14. Two-Tone Output IMD3 vs. Frequency at Maximum Gain,
RL = 1 kΩ, VOUT = 1 V p-p Composite Differential
1.0
GAIN ERROR (dB)
0.5
–40°C
0
+85°C
–1.0
ERROR AT –40°C AND +85°C WITH RESPECT TO 25°C.
SHADING INDICATES ±3σ FROM THE MEAN. DATA
BASED ON 30 PARTS FROM ONE BATCH LOT.
0.5
–40°C
0
+85°C
–0.5
–1.0
–1.5
FREQUENCY (MHz)
–80
–90
1.0
1000
–78
+85°C
–88
1.5
100
–76
–40°C
–86
FREQUENCY (MHz)
03692-0-007
GAIN ERROR (dB)
–70
–80
1.5
10
–68
–78
2.0
–2.0
–66
+25°C
–76
2.0
–1.5
–64
–74
0
Figure 11. Two-Tone Output IMD3 vs. Gain Code at 70 MHz, RL = 1 kΩ,
VOUT = 1 V p-p Composite Differential
–0.5
–62
–94
03692-0-027
–85
60
4
400
–60
–72
HIGH GAIN
MODE
40
350
SHADING INDICATES ±3σ FROM
THE MEAN. DATA BASED ON 30
PARTS FROM TWO BATCH LOTS.
–70
–70
20
300
–68
LOW GAIN MODE
0
–40°C, 1kΩ LOAD
250
Figure 13. Output P1dB vs. Frequency
–65
–75
6
FREQUENCY (MHz)
SHADING INDICATES ±3σ FROM THE
MEAN. DATA BASED ON 30 PARTS
FROM TWO BATCH LOTS.
–60
10
10
Figure 10. Output P1dB vs. Gain Code at 70 MHz
–55
12
OUTPUT IMD (dBc) –40°C, +85°C
0
16
03692-0-030
LOW GAIN MODE
12
+85°C, 100Ω LOAD
18
OUTPUT P1dB (dBm) +25°C
OUTPUT P1dB (dBm) –40°C, +85°C
HIGH GAIN MODE
03692-0-028
OUTPUT P1dB (dB)
16
18
+25°C, 100Ω LOAD
100Ω LOAD
–2.0
ERROR AT –40°C AND +85°C WITH RESPECT TO 25°C.
SHADING INDICATES ±3σ FROM THE MEAN. DATA
BASED ON 30 PARTS FROM ONE BATCH LOT.
10
100
1000
FREQUENCY (MHz)
Figure 15. Gain Error over Temperature vs. Frequency, RL = 1 kΩ
Figure 12. Gain Error over Temperature vs. Frequency, RL = 100 Ω
Rev. 0 | Page 8 of 28
03692-0-006
LOW GAIN MODE
03692-0-083
20
0
0
–10
–10
LOW GAIN RL = 1kΩ
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
AD8370
–20
–30
LOW GAIN, RL = 1kΩ
–40
HIGH GAIN, RL = 100Ω
LOW GAIN, RL = 100Ω
–50
–60
–70
–80
HIGH GAIN RL = 1kΩ
–20
HIGH GAIN RL = 100Ω
–30
LOW GAIN RL = 100Ω
–40
–50
–60
–70
–80
HIGH GAIN, RL = 1kΩ
80
100
120
140
–90
GAIN CODE
0
60
HARMONIC DISTORTION (dBc)
–10
150
30
5MHz
0
330
210
270
HD3 RL = 100Ω
–30
–40
–50
HD3 RL = 1kΩ
–60
–70
0
–50
100
RESISTANCE (Ω)
150
REACTANCE (j Ω)
50
–100
0
400
500
600
–150
700
FREQUENCY (MHz)
150
200
250
300
350
400
120
80
100
60
80
40
60
20
40
0
16 DIFFERENT GAIN
CODES REPRESENTED
R+jX FORMAT
20
03692-0-031
50
100
Figure 20. Harmonic Distortion vs. Frequency at Maximum Gain,
VOUT = 2 V p-p Composite Differential
16 DIFFERENT GAIN
CODES REPRESENTED
R+jX FORMAT
200
50
FREQUENCY (MHz)
100
250
RESISTANCE (Ω)
HD2 RL = 100Ω
–20
0
Figure 17. Input and Output Reflection Coefficients, S11 and S22,
ZO = 100 Ω Differential
300
140
–90
03692-0-059
300
200
120
–80
240
100
100
HD2 RL = 1kΩ
S11
0
80
0
1GHz
180
60
Figure 19. Third-Order Harmonic Distortion vs. Gain Code at 70 MHz,
VOUT = 2 V p-p Differential
90
S22
40
GAIN CODE
Figure 16. Second-Order Harmonic Distortion vs. Gain Code at 70 MHz,
VOUT = 2 V p-p Differential
120
20
03692-0-036
60
03692-0-029
40
Figure 18. Input Resistance and Reactance vs. Frequency
–20
0
0
100
200
300
400
500
600
–40
700
FREQUENCY (MHz)
Figure 21. Output Resistance and Reactance vs. Frequency
Rev. 0 | Page 9 of 28
REACTANCE (j Ω)
20
03692-0-033
0
03692-0-057
–90
AD8370
1400
860
RL = 1kΩ
840
1300
HIGH GAIN MODE
1200
780
760
LOW GAIN MODE
1100
900
740
800
720
700
700
0
10
20
30
40
50
60
70
80
90 100 110 120 130
GAIN CODE
RL = 100Ω
1000
600
0
100
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
03692-0-034
GROUP DELAY (ps)
800
03692-0-032
GROUP DELAY (ps)
820
Figure 25. Group Delay vs. Frequency at Maximum Gain
Figure 22. Group Delay vs. Gain Code at 70 MHz
120
80
110
70
LG32, LG127
100
60
HG32, HG127
80
CMRR (dB)
PSRR (dB)
90
70
60
50
40
30
50
20
40
1
10
100
1000
FREQUENCY (MHz)
0
03692-0-013
20
10
Figure 23. Power Supply Rejection Ratio vs. Frequency at Maximum Gain
1000
Figure 26. Common-Mode Rejection Ratio vs. Frequency
0
12
NOISE SPECTRAL DENSITY (nV/ Hz)
FORWARD TRANSMISSION, HG0
–20
FORWARD TRANSMISSION, LG0
–40
–60
–80
–100
FORWARD TRANSMISSION, PWUP LOW
10
8
LG127
6
4
HG18
2
HG127
–120
10
100
FREQUENCY (MHz)
1000
0
10
110
210
310
410
510
FREQUENCY (MHz)
Figure 27. Input Referred Noise Spectral Density vs.
Frequency at Various Gains
Figure 24. Various Forms of Isolation vs. Frequency
Rev. 0 | Page 10 of 28
610
03692-0-010
REVERSE TRANSMISSION, HG127
03692-0-009
ISOLATION (dB)
100
FREQUENCY (MHz)
03692-0-005
10
30
AD8370
VOUT DIFFERENTIAL
VOPHI
VOLTAGE (1V/DIV)
DIFFERENTIAL VOUT
DIFFERENTIAL VIN
GND
TIME (2ns/DIV)
03692-0-067
GND
03692-0-069
VOLTAGE (600mV/DIV)
VOPLO
TIME (2ns/DIV)
Figure 28. DC-Coupled Large Signal Pulse Response
Figure 31. Overdrive Recovery
85
DIFFERENTIAL OUTPUT (50mV/DIV)
80
SUPPLY CURRENT (mA)
ZERO
PWUP (2V/DIV)
GAIN CODE HG127
75
70
LOW GAIN
65
HIGH GAIN
60
55
GND
03692-0-068
TIME (40ns/DIV)
50
0
16
32
48
64
80
96
112
128
GAIN CODE
03692-0-014
INPUT = –30dBm, 70MHz 100 AVERAGES
Figure 32. Supply Current vs. Gain Code
Figure 29. PWUP Time Domain Response
35
DIFFERENTIAL OUTPUT (10mV/DIV)
MEAN: 51.9
σ: 0.518
30
ZERO
25
DATA FROM 136 PARTS
FROM ONE BATCH LOT
COUNT
6dB GAIN STEP (HG36 TO LG127)
LTCH (2V/DIV)
20
15
10
TIME (20ns/DIV)
Figure 30. Gain Step Time Domain Response
0
50
51
52
53
54
55
GAIN (V/V)
Figure 33. Distribution of Voltage Gain, HG127, 70 MHz, RL = 100 Ω
Rev. 0 | Page 11 of 28
03692-0-073
5
INPUT = –30dBm, 70MHz
NO AVERAGING
03692-0-035
GND
AD8370
2.75
2.70
+85°C
2.65
2.55
2.50
–40°C
2.45
LOW GAIN MODE
2.40
0
32
64
96
HIGH GAIN MODE
0
32
64
96
128
GAIN CODE
03692-0-071
VCM (V)
+25°C
2.60
Figure 34. Common-Mode Output Voltage vs. Gain Code at
Various Temperatures
Rev. 0 | Page 12 of 28
AD8370
THEORY OF OPERATION
INHI/INLO
2kΩ
VCC/2
1mA
Figure 36. INHI/INLO Simplified Schematic
The digitally controlled gm section has 42 dB of controllable
gain and makes gain the adjustments within each gain range.
The step size resolution ranges from a fine ~ 0.07 dB up to a
coarse 6 dB per bit, depending on the gain code. As shown in
Figure 37, of the 42 dB total range, 28 dB has resolution of
better than 2 dB, and 22 dB has resolution of better than 1 dB.
The three basic building blocks of the AD8370 are a high/low
gain selectable input preamplifier, a digitally controlled
transconductance (gm) block, and a fixed gain output stage.
VCCO
3
11
VCCO
6
5
VOCM
7
OCOM
8
OPHI
INLO 16
9
OPLO
ICOM 15
10
OCOM
BIAS CELL
ICOM 2
INHI 1
TRANSCONDUCTANCE
OUTPUT
AMP
The curves in Figure 37 show typical input levels that can be
applied to this amplifier at different gain settings. The maximum input was determined by finding the 1 dB compression or
expansion point of the VOUT/VSOURCE gain. Note that this is not
VOUT/VIN. In this way, the change in the input impedance of the
device is also taken into account.
3.2
SHIFT REGISTER
AND LATCHES
DATA CLCK LTCH
Figure 35. Functional Block Diagram
PREAMPLIFIER
There are two selectable input preamplifiers. Selection is made
by the most significant bit (MSB) of the serial gain control dataword. In the high gain mode, the overall device gain is 7.1 Volts/
Volt (17 dB) above the low gain setting. The two preamplifiers
give the AD8370 the ability to accommodate a wide range of
input amplitudes. The overlap between the two gain ranges
allows the user some flexibility based on noise and distortion
demands. See the Choosing between Gain Ranges section for
more information.
<0.5dB
RES
2.8
Rev. 0 | Page 13 of 28
34dB
GAIN
2.0
LOW GAIN
<1dB
RES
2.4
VOUT [V peak] (V)
13
12
03692-0-001
AD8370
14
17dB
GAIN
HIGH GAIN
<0.5dB
RESOLUTION
<2dB
RES
1.6
12dB
GAIN
1.2
0.1dB GAIN
6dB
GAIN
0.8
–5dB GAIN
0.4
–8dB GAIN
<1dB
RES
<2dB
RES
–11dB GAIN
–25dB GAIN
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSOURCE [V peak] (V)
Figure 37. Gain Resolution and Nominal Input and
Output Range over the Gain Range
1.8
03692-0-023
VCCI
PRE
AMP
1mA
TRANSCONDUCTANCE STAGE
BLOCK ARCHITECTURE
PWUP 4
The input impedance is approximately 200 Ω differential,
regardless of which preamplifier is selected. Note that the input
impedance is formed by using active circuit elements and is not
set by passive components. See Figure 36 for a simplified
schematic of the input interface.
03692-0-018
The AD8370 is a low cost, digitally controlled, fine adjustment
variable gain amplifier that provides both high IP3 and low
noise figure. The AD8370 is fabricated on an ADI proprietary
high performance 25 GHz silicon bipolar process. The –3 dB
bandwidth is approximately 750 MHz throughout the variable
gain range. The typical quiescent current of the AD8370 is
78 mA. A power-down feature reduces the current to less than
4 mA. The input impedance is approximately 200 Ω differential,
and the output impedance is approximately 100 Ω differential to
be compatible with saw filters and matching networks used in
intermediate frequency (IF) radio applications. Because there is
no feedback between the input and output and stages within the
amplifier, the input amplifier is isolated from variations in
output loading and from subsequent impedance changes, and
excellent input to output isolation is realized. Excellent distortion performance and wide bandwidth make the AD8370 a
suitable gain control device for modern differential receiver
designs. The AD8370 differential input and output configuration
is ideally suited to fully differential signal chain circuit designs,
although it can be adapted to single-ended system applications,
if required.
AD8370
OUTPUT AMPLIFIER
Table 4. Serial Programming Timing Parameters
The output impedance is approximately 100 Ω differential and,
like the input preamplifier, this impedance is formed using
active circuit elements. See Figure 38 for a simplified schematic
of the output interface.
Parameter
Clock Pulse Width (TPW)
Clock Period (TCK)
Setup Time Data vs. Clock (TDS)
Setup Time Latch vs. Clock (TES)
Hold Time Latch vs. Clock (TEH)
OPHI/OPLO
Min
25
ns
50
10
20
10
ns
ns
ns
ns
10µA
740Ω
VCC/2
03692-0-017
03692-0-019
CLCK/DATA/LTCH/PWUP
Figure 38. OPHI/OPLO Simplified Circuit
Figure 40. Simplified Circuit for Digital Inputs
The gain of the output amplifier, and thus the AD8370 as a
whole, is load dependent. The following equation can be used to
predict the gain deviation of the AD8370 from that at 100 Ω as
the load is varied:
1.98
98
1+
RLOAD
VOCM
75Ω
VCC/2
For example, if RLOAD is 1 kΩ, the gain is a factor of 1.80 (5.12 dB)
above that at 100 Ω, all other things being equal. If RLOAD is 50 Ω,
the gain is a factor of 0.669 (3.49 dB) below that at 100 Ω.
Figure 41. Simplified Circuit for VOCM Output
DIGITAL INTERFACE AND TIMING
The digital control port uses a standard TTL interface. The 8-bit
control word is read in a serial fashion when the LTCH pin is
held low. The levels presented to the DATA pin are read on each
rising edge of the CLCK signal. Figure 39 illustrates the timing
diagram for the control interface. Minimum values for timing
parameters are presented in Table 4. Figure 40 is a simplified
schematic of the digital input pins.
TDS
DATA
(Pin 14)
MSB
MSB-1 MSB-2 MSB-3 LSB+3 LSB+2 LSB+1
TCK
LSB
TPW
CLCK
(Pin 13)
TEH
03692-0-038
TES
LTCH
(Pin 12)
03692-0-020
GainDeviation =
Figure 39. Digital Timing Diagram
Rev. 0 | Page 14 of 28
Unit
AD8370
APPLICATIONS
BASIC CONNECTIONS
Figure 42 shows the minimum connections required for basic
operation of the AD8370. Supply voltages between 3.0 V and
5.5 V are allowed. The supply to the VCCO and VCCI pins
should be decoupled with at least one low inductance, surfacemount ceramic capacitor of 0.1 µF placed as close as possible to
the device.
INLO
ICOM
DATA
CLCK
12
11
10
9
OPLO
13
OCOM
14
LTCH
15
VCCO
16
RL
INHI
ICOM
VCCI
PWUP
VOCM
VCCO
OCOM
OPHI
AD8370
RS
AV = GainCode Vernier(1 + (PreGain − 1) MSB)
1nF
RS
BALANCED
SOURCE
The theoretical linear voltage gain can be expressed with respect
to the gain code as
where:
SERIAL CONTROL
INTERFACE
1nF
2
in that range is given by LG127. The same is true for the high
gain range. Both LG0 and HG0 essentially turn off the variable
transconductance stage, and thus no output is available with
these codes. See Figure 24.
1
2
3
4
5
6
7
8
BALANCED
LOAD
AV is the linear voltage gain.
GainCode is the digital gain control word minus the MSB (the
final 7 bits).
Vernier = 0.055744 V/V
PreGain = 7.079458 V/V
MSB is the most significant bit of the 8-bit gain control word.
The MSB sets the device in either high gain mode (MSB = 1 ) or
low gain mode (MSB = 0).
2
1nF
1nF
1nF
0.1µF
03692-0-037
0.1µF
+VS (3.0V TO 5.0V)
For example, a gain control word of HG45 (or 10101101 binary)
results in a theoretical linear voltage gain of 17.76 Volts/Volt,
calculated as
45 × 0.055744 × (1 + (7.079458 − 1) × 1)
Figure 42. Basic Connections
The AD8370 is designed to be used in differential signal chains.
Differential signaling allows improved even-order harmonic
cancellation and better common-mode immunity than can be
achieved using a single-ended design. To fully exploit these
benefits, it is necessary to drive and load the device in a
balanced manner. This requires some care to ensure that the
common-mode impedance values presented to each set of
inputs and outputs are balanced. Driving the device with an
unbalanced source can degrade the common-mode rejection
ratio. Loading the device with an unbalanced load can cause
degradation to even-order harmonic distortion and premature
output compression. In general, optimum designs are fully
balanced, although the AD8370 still provides impressive
performance when used in an unbalanced environment.
The AD8370 is a fine adjustment, variable gain amplifier. The
gain control transfer function is linear in voltage gain. On a
decibel scale, this results in the logarithmic transfer functions
indicated in Figure 4. At the low end of the gain transfer
function, the slope is steep, providing a rather coarse control
function. At the high end of the gain control range, the decibel
step size decreases, allowing precise gain adjustment.
GAIN CODES
The AD8370’s two gain ranges are referred to as high gain (HG)
and low gain (LG). Within each range, there are 128 possible
gain codes. Therefore, the minimum gain in the low gain range
is given by the nomenclature LG0 whereas the maximum gain
Increments or decrements in gain within either gain range are
simply a matter of operating on the GainCode. Six –dB gain
steps, which are equivalent to doubling or halving the linear
voltage gain, are accomplished by doubling or halving the
GainCode.
When power is first applied to the AD8370, the device is
programmed to code LG0 to avoid overdriving the circuitry
following it.
POWER-UP FEATURE
The power-up feature does not affect the GainCode and the gain
setting is preserved when in power-down mode. Powering
down the AD8370 (bringing PWUP low while power is still
applied to the device) does not erase or change the GainCode
from the AD8370, and the same gain code is in place when the
device is powered up, that is, when PWUP is brought high
again. Removing power from the device all together and
reapplying, however, reprograms to LG0.
CHOOSING BETWEEN GAIN RANGES
There is some overlap between the two gain ranges; users can
choose which one is most appropriate for their needs. When
deciding which preamp to use, consider resolution, noise,
linearity, and spurious-free dynamic range (SFDR). The most
important points to keep in mind are
•
The low gain range has better gain resolution.
•
The high gain range has a better noise figure.
Rev. 0 | Page 15 of 28
AD8370
•
The high gain range has better linearity and SFDR at
higher gains.
•
Conversely, the low gain range has higher SFDR at lower
gains.
LAYOUT AND OPERATING CONSIDERATIONS
Figure 43 provides a summary of noise, OIP3, IIP3, and SFDR
as a function of device power gain. SFDR is defined as
SFDR =
2
(IIP3 −NF − N S )
3
When laying out an RF trace with a controlled impedance,
consider the following:
where:
IIP3 is the input third-order intercept point, the output
intercept point in dBm minus the gain in dB.
NF is the noise figure in dB.
NS is source resistor noise, –174 dBm for a 1 Hz bandwidth at
300°K (27°C).
In general, NS = 10 log10(kTB), where k = 1.374 ×10−23 , T is the
temperature in degrees Kelvin, and B is the noise bandwidth in
Hertz.
•
Space the ground plane to either side of the signal trace at
least 3 line-widths away to ensure that a microstrip
(vertical dielectric) line is formed, rather than a coplanar
(lateral dielectric) waveguide.
•
Ensure that the width of the microstrip line is constant and
that there are as few discontinuities as possible , such as
component pads, along the length of the line. Width variations cause impedance discontinuities in the line and may
result in unwanted reflections.
•
Do not use silkscreen over the signal line because it alters
the line impedance.
•
Keep the length of the input and output connection lines
as short as possible.
180
NF LOW GAIN
40
OIP3 LOW GAIN
OIP3 HIGH GAIN
160
IIP3 LOW GAIN
IIP3 HIGH GAIN
150
140
10
NF HIGH GAIN
0
130
–10
120
–20
–30
–30
SFDR LOW GAIN
100
–10
0
10
20
30
40
POWER GAIN (dB)
Figure 44 shows the cross section of a PC board and Table 5
show the dimensions that provide a 100 Ω line impedance for
FR-4 board material with εr = 4.6.
Table 5.
100 Ω
22 mils
53 mils
2 mils
W
H
T
110
SFDR HIGH GAIN
–20
SFDR (dB)
30
170
03692-0-004
NOISE FIGURE (dB), OIP3 AND IIP3 (dBm)
50
20
Each input and output pin of the AD8370 presents either a
100 Ω or 50 Ω impedance relative to their respective ac grounds.
To ensure that signal integrity is not seriously impaired by the
printed circuit board, the relevant connection traces should
provide an appropriate characteristic impedance to the ground
plane. This can be achieved through proper layout.
3W
50 Ω
13 mils
8 mils
2 mils
W
3W
Figure 43. OIP3, IIP3, NF, and SFDR Variation with Gain
T
H
ER
03692-0-021
As the gain increases, the input amplitude required to deliver
the same output amplitude is reduced. This results in less
distortion at the input stage, and therefore the OIP3 increases.
At some point, the distortion of the input stage becomes small
enough such that the nonlinearity of the output stage becomes
dominant. The OIP3 does not improve significantly as the gain
is increased beyond this point, which explains the knee in the
OIP3 curve. The IIP3 curve has a knee for the same reason;
however, as the gain is increased beyond the knee, the IIP3
starts to decrease rather than increase. This is because in this
region OIP3 is constant, therefore the higher the gain, the lower
the IIP3. The two gain ranges have equal SFDR at approximately
13 dB power gain.
Figure 44. Cross-Sectional View of a PC Board
It possible to approximate a 100 Ω trace on a board designed
with the 50 Ω dimensions above by removing the ground plane
within 3 line-widths of the area directly below the trace.
The AD8370 contains both digital and analog sections. Care
should be taken to ensure that the digital and analog sections
are adequately isolated on the PC board. The use of separate
ground planes for each section connected at only one point via
a ferrite bead inductor ensures that the digital pulses do not
adversely affect the analog section of the AD8370.
Rev. 0 | Page 16 of 28
AD8370
0.5
High transient and noise levels on the power supply, ground,
and digital inputs can, under some circumstances, reprogram the
AD8370 to an unintended gain code. This further reinforces the
need for proper supply bypassing and decoupling. The user
should also be aware that probing the AD8370 and associated
circuitry during circuit debug may also induce the same effect.
HIGH GAIN MODE
(GAIN CODE HG255)
0
–0.5
LOW GAIN MODE
(GAIN CODE LG127)
–1.0
0
100
200
300
400
500
FREQUENCY (MHz)
03692-0-040
DIFFERENTIAL BALANCE (dB)
Due to the nature of the AD8370’s circuit design, care must be
taken to minimize parasitic capacitance on the input and output.
The AD8370 could become unstable with more than a few pF of
shunt capacitance on each input. Using resistors in series with
input pins is recommended under conditions of high source
capacitance.
Figure 46. Differential Output Balance for a Single-Ended Input Drive at
Maximum Gain (RL = 1 kΩ, CAC = 10 nF)
PACKAGE CONSIDERATIONS
The package of the AD8370 is a compact, thermally enhanced
TSSOP 16-lead design. A large exposed paddle on the bottom of
the device provides both a thermal benefit and a low inductance
path to ground for the circuit. To make proper use of this packaging feature, the PCB needs to make contact directly under the
device, connected to an ac/dc common ground reference with
as many vias as possible to lower the inductance and thermal
impedance.
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
SERIAL CONTROL
INTERFACE
CAC
Figure 46 illustrates the differential balance at the output for a
single-ended input drive for multiple gain codes. The differential
balance is better than 0.5 dB for signal frequencies less than
250 MHz. Figure 47 depicts the differential balance over the
entire gain range at 10 MHz. The balance is degraded for lower
gain settings because the finite common gain allows some of the
input signal applied to INHI to pass directly through to the
OPLO pin. At higher gain settings, the differential gain dominates
and balance is restored.
0.6
LOW GAIN MODE
CAC
HIGH GAIN MODE
10
9
OPLO
11
OCOM
12
LTCH
13
VCCO
14
CLCK
15
DATA
INLO
16
ICOM
RS
SINGLEENDED
SOURCE
DIFFERENTIAL BALANCE (dB)
0.5
RL
INHI
ICOM
VCCI
PWUP
VOCM
VCCO
OCOM
OPHI
AD8370
1
2
3
4
5
6
7
8
0.4
0.3
0.2
0.1
0.1µF
1nF
0.1µF
+VS
0
Figure 45. Single-Ended-to-Differential Conversion
The AD8370 is primarily designed for differential signal interfacing. The device can be used for single-ended-to-differential
conversion simply by terminating the unused input to ground
using a capacitor as depicted in Figure 45. The ac coupling
capacitors should be selected such that their reactance is negligible at the frequency of operation. For example, using 1 nF
capacitors for CAC presents a capacitive reactance of –j1.6 Ω on
each input node at 100 MHz. This attenuates the applied input
voltage by 0.003 dB. If 10 pF capacitors had been selected, the
voltage delivered to the input would be reduced by 2.1 dB when
operating with a 200 Ω source impedance.
0
32
64
96
0
32
64
GAIN CODE
96
128
03692-0-041
CAC
03692-0-039
CAC
Figure 47. Differential Output Balance at 10 MHz for a Single-Ended Drive vs.
Gain Code (RL = 1 kΩ, CAC = 10 nF)
Even though the amplifier is no longer being driven in a balanced manner, the distortion performance remains adequate for
most applications. Figure 48 illustrates the harmonic distortion
performance of the circuit in Figure 45 over the entire gain range.
If the amplifier is driven in single-ended mode, the input
impedance varies depending on the value of the resistor used to
terminate the other input as follows:
RinSE = RinDIFF + RTERM
where RTERM is the termination resistor connected to the other
input.
Rev. 0 | Page 17 of 28
AD8370
The AD8370 is also a dc accurate variable gain amplifier. The
common-mode dc voltage present at the output pins is internally
set to midsupply using what is essentially a buffered resistive
divider network connected between the positive supply rail and
the common (ground) pins. The input pins are at a slightly
higher dc potential, typically 250 mV to 550 mV above the output pins, depending on gain setting. In a typical single-supply
application, it is necessary to raise the common-mode reference
level of the source and load to roughly midsupply to maintain
symmetric swing and to avoid sinking or sourcing strong bias
currents from the input and output pins. It is possible to use
balanced dual supplies to allow ground referenced source and
load as indicated in Figure 49. By connecting the VOCM pin
and unused input to ground, the input and output commonmode potentials are forced to virtual ground. This allows direct
coupling of ground referenced source and loads. The initial
differential input offset is typically only a few 100 µV. Over
temperature, the input offset could be as high as a few tens of
mVs. If precise dc accuracy is need over temperature and time, it
may be necessary to periodically measure the input offset and to
apply the necessary opposing offset to the unused differential
input, canceling the resulting output offset.
–40
HARMONIC DISTORTION (dBc)
–50
–60
HD2
HD2
–70
–80
HD3
HD3
–90
LOW GAIN MODE
0
32
64
HIGH GAIN MODE
96
0
32
64
96
03692-0-042
–100
128
GAIN CODE
Figure 48. Harmonic Distortion of the Circuit in Figure 45
DC-COUPLED OPERATION
–2.5V
SERIAL CONTROL
INTERFACE
0V
1nF
DATA
CLCK
12
11
10
9
OPLO
13
OCOM
14
LTCH
15
VCCO
16
INLO
RS
SINGLEENDED
GROUND
REFERENCED
SOURCE
ICOM
RT
RL
INHI
ICOM
VCCI
PWUP
VOCM
VCCO
OCOM
OPHI
AD8370
1
2
3
4
5
6
7
8
0V
–2.5V
0.1µF
03692-0-043
1nF
+2.5V
0.1µF
To address situations where dual supplies are not convenient, a
second option is presented in Figure 50. The AD8138 differential
amplifier is used to translate the common-mode level of the
driving source to midsupply, which allows dc accurate performance with a ground-referenced source without the need for dual
supplies. The bandwidth of the solution in Figure 50 is limited
by the gain-bandwidth product of the AD8138. The normalized
frequency response of both implementations is shown in Figure 51.
10
SERIAL CONTROL
INTERFACE
100Ω
RT
2
499Ω
9
OPLO
PWUP
VOCM
VCCO
OCOM
OPHI
2
3
4
5
6
7
8
AD8370
USING DUAL
±2.5V SUPPLY
–4
–6
10
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
VOCM
1nF
03692-0-044
0.1µF
0
–2
–10
+5V
SINGLE-ENDED GROUND
REFERENCED SOURCE
2
1
100Ω
1nF
AD8370 WITH
AD8138 SINGLE
+5V SUPPLY
4
–8
RL
1
6
Figure 50. DC Coupling the AD8370. The AD8138 is used as a unity gain level
shifting amplifier to lift the common-mode level of the source to midsupply.
Rev. 0 | Page 18 of 28
Figure 51. Normalized Frequency Response of the Two Solutions in
Figure 49 and Figure 50
03692-0-045
10
OCOM
LTCH
VCCO
11
VCCI
RS
12
ICOM
499Ω
13
AD8370
VOCM
AD8138
14
INHI
RT
15
CLCK
INLO
16
DATA
+5V
499Ω
ICOM
499Ω
VOCM
NORMALIZED RESPONSE (dB)
8
Figure 49. DC Coupling the AD8370. Dual supplies are used to set the input
and output common-mode levels to 0 V.
AD8370
Although the AD8370 is designed to provide a 100 Ω output
source impedance, the device is capable of driving a variety of
loads while maintaining reasonable gain and distortion performance. A common application for the AD8370 is ADC
driving in IF sampling receivers and broadband wide dynamic
range digitizers. The wide gain adjustment range allows the use
of lower resolution ADCs. Figure 52 illustrates a typical ADC
interface network.
ROP
CAC
ZS
RIP
AD8370
VIN
ZP
100Ω
RT
ZIN
ADC
VOCM
ROP
CAC
ZS
RIP
03692-0-046
VIN
Figure 52. Generic ADC Interface
Many factors need to be considered before defining component
values used in the interface network, such as the desired frequency range of operation, the input swing, and input impedance
of the ADC. AC coupling capacitors, CAC, should be used to
block any potential dc offsets present at the AD8370 outputs,
which would otherwise consume the available low-end range of
the ADC. The CAC capacitors should be large enough so that
they present negligible reactance over the intended frequency
range of operation. The VOCM pin may serve as an external
reference for ADCs that do not include an on-board reference.
In either case, it is suggested that the VOCM pin be decoupled
to ground through a moderately large bypassing capacitor (1 nF
to 10 nF) to help minimize wideband noise pick-up.
After defining reasonable values for coupling capacitors,
suppressing resistors, and the terminating resistor, it is time to
design the intermediate filter network. The example in
Figure 52 suggests a second-order low-pass filter network
comprised of series inductors and a shunt capacitor. The order
and type of filter network used depends on the desired high
frequency rejection required for the ADC interface, as well as
on pass-band ripple and group delay. In some situations, the
signal spectra may already be sufficiently band-limited such
that no additional filter network is necessary, in which case ZS
would simply be a short and ZP would be an open. In other
situations, it may be necessary to have a rather high-order antialiasing filter to help minimize unwanted high frequency
spectra from being aliased down into the first Nyquist zone of
the ADC.
To properly design the filter network, it is necessary to consider
the overall source and load impedance presented by the AD8370
and ADC input, including the additional resistive contribution
of suppression and terminating resistors. The filter design can
then be handled by using a single-ended equivalent circuit as
shown in Figure 53. A variety of references that address filter
synthesis are available. Most provide tables for various filter
types and orders, indicating the normalized inductor and capacitor values for a 1 Hz cutoff frequency and 1 Ω load. After scaling
the normalized prototype element values by the actual desired
cut-off frequency and load impedance, it is simply a matter of
splitting series element reactances in half to realize the final
balanced filter network component values.
SOURCE
RS
Depending on the input impedance presented by the input
system of the ADC, it may be desirable to terminate the ADC
input down to a lower impedance by using a terminating
resistor, RT. The high frequency response of the AD8370
exhibits greater peaking when driving very light loads. In
addition, the terminating resistor helps to better define the
input impedance at the ADC input. Any part-to-part variability
of ADC input impedance is reduced when shunting down the
ADC inputs by using a moderate tolerance terminating resistor
(typically a 1% value is acceptable).
ZS
SINGLE-ENDED
EQUIVALENT
VS
Often it is wise to include input and output parasitic suppression
resistors, RIP and ROP. Parasitic suppressing resistors help to
prevent resonant effects that occur as a result of internal bondwire inductance, pad to substrate capacitance, and stray
capacitance of the printed circuit board trace artwork. If
omitted, undesirable settling characteristics may be observed.
Typically, only 10 Ω to 25 Ω of series resistance is all that is
needed to help dampen resonant effects. Considering that most
ADCs present a relatively high input impedance, very little
signal is lost across the RIP and ROP series resistors.
LOAD
RS
2
RS
2
RL
ZS
2
BALANCED
CONFIGURATION
VS
ZP
ZP
RL
2
RL
2
ZS
2
03692-0-047
ADC INTERFACING
Figure 53. Single-Ended-to-Differential Network Conversion
As an example, a second-order Butterworth low-pass filter
design is presented where the differential load impedance is
1200 Ω, and the padded source impedance of the AD8370 is
assumed to be 120 Ω. The normalized series inductor value for
the 10-to-1 load-to-source impedance ratio is 0.074H, and the
normalized shunt capacitor is 14.814 F. For a 70 MHz cutoff
frequency, the single-ended equivalent circuit consists of a
200 nH series inductor followed by a 27 pF capacitor. To realize
the balanced equivalent, simply split the 200 nH inductor in
half to realize the network shown in Figure 54.
Rev. 0 | Page 19 of 28
AD8370
RS =
RS
= 0.1
RL
0
LN = 0.074H
–10
NORMALIZED
SINGLE-ENDED
EQUIVALENT
VS
CN
–20
RL= 1Ω
14.814F
–30
–40
fC = 1Hz
dBFS
RS = 120Ω
–50
200nH
–60
–70
–80
DE-NORMALIZED
SINGLE-ENDED
EQUIVALENT
VS
RL= 1200Ω
27pF
–90
–100
–110
fC = 70MHz
–130
100nH
0
BALANCED
CONFIGURATION
RS
= 60Ω
2
20
27pF
RL
2 = 600Ω
100nH
30
40
50
60
Figure 55. FFT Plot of Two-Tone Intermodulation Distortion at
42 MHz for the Circuit in Figure 56
In Figure 55, the intermodulation products are comparable to
the noise floor of the ADC. The spurious-free dynamic range of
the combination is better than 66 dB for a 70 MHz measurement
bandwidth.
Figure 54. Second-Order Butterworth Low-Pass Filter Design Example
A complete design example is shown in Figure 56. The AD8370
is configured for single-ended-to-differential conversion with
the input terminated down to present a single-ended 75 Ω input.
A sixth-order Chebyshev differential filter is used to interface
the output of the AD8370 to the input of the AD9430 170 MSPS
12-bit ADC. The filter minimizes aliasing effects and improves
harmonic distortion performance.
3 V OPERATION
It is possible to operate the AD8370 at voltages as low as 3 V
with only minor performance degradation. Table 6 gives typical
specifications for operation at 3 V.
Table 6.
Parameter
Ouptut IP3
P1dB
−3 dB Bandwidth
IMD3
The input of the AD9430 is terminated with a 1.5 kΩ resistor so
that the overall load presented to the filter network is ~1 kΩ.
The variable gain of the AD8370 extends the useable dynamic
range of the ADC. The measured intermodulation distortion of
the combination is presented in Figure 55 at 42 MHz.
Typical (70 MHz, RL = 100 Ω)
+23.5 dBm
+12.7 dBm
650 MHz (HG 127)
−82 dBc (RL = 1 kΩ)
SERIAL CONTROL INTERFACE
FROM 75Ω
Tx-LINE
CAC
CAC
100nF
68nH
180nH
220nH
25Ω
VINA
INLO
DATA
CLCK
12
11
10
9
OPLO
13
OCOM
14
LTCH
15
VCCO
16
ICOM
120Ω
100nF
AD8370
ICOM
VCCI
PWUP
VOCM
VCCO
OCOM
OPHI
27pF
INHI
1
2
3
4
5
6
7
8
CAC
CAC
68nH
39pF
180nH
27pF
220nH
1.5kΩ
AD9430
25Ω
VINB
100nF
1nF
100nF
0.1µF
0.1µF
03692-0-049
RS
70
FREQUENCY (MHz)
03692-0-048
VS
10
RL
2 = 600Ω
03692-0-050
–120
RS
= 60Ω
2
+VS
Figure 56. ADC Interface Example
Rev. 0 | Page 20 of 28
AD8370
EVALUATION BOARD AND SOFTWARE
The evaluation board allows quick testing of the AD8370 by
using standard 50 Ω test equipment. The schematic is shown in
Figure 57. Transformers T1 and T2 are used to transform 50 Ω
source and load impedances to the desired input and output
reference levels. The top and bottom layers are shown in
Figure 61 and Figure 62. The ground plane was removed under
the traces between T1 and pins INHI and INLO to approximate
a 100 Ω characteristic impedance.
1
2
3
14
15
4
16
5
The evaluation board comes with the AD8370 control software
that allows serial gain control from most computers. The
evaluation board is connected via a cable to the parallel port of
the computer. Simply by adjusting the slider bar in the control
software, the gain code is automatically updated to the AD8370.
6
17
18
7
19
8
20
9
21
10
22
11
23
12
24
13
25
D-SUB 25 PIN MALE
L2*
C9
R7 R6 R5
1kΩ 1kΩ 1kΩ
C1
12
11
10
9
LTCH
OCOM
OPLO
13
VCCO
R2
0Ω
14
CLCK
1:4
15
DATA
T2
16
INLO
T1
ICOM
R4
0Ω
PWUP
VOCM
VCCO
OCOM
OPHI
1
2
3
4
5
6
7
8
JTX-2-10T
2:1
AD8370
R1
0Ω
VCCI
50Ω Tx LINE
1nF
ICOM
50Ω Tx LINE
OUT+
50Ω Tx LINE
OUT–
R3
0Ω
C2
C4
1nF
1nF
C8
0.1µF
C5
0.1µF
C6
1µF
SW1
PWUP
L1*
VOCM
+VS
R9
OPEN
R8 49.9Ω
C7
0.1µF
GND
C10 OPEN
P2
1
2
3
4
5
VS
GND
*EMI SUPPRESSION FERRITE
HZ1206E601R-00
Figure 57. AD8370 Evaluation Board Schematic
Rev. 0 | Page 21 of 28
03692-0-051
IN–
TC4-1W
50Ω Tx LINE
C3
1nF
INHI
IN+
OPEN
AD8370
Figure 58. Evaluation Software
Table 7. AD8370 Evaluation Board Configuration Options
Component
VS, GND,
VOCM
SW1, R8, C10,
PWUP
P1, R5, R6, R7,
C9
J1, J2, J6, J7
C1, C2, C3, C4
T1, T2
R1, R2, R3, R4
C5, C6, C7, C8
L1, L2
Function
Power Interface Vector Pins. Apply supply voltage between VS and GND. The VOCM pin
allows external monitoring of the common-mode input and output bias levels.
Device Enable. Set to position B to power up the device. When in position A, the PWUP
pin is connected to the PWUP vector pin. The PWUP pin allows external power cycling
of the device. R8 and C10 are provided to allow for proper cable termination.
Serial Control Interface. The evaluation board can be controlled using most PCs.
Windows® based control software is shipped with the evaluation kit. A 25-pin D-sub
connector cable is required to connect the PC to the evaluation board. It may be
necessary to use a capacitor on the clock line, depending on the quality of the PC port
signals. A 1 nF capacitor for C9 is usually sufficient for reducing clock overshoot.
Input and Output Signal Connectors. These SMA connectors provide a convenient way
to interface the evaluation board with 50 Ω test equipment. Typically the device is
evaluated using a single-ended source and load. The source should connect to J1 (IN+),
and the load should connect to J6 (OUT+).
AC Coupling Capacitors. Provide ac coupling of the input and output signals.
Impedance Transformers. T1 provides a 50 Ω to 200 Ω impedance transformation. T2
provides a 100 Ω to 50 Ω impedance transformation.
Single-Ended or Differential. R2 and R4 are used to ground the center tap of the
secondary windings on transformers T1 and T2. R1 and R3 should be used to ground J2
and J7 when used in single ended applications.
Power Supply Decoupling. Nominal supply decoupling consists of a ferrite bead series
inductor followed by a 1 µF capacitor to ground followed by a 0.1 µF capacitor to
ground positioned as close to the device as possible. C7 provides additional decoupling
of the input common-mode voltage. L1 provides high frequency isolation between the
input and output power supply. L2 provides high frequency isolation between the
analog and digital ground.
Rev. 0 | Page 22 of 28
Default Condition
Not applicable
SW1 = installed
R8 = 49.9 Ω (Size 0805)
C10 = open (Size 0805)
P1 = installed
R5, R6, R7 = 1 kΩ (Size 0603)
C9 = open (Size 0603)
Not applicable
C1, C2, C3, C4 = 1 nF (Size 0603)
T1 = TC4 −1W (MiniCircuits)
T2 = JTX−2−10T (MiniCircuits)
R1, R2, R3, R4 = 0 Ω (Size 0603)
C6 = 1 µF (Size 0805)
C5, C7, C8 = 0.1 µF (Size 0603)
L1, L2 = HZ1206E601R-00
(Steward, Size 1206)
Figure 59. Evaluation Board Top Silkscreen
03692-0-077
03692-0-076
AD8370
03692-0-078
03692-0-079
Figure 61. Evaluation Board Top
Figure 62. Evaluation Board Bottom
Figure 60. Evaluation Board Bottom Silkscreen
Rev. 0 | Page 23 of 28
AD8370
APPENDIX
CHARACTERIZATION EQUIPMENT
DEFINITIONS OF SELECTED PARAMETERS
An Agilent N4441A Balanced Measurement System was used to
obtain the gain, phase, group delay, reverse isolation, CMRR,
and s-parameter information contained in this data sheet. With
the exception for the s-parameter information, T-attenuator
pads were used to match the 50 Ω impedance of this instrument’s
ports to the AD8370. An Agilent 4795A Spectrum Analyzer was
used to obtain nonlinear measurements IMD, IP3, and P1dB
through matching baluns and/or attenuator networks. Various
other measurements were taken with setups shown in this
section.
Common-mode rejection ratio (Figure 26) has been defined for
this characterization effort as
Differenti al Mode Gain
Common Mode Gain
where the numerator is the gain into a differential load at the
output due to a differential source at the input, and the
denominator is the gain into a differential-mode load at the
output due to a common-mode source at the input. In terms of
mixed-mode s-parameters, this equates to
COMPOSITE WAVEFORM ASSUMPTION
The nonlinear two-tone measurements made for this data sheet,
i.e., IMD and IP3, are based on the assumption of a fixed value
composite waveform at the output, generally 1 V p-p. The frequencies of interest dictate the use of RF test equipment, and
because this equipment is generally not designed to work in
units of volts, but rather watts and dBm, an assumption was
made to facilitate equipment setup and operation. Two sinusoidal
tones can be represented as
SDD21
SDC21
More information on mixed-mode s-parameters can be
obtained in a reference by Bockelman, D.E. and Eisenstadt,
W.R., Combined Differential and Common-Mode Scattering
Parameters: Theory and Simulation. IEEE Transactions on
Microwave Theory and Techniques, v 43, n 7, 1530 (July 1995).
Reverse isolation (Figure 24) is defined as SDD12.
Power supply rejection ratio (PSRR) has been defined as
V1 = V sin (2∏f1t)
Adm
As
V2 = V sin (2∏f2t)
The RMS average voltage of one tone is
1
T
T
∫
(V1 ) 2 dt =
0
where Adm is the differential mode forward gain (SDD21), and
As is the gain from the power supply pins (VCCI and VCCO,
taken together) to the output (OPLO and OPHI, taken differentially), corrected for impedance mismatch. The following
reference provides more information: Gray, P.R., Hurst, P.J.,
Lewis, S.H. and Meyer, R.G., Analysis and Design of Analog
Integrated Circuits, 4th Edition, John Wiley & Sons, Inc., page 422.
1
2
where T is the period of the waveform. The RMS average
voltage of the two-tone composite signal is
1
T
T
∫ (V
1
+ V2 ) 2 dt = 1
0
It can be shown that the average power of this composite
waveform is twice (3 dB) that of the single tone. This also means
that the composite peak-to-peak voltage is twice (6 dB) that of a
single tone. This principle can be used to set correct input
amplitudes from generators scaled in dBm and is correct if the
two tones are of equal amplitude and are reasonably close in
frequency.
Rev. 0 | Page 24 of 28
AD8370
–22.5dB
PORT 1
SERIAL DATA
SOURCE
VS 5.0V
1nF
1nF
T1
T2
LTCH
VCCO
OCOM
OPLO
VCCO
OCOM
OPHI
1
2
3
4
5
6
7
8
ICOM
CLCK
9
VOCM
10
PWUP
11
VCCI
12
ICOM
13
INHI
0Ω
14
MINICIRCUITS
TC2-1T
PORT 2
AGILENT 8753D
NETWORK ANALYZER
15
INLO
16
DATA
MINICIRCUITS
TC4-1W
AD8370
1nF
1nF
VS 5.0V
1µF
1nF
1nF
1nF
03692-0-064
VS 5.0V
1µF
Figure 63. PSRR Adm Test Setup
PORT 1
BIAS TEE
CONNECTION
TO PORT 1
SERIAL DATA
SOURCE
1nF
VCCO
OCOM
OPLO
OCOM
OPHI
3
4
5
6
7
8
DATA
2
INLO
1
ICOM
VCCO
9
LTCH
10
VOCM
11
CLCK
12
PWUP
13
VCCI
14
ICOM
15
INHI
16
MINICIRCUITS
TC2-1T
AD8370
1nF
1nF
1nF
03692-0-066
200Ω
PORT 2
AGILENT 8753D
NETWORK ANALYZER
1nF
Figure 64. PSRR As Test Setup
Rev. 0 | Page 25 of 28
AD8370
HP8133A
3GHz PULSE
GENERATOR
50Ω
INPUT
AUX IN
TEKTRONIX TDS5104
DPO OSCILLOSCOPE
50Ω
INPUT
TRIG
3dB
ATTEN
OUT
6dB
SPLITTER
50Ω
50Ω
INPUT INPUT
SERIAL DATA
SOURCE
VS 5.0V
3dB
ATTEN
475Ω
2dB
ATTEN
52.3Ω
LTCH
VCCO
OCOM
OPLO
OCOM
OPHI
3
4
5
6
7
8
DATA
2
ICOM
VCCO
9
CLCK
10
VOCM
11
PWUP
12
VCCI
13
1
INLO
200Ω
14
ICOM
3dB
ATTEN
AD8370
6dB
SPLITTER
OUT
15
INHI
16
475Ω
3dB
ATTEN
2dB
ATTEN
52.3Ω
1µF
1nF
1nF
1nF
03692-0-080
VS 5.0V
1µF
VS 5.0V
Figure 65. DC Pulse Response and Overdrive Recovery Test Setup
AGILENT 8648D
SIGNAL
GENERATOR
TEKTRONIX
TDS5104 DPO
OSCILLOSCOPE
SERIAL DATA
SOURCE
TEKTRONIX
P6205 ACTIVE
FET PROBE
RF OUT
VS 5.0V
1nF 475Ω
1nF
14
13
12
11
10
9
DATA
CLCK
LTCH
VCCO
OCOM
OPLO
MINICIRCUITS
JTX-2-10T
105Ω
INHI
ICOM
VCCI
PWUP
VOCM
VCCO
OCOM
OPHI
AD8370
1
2
3
4
5
6
7
8
1nF 475Ω
1nF
VS 5.0V
VS 5.0V
1µF
50Ω INPUT
1nF
1nF
1nF
1µF
Figure 66. Gain Step Time Domain Response Test Setup
Rev. 0 | Page 26 of 28
03692-0-081
0Ω
15
INLO
T2
16
ICOM
T1
MINICIRCUITS
TC4-1W
50Ω INPUT
AD8370
AGILENT 8648D
SIGNAL
GENERATOR
10MHz REF OUT
TEKTRONIX
TDS5104 DPO
OSCILLOSCOPE
SERIAL DATA
SOURCE
RF OUT
VS 5.0V
1nF 475Ω
1nF
11
10
9
OPLO
CLCK
12
OCOM
13
LTCH
14
VCCO
15
DATA
MINICIRCUITS
JTX-2-10T
105Ω
INHI
ICOM
VCCI
PWUP
VOCM
VCCO
OCOM
OPHI
AD8370
1
2
3
4
5
6
7
8
1nF 475Ω
1nF
10MHz IN
OUTPUT
AGILENT 33250A
FUNCTION/ARBITRARY
WAVEFORM
GENERATOR
VS 5.0V
VS 5.0V
1µF
50Ω INPUT
1nF
1nF
52.3Ω
TEKTRONIX
P6205 ACTIVE
FET PROBE
50Ω INPUT
1µF
1nF
Figure 67. PWUP Response Time Domain Test Setup
Rev. 0 | Page 27 of 28
03692-0-082
0Ω
16
INLO
T2
MINICIRCUITS
TC4-1W
ICOM
T1
AD8370
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
BOTTOM
VIEW
9
4.50
4.40
4.30
TOP
VIEW
1
EXPOSED
PAD
(Pins Up)
6.40
BSC
3.00
SQ
8
1.05
1.00
0.80
1.20 MAX
0.15
0.00 SEATING 0.65
BSC
PLANE
0.30
0.19
0.20
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-ABT
Figure 68. 16-Lead TSSOP (RE-16)
ORDERING GUIDE
Model
AD8370ARE
AD8370ARE-REEL7
AD8370-EVAL
Temperature
–40°C to +85°C
–40°C to +85°C
Package Description
16-lead TSSOP, Tube
16-lead TSSOP, 7” Reel
Evaluation Board
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03692-0-1/04(0)
Rev. 0 | Page 28 of 28
Package Option
RE-16
RE-16