AD ADM1068ACP Super sequencerâ ¢ and monitor Datasheet

FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
8 supply fault detectors enable supervision of supplies to
better than 1% accuracy
4 selectable input attenuators allow supervision:
Supplies up to 14.4 V on VH
Supplies up to 6 V on VP1–3
4 dual-function inputs, VX1–4
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable output drivers (PDO1–8):
Open collector with external pull-up
Push/pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge-pumped high drive for use with external
N-FET (PDO1–6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs:
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Device powered by the highest of VP1–3, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPn = 1.2 V
32-lead 7 mm × 7 mm LQFP package
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND
VREF
SDA SCL A1
A0
SMBus
INTERFACE
ADM1068
EEPROM
VX1
VX2
VX3
VX4
CONFIGURABLE
OUTPUT
DRIVERS
DUALFUNCTION
INPUTS
PDO1
PDO2
PDO3
(HV CAPABLE
OF DRIVING
GATES OF
N-CHANNEL FET)
(LOGIC INPUTS
OR
SFDs)
PDO4
PDO5
PDO6
SEQUENCING
ENGINE
VP1
VP2
CONFIGURABLE
OUTPUT
DRIVERS
PROGRAMMABLE
RESET
GENERATORS
VP3
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
(SFDs)
VH
AGND
VDDCAP
PDO7
PDO8
PDOGND
VDD
ARBITRATOR
04734-001
Preliminary Technical Data
Super Sequencer™ and Monitor
ADM1068
GND
Figure 1.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1068 is a configurable supervisory/sequencing device
that offers a single-chip solution for supply monitoring and
sequencing in multiple supply systems.
(continued on Page 3)
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADM1068
Preliminary Technical Data
TABLE OF CONTENTS
General Description ......................................................................... 3
Warnings...................................................................................... 15
Specifications..................................................................................... 4
SMBus Jump/Unconditional Jump .......................................... 15
Pin Configuration and Function Descriptions............................. 6
Sequencing Engine Application Example ............................... 16
Absolute Maximum Ratings............................................................ 7
Sequence Detector...................................................................... 17
Thermal Characteristics .............................................................. 7
Monitoring Fault Detector ........................................................ 17
ESD Caution.................................................................................. 7
Timeout Detector ....................................................................... 17
Typical Performance Characteristics ............................................. 8
Fault Reporting........................................................................... 17
Powering the ADM1068 ................................................................ 10
Applications Diagram .................................................................... 18
Inputs................................................................................................ 11
Communicating with the ADM1068 ........................................... 19
Supply Supervision..................................................................... 11
Configuration Download at Power-Up................................... 19
Programming the Supply Fault Detectors............................... 11
Updating the Configuration ..................................................... 19
Input Comparator Hysteresis.................................................... 12
Updating the Sequencing Engine............................................. 20
Input Glitch Filtering ................................................................. 12
Internal Registers........................................................................ 20
Supply Supervision with VXn Inputs....................................... 12
EEPROM ..................................................................................... 20
VXn Pins as Digital Inputs........................................................ 13
Serial Bus Interface..................................................................... 20
Outputs ............................................................................................ 14
Write Operations ........................................................................ 22
Supply Sequencing through Configurable Output Drivers .. 14
Read Operations......................................................................... 24
Sequencing Engine ......................................................................... 15
Outline Dimensions ....................................................................... 26
Overview...................................................................................... 15
Ordering Guide .......................................................................... 26
REVISION HISTORY
11/04—Preliminary PrB: Preliminary Version
Rev. PrB | Page 2 of 28
Preliminary Technical Data
ADM1068
GENERAL DESCRIPTION
(continued from Page 1)
The device provides up to eight programmable inputs for
monitoring under, over, or out-of-window faults on up to eight
supplies. In addition, eight programmable outputs can be used
as logic enables. Six of them can also provide up to a 12 V
output for driving the gate of an N-channel FET, which can be
placed in the path of a supply.
The logical core of the device is a sequencing engine. This statemachine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can be
programmed using an intuitive GUI-based software package
provided by ADI.
10µF
REFOUT
REFGND
SDA SCL A1
A0
SMBus
INTERFACE
VREF
ADM1068
OSC
DEVICE
CONTROLLER
EEPROM
GPI SIGNAL
CONDITIONING
CONFIGURABLE
O/P DRIVER
(HV)
SFD
VX1
PDO1
PDO2
PDO3
PDO4
VX2
PDO5
GPI SIGNAL
CONDITIONING
VX3
SEQUENCING
ENGINE
PDO6
SFD
VX4
VP1
CONFIGURABLE
O/P DRIVER
(HV)
SELECTABLE
ATTENUATOR
SFD
CONFIGURABLE
O/P DRIVER
(LV)
PDO7
SELECTABLE
ATTENUATOR
SFD
CONFIGURABLE
O/P DRIVER
(LV)
PDO8
VP2
VP3
PDOGND
AGND
VDDCAP
10µF
REG 5.25V
CHARGE PUMP
VDD
ARBITRATOR
GND
VCCP
10µF
Figure 2. Detailed Block Diagram
Rev. PrB | Page 3 of 28
04734-002
VH
ADM1068
Preliminary Technical Data
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPn
VP
VH
VDDCAP
CVDDCAP
POWER SUPPLY
Supply Current, IVH, IVPn
Additional Currents
All PDO FET Drivers On
Min
Typ
Max
Unit
Test Conditions/Comments
4.75
6.0
14.4
5.4
V
V
V
V
µF
Minimum supply required on one of VPn, VH
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
4.2
6
mA
VDDCAP = 4.75 V, PDO1–8 off
mA
3.0
2.7
10
1
10
mA
VDDCAP = 4.75 V, PDO1–6 loaded with 1 µA each,
PDO7–8 off
Maximum additional load that can be drawn from
all PDO pull-ups to VDDCAP
1 ms duration only, VDDCAP = 3 V
±0.05
±0.05
%
%
Midrange
High range
Current Available from VDDCAP
2
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPn Pins
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VX Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
6
2.5
2.5
1.25
0.573
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
Load Regulation
PSRR
14.4
6
V
V
±0.1
%
Low range and midrange
6
3
1.375
V
V
V
No input attenuation error
1
MΩ
0.573
Threshold Resolution
Digital Glitch Filter
1.375
±1
8
0
100
2.043
mA
2.048
−0.25
0.25
1
2
60
2.053
V
%
No input attenuation error
VREF error + DAC nonlinearity + comparator offset
error
Bits
µs
µs
Minimum programmable filter length
Maximum programmable filter length
V
mV
mV
µF
mV
dB
No load
Sourcing current, IDACnMAX = −100 µA
Sinking current, IDACnMAX = 100 µA
Capacitor required for decoupling, stability
Per 100 µA
dc
Rev. PrB | Page 4 of 28
Preliminary Technical Data
Parameter
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode (PDO1–6)
Output Impedance
VOH
IOUTAVG
Standard (Digital Output) Mode (PDO1–8)
VOH
ADM1068
Min
Typ
Max
Unit
Test Conditions/Comments
11
10.5
500
12.5
12
20
14
13.5
kΩ
V
V
µA
IOH = 0
IOH = 1 µA
2 V < VOH < 7 V
2.4
2
V
V
V
V
mA
mA
kΩ
mA
10
110
µA
kHz
4.5
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPn)2
Three-State Output Leakage Current
Oscillator Frequency
DIGITAL INPUTS (VXn, A0, A1)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
Programmable Pull-Down Current,
IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL2
SERIAL BUS TIMING
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
1
2
VPU − 0.3
0
0.50
20
60
20
90
100
2.0
0.8
−1
1
5
20
2.0
0.8
0.4
400
4.7
4.7
4
4.7
4
1000
300
250
5
1
10
V
V
µA
µA
pF
µA
VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA
VPU to Vpn = 6.0 V, IOH = 0 mA
VPU ≤ 2.7 V, IOH = 0.5 mA
IOL = 20 mA
Maximum sink current per PDO pin
Maximum total sink for all PDOs
Internal pull-up
Current load on any VPn pull- ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
VPDO = 14.4 V
All on-chip time delays derived from this clock
Maximum VIN = 5.5 V
Maximum VIN = 5.5 V
VIN = 5.5 V
VIN = 0
VDDCAP = 4.75, TA = 25°C, if known logic state is
required
V
V
V
IOUT = −3.0 mA
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µA
VIN = 0
µs
At least one of the VH, VP1–3 pins must be ≥3.0 V to maintain the device supply on VDDCAP.
Specification is not production tested, but is supported by characterization data at initial product release.
Rev. PrB | Page 5 of 28
ADM1068
Preliminary Technical Data
A0
VCCP
PDOGND
GND
VDDCAP
SDA
SCL
A1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
25
32
24
1
PIN 1
INDICATOR
ADM1068
TOP VIEW
(Not to Scale)
8
17
16
NC
NC
NC
NC = NO CONNECT
AGND
REFGND
NC
REFOUT
NC
9
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
04734-003
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
Figure 3. LQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin No.
11, 13-16
1–4
Mnemonic
NC
VX1–4
5–7
VP1–3
8
VH
9
10
12
17-24
25
26
27
28
29
30
31
32
AGND
REFGND
REFOUT
PDO8–1
PDOGND
VCCP
A0
A1
SCL
SDA
VDDCAP
GND
Description
No connection.
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to these pins, the output of which connects to a supply fault detector. These
pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to this pin, the output of which connects to a supply fault detector. This pin
allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
Ground Return for Input Attenuators.
Ground Return for On-Chip Reference Circuits.
2.048 V Reference Output.
Programmable Output Drivers.
Ground Return for Output Drivers.
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin and GND.
Logic Input. This pin sets the seventh bit of the SMBus interface address.
Logic Input. This pin sets the sixth bit of the SMBus interface address.
SMBus Clock Pin. Open-drain output requires external resistive pull-up.
SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
Device Supply Voltage. Linearly regulated from the highest of the VP1–3, VH pins to a typical of 4.75 V.
Supply Ground.
Rev. PrB | Page 6 of 28
Preliminary Technical Data
ADM1068
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Voltage on VH Pin
Voltage on VP Pins
Voltage on VX Pins
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Lead Temperature, Soldering
Vapor Phase, 60 s
ESD Rating, All Pins
Rating
16 V
7V
−0.3 V to +6.5 V
±5 mA
±20 mA
150°C
−65°C to +150°C
215°C
2000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
32-lead LQFP package: θJA = 17°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 7 of 28
ADM1068
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
6
180
160
5
140
120
IVP1 (µA)
VVDDCAP (V)
4
3
2
100
80
60
40
0
0
1
2
3
4
5
04734-053
04734-050
1
20
0
6
0
1
2
3
VVP1 (V)
4
5
6
VVP1 (V)
Figure 4. VVDDCAP vs. VVP1
Figure 7. IVP1 vs. VVP1 (VP1 Not as Supply)
5.0
6
4.5
5
4.0
3.5
3.0
IVH (mA)
3
2
2.5
2.0
1.5
1.0
04734-051
1
0
0
2
4
6
8
10
12
14
04734-054
VVDDCAP (V)
4
0.5
0
0
16
2
4
6
8
10
12
14
16
VVH (V)
VVH (V)
Figure 8. IVH vs. VVH (VH as Supply)
Figure 5. VVDDCAP vs. VVH
350
5.0
4.5
300
4.0
250
IVH (µA)
3.0
2.5
2.0
1.5
200
150
100
1.0
0.5
0
0
1
2
3
4
5
50
04734-055
04734-052
IVP1 (mA)
3.5
0
0
6
1
2
3
4
VVH (V)
VVP1 (V)
Figure 9. IVH vs. VVH (VH Not as Supply)
Figure 6. IVP1 vs. VVP1 (VP1 as Supply)
Rev. PrB | Page 8 of 28
5
6
Preliminary Technical Data
ADM1068
4.5
14
4.0
12
VP1 = 5V
3.0
VPDO1 (V)
8
6
2.5
VP1 = 3V
2.0
1.5
4
1.0
0.5
04734-056
2
0
0
2.5
5.0
7.5
10.0
12.5
04734-058
VPDO1 CHARGE PUMPED
3.5
10
0
0
15.0
10
20
30
40
50
60
ILOAD (µA)
ILOAD CURRENT (µA)
Figure 12. VPDO1 (Weak Pull-Up to VP) vs. ILOAD
Figure 10. VPDO1 (FET Drive Mode) vs. ILOAD
2.058
5.0
4.5
4.0
2.053
REFOUT (V)
3.0
VP1 = 5V
2.5
VP1 = 3V
2.0
1.5
VP1 = 3.0V
2.048
VP1 = 4.75V
2.043
0.5
0
0
1
2
3
4
5
6
2.038
–40
04734-061
1.0
04734-057
VPDO1 (V)
3.5
–20
0
20
40
60
TEMPERATURE (°C)
ILOAD (mA)
Figure 13. REFOUT vs. Temperature
Figure 11. VPDO1 (Strong Pull-Up VP) vs. ILOAD
Rev. PrB | Page 9 of 28
80
100
ADM1068
Preliminary Technical Data
POWERING THE ADM1068
An external capacitor to GND is required to decouple the onchip supply from noise. This capacitor should be connected to
the VDDCAP pin, as shown in Figure 14. The capacitor has
another use during brownouts (momentary loss of power).
Under these conditions, when the input supply (VPn or VH)
dips transiently below VDD, the synchronous rectifier switch
immediately turns off so that it does not pull VDD down. The
VDD cap can then act as a reservoir to keep the device active
until the next highest supply takes over the powering of the
device. 10 µF is recommended for this reservoir/decoupling
function.
Note that when two or more supplies are within 100 mV of each
other, the supply that takes control of VDD first keeps control.
For example, if VP1 is connected to a 3.3 V supply, then VDD
powers up to approximately 3.1 V through VP1. If VP2 is then
connected to another 3.3 V supply, VP1 still powers the device,
unless VP2 goes 100 mV higher than VP1.
VDDCAP
VP1
IN
OUT
4.75V
LDO
EN
VP2
IN
OUT
4.75V
LDO
EN
VP3
IN
OUT
4.75V
LDO
EN
VH
Rev. PrB | Page 10 of 28
IN
OUT
4.75V
LDO
INTERNAL
DEVICE
SUPPLY
EN
SUPPLY
COMPARATOR
04734-022
The ADM1068 is powered from the highest voltage input on
either the positive-only supply inputs (VPn) or the high voltage
supply input (VH). This technique offers improved redundancy
as the device is not dependent on any particular voltage rail to
keep it operational. The same pins are used for supply fault
detection (discussed later in the next section). A VDD arbitrator
on the device chooses which supply to use. The arbitrator can
be considered an OR’ing of four LDOs together. A supply
comparator chooses which of the inputs is highest and selects
this one to provide the on-chip supply. There is minimal
switching loss with this architecture (~0.2 V), resulting in the
ability to power the ADM1068 from a supply as low as 3.0 V.
Note that the supply on the VXn pins cannot be used to power
the device.
Figure 14. VDD Arbitrator Operation
Preliminary Technical Data
ADM1068
INPUTS
SUPPLY SUPERVISION
The resolution is given by
The ADM1068 has eight programmable inputs. Four of these
are dedicated supply fault detectors (SFDs). These dedicated
inputs are called VH and VP1–3 by default. The other four
inputs are labeled VX1–VX4 and have dual functionality. They
can be used as either supply fault detectors, with similar
functionality to VH and VP1–3, or CMOS/TTL-compatible
logic inputs to the devices. Therefore, the ADM1068 can have
up to eight analog inputs, a minimum of four analog inputs and
four digital inputs, or a combination. If an input is used as an
analog input, it cannot be used as a digital input. Therefore, a
configuration requiring eight analog inputs has no digital inputs
available. Table 5 shows the details of each of the inputs.
RANGE
SELECT
ULTRA
LOW
+
VPn
VREF
OV
COMPARATOR
–
GLITCH
FILTER
FAULT
OUTPUT
LOW
–
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
(14.4 V − 4.8 V)/255 = 37.6 mV
Table 4 lists the upper and lower limit of each available range,
the bottom of each range (VB), and the range itself (VR).
Table 4. Voltage Range Limits
Voltage Range (V)
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
4.8 to 14.4
VB (V)
0.573
1.25
2.5
4.8
VR (V)
0.802
1.75
3.5
9.6
The threshold value required is given by
VT = (VR × N)/255 + VB
+
where:
UV
FAULT TYPE
COMPARATOR
SELECT
04734-023
MID
Step Size = Threshold Range/255
Figure 15. Supply Fault Detector Block
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1068 has up to eight supply fault detectors (SFDs) on
its eight input channels. These highly programmable reset
generators enable the supervision of up to eight supply voltages.
The supplies can be as low as 0.573 V and as high as 14.4 V. The
inputs can be configured to detect an undervoltage fault (the
input voltage droops below a preprogrammed value), an
overvoltage fault (the input voltage rises above a
preprogrammed value) or an out-of-window fault
(undervoltage or overvoltage). The thresholds can be
programmed to an 8-bit resolution in registers provided in the
ADM1068. This translates to a voltage resolution that is
dependent on the range selected.
VT is the desired threshold voltage (UV or OV).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is
given by
N = 255 × (VT − VB)/VR
For example, if the user wants to set a 5 V OV threshold on VP1,
the code to be programmed in the PS1OVTH register
(discussed in the AN-698 application note) is given by
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
Table 5. Input Functions, Thresholds, and Ranges
Input
VH
Function
High V Analog Input
VPn
Positive Analog Input
VXn
High Z Analog Input
Digital Input
Voltage Range (V)
2.5–6.0
4.8–14.4
0.573–1.375
1.25–3.00
2.5–6.0
0.573–1.375
0–5
Maximum Hysteresis
425 mV
1.16 V
97.5 mV
212 mV
425 mV
97.5 mV
N/A
Rev. PrB | Page 11 of 28
Voltage Resolution (mV)
13.7
37.6
3.14
6.8
13.7
3.14
N/A
Glitch Filter (µs)
0–100
0–100
0–100
0–100
0–100
0–100
0–100
ADM1068
Preliminary Technical Data
The UV and OV comparators shown in Figure 15 are always
looking at VPn. To avoid chattering (multiple transitions when
the input is very close to the set threshold level), these comparators have digitally programmable hysteresis. The hysteresis can
be programmed up to the values shown in Table 5.
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program how much above the
UV threshold the input must rise again before a UV fault is
deasserted. Similarly, the user can program how much below the
OV threshold an input must fall again before an OV fault is
deasserted.
The hysteresis figure is given by
INPUT PULSE SHORTER
THAN GLITCH FILTER TIMEOUT
INPUT PULSE LONGER
THAN GLITCH FILTER TIMEOUT
PROGRAMMED
TIMEOUT
PROGRAMMED
TIMEOUT
INPUT
INPUT
T0
TGF
T0
TGF
OUTPUT
OUTPUT
T0
VHYST = VR × NTHRESH/255
TGF
T0
TGF
04734-024
INPUT COMPARATOR HYSTERESIS
Figure 16. Input Glitch Filter Function
SUPPLY SUPERVISION WITH VXn INPUTS
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 5.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators.
This allows the user to remove any spurious transitions such as
supply bounce at turn-on. The glitch filter function is additional
to the digitally programmable hysteresis of the SFD comparators. The glitch filter timeout is programmable up to 100 µs.
For example, when the glitch filter timeout is 100 µs, any pulses
appearing on the input of the glitch filter block that are less than
100 µs in duration are prevented from appearing on the output
of the glitch filter block. Any input pulse that is longer than
100 µs does appear on the output of the glitch filter block. The
output is delayed with respect to the input by 100 µs. The
filtering process is shown in Figure 16.
The VXn inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected as
an analog (SFD) input, the VXn pins have very similar functionality to the VH and VPn pins. The major difference is that
the VXn pins have only one input range: 0.573 V to 1.375 V.
Therefore, these inputs can directly supervise only the very low
supplies. However, the input impedance of the VXn pins is high,
allowing an external resistor divide network to be connected to
the pin. Thus, any supply can be potentially divided down into
the input range of the VXn pin and supervised. This enables the
ADM1068 to monitor other supplies such as +24 V, +48 V, and
−5 V.
An additional supply supervision function is available when the
VXn pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedicated analog inputs, VP1–3 and VH. The analog function of
VX1 is mapped to VP1, VX2 is mapped to VP2, and so on. VX4
is mapped to VH. In this case, these SFDs can be viewed as a
secondary or warning SFD.
The secondary SFDs are fixed to the same input range as the
primary SFD. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be
generated on a single supply using only one pin. For example, if
VP1 is set to output a fault if a 3.3 V supply droops to 3.0 V,
VX1 can be set to output a warning at 3.1 V. Warning outputs
are available for readback from the status registers. They are also
OR’ed together and fed into the sequencing engine (SE),
allowing warnings to generate interrupts on the PDOs.
Therefore, in the example above, if the supply droops to 3.1 V, a
warning is generated, and remedial action can be taken before
the supply drops out of tolerance.
Rev. PrB | Page 12 of 28
Preliminary Technical Data
ADM1068
As mentioned previously, the VXn input pins on the ADM1068
have dual functionality. The second function is as a digital input
to the device. Therefore, the ADM1068 can be configured for up
to four digital inputs. These inputs are TTL/CMOS-compatible.
Standard logic signals can be applied to the pins: RESET from
reset generators, PWRGOOD signals, fault flags, manual resets,
and so on. These signals are available as inputs to the SE, and
can be used to control the status of the PDOs. The inputs can be
configured to detect either a change in level or an edge.
The digital blocks feature the same glitch filter function that is
available on the SFDs. This enables the user to ignore spurious
transitions on the inputs. For example, the filter can be used to
debounce a manual reset switch.
When configured as digital inputs, each of the VXn pins has a
weak (10 µA) pull-down current source available for placing the
input in a known condition, even if left floating. The current
source, if selected, weakly pulls the input to GND.
VXn
(DIGITAL INPUT)
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, once the logic transition is detected, a pulse of
programmable width is output from the digital block. The width
is programmable from 0 µs to 100 µs.
+
DETECTOR
GLITCH
FILTER
–
VREF = 1.4V
Figure 17. VXn Digital Input Function
Rev. PrB | Page 13 of 28
TO
SEQUENCING
ENGINE
04734-027
VXn PINS AS DIGITAL INPUTS
ADM1068
Preliminary Technical Data
OUTPUTS
from a backplane supply (a PDO can sustain greater than 10.5 V
into a 1 µA load). The pull-down switches can also be used to
drive status LEDs directly.
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
Supply sequencing is achieved with the ADM1068 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PnPDOCFG
configuration register (see the AN-698 application note for
details).
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing
engine (SE). The SE determines what action is to be taken with
the PDOs based on the condition of the inputs of the ADM1068.
Therefore, the PDOs can be set up to assert when the SFDs are
in tolerance, the correct input signals are received on the VXn
digital pins, no warnings are received from any of the inputs of
the device, and so on. The PDOs can be used for a variety of
functions. The primary function is to provide enable signals for
LDOs or dc/dc converters, which generate supplies locally on a
board. The PDOs can also be used to provide a POWER_GOOD
signal when all the SFDs are in tolerance, or a RESET output if
one of the SFDs goes out of specification (this can be used as a
status signal for a DSP, FPGA, or other microcontroller).
The data sources are
• Output from the SE.
• Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence.
• On-Chip Clock. A 100 kHz clock is generated on the device.
This clock can be made available on any of the PDOs. It can
be used, for example, to clock an external device such as
an LED.
By default, the PDOs are pulled to GND by a weak (20 kΩ) onchip pull-down resistor. This is also the condition of the PDOs
on power-up, until the configuration is downloaded from
EEPROM and the programmed setup is latched. The outputs
are actively pulled low once a supply of 1 V or greater is on VPn
or VH. The outputs remain high impedance prior to 1 V
appearing on VPn or VH. This provides a known condition for
the PDOs during power-up. The internal pull-down can be
overdriven with an external pull-up of suitable value tied from
the PDO pin to the required pull-up voltage. The 20 kΩ resistor
must be accounted for in calculating a suitable value. For
example, if PDOn must be pulled up to 3.3 V, and 5 V is available
as an external supply, the pull-up resistor value is given by
The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as follows:
• Open-drain (allowing the user to connect an external pull-up
resistor)
• Open-drain with weak pull-up to VDD
• Push/pull to VDD
• Open-drain with weak pull-up to VPn
• Push/pull to VPn
• Strong pull-down to GND
• Internally charge-pumped high drive (12 V, PDO1–6 only)
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
The last option (available only on PDO1–6) allows the user to
directly drive a voltage high enough to fully enhance an external
N-FET, which is used to isolate, for example, a card-side voltage
Therefore,
RUP = (100 kΩ − 66 kΩ)/3.3 = 10 kΩ
VFET (PDO1-6 ONLY)
VDD
VP4
10Ω
20kΩ
10Ω
10Ω
20kΩ
VP1
SEL
20kΩ
CFG4 CFG5 CFG6
SE DATA
PDO
SMBus DATA
Figure 18. Programmable Driver Output
Rev. PrB | Page 14 of 28
04734-028
20kΩ
CLK DATA
Preliminary Technical Data
ADM1068
SEQUENCING ENGINE
The ADM1068’s sequencing engine (SE) provides the user with
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex
control of boards such as power-up and power-down sequence
control, fault event handling, interrupt generation on warnings,
and so on. A watchdog function that verifies the continued
operation of a processor clock can be integrated into the SE
program. The SE can also be controlled via the SMBus, giving
software or firmware control of the board sequencing.
• Transition from one state to the next is made in less than
20 µs, which is the time needed to download a state definition
from EEPROM to the SE.
MONITOR
FAULT
STATE
TIMEOUT
SEQUENCE
04734-029
OVERVIEW
Figure 19. State Cell
The SE state machine comprises 63 state cells. Each state has the
following attributes:
• Monitors signals indicating the status of the eight input pins,
VP1 to VP3, VH, and VX1 to VX4.
• Can be entered from any other state.
• Three exit routes move the state machine on to a next state:
sequence detection, fault monitoring, and timeout.
• Delay timers for the sequence and timeout blocks can be
programmed independently, and change with each state
change. The range of timeouts is from 0 ms to 400 ms.
The ADM1068 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be
generated when the ADC readings violate their limit register
value or when the secondary voltage monitors on VP1–3 and
VH. The warnings are all OR’ed together and are available as a
single warning input to each of the three blocks that enable
exiting from a state.
SMBUS JUMP/UNCONDITIONAL JUMP
The SE can be forced to advance to the next state unconditionally. This enables the user to force the SE to advance. Examples
of where this might be used include moving to a margining
state or debugging a sequence. The SMBus jump or go-to
command can be seen as another input to sequence and
timeout blocks, which provide an exit from each state.
• Output condition of the 8 PDO pins is defined and fixed
within a state.
Table 6. Sample Sequence State Entries
State
IDLE1
IDLE2
EN3V3
Sequence
If VX1 is low , go to state IDLE2.
If VP1 is okay, go to state EN3V3.
If VP2 is okay, go to state EN2V5.
DIS3V3
EN2V5
If VX1 is high, go to state IDLE1.
If VP3 is okay, go to state PWRGD.
DIS2V5
FSEL1
FSEL2
PWRGD
If VX1 is high, go to state IDLE1.
If VP3 is not okay, go to state DIS2V5.
If VP2 is not okay, go to state DIS3V3.
If VX1 is high, go to state DIS2V5.
Timeout
Monitor
If VP2 is not okay after 10 ms, go to
state DIS3V3.
If VP1 is not okay, go to state IDLE1.
If VP3 is not okay after 20 ms, go to
state DIS2V5.
If VP1 or VP2 is not okay, go to state FSEL2.
If VP1 or VP2 is not okay, go to state FSEL2.
If VP1 is not okay, go to state IDLE1.
If VP1, VP2, or VP3 is not okay, go to state
FSEL1.
Rev. PrB | Page 15 of 28
ADM1068
Preliminary Technical Data
SEQUENCE
STATES
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 20 shows how the simple building block of a
single SE state can be used to build a power-up sequence for a
3-supply system.
IDLE1
VX1 = 0
Table 7 lists the PDO outputs for each state in the same SE
implementation. In this system, the presence of a good 5 V supply
on VP1 and the VX1 pin held low are the triggers required for a
power-up sequence to start. The sequence intends to turn on
the 3.3 V supply next, then the 2.5 V supply (assuming successful
turn-on of the 3.3 V supply). Once all three supplies are good,
the PWRGD state is entered, where the SE remains until a fault
occurs on one of the three supplies, or it is instructed to go
through a power-down sequence by VX1 going high.
IDLE2
VP1 = 1
MONITOR FAULT
STATES
TIMEOUT
STATES
EN3V3
10ms
VP1 = 0
VP2 = 1
EN2V5
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following sections, which describe the
individual blocks, use this sample application to demonstrate
the state machine’s actions.
DIS3V3
20ms
(VP1 + VP2) = 0
VX1 = 1
VP3 = 1
PWRGD
DIS2V5
VP2 = 0
(VP1 + VP2 + VP3) = 0
VX1 = 1
FSEL1
VX1 = 1
(VP1 +
VP2) = 0
VP3 = 0
FSEL2
VP1 = 0
04734-030
VP2 = 0
Figure 20. Sample Application Flow Diagram
Table 7. PDO Outputs for Each State
PDO Outputs
PDO1 = 3V3ON
PDO2 = 2V5ON
PDO3 = FAULT
IDLE1
0
0
0
IDLE2
0
0
0
EN3V3
1
0
0
EN2V5
1
1
0
DIS3V3
0
1
1
Rev. PrB | Page 16 of 28
DIS2V5
1
0
1
PWRGD
1
1
0
FSEL1
1
1
1
FSEL2
1
1
1
Preliminary Technical Data
ADM1068
MONITORING FAULT
DETECTOR
SEQUENCE DETECTOR
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the inputs to
the SE to change state, and is most often used as the gate on
successful progress through a power-up or power-down
sequence. A timer block is included in this detector, which can
insert delays into a power-up or power-down sequence, if
required. Timer delays can be set from 10 µs to 400 ms.
Figure 21 is a block diagram of the sequence detector.
1-BIT FAULT
DETECTOR
VP1
MASK
SENSE
1-BIT FAULT
DETECTOR
VX4
VP1
VX4
SUPPLY FAULT
DETECTION
FAULT
SUPPLY FAULT
DETECTION
FAULT
LOGIC INPUT CHANGE
OR FAULT DETECTION
MASK
SENSE
SEQUENCE
DETECTOR
1-BIT FAULT
DETECTOR
LOGIC INPUT CHANGE
OR FAULT DETECTION
TIMER
FAULT
WARNINGS
INVERT
MASK
SELECT
04734-032
FORCE FLOW
(UNCONDITIONAL JUMP)
Figure 21. Sequence Detector Block Diagram
The sequence detector can also help to identify monitoring
faults. In the sample application shown in Figure 20, the FSEL1
and FSEL2 states first identify which of the VP1,VP2, or VP3
pins has faulted, and then they take the appropriate action.
MONITORING FAULT DETECTOR
The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate, which can detect when an input deviates from its
expected condition. The clearest demonstration of the use of
this block is in the PWRGD state, where the monitor block
indicates that a failure on one or more of the VP1,VP2, or VP3
inputs has occurred.
No programmable delay is available in this block, because the
triggering of a fault condition is likely to be caused when a
supply falls out of tolerance. In this situation, the user would
want to react as quickly as possible. Some latency occurs when
moving out of this state, however, because it takes a finite
amount of time (~20 µs) for the state configuration to
download from EEPROM into the SE. Figure 22 is a block
diagram of the monitoring fault detector.
04734-033
WARNINGS
Figure 22. Monitoring Fault Detector Block Diagram
TIMEOUT DETECTOR
The timeout detector allows the user to trap a failure to make
proper progress through a power-up or power-down sequence.
In the sample application shown in Figure 20, the timeout nextstate transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted upon entry to this
state (on the PDO1 output pin) to turn on a 3.3 V supply. This
supply rail is connected to the VP2 pin, and the sequence detector looks for the VP2 pin to go above its UV threshold, which is
set in the supply fault detector (SFD) attached to that pin.
The power-up sequence progresses when this change is
detected. If, however, the supply fails (perhaps due to a short
circuit overloading this supply), then the timeout block traps
the problem. In this example, if the 3.3 V supply fails within
10 ms, then the SE moves to the DIS3V3 state and turns off this
supply by bringing PDO1 low. It also indicates that a fault has
occurred by taking PDO3 high. Timeout delays of from 100 µs
to 400 ms can be programmed.
FAULT REPORTING
The ADM1068 has a fault latch for recording faults. Two
registers are set aside for this purpose. A single bit is assigned to
each input of the device, and a fault on that input sets the
relevant bit. The contents of the fault register can be read out
over the SMBus to determine which input(s) faulted. The fault
register can be enabled/disabled in each state. This ensures that
only real faults are captured and not, for example, undervoltage
trips when the SE is executing a power-down sequence.
Rev. PrB | Page 17 of 28
ADM1068
Preliminary Technical Data
APPLICATIONS DIAGRAM
12V IN
12V OUT
5V IN
5V OUT
3V IN
3V OUT
IN
DC-DC1
EN
VH
5V OUT
3V OUT
3.3V OUT
1.25V OUT
1.2V OUT
0.9V OUT
OUT
3.3V OUT
ADM1068
PDO1
PDO2
VP1
VP2
VP3
IN
DC-DC2
PDO3
PDO4
PDO5
VX1
VX2
VX3
EN
OUT
1.25V OUT
POWER_GOOD
PDO6
SIGNAL_VALID
RESET_L
PDO7
IN
DC-DC3
VX4
PDO8
EN
OUT
1.25V OUT
3.3V OUT
VCCP VDDCAP GND
IN
10µF
10µF
EN
Figure 23. Applications Diagram
Rev. PrB | Page 18 of 28
OUT
0.9V OUT
04734-068
LDO
Preliminary Technical Data
ADM1068
COMMUNICATING WITH THE ADM1068
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1068 (UV/OV thresholds, glitch
filter timeouts, PDO configurations, and so on) is dictated by
the contents of RAM. The RAM is comprised of digital latches
that are local to each of the functions on the device. The latches
are double-buffered and have two identical latches, Latch A and
Latch B. Therefore, when an update to a function occurs, the
contents of Latch A are updated first, and then the contents of
Latch B are updated with identical data. The advantages of this
architecture are explained in detail in this section.
The latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the
EEPROM (nonvolatile memory) to the local latches. This
download occurs in steps, as follows:
1.
With no power applied to the device, the PDOs are all high
impedance.
2.
When 1 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPn), the PDOs are all weakly
pulled to GND with a 20 kΩ impedance.
3.
When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
4.
The EEPROM downloads its contents to all Latch As.
5.
Once the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
6.
At 0.5 ms after the configuration download completes, the
first state definition is downloaded from EEPROM into
the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1068 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
EEPROM into the RAM registers, the user might need to alter
the configuration of functions on the ADM1068, such as changing the UV or OV limit of an SFD, changing the fault output of
an SFD, or adjusting the rise time delay of one of the PDOs.
The ADM1068 provides several options that allow the user to
update the configuration over the SMBus interface. The
following options are controlled in the UPDCFG register:
1.
Update the configuration in real time. The user writes to
RAM across the SMBus and the configuration is updated
immediately.
2.
Update the Latch As without updating the Latch Bs. With
this method, the configuration of the ADM1068 remains
unchanged and continues to operate in the original setup
until the instruction is given to update the Latch Bs.
3.
Change EEPROM register contents without changing the
RAM contents, and then download the revised EEPROM
contents to the RAM registers. Again, with this method, the
configuration of the ADM1068 remains unchanged and
continues to operate in the original setup until the
instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents, if
revisions to the configuration are unsatisfactory. For example, if
the user needs to alter an OV threshold, this can be done by
updating the RAM register as described in Option 1. However,
if the user is not satisfied with the change and wants to revert to
the original programmed value, then the device controller can
issue a command to download the EEPROM contents to the
RAM again, as described in Option 3, restoring the ADM1068
to its original configuration.
The topology of the ADM1068 makes this type of operation
possible. The local, volatile registers (RAM) are all doublebuffered latches. Setting Bit 0 of the UPDCFG register to 1
leaves the double-buffered latches open at all times. If Bit 0 is set
to 0, then, when a RAM write occurs across the SMBus, only the
first side of the double-buffered latch is written to. The user
must then write a 1 to Bit 1 of the UPDCFG register. This
generates a pulse to update all the second latches at once.
EEPROM writes occur in a similar way.
The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If low, then the contents of a page
cannot be erased, even if the command code for page erasure is
programmed across the SMBus. The bitmap for the UPDCFG
register is shown in the AN-698 application note. A flow chart
for download at power-up and subsequent configuration
updates is shown in Figure 24.
Rev. PrB | Page 19 of 28
ADM1068
Preliminary Technical Data
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
D
A
T
A
R
A
M
L
D
U
P
D
LATCH A
LATCH B
EEPROM
FUNCTION
(OV THRESHOLD
ON VP1)
04734-035
POWER-UP
(VCC > 2.5V)
Figure 24. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same
way as regular configuration latches. The SE has its own
dedicated 512-byte EEPROM for storing state definitions,
providing 63 individual states with a 64-bit word each (one state
is reserved). At power-up, the first state is loaded from the SE
EEPROM into the engine itself. When the conditions of this
state are met, the next state is loaded from EEPROM into the
engine, and so on. The loading of each new state takes approximately 10 µs.
To alter a state, the required changes must be made directly to
EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to EEPROM.
INTERNAL REGISTERS
The ADM1068 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADM1068, the first byte
of data is always a register address, which is written to the
address pointer register.
The major differences between the EEPROM and other
registers are
•
An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased.
•
Writing to EEPROM is slower than writing to RAM.
•
Writing to the EEPROM should be restricted, because it
has a limited write/cycle life of typically 10,000 write
operations due to the usual EEPROM wear-out
mechanisms.
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Pages 0 to 6, starting at Address 0xF800, hold the
configuration data for the applications on the ADM1068 (the
SFDs, PDOs, and so on). These EEPROM addresses are the
same as the RAM register addresses, prefixed by F8. Page 7 is
reserved. Pages 8 to 15 are for customer use.
Data can be downloaded from EEPROM to RAM in one of the
following ways:
•
At power-up, when Pages 0 to 6 are downloaded.
•
By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Pages 0 to 6.
Configuration Registers
SERIAL BUS INTERFACE
These registers provide control and configuration for various
operating parameters of the ADM1068.
The ADM1068 is controlled via the serial system management
bus (SMBus). The ADM1068 is connected to this bus as a slave
device, under the control of a master device. It takes approximately 1 ms after power-up for the ADM1068 to download
from its EEPROM. Therefore, access to the ADM1068 is restricted until the download is completed.
EEPROM
The ADM1068 has two 512-byte cells of nonvolatile, electrically
erasable, programmable read-only memory (EEPROM), from
Register Addresses 0xF800 to 0xFBFF. The EEPROM is used for
permanent storage of data that is not lost when the ADM1068 is
powered down. One EEPROM cell contains the configuration
data of the device; the other contains the state definitions for
the SE. Although referred to as read-only memory, the
EEPROM can be written to as well as read from via the serial
bus in exactly the same way as the other registers.
Identifying the ADM1068 on the SMBus
The ADM1060 has a 7-bit serial bus slave address. The device is
powered up with a default serial bus address. The five MSBs of
the address are set to 01101; the two LSBs are determined by the
logical states of Pins A1 and A0. This allows the connection of
four ADM1068s to one SMBus.
Rev. PrB | Page 20 of 28
Preliminary Technical Data
ADM1068
The device also has several identification registers (read-only),
which can be read across the SMBus. Table 8 lists these registers
with their values and functions.
All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the
R/W bit is a 0, the master writes to the slave device. If the
R/W bit is a 1, the master reads from the slave device.
Table 8. Identification Register Values and Functions
Name
MANID
Address
0xF4
Value
0x41
REVID
MARK1
MARK2
0xF5
0xF6
0xF7
0x00
0x00
0x00
Function
Manufacturer ID for Analog
Devices
Silicon revision
S/w brand
S/w brand
2.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-tohigh transition when the clock is high might be interpreted
as a stop signal. If the operation is a write operation, the
first data byte after the slave address is a command byte.
This tells the slave device what to expect next. It might be
an instruction telling the slave device to expect a block
write, or it might simply be a register address that tells the
slave where subsequent data is to be written. Because data
can flow in only one direction, as defined by the R/W bit,
sending a command to a slave device during a read
operation is not possible. Before a read operation, it might
be necessary to perform a write operation to tell the slave
what sort of read operation to expect and/or the address
from which data is to be read.
3.
When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the
data line high during the 10th clock pulse to assert a stop
condition. In read mode, the master device releases the
SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is
known as no acknowledge. The master then takes the data
line low during the low period before the tenth clock pulse,
then high during the tenth clock pulse to assert a stop
condition.
General SMBus Timing
Figure 25, Figure 26, and Figure 27 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
The general SMBus protocol operates as follows:
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data-line SDA, while the serial clock-line SCL remains
high. This indicates that a data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next 8 bits, consisting of a 7-bit
slave address (MSB first) plus a R/W bit. This bit determines the direction of the data transfer, that is, whether
data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse.
1
9
1
9
SCL
1
SDA
0
0
0
1
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
D0
ACK. BY
SLAVE
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
FRAME 3
DATA BYTE
D1
D0
D7
D6
ACK. BY
SLAVE
D5
D4
D2
FRAME N
DATA BYTE
Figure 25. General SMBus Write Timing Diagram
Rev. PrB | Page 21 of 28
D3
D1
D0
ACK. BY
SLAVE
STOP
BY
MASTER
04734-036
1.
ADM1068
Preliminary Technical Data
1
9
1
9
SCL
1
SDA
0
0
0
1
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
1
D0
ACK. BY
MASTER
FRAME 1
SLAVE ADDRESS
9
FRAME 2
DATA BYTE
1
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
FRAME 3
DATA BYTE
D1
D0
D7
D6
D5
D4
ACK. BY
MASTER
D3
D2
D1
D0
NO ACK.
FRAME N
DATA BYTE
STOP
BY
MASTER
04734-037
SDA
(CONTINUED)
Figure 26. General SMBus Read Timing Diagram
tR
tF
t HD; STA
t LO W
SCL
t HI G H
t HD; STA
t HD; DAT
t SU; STA
t SU; STO
t SU; DAT
t BUF
P
S
S
P
04734-038
SDA
Figure 27. Serial Bus Timing Diagram
SMBus Protocols for RAM and EEPROM
Data can be written to and read from both RAM and EEPROM
as single data bytes. Data can be written only to unprogrammed
EEPROM locations. To write new data to a programmed location, it must first be erased. EEPROM erasure cannot be done at
the byte level. The EEPROM is arranged as 32 pages of 32 bytes
each, and an entire page must be erased.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
The ADM1068 uses the following SMBus write protocols.
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
5.
The slave asserts ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in the diagrams:
S
P
R
W
A
Start
Stop
Read
Write
Acknowledge
A
No acknowledge
In the ADM1068, the send byte protocol is used for two
purposes:
•
To write a register address to RAM for a subsequent single
byte read from the same address, or a block read or write
starting at that address, as shown in Figure 28.
1
S
2
SLAVE
ADDRESS
W
3
4
5
6
A
REGISTER
ADDRESS
(0x00 TO 0xDF)
A
P
04734-039
The ADM1068 contains volatile registers (RAM) and nonvolatile registers (EEPROM). User RAM occupies address locations
from 0x00 to 0xDF; EEPROM occupies addresses from 0xF800
to 0xFBFF.
Figure 28. Setting a RAM Address for Subsequent Read
Rev. PrB | Page 22 of 28
Preliminary Technical Data
S
2
SLAVE
ADDRESS
W
3
4
5
6
A
COMMAND
BYTE
(0xFE)
A
P
To write a single byte of data to RAM. In this case, the
command byte is the RAM address from 0x00 to 0xDF and
the only data byte is the actual data, as shown in Figure 30.
1
•
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
6
7 8
2
3
4
5
6
7 8
Figure 31. Setting an EEPROM Address
Note, for page erasure, that because a page consists of
32 bytes, only the three MSBs of the address low byte are
important. The lower five bits of the EEPROM address low
byte specify the addresses within a page and are ignored
during an erase operation.
Write Byte/Word
2.
5
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S
W A
A
A P
ADDRESS
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
As soon as the ADM1068 receives the command byte, page
erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1068 is
accessed before erasure is complete, it responds with a no
acknowledge (NACK).
The master device asserts a start condition on SDA.
4
RAM
ADDRESS
A DATA A P
(0x00 TO 0xDF)
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of the EEPROM address
from 0xF8 to 0xFB. The only data byte is the low byte of
the EEPROM address, as shown in Figure 31.
1
1.
3
Figure 30. Single Byte Write to RAM
Figure 29. EEPROM Page Erasure
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device, as
follows:
2
SLAVE
S ADDRESS W A
04734-042
1
•
04734-040
The master sends a command code that tells the slave
device to erase the page. The ADM1068 command code for
a page erasure is 0xFE (1111 1110). Note that, for a page
erasure to take place, the page address has to be given in
the previous write word transaction (see the Write
Byte/Word section). Also, Bit 2 in the UPDCFG register
(Address 0x90) must be set to 1.
In the ADM1068, the write byte/word protocol is used for three
purposes:
•
To write a single byte of data to EEPROM. In this case, the
command byte is the high byte of the EEPROM address
from 0xF8 to 0xFB. The first data byte is the low byte of the
EEPROM address, and the second data byte is the actual
data, as shown in Figure 32.
1
2
3
4
5
6
7
8
9 10
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S
W A
A
A DATA A P
ADDRESS
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
04734-043
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before
writing to one or more EEPROM memory locations that
are already programmed, the page or pages containing
those locations must first be erased. EEPROM memory is
erased by writing a command byte.
04734-041
•
ADM1068
Figure 32. Single Byte Write to EEPROM
Block Write
5.
The slave asserts ACK on SDA.
6.
The master sends a data byte.
7.
The slave asserts ACK on SDA.
8.
The master sends a data byte (or asserts a stop condition at
this point).
9.
The slave asserts ACK on SDA.
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1068, a send byte operation sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by
the write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code that tells the slave
device to expect a block write. The ADM1068 command
code for a block write is 0xFC (1111 1100).
10. The master asserts a stop condition on SDA to end the
transaction.
Rev. PrB | Page 23 of 28
ADM1068
Preliminary Technical Data
The slave asserts ACK on SDA.
6.
The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
7.
The slave asserts ACK on SDA.
8.
The master sends N data bytes.
9.
The slave asserts ACK on SDA after each data byte.
In the ADM1068, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 34.
1
2
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
04734-045
5.
Figure 34. Single Byte Read from EEPROM or RAM
Block Read
10. The master asserts a stop condition on SDA to end the
transaction.
2
3
4
5
6
7
8
9
10
S SLAVE
W A COMMAND 0xFC A BYTE A DATA A DATA A DATA A P
2
N
1
ADDRESS
(BLOCK WRITE)
COUNT
04734-044
1
Figure 33. Block Write to EEPROM or RAM
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except
•
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF), to avoid writing to
invalid addresses.
•
If the addresses cross a page boundary, both pages must be
erased before programming.
Note that the ADM1068 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 µs, which would limit the SMBus clock for
repeated or block write operations. The ADM1068 pulls SCL
low and extends the clock pulse when it cannot accept any
more data.
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1068, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as
follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code that tells the slave
device to expect a block read. The ADM1068 command
code for a block read is 0xFD (1111 1101).
5.
The slave asserts ACK on SDA.
6.
The master asserts a repeat start condition on SDA.
7.
The master sends the 7-bit slave address followed by the
read bit (high).
8.
The slave asserts ACK on SDA.
9.
The ADM1068 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1068
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus 1.1 specification.
READ OPERATIONS
The ADM1068 uses the following SMBus read protocols.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives a data byte.
5.
The master asserts no acknowledge on SDA.
6.
The master asserts a stop condition on SDA, and the
transaction ends.
10. The master asserts ACK on SDA.
11. The master receives 32 data bytes.
12. The master asserts ACK on SDA after each data byte.
13. The master asserts a stop condition on SDA to end the
transaction.
Rev. PrB | Page 24 of 28
Preliminary Technical Data
2
3
4
5 6
7
8
9
10
11
12
2.
DATA
BYTE
SLAVE
SLAVE
COMMAND 0xFD
A
S ADDRESS W A (BLOCK READ) A S ADDRESS R A COUNT A
1
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
P
04734-046
13 14
DATA A
32
Figure 35. Block Read from EEPROM or RAM
C(x) = x8 + x2 + x1 + 1
See the SMBus 1.1 specification for details.
Error Correction
The ADM1068 provides the option of issuing a PEC (packet
error correction) byte after a write to RAM, a write to EEPROM,
a block write to RAM/EEPROM, or a block read from RAM/
EEPROM. This enables the user to verify that the data received
by or sent from the ADM1068 is correct. The PEC byte is an
optional byte sent after that last data byte has been written to or
read from the ADM1068. The protocol is as follows:
1.
A no acknowledge (NACK) is generated after the PEC byte
to signal the end of the read.
An example of a block read with the optional PEC byte is
shown in Figure 36.
1
2
3
4
5 6
7
8
9
10
11
12
DATA
BYTE
SLAVE
SLAVE
COMMAND 0xFD
A
S ADDRESS W A (BLOCK READ) A S ADDRESS R A COUNT A
1
The ADM1068 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the
PEC byte is incorrect.
Rev. PrB | Page 25 of 28
13 14 15
DATA
32
A PEC A P
Figure 36. Block Read from EEPROM or RAM with PEC
04734-047
1
ADM1068
ADM1068
Preliminary Technical Data
OUTLINE DIMENSIONS
0.75
0.60
0.45
1.60
MAX
9.00 BSC SQ
32
25
1
24
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.10 MAX
COPLANARITY
VIEW A
8
17
9
0.80
BSC
LEAD PITCH
VIEW A
16
0.45
0.37
0.30
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBA
Figure 37. 32-Lead Low Profile Quad Flat Package [LQFP]
(ST-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1068ACP
ADM1068ACP-REEL
ADM1068ACP-REEL7
EVAL-ADM1068LQEB
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Description
32-Lead LQFP
32-Lead LQFP
32-Lead LQFP
ADM1068 Evaluation Kit
Rev. PrB | Page 26 of 28
Package Option
ST-32-2
ST-32-2
ST-32-2
Preliminary Technical Data
ADM1068
NOTES
Rev. PrB | Page 27 of 28
ADM1068
Preliminary Technical Data
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04734–0–11/04(PrB)
Rev. PrB | Page 28 of 28
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