Integrated Circuit Systems, Inc. ICS9148-12 Pentium/ProTM System Clock Chip General Description Features The ICS9148-12 is a Clock Synthesizer chip for Pentium and PentiumPro CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four strong CPU, seven PCI and eight SDRAM clocks. Two reference outputs are available equal to the crystal frequency. Stronger drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. This device meets rise and fall requirements with 2 loads per CPU output (ie, one clock to CPU and NB chipset, one clock to two L2 cache inputs). PWR_DWN# pin allows low power mode by stopping crystal OSC and PLL stages. For optional power management, CPU_STOP# can stop CPU (0:3) clocks and PCI_STOP# will stop PCICLK (0:5) clocks. CPU and IOAPIC output buffer strength controlled by CPU 3.3_2.5# pin to match VDDL voltage. PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. CPU outputs are stronger drive for multiple loads per pin (ie CPU and NB on one pin) Generates system clocks for CPU, IOAPIC, SDRAM, PCI, plus 14.314 MHz REF(0:1), USB, Plus Super I/O Supports single or dual processor systems I2C serial configuration interface provides output clock disabling and other functions MODE input pin selects optional power management input control pins Two fixed outputs separately selectable as 24 or 48MHz Separate 2.5V and 3.3V supply pins 2.5V or 3.3V outputs: CPU, IOAPIC 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz CPU 3.3_2.5# logic pin to adjust output strength No power supply sequence requirements Uses external 14.318MHz crystal 48 pin 300 mil SSOP and 240 mil TSSOP Output enable register for serial port control: 1 = enable 0 = disable The ICS9148-12 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply. Pin Configuration Block Diagram 48-Pin SSOP & TSSOP Functionality VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70°C Crystal (X1, X2) = 14.31818 MHz 0 CPUCLK, SDRAM (MHz) 60 PCICLK (MHz) 30 1 66.6 33.3 SEL Pentium is a trademark on Intel Corporation. 9148-12 Rev F 4/1/99 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9148-12 Pin Descriptions PIN NUMBER PIN NAME TYPE 2, 1 3, 10, 17, 24, 31, 37, 43 4 REF (0:1) OUT Reference clock Output GND PW R Ground (common) X1 IN 5 X2 OU T 6 MODE IN 7, 15 VDD2 PWR Supply for PCICLK_F, PCICLK (0:5), nominal 3.3V 8 PCICLK_F OUT Free running PCI clock, not affected by PCI_STOP# 9, 11, 12, 13, 14, 16 PCICLK (0:5) OUT 18 SEL66/60# IN Selects 60MHz or 66.6MHz for SDRAM and CPU 19 SDATA IN I2C data input 20 SCLK IN I2C clock input 21 VDD4 PWR Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V 22 48/24MHzA OUT 48/24MHz driver output for USB or Super I/O 23 48/24MHzB OUT 48/24MHz driver output for USB or Super I/O 25 VD D PWR Supply for PLL core, nominal 3.3V SDRAM7 OUT SDRAM clock 60/66.6MHz (selected) PCI_STOP# IN SDRAM6 OUT CPU_STOP# IN 28, 34 VDD3 PWR 40 VDDL2 PWR Halts CPU clocks at logic "0" level when low Supply for SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, nominal 3.3V Supply for CPUCLK (0:3), either 2.5 or 3.3V nominal 42, 41, 39, 38 CPUCLK (0:3) OUT CPUCLK clock output, powered by VDDL2 36, 35, 33, 32, 30, 29 SDRAM (0:5) OUT SDRAMs clock at 60 or 66.6MHz (selected) 44 PWR_DWN# IN 45 IOAPIC OUT IOAPIC clock output, (14.318MHz) powered by VDDL1 46 VDDL1 PWR 47 CPU3.3-2.5# IN 48 VDD1 PWR Supply for IOAPIC, either 2.5 or 3.3V nominal 3.3 or 2.5 VDD buffer strength selection, has pullup to VDD, nominal 30K resistor. Supply for REF (0:1), X1, X2, nominal 3.3V 26 27 DESCRIPTION Crystal or reference input, has internal crystal load cap Crystal output, has internal load cap and feedback resistor to X1 Input function selection PCI clocks Halts PCI Bus (0:5) at logic "0" level when low SDRAM clock 60/66.6MHz (selected) Powers down chip, active low Power Groups VDD = Supply for PLL core VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP# VDD4 = 48/24MHzA, 48/24MHzB VDDL1 = IOAPIC VDDL2 = CPUCLK (0:3) 2 ICS9148-12 Power-On Conditions SEL 66/60# MODE 1 1 0 1 1 PIN # 38, 39, 41, 42 36, 35, 33, 32, 30, 29, 27, 26 16, 14, 13, 12, 11, 9, 8 38, 39, 41, 42 36, 35, 33, 32, 30, 29, 27, 26 16, 14, 13, 12, 11, 9, 8 DESCRIPTION CPUCLKs 26 PCI_STOP# 27 CPU_STOP# 8 PCICLK_F 38, 39, 41, 42 CPUCLKs 0 SDRAM 66.6 MHz - All SDRAM outputs PCICLKs 33.3 MHz - w/serial config enable/disable CPUCLKs 60 MHz - w/serial config enable/disable SDRAM 60 MHz - w/serial config enable/disable PCICLKs 30 MHz - w/serial config enable/disable 0 36, 35, 33, 32, 30, 29 16, 14, 13, 12, 11, 9 SDRAM PCICLKs 26 PCI_STOP# 27 CPU_STOP# 8 PCICLK_F 38, 39, 41, 42 CPUCLKs 0 36, 35, 33, 32, 30, 29 16, 14, 13, 12, 11, 9 FUNCTION 66.6 MHz - w/serial config enable/disable SDRAM PCICLKs Power Management, PCI (0:5) Clocks Stopped when low Power Management, CPU (0:5) Clocks Stopped when low 33.3 MHz - 33.3 MHz - PCI Clock Free running for Power Management 66.6 MHz - CPU Clocks w/external Stop Control and serial config individual enable/disable. 66.6 MHz - SDRAM Clocks w/serial config individual enable/disable. 33.3 MHz - PCI Clocks w/external Stop control and serial config individual enable/disable. Power Management, PCI (0:5) Clocks Stopped when low Power Management, CPU (0:5) Clocks Stopped when low 30 MHz - PCI Clock Free running for Power Management 60 MHz - CPU Clocks w/external Stop control and serial config individual enable/disable. 60 MHz - SDRAM Clocks w/serial config individual enable/disable. 30 MHz - PCI Clocks w/external Stop control and serial config individual enable/disable. Example: a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively. b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively. Power-On Default Conditions At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then produced are on the MODE pin as shown in the table below. CLOCK REF (0:1) I OA P I C 0 48/24 MHz D E FAU LT C O N D I T I O N AT P OW E R - U P 14.31818 MHz 14.31818 MHz 48 MHz 3 ICS9148-12 Technical Pin Function Descriptions VDD(1,2,3,4) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:1), PCICLK, 48/24MHzA/B and SDRAM(0:7). SDRAM(0:7) These Output Clocks are use to drive Dynamic RAMs and are low skew copies of the CPU Clocks. The voltage swing of the SDRAMs output is controlled by the supply voltage that is applied to VDD3 of the device, operates at 3.3 volts. This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. 48/24MHzA, B This is a fixed frequency Clock output that is typically used to drive Super I/O devices. Outputs A and B are defined as 24 or 48MHz by I2C register (see table). VDDL1,2 This is the power supplies for the CPUCLK and IOAPCI output buffers. The voltage level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. IOAPIC This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or 3.3volts. REF(0:1) The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. See the data tables for the value of this capacitor. PCICLK_F This Output is equal to PCICLK(0:5) and is FREE RUNNING, and will not be stopped by PCI_STP#. PCICLK (0:5) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/2 CPU frequency. SELECT 66.6/60MHz# This Input pin controls the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. If a logic 1 value is present on this pin, the 66.6 MHz Clock will be selected. If a logic 0 is used, the 60MHz frequency will be selected. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor that is connected to ground. See the Data Sheet for the value of this capacitor. MODE This Input pin is used to select the Input function of the I/ O pins. An active Low will place the I/O pins in the Input mode and enable those stop clock functions. CPUCLK (0:3) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks are controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. 4 ICS9148-12 Technical Pin Function Descriptions CPU3.3_2.5# This Input pin controls the CPU and IOAPIC output buffer strength for skew matching CPU and SDRAM outputs to compensate for the external VDDL supply condition. It is important to use this function when selecting power supply requirements for VDDL1,2. A logic 0 (ground) will indicate 2.5V operation and a logic 1 will indicate 3.3V operation. This pin has an internal pullup resistor to VDD. PWR_DWN# This is an asynchronous active Low Input pin used to Power Down the device into a Low Power state by not removing the power supply. The internal Clocks are disabled and the VCO and Crystal are stopped. Powered Down will also place all the Outputs in a low state at the end of their current cycle. The latency of Power Down will not be greater than 3ms. The I2C inputs will be Tri-Stated and the device will retain all programming information. This input pin only valid when MODE=0 (Power Management Mode) CPU_STOP# This is a synchronous active Low Input pin used to stop the CPUCLK clocks in an active low state. All other Clocks including SDRAM clocks will continue to run while this function is enabled. The CPUCLKs will have a turn ON latency of at least 3 CPU clocks. This input pin only valid when MODE=0 (Power Management Mode) PCI_STOP# This is a synchronous active Low Input pin used to stop the PCICLK clocks in an active low state. It will not effect PCICLK_F nor any other outputs. This input pin only valid when MODE=0 (Power Management Mode) I2C The SDATA and SCLOCK Inputs are use to program the device. The clock generator is a slave-receiver device in the I2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I 2 C specification in Philips I2C Peripherals Data Handbook (1996) should be followed. 5 ICS9148-12 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 6 ICS9148-12 Select Functions Functionality CPU PCI, PCI_F SDRAM REF IOAPIC 24 MHz Selection 48 MHz Selection Tristate HI - Z HI - Z HI - Z HI - Z HI - Z HI - Z HI - Z Testmode TCLK/21 TCLK/41 TCLK/21 TCLK1 TCLK1 TCLK/41 TCLK/21 Notes: 1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode. Serial Configuration Command Bitmaps Byte 0: Functional and Frequency Select Clock Register (default on Bits 7, 6, 5, 4, 1, 0 = 0) (default on Bits 3, 2 = 1) Note: PWD = Power-Up Default BIT Bit 7 Bit 6 PIN# - Bit 5 - Bit 4 Bit 3 Bit 2 23 22 Bit 1 Bit 0 - DESCRIPTION R e s e r ve d Must be 0 for normal operation In Spread Spectrum, Controls type ( 0 = c e n t e r e d , 1 = d ow n s p r e a d ) In Spread Spectrum, Controls Spreading (0=1.8% 1=0.6%) 4 8 / 2 4 M H z ( F r e q u e n cy S e l e c t ) 1 = 4 8 M H z , 0 = 2 4 M H z 4 8 / 2 4 M H z ( F r e q u e n cy S e l e c t ) 1 = 4 8 M H z , 0 = 2 4 M H z Bit0 Bit1 1 - Tr i - S t a t e 1 0 - Spread Spectrum Enable 1 1 - Te s t m o d e 0 0 - Normal operation 0 7 PWD 0 0 0 0 1 1 0 0 ICS9148-12 Byte 2: PCICLK Clock Register Byte 1: CPU, 24/48 MHz Clock Register DESCRIPTION BIT PIN# PWD 48/24 MHz (Act/Inact) Bit 7 - 1 1 48/24 MHz (Act/Inact) Bit 6 8 1 PCICLK_F (Act/Inact) 1 R e s e r ve d Bit 5 16 1 PCICLK5 (Act/Inact) 1 R e s e r ve d Bit 4 14 1 PCICLK4 (Act/Inact) 13 1 PCICLK3 (Act/Inact) 1 PCICLK2 (Act/Inact) BIT PIN# PWD Bit 7 23 1 Bit 6 22 Bit 5 - Bit 4 - Bit 3 38 1 CPUCLK3 (Act/Inact) Bit 3 Bit 2 39 1 CPUCLK2 (Act/Inact) Bit 2 12 DESCRIPTION R e s e r ve d Bit 1 41 1 CPUCLK1 (Act/Inact) Bit 1 11 1 PCICLK1 (Act/Inact) Bit 0 42 1 CPUCLK0 (Act/Inact) Bit 0 9 1 PCICLK0 (Act/Inact) Notes: 1 = Enabled; 0 = Disabled, outputs held low Notes: 1 = Enabled; 0 = Disabled, outputs held low Byte 3: SDRAM Clock Register Byte 4: SDRAM Clock Register BIT PIN# PWD Bit 7 26 1 BIT DESCRIPTION PIN# PWD DESCRIPTION SDRAM7 (Act/Inact) Bit 7 - 1 R e s e r ve d Bit 6 - 1 R e s e r ve d Bit 6 27 1 SDRAM6 (Act/Inact) Bit 5 29 1 SDRAM5 (Act/Inact) Bit 5 - 1 R e s e r ve d - 1 R e s e r ve d - 1 R e s e r ve d Bit 4 30 1 SDRAM4 (Act/Inact) Bit 4 Bit 3 32 1 SDRAM3 (Act/Inact) Bit 3 Bit 2 33 1 SDRAM2 (Act/Inact) Bit 2 - 1 R e s e r ve d - 1 R e s e r ve d - 1 R e s e r ve d Bit 1 35 1 SDRAM1(Act/Inact) Bit 1 Bit 0 36 1 SDRAM0 (Act/Inact) Bit 0 Notes: 1 = Enabled; 0 = Disabled, outputs held low Notes: 1 = Enabled; 0 = Disabled, outputs held low Byte 5: Peripheral Clock Register Byte 6: Optional Register for Future BIT PIN# PWD Bit 7 - 1 R e s e r ve d DESCRIPTION Bit 7 - 1 R e s e r ve d Bit 6 - 1 R e s e r ve d Bit 6 - 1 R e s e r ve d Bit 5 - 1 R e s e r ve d Bit 5 - 1 R e s e r ve d Bit 4 45 1 IOAPIC0 (Act/Inact) Bit 4 - 1 R e s e r ve d Bit 3 - 1 R e s e r ve d Bit 3 - 1 R e s e r ve d Bit 2 - 1 R e s e r ve d Bit 2 - 1 R e s e r ve d BIT PIN# PWD DESCRIPTION Bit 1 1 1 REF1 (Act/Inact) Bit 1 - 1 R e s e r ve d Bit 0 2 1 REF0 (Act/Inact) Bit 0 - 1 R e s e r ve d Notes: 1 = Enabled; 0 = Disabled, outputs held low Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for future applications. Note: PWD = Power-Up Default Note: PWD = Power-Up Default 8 ICS9148-12 Power Management Clock Enable Configuration C P U _ S TO P # P C I _ S TO P # P W R _ DW N # CPUCLK PCICLK X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 L ow Low Low 66.6/60 MHz 66.6/60 MHz L ow Low 33.3/30 MHz Low 33.3/30 MHz Other Clocks, SDRAM, R E F, I OA P I C s , 48/24 MHz A 48/24 MHz B Stopped Running Running Running Running Crystal VCOs O ff Running Running Running Running O ff Running Running Running Running Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also. ICS9148-12 Power Management Requirements SIGNAL SIGNAL STATE C P U _ S TO P # 0 (Disabled)2 1 (Enabled)1 0 (Disabled)2 1 (Enabled)1 1 (Normal Operation)3 0 (Power Down)4 P C I _ S TO P # PWR_DWN# L a t e n cy No. of rising edges of free running PCICLK 1 1 1 1 3mS 2max Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only. The REF and IOAPIC will be stopped independant of these. 9 ICS9148-12 CPU_STOP# Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9148-12. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs. Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9148-12. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state. PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9148-12. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-12 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. (Drawing shown on next page.) 10 ICS9148-12 Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state. PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internal by the ICS9148-12 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be less than 3mS. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during the power down operations. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated. 11 ICS9148-12 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 IDD3.3PD CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M VDD = 3.3 V; CIN CINX Logic Inputs X1 & X2 pins Transition Time1 Ttrans To 1st crossing of target Freq. Settling Time1 Ts From 1st crossing to 1% target Freq. TSTAB From VDD = 3.3 V to 1% target Freq. 1 Skew 1 MIN 2 VSS-0.3 TYP MAX UNITS VDD+0.3 V 0.8 V µA 0.1 5 µA 2.0 µA -100 60 100 mA -5 -200 CL = 0 pF; With input address to Vdd or GND Fi Clk Stabilization 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP 400 600 14.318 27 TCPU-SDRAM1 VT = 1.5 V TCPU-PCI1 VT = 1.5 V; 36 µA MHz 5 45 pF pF 3 ms ms 1.5 200 3.2 3 mS 500 4.5 ps ns Guarenteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current 1 Skew 1 SYMBOL IDD2.5OP IDD2.5P D CONDITIONS CL = 0 pF; Select @ 66M MIN CL = 0 pF; TCP U-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads TCP U-P CI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads Guarenteed by design, not 100% tested in production. 12 1 TYP 5 MAX 20 UNITS mA 0.21 1.0 µA 150 2.8 500 4 ps ns ICS9148-12 Electrical Characteristics - CPU TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO2 Output Impedance RDSP 2A Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew RDSN2A VOH2A VOL2A IOH2A IOL2A t r2A t f2A 1 1 1 1 d t2A 1 t sk2A tj1s2A 1 t jabs2A 1 1 1 MIN 60 VO = VDD *(0.5) 10 VO = VDD *(0.5) IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V 10 2.4 TYP MAX UNITS 66 MHz 20 Ω 20 Ω V V mA mA 2.5 0.35 -52 59 0.4 -48 VOL = 0.4 V, VOH = 2.4 V 1.1 2.85 ns VOH = 2.4 V, VOL = 0.4 V 0.95 2.85 ns 51 55 % VT = 1.5 V 80 250 ps VT = 1.5 V 170 250 ps VT = 1.5 V 60 150 ps 100 +250 ps TYP MAX UNITS 66 MHz 49.3 VT = 1.5 V 1 t jcyc-cyc2A Jitter CONDITIONS 45 VT = 1.5 V -250 Guarenteed by design, not 100% tested in production. Electrical Characteristics - CPU TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO2 Output Impedance RDSP 2B Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 1 1 RDSN2B VOH2B VOL2B IOH2B IOL2B t r2B 1 1 Fall Time tf2B Duty Cycle 1 d t2B Skew t sk2B 1 1 t jcyc-cyc2B Jitter tj1s2B 1 1 t jabs2B 1 CONDITIONS MIN 60 VO = VDD *(0.5) 10 20 Ω VO = VDD *(0.5) IOH = -8.0 mA IOL = 21 mA VOH = 1.8 V VOL = 0.5 V 10 2.1 20 Ω V V mA mA 2.15 0.3 -22 36 0.4 -18 VOL = 0.4 V, VOH = 2.0 V 1.2 1.5 ns VOH = 2.0 V, VOL = 0.4 V 0.95 1.3 ns 50 55 ns VT = 1.25 V 60 250 ps VT = 1.25 V 150 250 ps VT = 1.25 V 50 150 ps 80 +250 ps 33 VT = 1.25 V 45 VT = 1.25 V -250 Guarenteed by design, not 100% tested in production. 13 ICS9148-12 Electrical Characteristics - PCI TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP 1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter RDSN1 VOH1 VOL1 IOH1 IOL1 t r1 tf1 1 1 1 dt1 1 t sk1 tj1s1 1 1 MIN 30 TYP - MAX UNITS 33 MHz VO = VDD *(0.5) 12 55 Ω VO = VDD *(0.5) IOH = -14.5 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V 12 2.4 55 Ω V V mA mA 2.7 0.2 -47 47.5 0.4 -22 VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns 51 55 % VT = 1.5 V 100 250 ps VT = 1.5 V 50 150 ps -250 120 250 ps MIN 60 TYP 17.1 VT = 1.5 V 1 tjabs1 1 1 CONDITIONS 45 VT = 1.5 V Guarenteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO3 Output Impedance RDSP 3 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter RDSN3 VOH3 VOL3 IOH3 IOL3 Tr3 Tf3 1 1 1 Dt3 1 Tsk3 Tj1s3 1 1 MAX UNITS 66 MHz VO = VDD *(0.5) 10 24 Ω VO = VDD *(0.5) IOH = -24 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V 10 2.4 24 Ω V V mA mA 2.5 0.35 -47 47.5 0.4 -40 VOL = 0.4 V, VOH = 2.4 V 1.45 1.7 ns VOH = 2.4 V, VOL = 0.4 V 1.2 1.5 ns 51 55 % VT = 1.5 V 80 250 ps VT = 1.5 V 40 150 ps - 250 ps 41 VT = 1.5 V 1 Tjabs3 1 1 CONDITIONS 45 VT = 1.5 V -250 Guarenteed by design, not 100% tested in production. 14 ICS9148-12 Electrical Characteristics - IOAPIC TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO4 Output Impedance RDSP 4A Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter RDSN4A VOH4A VOL4A IOH4A IOL4A t r4A tf4A 1 1 1 d t4A 1 tj1s4A MIN TYP 14.318 10 30 Ω VO = VDD *(0.5) IOH = -13 mA IOL = 18 mA VOH = 2.0 V VOL = 0.8 V 10 2.5 30 Ω V V mA mA 2.6 0.35 -29 37 0.4 -23 VOL = 0.4 V, VOH = 2.4 V 1.1 2 ns VOH = 2.4 V, VOL = 0.4 V 1.6 2 ns 51 55 % 160 350 ps - 600 pS 33 45 VT = 1.5 V 1 MAX UNITS MHz VO = VDD *(0.5) VT = 1.5 V 1 t jabs4A 1 1 CONDITIONS VT = 1.5 V -600 Guarenteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency SYMBOL FO4 Output Impedance RDSP 4B Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 1 1 RDSN4B VOH4\B VOL4B IOH4B IOL4B tr4B 1 1 Fall Time tf4B Duty Cycle 1 d t4B Jitter tj1s4B 1 1 tjabs4B 1 CONDITIONS MIN 60 TYP MAX UNITS 66 MHz VO = VDD *(0.5) 10 30 Ω VO = VDD *(0.5) IOH = -5.5 mA IOL = 9.0 mA VOH = 1.7 V VOL = 0.7 V 10 2.1 30 Ω V V mA mA 2.2 0.25 -17 16 0.3 -15 VOL = 0.4 V, VOH = 2.0 V 1.4 1.6 ns VOH = 2.0 V, VOL = 0.4 V 1.1 1.6 ns 53 60 % 130 300 ps - 700 pS 15 VT = 1.25 V 40 VT = 1.25 V VT = 1.25 V -700 Guarenteed by design, not 100% tested in production. 15 ICS9148-12 Electrical Characteristics - REF0 TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter SYMBOL FO7 RDSP 7 RDSN7 VOH7 VOL7 IOH7 IOL7 Tr7 Tf7 1 1 Dt7 1 Tj1s7 VO = VDD *(0.5) VO = VDD *(0.5) IOH = -24 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V MIN 10 10 2.4 41 2.5 0.35 -47 47.5 MAX UNITS MHz 24 Ω 24 Ω V 0.4 V -40 mA mA 1.8 2 ns VOH = 2.4 V, VOL = 0.4 V 1.4 2 ns 52 45 % 150 350 ps -600 - 600 pS MIN TYP 24 48 14.318 45 VT = 1.5 V 1 TYP 14.318 VOL = 0.4 V, VOH = 2.4 V VT = 1.5 V 1 Tjabs7 1 CONDITIONS VT = 1.5 V Guarenteed by design, not 100% tested in production. Electrical Characteristics - 24M, 48M, REF(1:2) TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output Frequency Output Frequency Output Frequency SYMBOL FO24M FO48M FOREF Output Impedance RDSP 5 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter 1 RDSN5 VOH5 VOL5 IOH5 IOL5 t r5 tf5 1 1 1 dt5 1 1 1 tjabs5A 1 1 tjabs5B 1 VO = VDD *(0.5) 20 VO = VDD *(0.5) IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V 20 2.4 MAX UNITS MHz MHz MHz 60 Ω 60 Ω V V mA mA 2.5 0.2 -29 25 0.4 -22 VOL = 0.4 V, VOH = 2.4 V 1.8 4 ns VOH = 2.4 V, VOL = 0.4 V 1.7 4 ns 51 55 % VT = 1.5 V; Fixed Clocks 50 150 ps VT = 1.5 V; Ref Clocks 150 350 16 VT = 1.5 V tj1s5A tj1s5B CONDITIONS 45 VT = 1.5 V; Fixed Clocks -250 120 250 VT = 1.5 V; Ref Clocks -600 - 600 Guarenteed by design, not 100% tested in production. 16 ps ICS9148-12 SSOP Package SYMBOL A A1 A2 B C D E e H h L N ∝ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .006 .0085 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS AC MIN. .620 D NOM. .625 N MAX. .630 48 This table in inches Ordering Information ICS9148yF-12 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 17 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9148-12 240 mil (6.10mm)TSSOP Package SYMBOL MIN. MIN. NOM. MAX — — 1.10 12.40 12.50 12.60 48 A1 0.05 — 0.15 13.90 14.00 14.10 56 A2 0.85 0.90 0.95 b 0.17 — 0.27 C 0.09 — 0.20 E1 6.00 α 6.20 8.10 BSC 0.50 N Example: 6.10 0.50 BSC E L NOM. MAX. See Variations e ICS9148G-12 N D A D Ordering Information VARIATIONS COMMON DIMENSIONS 0.60 0.70 See Variations 0° — 8° Diminisions are in millimeters ICS XXXX G - PPP 240TSSOP_AN Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 18 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.