Maxim MAX8513EEI Wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset Datasheet

19-3178; Rev 0; 2/04
KIT
ATION
EVALU
E
L
B
A
AVAIL
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
A sequence input allows the outputs to either power up
together, or for the DC-DC regulator to power up first
and each LDO controller to power up in sequence. An
input power-fail output (PFO) is provided for input
power-fail warning, such as in dying-gasp applications.
A power-on reset circuit with a 140ms delay is also
included to indicate when all outputs have achieved
regulation and stabilized.
Applications
xDSL, Cable, ISDN Modems, and Routers
Wireless Routers
Features
♦ Low-Cost DC-DC Controller with Two LDOs
♦ Wide Input Range: 4.5V to 28V
♦ 300kHz to 1.4MHz Adjustable Switching
Frequency
♦ Low Noise for High Data-Rate xDSL Applications
♦
♦
♦
♦
Synchronizable to External Clock
Adjustable Soft-Start
Lossless Adjustable Foldback Current Limit
Power-On Reset with 140ms Delay
♦ Adjustable Input Power-Fail Warning for Dying
Gasp
♦ Selectable Output-Voltage Sequencing or
Output-Voltage Tracking
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX8513EEI
-40°C to +85°C
28 QSOP
MAX8514EEI
-40°C to +85°C
28 QSOP
MAX8514AEI
-40°C to +125°C
28 QSOP
Functional Diagram
VIN
(4.5V TO 28V)
MAX8513
ON
OFF
SYNC
OUTPUT
POWER-ON RESET
STEPDOWN
CONTROLLER
LDO
CONTROLLER 1
VOUT2
(0.8V TO VOUT1)
Set-Top Boxes
Automotive Dashboard Electronics
INPUT POWERFAIL MONITOR
Pin Configurations appear at end of data sheet.
VOUT1
(1.25V TO 5.5V)
LDO
CONTROLLER 2
VOUT3
(0.8V TO 27V)
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8513/MAX8514
General Description
The MAX8513/MAX8514 integrate a voltage-mode
PWM step-down DC-DC controller and two LDO controllers, a voltage monitor, and a power-on reset for the
lowest-cost power-supply and monitoring solution for
xDSL modems, routers, gateways, and set-top boxes.
The DC-DC controller switching frequency can be set
with an external resistor from 300kHz to 1.4MHz, to allow
for the optimization of cost, size, and efficiency. For noisesensitive applications, the DC-DC controller can also be
synchronized to an external clock, minimizing noise interference. Operation above 1.1MHz reduces noise for high
data-rate xDSL applications. An adjustable soft-start and
adjustable foldback current limit provide reliable startup
and fault protection. The DC-DC controller output voltage
can be set externally to a voltage from 1.25V to 5.5V.
Current limiting is accomplished by inductor current sensing for improved efficiency, or by an external sense resistor for better accuracy.
The MAX8513/MAX8514s’ first LDO controller is
designed to provide a low-cost, high-current regulated
output from 0.8V to 5.5V using an N-channel MOSFET or
a low-current output using a low-cost NPN transistor. The
MAX8513’s second regulator can be used to generate
0.8V to 27V output with a low-cost PNP transistor. Both
LDO regulators can operate either from the DC-DC controller output or from a higher voltage derived with a flyback overwinding on the DC-DC converter inductor. The
MAX8514’s second LDO regulator is designed to provide a negative output with an NPN transistor.
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
ABSOLUTE MAXIMUM RATINGS
IN, DRV3P, SUP2 to GND.......................................-0.3V to +30V
DRV2 to GND ..........................................-0.3V to (VSUP2 + 0.3V)
DRV3N to GND......................(VSUP3N - 28V) to (VSUP3N + 0.3V)
FREQ, PFI, PFO, POR, SUP3N, SYNC/EN,
CSP, CSN to GND ................................................-0.3V to +6V
VL to GND ...................-0.3V to the lesser of (VIN + 0.3V) or +6V
COMP1, FB1, FB2, FB3P, FB3N, REF, ILIM,
SS, SEQ to GND......................................-0.3V to (VVL + 0.3V)
PVL to PGND ............................................................-0.3V to +6V
DL to PGND...............................................-0.3V to (VPVL + 0.3V)
BST to LX..................................................................-0.3V to +6V
DH to LX ....................................................-0.3V to (VBST + 0.3V)
PGND to GND .......................................................-0.3V to +0.3V
VL Short Circuit to GND .............................................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin QSOP (derate 10.8mW/°C above +70°C).........860mW
Operating Temperature Range
MAX8513EEI, MAX8514EEI .............................-40°C to +85°C
MAX8514AEI..................................................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VLX = VSUP2 = 12V, VPVL = VBST - VLX = VDRV3P = 5V, VSUP3N = 3.3V, VDRV3N = -5V, CVL = 4.7µF, CREF = 0.22µF, RFREQ =
15.0kΩ, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL
IN Operating Range
IN = VL
5.5
28.0
4.5
5.5
V
IN Supply Current
VFB1 = 1.3V, VFB2 = VFB3 = 1.0V, does not
include switching current to PVL and BST,
SYNC/EN = VL
2.6
3.2
mA
IN Shutdown Current
VSYNC/EN = 0, RFREQ = 50kΩ
200
300
µA
5
5.25
V
560
mV
VL REGULATOR
VL Output Voltage
VIN = 6V to 28V, IVL = 0.1mA to 40mA
VL Dropout Voltage
From IN to VL, VIN = 5V, IVL = 40mA
VL Line Regulation
VIN = 6V to 28V, IVL = 5mA
VL Undervoltage Threshold
VL rising, VHYST = 675mV (typ)
4.75
0.05
3.6
%
4.2
V
OUT1 (BUCK CONVERTER)
Output Voltage Range
VOUT1
(Note 1)
1.25
FB1 Regulation Threshold
VFB1
1.234
1.25
Error-Amplifier Open-Loop
Voltage Gain
AVOL
65
90
-200
+10
FB1 Input Bias Current
IFB1_BIAS
VFB1 = 1.3V
Error-Amplifier Gain Bandwidth
5.50
V
1.259
V
dB
+200
25
nA
MHz
DH Output-Resistance High
RDH_HIGH
1.5
2.55
Ω
DH Output-Resistance Low
RDH_LOW
1.2
2.1
Ω
DL Output-Resistance High
RDL_HIGH
2.5
5
Ω
DL Output-Resistance Low
RDL_LOW
0.7
1.3
Driver Dead Time
2
tdt
Starts from VDL = 1V or (VDH - VLX) = 1V
50
_______________________________________________________________________________________
Ω
ns
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
(VIN = VLX = VSUP2 = 12V, VPVL = VBST - VLX = VDRV3P = 5V, VSUP3N = 3.3V, VDRV3N = -5V, CVL = 4.7µF, CREF = 0.22µF, RFREQ =
15.0kΩ, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Current-Limit Threshold (Positive)
Current-Limit Threshold
(Negative)
SYMBOL
VCS
VCS
MIN
TYP
MAX
VILIM = 2.00V, VCSN = 0 to 5.5V
CONDITIONS
246
275
300
VILIM = 0.50V, VCSN = 0 to 5.5V
50
67
81
VILIM = VVL, VCSN = 0 to 5.5V
151
170
188
VILIM = 2.00V, VCSN = 0 to 5.5V
-333
-272
-199
VILIM = 0.50V, VCSN = 0 to 5.5V
-90
-67
-42
-166
VILIM = VVL, VCSN = 0 to 5.5V
-210
CSP and CSN Bias Current
VCSP = VCSN = 0 to 5.5V
-120
ILIM Bias Current
VILIM = 1.25V
-5.3
SS Soft-Start Charge Current
VSS = 0.6V
15
Soft-Start Discharge Resistance
VLX = VIN = 28V, VBST = 33V, VPVL = 5V,
VSYNC/EN = 0
LX, BST, PVL Leakage Current
FB1 Power-On Reset Threshold
1.08
-5
UNITS
mV
mV
-122
+135
µA
-4.7
µA
25
35
µA
100
200
Ω
0.03
20
µA
1.125
1.20
V
28.0
V
OUT2 (POSITIVE LDO)
SUP2 Operating Range
VSUP2
(Note 1)
4.5
DRV2 Clamp Voltage
VDRV2
VFB2 = 0.75V
7.75
SUP2 Supply Current
SUP2 Shutdown Supply Current
VSYNC/EN = 0
FB2 Regulation Voltage
VFB2
FB2 Input Bias Current
IFB2_BIAS
0.784
VFB2 = 0.75V
9.00
V
160
300
µA
3
10
µA
0.80
0.808
V
0.01
100
nA
DRV2 Output Current Limit
VIN = 5V, VDRV2 = 5V, VFB2 = 0.77V
15
30
DRV2 Output Current Limit
During Soft-Start
VIN = 6V, VDRV2 = 5V, VFB2 = 0.70V
8
10
12
mA
0.690
0.720
0.742
V
0.12
0.2
0.36
S
28
V
FB2 Power-On Reset Threshold
FB2 to DRV2 Transconductance
GC2
IDRV2 = +250µA, -250µA
mA
OUT3P (POSITIVE PNP LDO) (MAX8513 ONLY)
DRV3P Operating Range
VDRV3P
FB3P Regulation Voltage
FB3P to DRV3P Large-Signal
Transconductance
Feedback Input Bias Current
Driver Sink Current
GC3P
1
VDRV3P = 5V, IDRV3P = 1mA
0.790
0.803
0.816
V
VDRV3P = 5V, IDRV3P = 0.5mA to 5mA
0.38
0.6
1.1
S
0.01
100
nA
VFB3P = 0.75V
VFB3P = 0.75V
FB3P POR Threshold
FB3P Soft-Start Period
DRV3P = 2.5V
15
DRV3P = 4.0V
35
mA
40
0.690
0.720
1312
0.742
V
Clock
Cycles
_______________________________________________________________________________________
3
MAX8513/MAX8514
ELECTRICAL CHARACTERISTICS (continued)
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VLX = VSUP2 = 12V, VPVL = VBST - VLX = VDRV3P = 5V, VSUP3N = 3.3V, VDRV3N = -5V, CVL = 4.7µF, CREF = 0.22µF, RFREQ =
15.0kΩ, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT3N (NEGATIVE NPN LDO CONTROLLER) (MAX8514 ONLY)
SUP3N Operating Range
(Note 1)
1.5
5.5
V
DRV3N Operating Range
(Note 1)
VSUP3N
- 21V
VSUP3N
- 1.5V
V
SUP3N Supply Current
VDRV3N = 1.5V, VSUP3N = 3.5V,
IDRV3N = -1mA (source)
1.1
2
mA
FB3N Regulation Voltage
VDRV3N = 1.5V, VSUP3N = 3.5V,
IDRV3N = -1mA (source)
-20
-5
+10
mV
0.225
0.36
0.550
S
60
1000
nA
FB3N to DRV3N Large-Signal
Transconductance
GC3N
VDRV3N = 0, IDRV3N = -0.5mA to -5mA
(source)
Feedback Input Bias Current
VFB3N = -100mV
Driver Source Current
VFB3N = 200mV, VDRV3N = 0,
VSUP3N = 3.5V
FB3N POR Threshold
13
25
450
500
FB3N Soft-Start Period
mA
550
mV
Clock
Cycles
2048
REFERENCE
REF Output Voltage
VREF
-2µA < IREF < +50µA
1.231
1.25
1.269
RFREQ = 10.7kΩ ±1% from FREQ to GND
1300
1390
1460
RFREQ = 15.0kΩ ±1% from FREQ to GND
933
985
1040
RFREQ = 50.0kΩ ±1% from FREQ to GND
260
290
324
V
OSCILLATOR
Frequency
fS
FREQ Resistance-Frequency
Product
Maximum Duty Cycle
(Measured at DH Pin)
RFREQ = 10.7kΩ ±1% from FREQ to GND
77
83
91
RFREQ = 15.0kΩ ±1% from FREQ to GND
80
87
95
RFREQ = 50.0kΩ ±1% from FREQ to GND
93
96
99
20
62
RFREQ = 10.7kΩ ±1% from FREQ to GND
SYNC/EN Pulse Width
Low or high (Note 1)
200
SYNC/EN Frequency Range
SYNC/EN input frequency needs to be
within ±30% of the value set at the FREQ
pin (Note 1)
200
SYNC/EN Input Voltage, High
4
VSYNC/EN = 0 to 5.5V
-1
_______________________________________________________________________________________
%
ns
ns
1850
2.4
SYNC/EN Input Voltage, Low
SYNC/EN Input Current
MHz
× kΩ
15.0
Minimum On-Time
(Measured at DH Pin)
kHz
kHz
V
0.8
V
+1
µA
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
(VIN = VLX = VSUP2 = 12V, VPVL = VBST - VLX = VDRV3P = 5V, VSUP3N = 3.3V, VDRV3N = -5V, CVL = 4.7µF, CREF = 0.22µF, RFREQ =
15.0kΩ, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SEQ, PFI, PFO, POR
SEQ Input-Voltage High
2.4
V
SEQ Input-Voltage Low
0.8
V
1
10
µA
IPOR = 1.6mA
10
200
IPOR = 0.1mA,
VIN = 1.0V
20
200
0.001
1
µA
140
315
560
ms
1.20
1.22
1.25
V
0.1
100
nA
IPFO = 1.6mA
20
200
IPFO = 0.1mA,
VIN = 1.0V
10
200
1
SEQ Input Current
VSEQ = 0 to VVL
POR Output-Voltage Low
VFB1, VFB2, VFB3P,
VFB3N, out-of-regulation
POR Output Leakage Current
VFB1, VFB2, and VFB3P or VFB3N, inregulation
POR Power-Ready Delay Time
From VFB1, VFB2, and VFB3P or VFB3N, inregulation to POR = high impedance
PFI Input Threshold
Falling, VHYST = 20mV
PFI Input Bias Current
VPFI = 1.0V
mV
PFO Output-Voltage Low
PFI = 1.1V
PFO Output Leakage Current
PFI = 1.4V, PFO = 5V
0.001
Junction temperature rising
+170
°C
25
°C
mV
µA
THERMAL PROTECTION
Thermal Shutdown
Thermal-Shutdown Hysteresis
ELECTRICAL CHARACTERISTICS
(VIN = VLX = VSUP2 = 12V, VPVL = VBST - VLX = VDRV3P = 5V, VSUP3N = 3.3V, VDRV3N = -5V, CVL = 4.7µF, CREF = 0.22µF, RFREQ =
15.0kΩ, TA = -40°C to +125°C (Note 2), unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
5.5
28.0
4.5
5.5
UNITS
GENERAL
IN Operating Range
IN = VL
V
IN Supply Current
VFB1 = 1.3V, VFB2 = VFB3 = 1.0V, does not
include switching current to PVL and BST,
SYNC/EN = VL
3.2
mA
IN Shutdown Current
VSYNC/EN = 0, RFREQ = 50kΩ
300
µA
VL REGULATOR
VL Output Voltage
VIN = 6V to 28V, IVL = 0.1mA to 40mA
VL Dropout Voltage
From IN to VL, VIN = 5V, IVL = 40mA
VL Undervoltage Threshold
VL rising, VHYST = 675mV (typ)
4.75
3.6
5.25
V
610
mV
4.2
V
_______________________________________________________________________________________
5
MAX8513/MAX8514
ELECTRICAL CHARACTERISTICS (continued)
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VLX = VSUP2 = 12V, VPVL = VBST - VLX = VDRV3P = 5V, VSUP3N = 3.3V, VDRV3N = -5V, CVL = 4.7µF, CREF = 0.22µF, RFREQ =
15.0kΩ, TA = -40°C to +125°C (Note 2), unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
OUT1 (BUCK CONVERTER)
Output Voltage Range
1.25
5.50
V
FB1 Regulation Threshold
VOUT1
VFB1
(Note 1)
1.225
1.265
V
Error-Amplifier Open-Loop
Voltage Gain
AVOL
65
VFB1 = 1.3V
-200
dB
FB1 Input Bias Current
IFB1_BIAS
+200
nA
DH Output-Resistance High
RDH_HIGH
2.55
Ω
DH Output-Resistance Low
RDH_LOW
2.1
Ω
DL Output-Resistance High
RDL_HIGH
5
Ω
DL Output-Resistance Low
RDL_LOW
1.3
Ω
VILIM = 2.00V, VCSN = 0 to 5.5V
243
VILIM = 0.50V, VCSN = 0 to 5.5V
49
83
VILIM = VVL, VCSN = 0 to 5.5V
147
190
VILIM = 2.00V, VCSN = 0 to 5.5V
-333
-199
VILIM = 0.50V, VCSN = 0 to 5.5V
-90
-42
VILIM = VVL, VCSN = 0 to 5.5V
-210
-122
CSP and CSN Bias Current
VCSP = VCSN = 0 to 5.5V
-120
+135
µA
ILIM Bias Current
VILIM = 1.25V
-5.7
-4.3
µA
SS Soft-Start Charge Current
VSS = 0.6V
15
35
µA
200
Ω
20
µA
1.08
1.20
V
V
Current-Limit Threshold
(Positive)
Current-Limit Threshold
(Negative)
VCS
VCS
Soft-Start Discharge Resistance
VLX = VIN = 28V, VBST = 33V, VPVL = 5V,
VSYNC/EN = 0
LX, BST, PVL Leakage Current
FB1 Power-On Reset Threshold
303
mV
mV
OUT2 (POSITIVE LDO)
SUP2 Operating Range
VSUP2
(Note 1)
4.5
28.0
DRV2 Clamp Voltage
VDRV2
VFB2 = 0.75V
7.75
9.00
V
300
µA
10
µA
SUP2 Supply Current
SUP2 Shutdown Supply Current
VSYNC/EN = 0
FB2 Regulation Voltage
VFB2
FB2 Input Bias Current
IFB2_BIAS
0.775
VFB2 = 0.75V
0.816
V
150
nA
DRV2 Output Current Limit
VIN = 5V, VDRV2 = 5V, VFB2 = 0.77V
12
DRV2 Output Current Limit
During Soft-Start
VIN = 6V, VDRV2 = 5V, VFB2 = 0.70V
8
12
mA
0.690
0.742
V
0.11
0.41
S
FB2 Power-On Reset Threshold
FB2 to DRV2 Transconductance
6
GC2
IDRV2 = +250µA, -250µA
_______________________________________________________________________________________
mA
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
(VIN = VLX = VSUP2 = 12V, VPVL = VBST - VLX = VDRV3P = 5V, VSUP3N = 3.3V, VDRV3N = -5V, CVL = 4.7µF, CREF = 0.22µF, RFREQ =
15.0kΩ, TA = -40°C to +125°C (Note 2), unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
OUT3P (POSITIVE PNP LDO) (MAX8513 ONLY)
DRV3P Operating Range
VDRV3P
FB3P Regulation Voltage
FB3P to DRV3P Large-Signal
Transconductance
VDRV3P = 5V, IDRV3P = 1mA
GC3P
VDRV3P = 5V, IDRV3P = 0.5mA to 5mA
Feedback Input Bias Current
VFB3P = 0.75V
Driver Sink Current
VFB3P = 0.75V
1
28
V
0.780
0.820
V
0.3
1.4
S
100
DRV3P = 2.5V
FB3P POR Threshold
15
nA
mA
0.690
0.742
V
OUT3N (NEGATIVE NPN LDO CONTROLLER) (MAX8514 ONLY)
SUP3N Operating Range
(Note 1)
1.5
5.5
V
DRV3N Operating Range
(Note 1)
VSUP3N
- 21V
VSUP3N
- 1.5V
V
SUP3N Supply Current
VDRV3N = 1.5V, VSUP3N = 3.5V,
IDRV3N = -1mA (source)
2
mA
FB3N Regulation Voltage
VDRV3N = 1.5V, VSUP3N = 3.5V,
IDRV3N = -1mA (source)
-20
+10
mV
0.225
0.550
S
1500
nA
FB3N to DRV3N Large-Signal
Transconductance
GC3N
VDRV3N = 0, IDRV3N = -0.5mA to -5mA
(source)
Feedback Input Bias Current
VFB3N = -100mV
Driver Source Current
VFB3N = 200mV, VDRV3N = 0,
VSUP3N = 3.5V
FB3N POR Threshold
13
mA
450
550
mV
-2µA < IREF < +50µA
1.22
1.27
V
RFREQ = 10.7kΩ ±1% from FREQ to GND
1300
1500
RFREQ = 15.0kΩ ±1% from FREQ to GND
917
1070
RFREQ = 50.0kΩ ±1% from FREQ to GND
250
335
RFREQ = 10.7kΩ ±1% from FREQ to GND
77
91
RFREQ = 15.0kΩ ±1% from FREQ to GND
80
95
RFREQ = 50.0kΩ ±1% from FREQ to GND
93
99
REFERENCE
REF Output Voltage
VREF
OSCILLATOR
Frequency
fS
Maximum Duty Cycle
(Measured at DH Pin)
Minimum On-Time
(Measured at DH Pin)
RFREQ = 10.7kΩ ±1% from FREQ to GND
SYNC/EN Pulse Width
Low or high (Note 1)
200
SYNC/EN Frequency Range
SYNC/EN input frequency needs to be
within ±30% of the value set at the FREQ
pin (Note 1)
200
62
kHz
%
ns
ns
1850
kHz
_______________________________________________________________________________________
7
MAX8513/MAX8514
ELECTRICAL CHARACTERISTICS (continued)
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VLX = VSUP2 = 12V, VPVL = VBST - VLX = VDRV3P = 5V, VSUP3N = 3.3V, VDRV3N = -5V, CVL = 4.7µF, CREF = 0.22µF, RFREQ =
15.0kΩ, TA = -40°C to +125°C (Note 2), unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
SYNC/EN Input-Voltage High
MIN
SYNC/EN Input-Voltage Low
SYNC/EN Input Current
MAX
UNITS
0.8
V
+1
µA
2.4
VSYNC/EN = 0 to 5.5V
-1
V
SEQ, PFI, PFO, POR
SEQ Input-Voltage High
2.4
SEQ Input-Voltage Low
SEQ Input Current
VSEQ = 0 to VVL
POR Output-Voltage Low
VFB1, VFB2, VFB3P,
VFB3N out-of-regulation
POR Output Leakage Current
VFB1, VFB2, and VFB3P or VFB3N, inregulation
POR Power-Ready Delay Time
From VFB1, VFB2, and VFB3P or VFB3N, inregulation to POR = high impedance
PFI Input Threshold
Falling, VHYST = 20mV
PFI Input Bias Current
VPFI = 1.0V
PFO Output-Voltage Low
PFI = 1.1V
PFO Output Leakage Current
PFI = 1.4V, PFO = 5V
0.8
V
10
µA
IPOR = 1.6mA
200
IPOR = 0.1mA,
VIN = 1.0V
200
mV
1
µA
140
560
ms
1.20
1.25
V
300
nA
IPFO = 1.6mA
200
IPFO = 0.1mA,
VIN = 1.0V
200
Note 1: Guaranteed by design, not production tested.
Note 2: Specifications to -40°C are guaranteed by design, not production tested.
8
V
_______________________________________________________________________________________
1
mV
µA
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
EFFICIENCY vs. IOUT1
(IOUT2 = 0, IOUT3 = 0)
90
80
40
30
VOUT1 = 3.3V, IOUT1 = 2A
VOUT2 = 2.5V, IOUT2 = 1.5A
VOUT3 = 12V, IOUT3 = 50mA
20
10
0
7
VIN = 12V
50
40
VIN = 16V
20
3.27
10
3.26
3.25
0.1
0.6
VOUT2 vs. IOUT2
1.1
1.6
2.1
2.6
3.1
3.6
0
4.1
12.20
12.15
VOUT1 (V)
3.31
VOUT3 (V)
3.32
12.00
3.29
2.48
11.90
3.28
2.47
11.85
11.80
2.45
11.75
0.6
0.8
1.0
3.27
VOUT1 = 3.3V AT 1A
VOUT2 = 2.5V AT 0.75A
3.26
3.25
0
5
9 10 11 12 13 14 15 16 17 18
OSCILLATOR FREQUENCY
vs. INPUT VOLTAGE
VOUT1 = 3.3V AT 1A
VOUT2 = 2.5V AT 0.75A
12.30
12.25
2.50
2.49
VOUT3 (V)
IOUT2 = 1.5A
12.15
12.10
12.05
2.48
12.00
2.47
11.95
2.46
11.90
2.45
IOUT3 = 0
IOUT3 = 50mA
VIN (V)
RFREQ = 10.7kΩ
1.42
TA = -40°C
1.41
TA = +25°C
1.40
1.39
1.38
1.37
TA = +85°C
1.36
1.35
11.85
9 10 11 12 13 14 15 16 17 18
1.43
OSCILLATOR FREQUENCY (MHz)
MAX8513/14 toc07
12.35
MAX8513/14 toc08
VOUT3 vs. VIN
12.20
8
8
VOUT2 vs. VIN
IOUT2 = 0
7
7
10 15 20 25 30 35 40 45 50
VIN (V)
2.52
2.51
IOUT1 = 3A
IOUT3 (mA)
VOUT1 = 3.3V AT 1A
VOUT3 = 12V AT 25mA
2.53
1.4
4.0
IOUT1 = 0
IOUT2 (A)
2.55
2.54
1.2
3.5
3.30
11.95
2.46
3.0
3.33
12.05
2.49
2.5
VOUT2 = 2.5V AT 0.75A
VOUT3 = 12V AT 25mA
3.34
2.51
2.50
2.0
VOUT1 vs. VIN
12.10
0.4
1.5
3.35
2.52
0.2
1.0
IOUT1 (A)
MAX8513/14 toc05
12.25
MAX8513/14 toc04
VOUT1 = 3.3V AT 1A
VOUT3 = 12V AT 25mA
0
0.5
VOUT3 vs. IOUT3
2.53
VOUT2 (V)
3.29
IOUT1 (A)
2.55
VOUT2 (V)
3.30
3.28
VIN (V)
2.54
3.31
30
0
9 10 11 12 13 14 15 16 17 18
8
3.32
MAX8513/14 toc06
50
60
MAX8513/14 toc09
60
3.33
VIN = 9V
70
VOUT2 = 2.5V AT 0.75A
VOUT3 = 12V AT 25mA
3.34
VOUT1 (V)
70
EFFICIENCY (%)
EFFICIENCY (%)
80
3.35
MAX8513/14 toc02
90
VOUT1 vs. IOUT1
100
MAX8513/14 toc01
100
MAX8513/14 toc03
EFFICIENCY vs. INPUT VOLTAGE
7
8
9 10 11 12 13 14 15 16 17 18
VIN (V)
7
8
9 10 11 12 13 14 15 16 17 18
VIN (V)
_______________________________________________________________________________________
9
MAX8513/MAX8514
Typical Operating Characteristics
(Circuit of MAX8513 evaluation kit, VIN = 12V, TA = +25°C, fS = 1.4MHz, unless otherwise noted.)
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
Typical Operating Characteristics (continued)
(Circuit of MAX8513 evaluation kit, VIN = 12V, TA = +25°C, fS = 1.4MHz, unless otherwise noted.)
OUTPUT1 LOAD-TRANSIENT RESPONSE
OUTPUT3 LOAD-TRANSIENT RESPONSE
MAX8513/14 toc10
MAX8513/14 toc11
IOUT2 = 0.75A, IOUT3 = 25mA
IOUT1 = 1A, IOUT2 = 0.75A
50mV/div
VOUT1
AC-COUPLED
50mV/div
VOUT2
AC-COUPLED
VOUT1
AC-COUPLED
VOUT2
AC-COUPLED
50mV/div
50mV/div
50mV/div
VOUT3
AC-COUPLED
VOUT3
AC-COUPLED
100mV/div
IOUT1
1A/div
0A
IOUT3
50mA/div
5mA
40µs/div
40µs/div
SWITCHING WAVEFORMS
(ALL OUTPUTS AT FULL LOAD)
SYNCHRONIZATION
MAX8513/14 toc13
MAX8513/14 toc12
VDH
10V/div
0V
VDH
5V/div
0V
VDL
5V/div
0V
VLX
10V/div
0V
VD2
(ANODE)
20V/div
0V
VDL
10V/div
0V
SYNC/EN
5V/div
0V
1µs/div
200ns/div
PFO RESPONSE
POR RESPONSE
MAX8513/14 toc14
MAX8513/14 toc15
PFO
2V/div
0V
POR
5V/div
0V
VIN
5V/div
0V
VOUT1
2V/div
0V
VOUT1
2V/div
0V
0V
VOUT2
5V/div
0V
VOUT3
10V/div
IOUT1 = 2A, IOUT2 = 1.5A, IOUT3 = 50mA
2ms/div
10
100ms/div
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
STAGGERED SEQUENCE (SEQ = GND)
TRACKING SEQUENCE (SEQ = VL)
MAX8513/14 toc16
MAX8513/14 toc17
SYNC/EN
5V/div
0V
SYNC/EN
5V/div
0V
VOUT3
5V/div
VOUT1
2V/div
VOUT2
2V/div
VOUT3
5V/div
VOUT1
2V/div
VOUT2
2V/div
0V
0V
2ms/div
4ms/div
OUTPUT1 SHORT CIRCUIT
(ALL OUTPUTS AT FULL LOAD)
OUTPUT1 SHORT CIRCUIT
(ALL OUTPUTS AT NO LOAD)
MAX8513/14 toc18
MAX8513/14 toc19
VOUT1
2V/div
VOUT1
2V/div
0V
0V
VLX
10V/div
VLX
10V/div
0V
0V
1L
2A/div
IL
2A/div
0A
0A
20µs/div
20µs/div
1.5
VIN = 12V
VOUT1 = 3.3V AT 2A
VOUT2 = 2.5V AT 1.5A
VOUT3 = 12V AT 50mA
1.3
1.1
NOISE (mV)
0.9
MAX8513/14 toc20
OUTPUT RIPPLE AND HARMONICS
(MEASURED AT OUT1)
0.7
0.5
0.3
0.1
-0.1
-0.3
-0.5
100
1100
2100
3100
4100
5100
FREQUENCY (kHz)
______________________________________________________________________________________
11
MAX8513/MAX8514
Typical Operating Characteristics (continued)
(Circuit of MAX8513 evaluation kit, VIN = 12V, TA = +25°C, fS = 1.4MHz, unless otherwise noted.)
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
MAX8513/MAX8514
Pin Description
12
PIN
NAME
MAX8513
MAX8514
PFI
1
1
Power-Fail Input. Connect PFI to an external resistive-divider between IN, PFI, and GND.
PFI senses VIN to detect voltage failure. Trip falling threshold at this input is 1.22V, with
20mV of hysteresis.
PFO
2
2
Power-Fail Output. Open-drain output that goes low if VPFI < 1.22V.
DH
3
3
OUT1 High-Side Gate-Drive Output. DH drives the high-side N-channel MOSFET (Q1 in the
Typical Applications Circuits). DH is a floating driver output that swings from LX to BST.
LX
4
4
OUT1 High-Side Driver Return Path. The high-side FET driver uses BST and LX for its
respective high and low-side supplies.
BST
5
5
OUT1 Boost Capacitor Connection for High-Side Gate Drive. Connect a 0.1µF ceramic
capacitor from BST to LX with a less than 5mm trace length.
DL
6
6
OUT1 Low-Side Gate-Drive Output. DL drives the low-side N-channel MOSFET (Q2 in the
Typical Applications Circuits). DL swings from 0 to VPVL.
PVL
7
7
OUT1 Gate-Drive Supply Bypass Connection. Connect PVL to VL through a 10Ω resistor
(R15), and bypass PVL to PGND with a minimum 1µF capacitor (C1).
PGND
8
8
Power-Ground Connection and Low-Side Supply for Dl Driver
VL
9
9
Internal +5V Linear-Regulator Bypass Pin. Bypass VL to GND with a minimum 2.2µF
ceramic capacitor (C10) and 5mm or less of trace length. VL should be connected to IN
when VIN < 5.5V.
COMP1
10
10
OUT1 Compensation Node. See the OUT1 Compensation section.
FB1
11
11
OUT1 Feedback Input. Connect a resistive-divider (R1, R2) from OUT1 to FB1 to GND to
regulate FB1 at 1.25V.
FUNCTION
FREQ
12
12
Oscillator Frequency-Set Input. A resistor from FREQ to GND sets the oscillator frequency
from 300kHz to 1.4MHz (f = 15MHz x kΩ / RFREQ). RFREQ is still required if an external clock
is used at SYNC/EN, and the SYNC/EN input frequency should be within ±30% of the
frequency set by RFREQ.
REF
13
13
1.25V Reference Output. Connect a 0.1µF or larger ceramic capacitor (C9) from REF to GND.
GND
14
14
Analog/Signal Ground
FB2
15
15
OUT2 Feedback Input. Connect a resistive-divider (R5, R6) from OUT2 to FB2 to GND to
regulate FB2 to 0.8V.
DRV2
16
16
OUT2 Gate Drive. DRV2 connects to the gate of an external N-channel MOSFET to form a
positive linear voltage regulator.
SUP2
17
17
Supply Input for DRV2. Connect to a voltage source of at least 1V above the maximum
desired DRV2 gate voltage.
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
PIN
NAME
MAX8513
MAX8514
SEQ
18
18
Connect to VL for output tracking. Connect to GND for output staggered sequence.
Staggered sequence ramps up VOUT2 and VOUT3 softly to avoid glitches on the previous
voltage due to charging of the LDO’s output capacitors.
FUNCTION
SYNC/EN
19
19
Shutdown Control and Synchronization Input. There are three operating modes:
• When SYNC/EN is low, the controller is off but the VL regulator is still running.
• When SYNC/EN is high, the controller is enabled with the switching frequency set by
RFREQ.
• When SYNC/EN is driven by an external clock, the controller is enabled and switches at
the external clock frequency.
N.C.
20
—
No Connection. Not internally connected. Connect to GND or leave floating.
SUP3N
—
20
OUT3N Base-Drive Supply. Connect SUP3N to any positive voltage between 1.5V and 5.5V
to provide power for the negative linear-regulator transistor driver.
DRV3P
21
—
OUT3P Base Drive. Connect DRV3P to the base of an external PNP pass transistor to form a
positive linear voltage regulator.
DRV3N
—
21
OUT3N Base Drive. Connect DRV3N to the base of an external NPN pass transistor to form
a negative linear voltage regulator.
IN
22
22
Main Voltage Input (4.5V to 28V). Bypass IN to GND, close to the IC, with a minimum 1µF
ceramic capacitor (C2). IN powers the linear regulator whose output is VL.
POR
23
23
Power-On Reset. Open-drain output that goes high after all outputs reach the regulation
limit and a 315ms delay time has elapsed.
FB3P
24
—
OUT3P Feedback Input. FB3P is referenced to 0.8V and connects to a resistive-divider
(R13, R14) to control a positive linear voltage regulator.
FB3N
—
24
OUT3N Feedback Input. Connect a resistive-divider (R13, R14) from OUT1 to FB3N to
OUT3N to regulate FB3N to 0V.
ILIM
25
25
ILIM Set Input. Connect a resistive-divider (R17, R18) from OUT1 to ILIM to GND. See the
Current Limit section.
CSP
26
26
Positive Current-Sense Input. Used to detect OUT1 current limit.
CSN
27
27
Negative Current-Sense Input. Used to detect OUT1 current limit.
SS
28
28
Analog Soft-Start Control Input. This pin goes into the positive input of the VOUT1’s error
amplifier. When the MAX8513/MAX8514 are turned on, SS is at GND and charges up to 1.25V
with a constant 25µA. Connect a capacitor (C13) from SS to GND for the desired soft-start time.
______________________________________________________________________________________
13
MAX8513/MAX8514
Pin Description (continued)
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
IN
SS
BST
SYNC/EN
S
Q
DH
R
Q
LX
PVL
VL
BIAS
1/7.5
DL
5µA
PGND
GND
CSP
FREQ
PWM
COMP.
SEQ
CSN
1VP-P
FB1
ERROR
AMP
PFI
COMP
1.25V
PFO
N
ILIM
SUP2
0.8V
POR
DRV2
GC2
N
FB2
0.8V
GC3P
REF
REFERENCE
DRV3P
N
N
FB3P
MAX8513
Figure 1. MAX8513 Functional Diagram
14
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
MAX8513/MAX8514
IN
SS
BST
SYNC/EN
S
Q
DH
R
Q
LX
PVL
VL
BIAS
1/7.5
DL
5µA
GND
PGND
CSP
FREQ
PWM
COMP.
SEQ
CSN
1VP-P
FB1
ERROR
AMP
PFI
COMP
1.25V
PFO
N
ILIM
SUP2
REFERENCE
0.8V
POR
DRV2
GC2
N
FB2
SUP3N
P
REF
GC3N
P
DRV3N
FB3N
MAX8514
Figure 2. MAX8514 Functional Diagram
______________________________________________________________________________________
15
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
Detailed Description
The MAX8513/MAX8514 combine a step-down DC-DC
converter and two LDOs, providing three output voltages for xDSL modem and set-top box applications.
The switching frequency is set with an external resistor
connected from the FREQ pin to GND, and is
adjustable from 300kHz to 1.4MHz. The main stepdown DC-DC controller operates in a voltage-mode,
pulse-width-modulation (PWM) control scheme. The
MAX8513/MAX8514 include two low-cost LDO controllers capable of delivering current from the DC-DC
main output, an extra winding, the input, or from an
alternate supply voltage. The first LDO controller drives
an external NMOS or NPN with a maximum drive of
7.75V. The second LDO controller provides either a
positive 0.8V to 27V output using an external PNP pass
device, or a negative -1V to -18V output with an external NPN pass device.
DC-DC Controller
The MAX8513/MAX8514 step-down DC-DC converters
use a PWM voltage-mode control scheme. An internal
high-bandwidth (25MHz) operational amplifier is used
as an error amplifier to regulate the output voltage. The
output voltage is sensed and compared with an internal
1.25V reference to generate an error signal. The error
signal is then compared with a fixed-frequency ramp
by a PWM comparator to give the appropriate duty
cycle to maintain output-voltage regulation. At the rising edge of the internal clock and when DL (the lowside MOSFET gate drive) is at 0V, the high-side
MOSFET turns on. When the ramp voltage reaches the
error-amplifier output voltage, the high-side MOSFET
latches off until the next clock pulse. During the highside MOSFET on-time, current flows from the input
through the inductor to the output capacitor and load.
At the moment the high-side MOSFET turns off, the
energy stored in the inductor during the on-time is
released to support the load. The inductor current
ramps down through the low-side MOSFET body diode.
After a fixed delay, the low-side MOSFET turns on to
shunt the current from its body diode for a lower voltage
drop to increase the efficiency. The low-side MOSFET
turns off at the rising edge of the next clock pulse, and
when its gate voltage discharges to zero, the high-side
MOSFET turns on after an additional fixed delay and
another cycle starts.
Current Limit
The MAX8513/MAX8514s’ switching regulator senses
the inductor current either through the DC resistance of
the inductor itself for lossless sensing, or through a
series resistor for more accurate sensing. When using
the DC resistance of the inductor, an RC filter circuit is
needed (see R19, R20, and C14 of the Typical
Applications Circuits and the Current-Limit Setting section). When peak voltage across the sensing circuit
(which occurs at the peak of the inductor current)
exceeds the current-limit threshold set by ILIM, the
controller turns off the high-side MOSFET and turns on
the low-side MOSFET. The inductor current ramps
down and DH turns on again if the inductor current is
below the current-limit threshold at the next clock
pulse. The MAX8513/MAX8514 current-limit threshold
can be set by two external resistors to be proportional
to the output voltage with an adjustable offset level,
providing foldback current-limit and short-circuit protection. This feature greatly reduces power dissipation
and prevents overheating of external components during an indefinite short-circuit at the output. See the
Foldback Current Limit section for how to set ILIM with
external resistors. The current-limit threshold defaults to
170mV when ILIM is connected to VL, and in this case,
the current limit functions as a constant current limit
only. The LDO controllers do not have current limit and
rely on input current limit for protection.
Synchronous-Rectifier Driver (DL)
Synchronous rectification reduces the conduction loss
in the rectifier by replacing the normal Schottky catch
diode with a low-on-resistance MOSFET switch. The
MAX8513/MAX8514 also use the synchronous rectifier
to ensure proper startup of the boost gate-drive circuit.
High-Side Gate-Drive Supply (BST)
A flying-capacitor boost circuit (see D1 and C3 in the
Typical Applications Circuits) generates the gate-drive
voltage for the high-side N-channel MOSFET. On startup, the synchronous rectifier (low-side MOSFET, Q2)
forces LX to ground and charges the boost capacitor
(C3) to VVL - VDIODE. On the second half-cycle, the
controller turns on the high-side MOSFET by closing an
internal switch between BST and DH. This boosts the
voltage at BST to VVL - VDIODE + VIN, providing the
necessary gate-to-source voltage to turn on the highside N-channel MOSFET.
The MAX8513/MAX8514 operate in forced-PWM mode,
so even under light load the controller maintains a constant switching frequency to minimize noise and possible interference with system circuitry.
16
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
Undervoltage Lockout
If V VL drops below 3.8V, the MAX8513/MAX8514
assume that the supply voltage is too low to make valid
decisions. When this happens, the undervoltage lockout (UVLO) circuitry inhibits switching, forces POR and
PFO low, and forces DL and DH gate drivers low. After
VVL rises above 3.9V, the controller powers up the outputs (see the Startup section).
Startup
The MAX8513/MAX8514 start switching when VVL rises
above the 3.9V UVLO threshold. However, the controller is not enabled unless all three of the following
conditions are met:
1) VVL exceeds the 3.9V UVLO threshold.
2) The internal reference exceeds 90% of its nominal
value.
3) The thermal limit is not exceeded.
Once the MAX8513/MAX8514 assert the internal enable
signal, the step-down controller starts switching and
enables soft-start. The soft-start circuitry gradually ramps
up to the reference voltage to control the rate-of-rise of
the step-down controller and reduce input surge currents. The soft-start period is determined by the value of
the capacitor from SS to GND (C13 in the Typical
Applications Circuits). SS sources a constant 25µA to
charge the soft-start capacitor to 1.25V.
Output-Voltage Sequencing
The MAX8513/MAX8514 can power up in either staggered-output sequencing or output tracking. For staggered-output sequencing, connect SEQ to GND. In this
configuration, VOUT1 comes up first. When it reaches
90% of the nominal regulated value, VOUT2 is softly
turned on. Once VOUT2 reaches 90% of its nominal regulated value, VOUT3 is softly turned on. Individual soft-start
on OUT2 and OUT3 eliminates glitches on the previous
stages due to the charging of output capacitors. See the
Typical Operating Characteristics section for the startup
and staggered-output-sequence waveforms.
Output-Voltage Tracking
When SEQ is connected to VL, all outputs rise up at the
same time and the external series pass transistors are
driven fully on until reaching the respective regulation
limits. Since the LDOs are powered from the main DCDC step-down converter, either directly or through a
coupled winding on the inductor, their outputs track the
DC-DC step-down output (OUT1). See the Typical
Operating Characteristics section for the startup outputtracking waveforms.
Power-On Reset
The MAX8513/MAX8514 provide a power-on-reset (POR)
signal, which goes high 315ms after all outputs reach
90% of their nominal regulated value. Therefore, by the
time POR goes high, all outputs are already stabilized at
nominal regulated voltages. See the Typical Operating
Characteristics section for the POR waveforms.
Input Power-Fail (PFI and PFO)
The MAX8513/MAX8514 have a built-in comparator to
detect the input voltage with an external resistivedivider at PFI, with a threshold of 1.22V. When the input
voltage drops and trips this comparator, the power-fail
output (PFO) goes low, while all outputs are still within
regulation limits. This is typically used for input powerfail warning for orderly system shutdown. The amount of
warning time depends on the input storage capacitor,
the input PFI trip voltage level, the main step-down output voltage, the total output power, and the efficiency.
See the Design Procedure section for how to calculate
the input capacitor to meet the required warning time.
Enable and Synchronization
The MAX8513/MAX8514 can be turned on with logic
high, and off with logic low at SYNC/EN. When SYNC/EN
is driven with an external clock, the internal oscillator
synchronizes the rising edge of the clock at SYNC/EN to
DH going high. When being driven by a synchronization
clock signal at SYNC/EN, the controller synchronizes to
the external clock within two cycles. The frequency at
SYNC/EN needs to be within ±30% of the value set by
RFREQ. See the Switching-Frequency Setting section.
______________________________________________________________________________________
17
MAX8513/MAX8514
Internal 5V Linear Regulator
All MAX8513/MAX8514 functions (except for the positive output LDO with an NFET or NPN, and the negative
LDO on the MAX8514) are powered from the on-chip
low-dropout 5V regulator with its input connected to IN.
Bypass the regulator’s output (VL) with a 2.2µF or
greater ceramic capacitor. The VIN to VVL dropout voltage is typically 350mV, so when VIN is greater than
5.5V, VVL is typically 5V. If VIN is between 4.5V and
5.5V, short VL to IN.
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
Thermal-Overload Protection
Thermal-overload protection limits the total power dissipation in the MAX8513/MAX8514. When the junction
temperature exceeds TJ = +170°C, a thermal sensor
shuts down the device, forcing DL and DH low and
allowing the IC to cool. The thermal sensor turns the part
on again after the junction temperature cools by 25°C,
resulting in a pulsed output during continuous thermaloverload conditions. During a thermal event, the main
step-down converter and the linear regulators are turned
off, POR and PFO go low, and soft-start is reset.
Design Procedure
OUT1 Voltage Setting
The output voltage is set by a resistive-divider network
from OUT1 to FB1 to GND (see R1 and R2 in the
Typical Applications Circuits). Select R2 between 5kΩ
and 15kΩ. Then R1 can be calculated by:
V

R1 = R2 ×  OUT1 - 1
 1.25V

Input Power-Fail Setting
The PFI input can monitor VIN to determine if it is falling.
When the voltage at PFI crosses 1.22V, the output
(PFO) goes low. The input voltage value at the PFI trip
threshold, VPFI, is set by a resistive-divider network
from IN to PFI to GND (see the Typical Applications
Circuits). Select R11, the resistor from PFI to GND
between 10kΩ and 40kΩ. Then R10, the resistor from
PFI to IN, is calculated by:
 V

R10 = R11 ×  PFI - 1
 1.22V

Switching-Frequency Setting
The resistor connected from FREQ to GND, RFREQ (R7
in the Typical Applications Circuits), sets the switching
frequency, fS, as shown by the equation below:
fS =
15 × 109
Hz × Ω
RFREQ
where RFREQ is in ohms.
value allows for a smaller inductor but results in higher
losses and higher output ripple. A good compromise
between size and efficiency is a 30% LIR. Once all of
the parameters are chosen, the inductor value is determined as follows:
L =
VOUT1 × (VIN - VOUT1)
VIN × fS × IOUT1_ MAX × LIR
where VOUT1 is the main switching regulator output and
fS is the switching frequency.
Choose a standard value close to the calculated value.
The exact inductor value is not critical and can be
adjusted to make tradeoffs between size, cost, and efficiency. Lower inductor values minimize size and cost,
but also increase the output ripple and reduce the efficiency due to higher peak currents. On the other hand,
higher inductor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the
benefit gained from lower AC current levels. Find a lowloss inductor with the lowest possible DC resistance that
fits the allotted dimensions. Ferrite cores are often the
best choice, although powdered iron is inexpensive and
can work well up to 300kHz. The chosen inductor’s saturation current rating must exceed the peak inductor current as calculated below:
IPEAK = IOUT1_ MAX +
(VIN
2 × L × fS × VIN
This peak value should be smaller than the value set at
ILIM when VOUT1 is at its nominal regulated voltage (see
the Current Limit and Current-Limit Setting sections).
In applications where a multiple winding inductor (coupled inductor) is used to generate the supply voltages
for the LDOs, the inductance value calculated above is
for the winding connected to the DC-DC step-down
(primary windings) inductance. The inductance seen
from the other windings (secondary windings) is proportional to the square of the turns ratio with respect to
the primary winding.
The turns ratio is important since it sets the LDOs’ supply voltage values. The voltage generated by the secondary winding (VSEC) together with the rectifier diode
and output capacitor is calculated as follows:
Inductor Value
There are several parameters that must be examined
when determining which inductor to use: input voltage,
output voltage, load current, switching frequency, and
LIR. LIR is the ratio of peak-to-peak inductor ripple current to the maximum DC load current. A higher LIR
18
- VOUT1) × VOUT1
VSEC = (VOUT1 + VQ2


) ×  nn2  - VD2
1
where VQ2 and VD2 are the voltage drops across the
low-side MOSFET on the primary side and the rectifier
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
It is important to have the secondary winding tightly
coupled with the primary winding to minimize leakage
inductance for higher efficiency. The positive voltage
generated by the secondary winding can also be
stacked with the main DC-DC step-down converter output to further improve efficiency and reduce winding
cost. In this case, the secondary-side voltage is:
VSEC = (VOUT1 + VQ2


) ×  nn2 
1
+ VOUT1 - VD2
Input Capacitor
The input-filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the AC-RMS current
through the ESR of the input capacitor (C2 in the Typical
Applications Circuits). The input capacitor must meet
the ripple-current requirement (IIN_RMS) imposed by the
switching currents defined by the following equation:
IIN _ RMS =
IOUT1 ×
VOUT1 × (VIN - VOUT1)
VIN
IIN_RMS has a maximum value when the input voltage
equals twice the output voltage (VIN = 2 × VOUT1), so
IIN_RMS(MAX) = IOUT1 / 2. Ceramic capacitors are recommended due to their low ESR and ESL at high frequency, with relatively low cost. Choose a capacitor that
exhibits less than 10°C temperature rise at the maximum
operating RMS current for optimum long-term reliability.
For applications that require input power-fail warning,
such as dying gasp, add a large-value electrolytic
capacitor (CS) to the input as a local energy storage
device to provide the power to the converter in case of
input power-fail. The capacitor value must be high
enough to meet the desired power-fail warning time,
tWARN, where tWARN is the time from when PFI trips the
PFO output to when the main output (OUT1) starts
dropping out of regulation. The value of the storage
capacitor, CS, can be calculated as:
 1



P
1
CS =  0.5 × OUT1  × 
η 
VDROOP 

 VPFI
×
t WARN
(VPFI - VDROOP )
where POUT1 is the total output power, η is the total
converter efficiency, VPFI is the input voltage value at
the input power-fail (PFI) trip threshold, and VDROOP is
the input voltage value where VOUT1 starts dropping
out of regulation.
VPFI and VDROOP can be calculated as:
R10 

VPFI = 1.22V × 1 +


R11 
where R10 and R11 are the resistive-dividers from IN to
PFI to GND in the Typical Applications Circuits.
VDROOP =
VOUT1
DMAX
where DMAX is the maximum duty cycle.
To ensure for worst-case component tolerances such
as capacitance of CS, converter efficiency, VPFI, and
VDROOP’s threshold over the operating temperature
range, it is recommended to select CS at least 1.5 times
the calculated value above.
Output Capacitor
The key selection parameters for the output capacitor
are the actual capacitance value, the equivalent series
resistance (ESR), the equivalent series inductance
(ESL), and the voltage-rating requirements. All of these
affect the overall stability, output ripple voltage, and
transient response.
The output ripple is composed of three components: variations in the charge stored in the output capacitor, the
voltage drop across the capacitor’s equivalent series
resistance (ESR), and equivalent series inductance (ESL)
caused by the current into and out of the capacitor.
______________________________________________________________________________________
19
MAX8513/MAX8514
diode on the secondary side (Q2 and D2 in the Typical
Applications Circuits). n2 and n1 are the number of
turns of the secondary winding and the primary winding, respectively.
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
The peak-to-peak output voltage ripple as a consequence of the ESR, ESL, and output capacitance is:
VRIPPLE(ESR) = IP-P × RESR
IP-P
VRIPPLE(C) =
8 × COUT × fS
where COUT is C4 in the Typical Applications Circuits.
VIN × ESL
L1A + ESL
 V -V
 V

and IP-P =  IN OUT1   OUT1 
f
L
V

  IN 
S
VRIPPLE(ESL) =
where IP-P is the peak-to-peak inductor current (see the
Inductor Selection section). An approximation of the
overall voltage ripple at the output is:
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL)
While these equations are suitable for initial capacitor
selection to meet the ripple requirement, final values may
also depend on the relationship between the LC doublepole frequency and the capacitor ESR zero. Generally,
the ESR zero is higher than the LC double pole (see the
Compensation Design section). Solid polymer electrolytic or ceramic capacitors are recommended due to their
low ESR and ESL at higher frequencies. Higher output
current may require paralleling multiple capacitors to
meet the output voltage ripple.
The MAX8513/MAX8514s’ response to a load transient
depends on the selected output capacitor. After a load
transient, the output instantly changes by (ESR ×
∆IOUT1) + (ESL × dIOUT1 / dt). Before the controller can
respond, the output deviates further depending on the
inductor and output capacitor values. After a short period of time (see the Typical Operating Characteristics),
the controller responds by regulating the output voltage
back to its nominal state. The controller response time
depends on the closed-loop bandwidth. With a higher
bandwidth the response time is faster, preventing the
output capacitor from further deviation from its regulating value. Be sure not to exceed the capacitor’s voltage
or current ratings.
MOSFET Selection
The MAX8513/MAX8514 drive two external, logic-level,
N-channel MOSFETs as the circuit switch elements.
The key selection parameters are:
• For on-resistance (RDS_ON), the lower the better.
20
• Maximum drain-to-source voltage (VDS) should be at
least 20% higher than the input supply rail at the
high-side MOSFET’s drain.
• For gate charges (QGS, QGD, QDS), the lower the
better.
Choose the MOSFETs with rated R DS_ON at V GS =
4.5V. For a good compromise between efficiency and
cost, choose the high-side MOSFET (Q1 in the Typical
Applications Circuits) that has conduction loss equal to
switching loss at nominal input voltage and maximum
output current. For the low-side MOSFET (Q2 in the
Typical Applications Circuits), make sure that it does
not spuriously turn on due to dV/dt caused by Q1 turning on as this results in shoot-through current degrading the efficiency. MOSFETs with a lower QGD / QGS
ratio have higher immunity to dV/dt.
For proper thermal management, the power dissipation
must be calculated at the desired maximum operating
junction temperature, maximum output current, and
worst-case input voltage. For Q2, the worst case is at
V IN_MAX . For Q1, it could be either at V IN_MIN or
VIN_MAX. Q1 and Q2 have different loss components
due to the circuit operation. Q2 operates as a zero voltage switch, where major losses are the channel conduction loss (PQ2CC) and the body-diode conduction
loss (PQ2DC).


V
PQ2CC = 1 - OUT1  × IOUT12 × RDS _ ON
V

IN 
PQ2DC = 2 × IOUT1 × VF × t dt × fS
where VF is the body-diode forward voltage drop, tdt =
50ns is the dead time between Q1 and Q2 switching
transitions, and fS is the switching frequency.
The total losses for Q2 are:
PQ2 _ TOTAL = PQ2CC + PQ2DC
Q1 operates as a duty-cycle control switch and has the
following major losses: the channel conduction loss
(PQ1CC), the V I overlapping switching loss (PQ1SW),
and the drive loss (PQ1DR). Q1 does not have bodydiode conduction loss because the diode never conducts current.
PQ1CC =
VOUT1
× IOUT12 × RDS _ ON
VIN
where RDS_ON is at the maximum operating junction
temperature.
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
+ QGD )
IGATE
where IGATE is the average DH high driver output-current capability determined by:
IGATE =
2.5V
R
( DH + RGATE )
LPAR =
where RDH is the high-side MOSFET driver’s on-resistance (1.5Ω typ) and RGATE is the internal gate resistance of the MOSFET (≈2Ω).
PQ1DR = QGS × VGS × fS ×
RGATE
RDH
(RGATE +
1) Connect a scope probe to measure VLX to GND,
and observe the ringing frequency, fR .
2) Find the capacitor value (connected from LX to
GND) that reduces the ringing frequency by half.
The circuit parasitic capacitance (CPAR) at LX is then
equal to 1/3rd the value of the added capacitance above.
The circuit parasitic inductance (LPAR) is calculated by:
)
where VGS ≈ VVL = 5V.
1
(2π
× fR )
2
× CPAR
The resistor for critical dampening (RSNUB) is equal to
(2π × fR × LPAR). Adjust the resistor value up or down to
tailor the desired damping and the peak voltage excursion. The capacitor (CSNUB) should be at least 2 to 4
times the value of the CPAR to be effective. The power
loss of the snubber circuit is dissipated in the resistor
(PRSNUB) and can be calculated as:
The total power loss in Q1 is:
PQ1 = PQ1CC + PQ1SW + PQ1DR
In addition to the losses above, allow approximately
20% more for additional losses due to MOSFET output
capacitances and Q2 body-diode reverse recovery
charge dissipated in Q1. This is not typically welldefined in MOSFET data sheets. Refer to the MOSFET
data sheet for the thermal-resistance specification to
calculate the PC board area needed to maintain the
desired maximum operating junction temperature with
the above calculated power dissipations.
To reduce EMI caused by switching noise, add a 0.1µF
or larger ceramic capacitor from the high-side MOSFET
drain to the low-side MOSFET source or add resistors
in series with DH and DL to slow down the switching
transitions. However, adding series resistors with DH
and DL increases the power dissipation in the MOSFET
when it switches, so be sure this does not overheat the
MOSFET. The minimum load current must exceed the
high-side MOSFET’s maximum leakage current over
temperature if fault conditions are expected.
MOSFET Snubber Circuit
Fast switching transitions cause ringing because of resonating circuit parasitic inductance and capacitance at
the switching nodes. This high-frequency ringing
occurs at LX’s rising and falling transitions and can
interfere with circuit performance and generate EMI. To
dampen this ringing, a series-RC snubber circuit is
added across each switch. The following is the procedure for selecting the value of the series-RC circuit:
PRSNUB = CSNUB × (VIN )
2
× fS
where VIN is the input voltage and fS is the switching
frequency. Choose an RSNUB power rating that meets
the specific application’s derating rule for the power
dissipation calculated.
Current-Limit Setting
The MAX8513/MAX8514 can provide foldback current
limit or constant current limit. Unless constant currentlimit operation is required, such as when driving a constant current load, foldback current limit should be
implemented. Foldback current limit reduces the power
dissipation of external components under overload or
short-circuit conditions.
Foldback Current Limit
For foldback current limit, the current-limit threshold is
set by an external resistive-divider from VOUT1 to ILIM to
GND (R17 and R18 of the Typical Applications Circuits).
This makes the voltage at ILIM a function of the internal
5µA current source and VOUT1. The current-limit comparator threshold is equal to VILIM / 7.5. This threshold is
compared with VSENSE. VSENSE is either the voltage
across the current-sense resistor or, for lossless sensing, the voltage across the inductor. When V SENSE
exceeds the current-limit threshold, the high-side
MOSFET turns off and the low-side MOSFET turns on.
This allows for a current foldback feature that reduces
the current-limit threshold during a short circuit. This
makes the current threshold limit, when VOUT = 0V, a
percentage of the current-limit threshold, when VOUT1 is
at its nominal regulated value.
______________________________________________________________________________________
21
MAX8513/MAX8514
PQ1SW = VIN × IOUT1 × fS ×
(QGS
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
To set the current limit and the current-limit foldback
thresholds, first select the foldback current-limit ratio
(PFB). This ratio is the foldback current limit (ILIMIT@0V)
divided by the current limit when VOUT1 equals its nominal regulated voltage (ILIMIT).
I
PFB = LIMIT @0V
ILIMIT
PFB is typically set to 0.5. To calculate the values of
R17 and R18 (in the Typical Applications Circuits), use
the following equations:
R17 =
R18 =
(PFB
× VOUT1 )
4.7µA × (1- PFB )
(7.5 × RCS _ MAX × ILIMIT × (1- PFB )) × R17
VOUT1 - (7.5 × RCS _ MAX × ILIMIT × (1- PFB ))
RCS_MAX is the maximum sensing resistance at the
high operating temperature. R CS can either be the
series resistance of the inductor or a discrete currentsense resistor value. ILIMIT is the peak inductor current
at maximum load, which equals:
 1 + LIR 
IOUT1_ MAX × 

 2 
If R18 results in a negative resistance, then decrease
RCS. This can be done by choosing an inductor with a
lower DC resistance or a lower value discrete currentsense resistor.
Constant Current Limit
For constant current-limit operation, connect ILIM to VL
for a default current-limit threshold of 170mV (typ). The
sensing resistor value must then be chosen so that:
RCS_MAX × ILIMIT < 151mV
the minimum value of the default threshold.
Alternately, the constant current-limit threshold can also
be set by using only R18, in which case R18 is calculated as follows:
C14 of the Typical Applications Circuits). Pick the value
of the filter capacitor, C14, from 0.22µF to 1µF (ceramic
X7R). Then calculate the value of R19 as follows:
R19 =
(
)
RL_DC is the nominal value of the inductor’s DC resistance. Additionally, R20 (in the Typical Applications
Circuits) is added in series with the CSN input to cancel
the drop due to input bias current into CSP that develops across R19. R20 should be set equal to R19.
Compensation Design
The MAX8513/MAX8514 use a voltage-mode control
scheme that regulates the output voltage by comparing
the error-amplifier output (COMP) with a fixed internal
ramp to produce the required duty cycle. The output
lowpass LC filter creates a double pole at the resonant
frequency, which has a gain drop of -40dB/decade and
a phase shift of approximately -180°/decade. The error
amplifier must compensate for this gain drop and
phase shift to achieve a stable high-bandwidth closedloop system.
The basic regulator loop consists of a power modulator,
an output feedback divider, and an error amplifier. The
power modulator has a DC gain set by VIN / VRAMP
(VRAMP = 1VP-P), with a double pole and a single zero
set by the output inductance (L), the output capacitance (COUT) (C4 in the Typical Applications Circuits),
and its equivalent series resistance (RESR). VRAMP is
the peak of the saw-toothed waveform at the input of
the PWM comparator (see the Functional Diagrams in
Figures 1 and 2). Below are equations that define the
power modulator:
GMOD(DC) =
fPMOD =
VIN
VRAMP
1
2π L × COUT
where L is L1A and COUT is C4 in the Typical Applications Circuits.
fZESR =
I
R18 = 7.5 × RCS _ MAX × LIMIT
4.7µA
L1A
2 × RL _ DC × C14
1
2π × COUT × RESR
When using the DC resistance of the inductor as a current-sense resistor, an RC filter is needed (R19 and
22
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
COUT = n × CEACH and
RESR _ EACH
RESR =
n
the -40dB/decade slope of the LC double pole, and the
resultant compensated loop crosses over at the
desired -20dB/decade slope. The error amplifier has a
dominant pole at very low frequency (≈0Hz), and two
separate zeros at:
fZ1 =
Thus the resulting fZESR is the same as that of each
capacitor.
The crossover frequency (fC), which is the frequency
when the closed-loop gain is equal to unity, should be
the smaller of 1/5th the switching frequency or 100kHz
(see the Switching-Frequency Setting section):
f
fC ≤ S or 100kHz
5
The loop-gain equation at the crossover frequency is:
GEA(fc)GMOD(fc) = 1
1
1
and fZ2 =
2π × R3 × C5
2π × (R1+ R4) × C11
and poles at:
1
and fP3 =
2π × R4 × C11
fP2 =
The error-amplifier equivalent circuit and its gain vs.
frequency plot are shown below in Figure 3.
In this case, fZ2 and fP1 are selected to have the converters’ closed-loop crossover frequency, fC, occur when the
error-amplifier gain has a +20dB/decade slope between
fZ2 and fP2. The error-amplifier gain at fC is:
where G EA(fc) is the error-amplifier gain at f C , and
GMOD(fc) is the power modular gain at fC.
The loop compensation is affected by the choice of output-filter capacitor used, due to the position of its ESR
zero frequency with respect to the desired closed-loop
crossover frequency. Ceramic capacitors are used for
higher switching frequencies (above 750kHz) because
of low capacitance and low ESR; therefore, the ESR
zero frequency is higher than the closed-loop crossover
frequency. While electrolytic capacitors (e.g., tantalum,
solid polymer, oscon, etc.) are needed for lower switching frequencies, because of high capacitance and ESR,
the ESR zero frequency is typically lower than the
closed-loop crossover frequency. Thus the compensation design procedure is separated into two cases:
GEA(fc) =
1
GMOD(fc)
The gain of the error amplifier between fZ1 and fZ2 is:
f
fZ2
GEA(fZ1-fZ2) = GEA(fc) Z2 =
fC
fCGMOD(fc)
C12
C11
R4
R3
VOUT1
R1
Case 1: Ceramic Output Capacitor (operating at
high switching frequencies, fZESR > fC)
GAIN
(dB)
C5
EA
R2
The modulator gain at fC is:
f

GMOD(fc) = GMOD(DC)  PMOD 
 fC 
1
 C5 × C12 
2π × R3 × 

 C5 + C12 
COMP
REF
CLOSED-LOOP GAIN
EA GAIN
2
Since the crossover frequency is lower than the output
capacitors’ ESR zero frequency and higher than the LC
double-pole frequency, the error-amplifier gain must
have a +20dB/decade slope at fC. This +20dB/decade
slope of the error amplifier at crossover then adds to
fZ1
fZ2
fP2
fP3
FREQUENCY
fC
Figure 3. Case 1: Error-Amplifier Compensation Circuit (ClosedLoop and Error-Amplifier Gain Plot)
______________________________________________________________________________________
23
MAX8513/MAX8514
When the output capacitance is comprised of paralleling n number of identical capacitors whose values are
CEACH with ESR of RESR_EACH, then:
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
This gain is also set by the ratio of R3/R1 where R1 is
calculated in the OUT1 Voltage Setting section. Thus:
R3 =
R1 × fZ2
fC × GMOD(fc)
Due to the underdamped (Q > 1) nature of the output
LC double pole, the error-amplifier zero frequencies
must be set less than the LC double-pole frequency to
provide adequate phase boost. Set the error-amplifier
first zero, fZ1, at 1/4th the LC double-pole frequency and
the second zero, fZ2, at the LC double-pole frequency.
Hence:
C5 =
2
π × R3 × fPMOD
Set the error-amplifier fP2 at fZESR, and fP3 to 1/2 the
switching frequency, if fZESR < 1/2 fS. If fZESR > 1/2 fS,
then set fP2 at 1/2 fS and fP3 at fZESR.
The gain of the error amplifier between fP2 and fP3 is
set by the ratio of R3/RI and is equal to:
R3
f
= GEA(fZ1-fZ2) P2
RI
fPMOD
where RI is the parallel combination of R1 and R4 and
is equal to:
R1 × R4
RI =
R1 + R4
Below is a numerical example to calculate the erroramplifier compensation values used in the Typical
Applications Circuit of Figure 5:
VIN = 12V (nomimal input voltage)
VRAMP = 1V
VOUT1 = 3.3V
VFB1 = 1.25V
L1A = 1.8µH
C4 = 47µF/ 6.3V ceramic, with RESR = 0.008Ω
fS = 1.4MHz
The LC double-pole frequency is calculated as:
fPMOD =
1
2π L1A × C4
1
2π 1.8 × 10-6 × 47 × 10-6
fZESR =
=
= 17.3kHz
1
=
2π × RESR × C4
1
= 423kHz
2π × 0.008 × 47 × 10-6
Pick R2 = 8.06kΩ.
 3.3V 
R1 = 8.06kΩ × 
- 1 = 13.3kΩ
 1.25V 
The modulator gain at DC is:
Therefore:
R3 × fPMOD
RI =
and
fP2 × GEA(fZ1-fZ2)
R1 × RI
R4 =
R1 - RI
C11 can then be calculated as:
1
C11 =
2π × R4 × fP2
GMOD(DC) =
VIN
VRAMP
= 12
Pick fC = 100kHz.
2
 17.4kHz 
GMOD(fc) = 12 × 
 = 0.363
 100kHz 
GEA(fZ1−fZ2) =
fPMOD
fCGMOD(fC)
17.4kHz
= 0.479
100kHz × 0.363
R3 = R1 × GEA(fZ1−fZ2)
=
and C12 as:
C12 =
24
C5
×
× R3 × fP3 -1)
π
2
C
5
(
= 13.3kΩ × 0.479 = 6.37kΩ
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
MAX8513/MAX8514
Use 6.8kΩ.
C12
2
2
C5 =
=
= 5.38nF
π × R3 × fPMOD
π × 6.8kΩ × 17.4kHz
C11
R4
R1
EA
R2
R3 × fPMOD
6.8kΩ × 17.4kHz
RI =
=
= 583Ω
fP2 × GEA(fZ1-fZ2)
423kHz × 0.479
R1 × RI
13.3kΩ × 583Ω
R4 =
=
= 609Ω
R1 - RI
13.3kΩ - 583Ω
C5
R3
VOUT1
Use 4.7nF.
GAIN
(dB)
VCOMP
VREF
CLOSED-LOOP GAIN
Use 620Ω.
C11 =
EA GAIN
1
1
=
= 607pF
2π × R4 × fP2 2π × 620Ω × 423kHz
Use 680pF.
Pick fP3 = 700kHz, which is the midpoint between fZESR
and 1/2 the switching frequency.
C5
(2π × C5 × R3 × fP3 ) -1
4.7nF
=
= 33.7pF
(2π × 4.7nF × 6.8kΩ × 700kHz) -1
fZ1
fZ2
fP2
fC
fP3
FREQUENCY
Figure 4. Case 2: Error-Amplifier Compensation Circuit (ClosedLoop and Error-Amplifier Gain Plot)
C12 =
Use 33pF.
Case 2: Electrolytic Output Capacitor (operating at
lower switching frequencies, fZESR < fC )
The modulator gain at fC is:
2
f
GMOD(fc) = GMOD(DC) PMOD
fZESRfC
The output capacitor’s ESR zero frequency is higher
than the LC double-pole frequency but lower than the
closed-loop crossover frequency. Here the modulator
already has a -20dB/decade slope; therefore, the erroramplifier gain must have a 0dB/decade slope at fC, so
the loop crosses over at the desired -20dB/decade
slope. The error-amplifier circuit configuration is the
same as Case 1; however, the closed-loop crossover
frequency is now between fP2 and fP3, as illustrated in
Figure 4.
The equations that define the error amplifier’s poles
and zeroes (fZ1, fZ2, fP2, and fP3) are the same as for
Case 1. However, fP2 is now lower than the closed-loop
crossover frequency.
The error-amplifier gain at fC is:
GEA(fc) =
1
GMOD(fc)
And the gain of the error amplifier between fZ1 and
fZ2 is:
f
fZ2
GEA(fZ1−fZ2) = GEA(fc) Z2 =
fP2
fP2GMOD(fc)
Due to the underdamped (Q > 1) nature of the output LC
double pole, the error-amplifier zero frequencies must be
set less than the LC double-pole frequency to provide
adequate phase boost. Set the first zero of the error
amplifier, fZ1, at 1/4th the LC double-pole frequency. Set
the second zero, fZ2, at the LC double-pole frequency.
Set the second pole, fP2, at fZESR.
______________________________________________________________________________________
25
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
This gain between fZ1 and fZ2 is also set by the ratio of
R3/R1, where R1 is selected in the OUT1 Voltage
Setting section. Therefore:
R3 =
R1 × fPMOD
fZESR × GMOD(fc)
And similar to Case 1, C5 can be calculated as:
C5 =
fPMOD =
=
fZESR =
2
π × R3 × fPMOD
=
1
2π L1A × C4
1
2π 6.2µH × 560µF
= 2.7kHz
1
2πRESR × C4
1
= 18.95kHz
2π × 0.015Ω × 560µF
Pick R2 = 8.06kΩ. Then:
Set the error-amplifier third pole, fP3, at approximately
1/2 the switching frequency. The gain of the error
amplifier at fC (between fP2 and fP3) is set by the ratio
of R3/RI and is also equal to:
GEA(fc) =
1
GMOD(fc)
where RI is:
3.3V
- 1 = 13.3kΩ
1.25V
VIN
= 12
GMOD(DC) =
VRAMP
R1 = 8.06kΩ ×
Pick fC = 50kHz, which is less than fS / 5.
2.7kHz2
= 0.0923
18.95kHz × 50kHz
fPMOD
GEA(fZ1−fZ2) =
fZESRGMOD(fc)
GMOD(DC) = 12 ×
RI =
R1 × R4
R1 + R4
Therefore:
2.7kHz
= 1.543
18.95kHz × 0.0923
R3 = R1 × GEA(fZ1-fZ2) = 13.3kΩ × 1.543 = 20.48kΩ
=
RI = R3 × GMOD(fc) × GD
Similar to Case 1, R4, C11, and C12 can be calculated as:
R1 × RI
R1 - RI
1
C11 =
2π × R4 × fZESR
C5
C12 =
2π × C5 × R3 × fP3 - 1
R4 =
Below is a numerical example to calculate the erroramplifier compensation values for Case 2:
VIN = 12V (nomimal input voltage)
VRAMP = 1V
VOUT1 = 3.3V
VFB1 = 1.25V
L1A = 6.2µH
C4 = 560µF/ 10V OS-Con capacitor, with ESR = 0.015Ω
Use 20kΩ.
2
2
=
= 11.8nF
π × R3 × fPMOD π × 20kΩ × 2.7kHz
C5 =
Use 12nF.
RI = R3 × GMOD(fc) = 20kΩ × 0.0923 = 1.846kΩ
R4 =
R1× RI 13.3kΩ × 1.846kΩ
=
= 2.14kΩ
R1- RI 13.3kΩ - 1.846kΩ
Use 2.2kΩ.
C11 =
1
1
=
= 3.82nF
2π × R4 × fZESR 2π × 2.2kΩ × 18.95kHz
Use 3.9nF.
Pick fP3 = fS / 2 = 150kHz.
fS = 300kHz
26
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
Use 47pF.
Linear-Regulator Controllers
OUT2 Voltage Selection
The MAX8513/MAX8514 OUT2 positive linear regulator’s output voltage is set by connecting a resistivedivider from OUT2 to FB2 to GND. The resistors in the
divider are selected to set the minimum output current
(IOUT2_MIN). For the Typical Applications Circuit (Figure
5 or Figure 6), the feedback resistors are set to R5 =
340Ω and R6 = 160Ω, where R5 is the resistor from
OUT2 to FB2 and R6 is the resistor from FB2 to GND.
These values set the minimum output current to
≈4.5mA, which works well with many MOSFETS.
In general,
IOUT2 _ MIN =
IOUT2 _ MAX
the feedback resistors (R5 and R6) set the output-voltage reference point as well as the minimum load.
The loop gain for the positive LDO output using an
NMOS transistor is:
0.8V
×
VOUT2
GC2 (1 + sCA × RA )
 sCOUT2 
s(CA + Cq)1+
(1+ sRA × Cq)
gC 

where COUT2 is C6 in the Typical Applications Circuits.
GC2 is the transconductance of the internal amplifier
(0.21S typ), and a dominant pole at a low frequency is
created from this transconductance and the compensation capacitor (CA in the Typical Applications Circuits
+ Q3’s gate capacitance (Cq)). A second pole occurs
due to COUT2 and the transconductance of Q3 (gC).
This transconductance varies from a minimum gC(MIN)
occurring at minimum load to a maximum g C(MAX)
occurring at maximum load. To calculate the gC at any
load current, the typical forward transconductance can
be extracted from the MOSFET’s data sheet (gfs), as
well as the current at which it is measured (IDfs). The
gC(MIN) and gC(MAX) can be calculated as:
333
gC(MAX) = gfs
Select R5 and R6 so:
0.8V
= IOUT2 _ MIN
R6
gC(MIN) = gfs
IOUT2(MAX)
IDfs
IOUT2(MIN)
IDfs
Poles occur at:
V

R5 = R6 ×  OUT2 - 1
 0.8V

OUT2 Stability
A transconductance amplifier drives the gate of the
NMOS transistor (Q3 in the Typical Applications
Circuits), with current proportional to the error signal
multiplied by the amplifier’s transconductance. The
error signal is the difference between VFB2 and the
internal 0.8V reference. VSUP2, the supply voltage for
the transconductance amplifier, must be at least 1V
greater than the maximum required gate voltage
(VDRV2). The output pass transistor (Q3) buffers the
DRV2 signal to produce the desired output voltage
(V OUT2 ). The output capacitor (C6 in the Typical
Applications Circuits) helps bypass the output, while
fPMAX =
gC(MAX)
2π × COUT2
gC(MIN)
and fPMIN =
2π × COUT2
If only a minimum gfs is given, initially assume the maximum is twice the minimum.
When using a bipolar transistor, the g C(MAX) and
gC(MIN) occur at the following:
I
gC(MIN) = OUT2MIN
VT
IOUT2MAX
gC(MAX) =
VT
where VT is the thermal voltage, 26mV.
______________________________________________________________________________________
27
MAX8513/MAX8514
C5
(2π × C5 × R3 × fP3 ) - 1
12nF
=
= 53.3pF
2π × 12nF × 20kΩ × 150kHz - 1
C12 =
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
A third pole occurs due to the input capacitance of the
NMOS transistor’s gate, C q (C iss from the MOSFET
data sheet), and the compensation resistor (RA). If an
NPN bipolar transistor is used instead, this third pole
can be calculated from the base capacitance (Cq =
CIBO from the NPN data sheet). To ensure stability, a
zero is added to the loop from the resistor (RA) and
capacitor (CA).
For good stability and transient response, first pick
COUT2 at approximately 6.8µF/A of load current. For the
Typical Applications Circuit, COUT2 is a 10µF ceramic
capacitor. Ensure that the zero formed from the ESR of
COUT2 is greater than the maximum bandwidth BWMAX
(calculated below). The maximum bandwidth should
also be less than the pole created by Q3’s gate capacitance (Cq) and the compensation resistor (RA).
1
 1

 1.3 × 2π × C R ,

G C

BWMAX = MIN
 1

1
×


×
R
C
π
2
ESR _ COUT2 OUT 
 10
The following equations set the compensation zero a
decade and a half below the maximum load pole and
ensure the above constraint is met. Choose the larger
of the two values for CA.

8 × VOUT × COUT × Cq × GC2 × gC(MAX) ×


gC(MAX) × RESR _ COUT2 + 1

13
×
,

gC(MAX) VOUT2 + IOUT2(MAX)

CA = MAX

GC2 × gC(MAX)

×
16 10 ×
gC(MAX) VOUT2 + IOUT2(MAX)

R
 ESR _ COUT2 COUT − Cq
(
)
(
)
V
C
RA = 10 10 × OUT2 OUT2 ×
CA
(gC(MAX) × RESR _ COUT2 + 1)
(gC(MAX)VOUT2 + IOUT2(MAX) )
MOSFET Transistor Selection
MAX8513/MAX8514s’ OUT2 uses N-channel MOSFETs
as the series pass transistor to improve efficiency for
high output current by not requiring a large amount of
28
drive current. The selected MOSFET must have the gate
threshold voltage meet the following criteria:
VGS _ MAX ≤ VDRV 2 - VOUT2
where V DRV2 is equal to 7.75V or V SUP2 - 1.5V
(whichever is less), and VGSMAX is the maximum gate
voltage required to yield the on-resistance specified by
the manufacturer’s data sheet. Logic-gate MOSFETs
are recommended.
NPN-Transistor Selection
The MAX8513/MAX8514s’ OUT2 can use a less expensive NPN transistor as the series pass transistor. In
selecting the appropriate NPN transistor, make sure the
beta is large enough so the regulator can provide
enough base current. The minimum beta of the transistor is:
β(MIN) =
IOUT2(MAX)
4mA
In addition, to avoid premature dropout, V CE_SAT ≤
VIN_MIN - VOUT2.
OUT3_ Transistor Selection
The pass transistors must meet specifications for current gain (β), input capacitance, collector-emitter saturation voltage, and power dissipation. The transistor’s
current gain limits the guaranteed maximum output current to:
V 

IOUT3P =  IDRV 3P _ MIN - - BE  β

R12 
where IDRV3P_MIN is the minimum base-drive current
and R12 is the pullup resistor connected between the
transistor’s base and emitter (see the Typical
Applications Circuits). In addition, to avoid premature
dropout VCE_SAT ≤ VIN_MIN - VOUT3. Furthermore, the
transistor’s current gain increases the linear regulator’s
DC loop gain (see the Stability Requirements section),
so excessive gain destabilizes the output. Therefore,
transistors with current gain over 100 at the maximum
output current, such as Darlington transistors, are not
recommended. The transistor’s input capacitance and
input resistance also create a second pole, which could
be low enough to destabilize the LDO when the output
is heavily loaded.
The transistor’s saturation voltage at the maximum output
current determines the minimum input-to-output voltage
differential that the linear regulator supports. Alternately,
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
When the MAX8513/MAX8514 are disabled, R26 discharges C7.
transistor’s specifications, the base-emitter resistor,
and the output capacitor determine the loop stability.
The total DC loop gain (AV) is the product of the gains
of the internal transconductance amplifier, the gain
from base to collector of the pass transistor (Q4 in the
Typical Applications Circuits), and the gain of the feedback divider.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base current. Its DC gain is approximately:
OUT3P Voltage Selection (PNP)
The MAX8513 positive linear-regulator output voltage,
VOUT3P, is set with a resistive-divider from OUT3P to
FB3P to GND. First, select R14 resistance value (below
1kΩ). Then, solve for R13 so:
GC3 _ × RIN || R12
where G C3_ is typically 0.6S (OUT3P) and 0.36S
(OUT3N), RIN is the input resistance of Q4, and can be
calculated by:
V

R13 = R14 OUT3P -1
 0.8V

where VOUT3P can range from +0.8V to +27V.
OUT3N Voltage Selection (NPN)
The MAX8514’s negative linear-regulator output voltage, VOUT3N, is a negative regulated voltage developed through the pass transistor Q4 (MAX8514 Typical
Applications Circuits). A resistive-divider from OUT3N
to FB3N to V REF3N forces V FB3N to regulate to 0V.
Calculate VOUT3N by first selecting R14 the resistor
from VREF3N to FB3N to be below 5kΩ, where VREF3N
is any positive voltage (usually VOUT1). R13 is then calculated by:
R13 =
 26mV
RIN = 
 IOUT3 _
The DC gain for the transistor (Q4), including the feedback divider, is approximately:
VREF
for OUT3P or
VT
VOUT3N × VREF3N
A Q4N =
(VREF3N - VOUT3N ) × VT
A Q4P =
VT is the thermal voltage for the transistor (typically 26mV
at TA = +27°C). The total DC loop gain for OUT3_ is:
(
-VOUT3N
× R14
VREF3N
SUP3N is the supply input for OUT3N’s transconductance amplifier. When OUT3N is used, SUP3N must be
connected to a voltage supply between 1.5V and 5.5V
that can source at least 25mA. Typically, VOUT1 can be
used as the supply input for SUP3N.
Stability Requirements
The MAX8513/MAX8514s’ DRV3P and DRV3N outputs
are designed to drive bipolar transistors (PNP types for
the MAX8513 with the DRV3P output, and NPN types
for the MAX8514 with the DRV3N output). These bipolar
transistors form linear regulators with positive outputs
(MAX8513 from 0.8V to 27V) and negative outputs
(MAX8514 from -18V to -1V). An internal transconductance amplifier is used to drive the external pass transistors. The transconductance amplifier, pass

β

)
A V = GC3 _ × RIN || R12 × A Q4 _
A dominant pole (fPOLE1) is created from the output
capacitance and load resistance:
fPOLE1 =
IOUT3 _ MAX
1
=
2π × COUT3 × ROUT3 2π × COUT3 × VOUT3 _
Unity-gain crossover (fC_OUT3_) should occur at:
fC _ OUT3 _ = A V × fPOLE1
A second pole is set by the input capacitance to the
base of Q4 (C Q4IN ), any external base-to-emitter
capacitance (CBE, see the Base-Drive Noise Reduction
section and Figure 7), the transistor’s input resistance
(RIN), and the base-to-emitter pullup resistor (R12):
______________________________________________________________________________________
29
MAX8513/MAX8514
the package’s power dissipation could limit the useable
maximum input-to-output voltage differential.
The maximum power-dissipation capability of the transistor’s package and mounting must allow the actual
power dissipation in the device without exceeding the
maximum junction temperature. The power dissipated
equals the maximum load current multiplied by the
maximum input-to-output voltage differential.
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
fPOLE2 =
1
2π(CBE + CQ4IN ) × RIN || R12
If the second pole occurs well after unity-gain
crossover, the linear regulator remains stable. If not,
then increase the output capacitance COUT3 (C8 in the
Typical Applications Circuits) so:
fPOLE2 > 2 × fC _ OUT3 _
If high-ESR capacitors are used for the output capacitor (COUT3), then cancel the ESR zero with a pole at
FB3_. This is accomplished by adding a capacitor
(CFB3_) from FB3_ to GND so:
CFB3 _ =
1
2π × R3 || R4 × fESR
OUT3_ Output Capacitors
Connect at least a 1µF capacitor between the linear regulator’s output and ground, as close to the MAX8513/
MAX8514 and the external pass transistors as possible.
Depending on the selected pass transistor, larger capacitor values may be required for stability (see the Stability
Requirements section). Once the minimum capacitor
value for stability is determined, verify that the linear regulator’s output does not contain excessive noise. Although
adequate for stability, small capacitor values can provide
too much bandwidth, making the linear regulator sensitive
to noise. Larger capacitor values reduce the bandwidth,
thereby reducing the regulator’s noise sensitivity. For the
negative linear regulator, if noise on the ground reference
causes the design to be marginally stable, bypass the
negative output back to its reference voltage (VREF3N,
Figure 6). This technique reduces the differential noise on
the output. Ensure the voltage rating of the capacitor
exceeds the output voltage.
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to system
noise, especially when the linear regulator is lightly
loaded. Capacitively coupled switching noise or inductively coupled EMI on the base drive causes fluctuations
in the base current, which appear as noise on the linear
regulator’s output. To avoid this, keep the base-drive
traces away from the step-down converter and as short
as possible to minimize noise coupling. Resistors in
series with the gate drivers (DH and DL) reduce the LX
switching noise generated by the step-down converter.
Additionally, a bypass capacitor (CBE) can be placed
across the base-to-emitter resistor (Figure 7). This bypass
capacitor, in addition to the transistor’s input capaci30
tance, reduces the frequency of the second pole (fPOLE2)
that could destabilize the linear regulator (see the Stability
Requirements section). Therefore, the stability requirements determine the maximum base-to-emitter capacitance (CBE) that can be added.
Transformer Selection
In systems where the step-down controller’s output
(OUT1) is not the highest voltage, a transformer can be
used to provide additional post-regulated, high-voltage
outputs. The transformer generates unregulated highvoltage supplies that power the positive and negative
linear regulators. These unregulated supply voltages
must be high enough to keep the pass transistors from
saturating. For positive output voltages, connect the
transformer as shown in the Typical Applications
Circuits where the minimum turns ratio (n2/n1) is determined by:
VOUT3 _ + VQ4(SAT) + VD2
n2
≥
n1
VOUT1
where VQ4(SAT) is OUT3P’s pass transistor’s saturation
voltage under full load. Since power transfer occurs
when the low-side MOSFET is on (DL = high), the transformer cannot support heavy loads with high duty
cycles on VOUT1.
Minimum Load Requirements
(Linear Regulators)
Under no-load conditions, leakage currents from the
pass transistors supply the output capacitor, even
when the transistor is off. Generally, this is not a problem since the feedback resistors’ current drains the
excess charge. However, charge can build up on the
output capacitor over temperature, making VOUT2/3 rise
above its set point. Care must be taken to ensure the
feedback resistors’ current exceeds the pass transistor’s leakage current over the entire temperature range.
Thermal Consideration
The power dissipated by the series pass transistor is
calculated by:
PD =
(| VIN - VOUT2 / 3 |) × IOUT2 / 3
where VIN is the input to the transistor of the LDO and
the absolute value of the difference between VIN and
VOUT2/3 is taken. VIN is derived from the transformer
winding ratio. The transistor must be adequately heat
sunk to prevent a thermal runaway condition. Refer to
the transistor data sheet for thermal calculation.
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
C1
1µF
R15
10Ω
C10
2.2µF
IN
R10
68.1kΩ
C2
10µF
D1
100mA, 30V
(CMOSH-3)
PVL
VL
BST
SUP2
PFI
C20
30V, 5.5A DUAL N-CHANNEL
1000pF
(FDS6984S)
Q1
DH
R11
12.4kΩ
EN/SYNC
C3
0.1µF
R25
5.1Ω
L1A
LX
C5
R3
6.8kΩ 4.7nF
R19
200Ω
Q2
FB1
C4
47µF
R20
200Ω
R1
13.3kΩ
DL
COMP1
C12
33pF
C14
CSP 0.47µF
PGND
R7
10.7kΩ
DRV2
R5
340Ω
MAX8513
Q3
30V, 23A
N-CHANNEL
MOSFET
(IRLR2703)
FB2
GND
C13
0.1µF
RA
100Ω
SEQ
SS
R6
160Ω
CA
0.68µF
R8
100kΩ
R9
100kΩ
PFO
POR
R12
1kΩ
L1B
R18
66.5kΩ
ILIM
DRV3P
R13
11.3kΩ
CSP
VOUT2
2.5V, 1.5A
PFO
VOUT1
CSN
C6
10µF
POR
R17
665kΩ
VOUT1
3.3V, 2A
R2
8.06kΩ
IC1
REF
C11
680pF
R4
620Ω
CSN
FB1
FREQ
C9
0.1µF
COUPLED INDUCTOR
L1A = 1.8µH, 4.5A/0.01Ω
n2/n1 = 20:6
(COILTRONICS, CTX 03-16101)
FB3P
R14
806Ω
R26
Q4 1.5kΩ
40V, 200mA
PNP
(MMBT3906)
C7
1µF
C8
1µF
D2
CMPD4448
VOUT3P
12V, 50mA
C22
1000pF
CSN
CSP
Figure 5. MAX8513 Typical Applications Circuit
______________________________________________________________________________________
31
MAX8513/MAX8514
VIN
MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
VIN 9V to 16V
C1
1µF
R15
10Ω
C10
2.2µF
IN
R10
68.1kΩ
C2
10µF
D1
100mA, 30V
(CMOSH-3)
PVL
VL
BST
SUP2
PFI
EN/SYNC
C3
0.1µF
R25
5.1Ω
R19
200Ω
Q2
C12
33pF
C14
CSP 0.47µF
PGND
R7
10.7kΩ
R1
13.3kΩ
CSN
R2
8.06kΩ
FB1
FREQ
IC1
DRV2
R5
1.74kΩ
MAX8514
REF
Q3
30V, 23A
N-CHANNEL
MOSFET
(IRLR2703)
FB2
GND
C13
0.1µF
C4
47µF
R20
200Ω
DL
COMP1
C9
0.1µF
COUPLED INDUCTOR
L1A = 1.8µH, 4.5A/0.01Ω
L1A
LX
C5
R3
6.8kΩ 4.7nF
FB1
30V, 5.5A DUAL N-CHANNEL
C20
(FDS6984S)
1000pF
Q1
DH
R11
12.4kΩ
RA
100Ω
SEQ
SS
R17
665kΩ
CA
0.68µF
R6
806Ω
PFO
PFO
POR
VOUT1
R12
1kΩ
L1B
R18
66.5kΩ
ILIM
DRV3P
R13
12.1kΩ
R26
Q4 1.5kΩ
40V, 200mA
NPN
(MMBT3904)
FB3P
CSP
C22
1000pF
CSN
R9
100kΩ
VOUT2
2.5V, 1.5A
POR
SUP3N
CSN
R8
100kΩ
C6
10µF
C7
1µF
C8
1µF
R14
3.31kΩ
D2
CMPD4448
VOUT3P
12V, 50mA
VREF3N
CSP
Figure 6. MAX8514 Typical Applications Circuit
32
______________________________________________________________________________________
C11
680pF
R4
620Ω
VOUT1
3.3V, 2A
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
MAX8513/MAX8514
VOUT1
L1B
C7
MAX8513
CBE
R12
DRV3P
Q4
R13
VOUT3P
FB3P
C8
R14
a) POSITIVE OUTPUT VOLTAGE
VOUT1
SUP3N
R14
VOUT1
FB3N
R13
VOUT3N
C8
DRV3N
Q4
C BE
R12
L1B
MAX8514
b) NEGATIVE OUTPUT VOLTAGE
C7
Figure 7. Base-Drive Noise Reduction
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention.
Follow these guidelines for good PC board layout:
Place decoupling capacitors as close to the IC pins as
possible. Keep separate the power-ground plane (connect to the sources of the low-side MOSFET, PGND,
and the output capacitor’s return). Connect the input
decoupling capacitors across the drain of the high-side
MOSFETs and the source of the low-side MOSFETs.
The signal-ground plane (connected to GND) is connected to the rest of the circuit-ground return. The two
ground planes then connect together with a single con-
nection at the IC. Keep the high-current paths as short
as possible. Connect the drains of the MOSFETS to a
large copper area to help in cooling the devices, further
improving efficiency and long-term reliability.
1) Ensure all feedback connections are short and
direct. Place the feedback resistors as close to the
IC as possible.
2) Route high-speed switching nodes away from sensitive analog areas (FB_, COMP, ILIM).
3) Ensure the current-sense paths for CSP and CSN
run parallel and close together to cancel any noise
pickup.
4) A reference PC board layout included in the
MAX8513 evaluation kit is also provided to further
aid layout.
______________________________________________________________________________________
33
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
MAX8513/MAX8514
Pin Configurations
TOP VIEW
PFI 1
28 SS
PFI 1
28 SS
PFO 2
27 CSN
PFO 2
27 CSN
DH 3
26 CSP
DH 3
26 CSP
LX 4
25 ILIM
LX 4
25 ILIM
BST 5
24 FB3P
BST 5
DL 6
MAX8513
PVL 7
23 POR
22 IN
PGND 8
21 DRV3P
VL 9
20 N.C.
COMP1 10
19 SYNC/EN
DL 6
24 FB3N
MAX8514
PVL 7
23 POR
22 IN
PGND 8
21 DRV3N
VL 9
20 SUP3N
COMP1 10
19 SYNC/EN
FB1 11
18 SEQ
FB1 11
18 SEQ
FREQ 12
17 SUP2
FREQ 12
17 SUP2
REF 13
16 DRV2
REF 13
16 DRV2
GND 14
15 FB2
GND 14
15 FB2
28 QSOP
28 QSOP
Chip Information
TRANSISTOR COUNT: 4824
PROCESS: BiCMOS
34
______________________________________________________________________________________
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX8513/MAX8514
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)