8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP AD7908/AD7918/AD7928 FUNCTIONAL BLOCK DIAGRAM FEATURES Fast throughput rate: 1 MSPS Specified for AVDD of 2.7 V to 5.25 V Low power 6.0 mW max at 1 MSPS with 3 V supply 13.5 mW max at 1 MSPS with 5 V supply Eight (single-ended) inputs with sequencer Wide input bandwidth AD7928, 70 dB min SINAD at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®/QSPI™/ MICROWIRE™/DSP compatible Shutdown mode: 0.5 μA max 20-lead TSSOP package Qualified for automotive applications AVDD REFIN VIN0 • • • • • • • • • • • • • T/H 8-/10-/12-BIT SUCCESSIVE APPROXIMATION ADC I/P MUX VIN7 SCLK CONTROL LOGIC SEQUENCER DOUT DIN CS VDRIVE GENERAL DESCRIPTION GND The AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 8-channel, successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz. The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7908/AD7918/AD7928 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7908/AD7918/AD7928 consume 2 mA maximum with 3 V supplies; with 5 V supplies, the current consumption is 2.7 mA maximum. Through the configuration of the control register, the analog input range for the part can be selected as 0 V to REFIN or 0 V to 2 × REFIN, with either straight binary or twos complement output coding. The AD7908/AD7918/AD7928 each feature eight singleended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. The conversion time for the AD7908/AD7918/AD7928 is determined by the SCLK frequency, which is also used as the master clock to control the conversion. 03089-001 AD7908/AD7918/AD7928 Figure 1. PRODUCT HIGHLIGHTS 1. High Throughput with Low Power Consumption. The AD7908/ AD7918/AD7928 offer up to 1 MSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7908/ AD7918/AD7928 dissipate just 6 mW of power maximum. 2. Eight Single-Ended Inputs with a Channel Sequencer. A sequence of channels can be selected, through which the ADC cycles and converts on. 3. Single-Supply Operation with VDRIVE Function. The AD7908/ AD7918/AD7928 operate from a single 2.7 V to 5.25 V supply. The VDRIVE function allows the serial interface to connect directly to either 3 V or 5 V processor systems independent of AVDD. 4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The parts also feature various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 μA max when in full shutdown. 5. No Pipeline Delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved. AD7908/AD7918/AD7928 TABLE OF CONTENTS Features .............................................................................................. 1 Control Register.............................................................................. 15 General Description ......................................................................... 1 Sequencer Operation ................................................................. 16 Functional Block Diagram .............................................................. 1 SHADOW Register .................................................................... 17 Product Highlights ........................................................................... 1 Circuit Information.................................................................... 18 Revision History ............................................................................... 2 Converter Operation.................................................................. 18 Specifications..................................................................................... 3 ADC Transfer Function............................................................. 19 AD7908 Specifications................................................................. 3 Handling Bipolar Input Signals ................................................ 19 AD7918 Specifications................................................................. 5 Typical Connection Diagram ................................................... 19 AD7928 Specifications................................................................. 7 Modes of Operation ................................................................... 21 Timing Specifications .................................................................. 9 Power vs. Throughput Rate....................................................... 23 Absolute Maximum Ratings.......................................................... 10 Serial Interface ............................................................................ 23 ESD Caution................................................................................ 10 Microprocessor Interfacing....................................................... 24 Pin Configuration and Function Descriptions........................... 11 Application Hints ....................................................................... 27 Terminology .................................................................................... 12 Outline Dimensions ....................................................................... 28 Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 29 Performance Curves................................................................... 13 Automotive Products ................................................................. 29 REVISION HISTORY 12/10—Rev. C to Rev. D Changes to Features Section............................................................ 1 Added Automotive SINAD and SNR Parameters (Table 1)........ 3 Added Automotive SINAD and SNR Parameters (Table 2)........ 5 Added Automotive SINAD and SNR Parameters (Table 3)........ 7 Added Automotive Temperature Range (Table 5) ....................... 7 Added Automotive Products Section .......................................... 28 Changes to Ordering Guide .......................................................... 28 6/06—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Reference Section....................................................... 21 9/03—Rev. 0 to Rev. A Changes to Figure 3........................................................................ 15 Changes to Reference section ....................................................... 18 11/08—Rev. B to Rev. C Changes to ESD Parameter, Table 5 ............................................. 10 Rev. D | Page 2 of 32 AD7908/AD7918/AD7928 SPECIFICATIONS AD7908 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY2 Resolution Integral Nonlinearity Differential Nonlinearity 0 V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 × REFIN Input Range B Version 1 Unit 49 48.5 49 48.5 −66 −64 dB min dB min dB min dB min dB max dB max −90 −90 10 50 −85 8.2 1.6 dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ 8 ±0.2 ±0.2 Bits LSB max LSB max ±0.5 ±0.05 ±0.2 ±0.05 LSB max LSB max LSB max LSB max Test Conditions/Comments fIN = 50 kHz sine wave, fSCLK = 20 MHz B models W models B models W models fa = 40.1 kHz, fb = 41.5 kHz fIN = 400 kHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 8 bits Straight binary output coding −REFIN to +REFIN biased about REFIN with twos complement output coding Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Ranges ±0.2 ±0.05 ±0.5 ±0.1 ±0.2 ±0.05 LSB max LSB max LSB max LSB max LSB max LSB max 0 to REFIN 0 to 2 × REFIN V V DC Leakage Current Input Capacitance REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 3 ±1 20 μA max pF typ 2.5 ±1 36 V μA max kΩ typ 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max μA max pF max Rev. D | Page 3 of 32 RANGE bit set to 1 RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V ±1% specified performance fSAMPLE = 1 MSPS Typically 10 nA, VIN = 0 V or VDRIVE AD7908/AD7918/AD7928 Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVDD VDRIVE IDD 4 Normal Mode (Static) Normal Mode (Operational) Using Auto Shutdown Mode Full Shutdown Mode Power Dissipation4 Normal Mode (Operational) Auto Shutdown Mode (Static) Full Shutdown Mode B Version 1 Unit Test Conditions/Comments VDRIVE − 0.2 V min 0.4 V max ±1 μA max 10 pF max Straight (natural) binary Twos complement ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V ISINK = 200 μA 800 300 300 1 ns max ns max ns max MSPS max 16 SCLK cycles with SCLK at 20 MHz Sine wave input Full-scale step input See Serial Interface section 2.7/5.25 2.7/5.25 V min/max V min/max 600 2.7 2 960 0.5 0.5 μA typ mA max mA max μA typ μA max μA max Digital inputs = 0 V or VDRIVE AVDD = 2.7 V to 5.25 V, SCLK On or Off AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz fSAMPLE = 250 kSPS (Static) SCLK on or off (20 nA typ) 13.5 6 2.5 1.5 2.5 1.5 mW max mW max μW max μW max μW max μW max AVDD = 5 V, fSCLK = 20 MHz AVDD = 3 V, fSCLK = 20 MHz AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V 1 Temperature ranges as follows: B version: −40°C to +85°C. See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. 2 Rev. D | Page 4 of 32 Coding bit set to 1 Coding bit set to 0 AD7908/AD7918/AD7928 AD7918 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY2 Resolution Integral Nonlinearity Differential Nonlinearity 0 V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 × REFIN Input Range Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 3 B Version 1 Unit 61 60.5 61 60.5 −72 −74 dB min dB min dB min dB min dB max dB max −90 −90 10 50 −85 8.2 1.6 dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ 10 ±0.5 ±0.5 Bits LSB max LSB max ±2 ±0.2 ±0.5 ±0.2 LSB max LSB max LSB max LSB max Test Conditions/Comments fIN = 50 kHz sine wave, fSCLK = 20 MHz B models W models B models W models fa = 40.1 kHz, fb = 41.5 kHz fIN = 400 kHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 10 bits Straight binary output coding −REFIN to +REFIN biased about REFIN with twos complement output coding ±0.5 ±0.2 ±2 ±0.2 ±0.5 ±0.2 LSB max LSB max LSB max LSB max LSB max LSB max 0 to REFIN 0 to 2 × REFIN ±1 20 V V μA max pF typ RANGE bit set to 1 RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V 2.5 ±1 36 V μA max kΩ typ ±1% specified performance 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max μA max pF max Rev. D | Page 5 of 32 fSAMPLE = 1 MSPS Typically 10 nA, VIN = 0 V or VDRIVE AD7908/AD7918/AD7928 Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVDD VDRIVE IDD 4 Normal Mode (Static) Normal Mode (Operational) Using Auto Shutdown Mode Full Shutdown Mode Power Dissipation4 Normal Mode (Operational) Auto Shutdown Mode (Static) Full Shutdown Mode B Version 1 Unit Test Conditions/Comments VDRIVE − 0.2 V min 0.4 V max ±1 μA max 10 pF max Straight (natural) binary Twos complement ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V ISINK = 200 μA 800 300 300 1 ns max ns max ns max MSPS max 16 SCLK cycles with SCLK at 20 MHz Sine wave input Full-scale step input See Serial Interface section 2.7/5.25 2.7/5.25 V min/max V min/max 600 2.7 2 960 0.5 0.5 μA typ mA max mA max μA typ μA max μA max Digital inputs = 0 V or VDRIVE AVDD = 2.7 V to 5.25 V, SCLK on or off AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz fSAMPLE = 250 kSPS (Static) SCLK on or off (20 nA typ) 13.5 6 2.5 1.5 2.5 1.5 mW max mW max μW max μW max μW max μW max AVDD = 5 V, fSCLK = 20 MHz AVDD = 3 V, fSCLK = 20 MHz AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V 1 Temperature ranges as follows: B version: –40°C to +85°C. See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. 2 Rev. D | Page 6 of 32 Coding bit set to 1 Coding bit set to 0 AD7908/AD7918/AD7928 AD7928 SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY2 Resolution Integral Nonlinearity Differential Nonlinearity 0 V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 × REFIN Input Range Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 3 B Version 1 Unit 70 69.5 69 70 69.5 −77 −73 −78 −76 dB min dB min dB min dB min dB min dB max dB max dB max dB max −90 −90 10 50 −85 8.2 1.6 dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ 12 ±1 −0.9/+1.5 Bits LSB max LSB max ±8 ±0.5 ±1.5 ±0.5 LSB max LSB max LSB max LSB max Test Conditions/Comments fIN = 50 kHz sine wave, fSCLK = 20 MHz @ 5 V, B models @ 5 V, W models @ 3 V typically 70 dB B models W models @ 5 V typically −84 dB @ 3 V typically −77 dB @ 5 V typically −86 dB @ 3 V typically −80 dB fa = 40.1 kHz, fb = 41.5 kHz fIN = 400 kHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 12 bits Straight binary output coding Typically ±0.5 LSB −REFIN to +REFIN biased about REFIN with twos complement output coding ±1.5 ±0.5 ±8 ±0.5 ±1 ±0.5 LSB max LSB max LSB max LSB max LSB max LSB max 0 to REFIN 0 to 2 × REFIN ±1 20 V V μA max pF typ RANGE bit set to 1 RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V 2.5 ±1 36 V μA max kΩ typ ±1% specified performance 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max μA max pF max Rev. D | Page 7 of 32 Typically ±0.8 LSB fSAMPLE = 1 MSPS Typically 10 nA, VIN = 0 V or VDRIVE AD7908/AD7918/AD7928 Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVDD VDRIVE IDD 4 Normal Mode (Static) Normal Mode (Operational) Using Auto Shutdown Mode Full Shutdown Mode Power Dissipation4 Normal Mode (Operational) Auto Shutdown Mode (Static) Full Shutdown Mode B Version 1 Unit Test Conditions/Comments VDRIVE − 0.2 V min 0.4 V max ±1 μA max 10 pF max Straight (natural) binary Twos complement ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V ISINK = 200 μA 800 300 300 1 ns max ns max ns max MSPS max 16 SCLK cycles with SCLK at 20 MHz Sine wave input Full-scale step input See Serial Interface section 2.7/5.25 2.7/5.25 V min/max V min/max 600 2.7 2 960 0.5 0.5 μA typ mA max mA max μA typ μA max μA max Digital inputs = 0 V or VDRIVE AVDD = 2.7 V to 5.25 V, SCLK on or off AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz fSAMPLE = 250 kSPS (Static) SCLK on or off (20 nA typ) 13.5 6 2.5 1.5 2.5 1.5 mW max mW max μW max μW max μW max μW max AVDD = 5 V, fSCLK = 20 MHz AVDD = 3 V, fSCLK = 20 MHz AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V 1 Temperature ranges as follows: B Version: −40°C to +85°C. See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. 2 Rev. D | Page 8 of 32 Coding bit set to 1 Coding bit set to 0 AD7908/AD7918/AD7928 TIMING SPECIFICATIONS AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted. 1 Table 4. tCONVERT tQUIET Limit at TMIN, TMAX AD7908/AD7918/AD7928 AVDD = 3 V AVDD = 5 V Unit 10 10 kHz min 20 20 MHz max 16 × tSCLK 16 × tSCLK 50 50 ns min t2 t3 3 t43 t5 t6 t7 t8 4 t9 t10 t11 t12 10 35 40 0.4 × tSCLK 0.4 × tSCLK 10 15/45 10 5 20 1 Parameter fSCLK 2 10 30 40 0.4 × tSCLK 0.4 × tSCLK 10 15/35 10 5 20 1 Description Minimum quiet time required between CS rising edge and start of next conversion CS to SCLK setup time Delay from CS until DOUT three-state disabled Data access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to DOUT valid hold time SCLK falling edge to DOUT high impedance DIN setup time prior to SCLK falling edge DIN hold time after SCLK falling edge 16th SCLK falling edge to CS high Power-up time from full power-down/auto shutdown mode ns min ns max ns max ns min ns min ns min ns min/max ns min ns min ns min μs max 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 2 200µA 1.6V CL 50pF 200µA IOH 03089-002 TO OUTPUT PIN IOL Figure 2. Load Circuit for Digital Output Timing Specifications Rev. D | Page 9 of 32 AD7908/AD7918/AD7928 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter AVDD to AGND VDRIVE to AGND Analog Input Voltage to AGND Digital Input Voltage to AGND Digital Output Voltage to AGND REFIN to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Commercial (B Version) Storage Temperature Range Automotive Temperature Range Junction Temperature TSSOP Package, Power Dissipation θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD 1 Rating −0.3 V to +7 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to +7 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +85°C −65°C to +150°C −40°C to +125°C 150°C 450 mW 143°C/W (TSSOP) 45°C/W (TSSOP) 215°C 220°C 1.5 kV Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 10 of 32 AD7908/AD7918/AD7928 SCLK 1 20 AGND DIN 2 19 VDRIVE 18 DOUT 17 AGND CS 3 AGND 4 AVDD 5 AVDD 6 AD7908/ AD7918/ AD7928 TOP VIEW (Not to Scale) 16 VIN0 15 VIN1 14 VIN2 AGND 8 13 VIN3 VIN7 9 12 VIN4 VIN6 10 11 VIN5 REFIN 7 03089-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 DIN 3 CS 4, 8, 17, 20 AGND 5, 6 AVDD 7 REFIN 16 to 9 VIN0 to VIN7 18 DOUT 19 VDRIVE Description Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7908/AD7918/AD7928. Data In. Logic input. Data to be written to the control register of the AD7908/AD7918/AD7928 is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section). Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7908/AD7918/AD7928, and also frames the serial data transfer. Analog Ground. This is the ground reference point for all analog circuitry on the AD7908/AD7918/AD7928. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. Analog Power Supply Input. The AVDD range for the AD7908/AD7918/AD7928 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, AVDD should be from 4.75 V to 5.25 V. Reference Input for the AD7908/AD7918/AD7928. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. Analog Input 0 through Analog Input 7. These are eight single-ended analog input channels that are multiplexed into the on-chip track-and-hold. The analog input channel to be converted is selected by using Address Bit ADD2 through Address Bit ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REFIN or 0 V to 2 × REFIN as selected via the RANGE bit in the control register. Any unused input channels must be connected to AGND to avoid noise pickup. Data Out. Logic output. The conversion result from the AD7908/AD7918/AD7928 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7908 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first; the data stream from the AD7918 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7928 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, provided MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the AD7908/AD7918/AD7928 operates. Rev. D | Page 11 of 32 AD7908/AD7918/AD7928 TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a position 1 LSB below the first code transition, and full scale, a position 1 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 1 LSB. Offset Error Match This is the difference in offset error between any two channels. Gain Error This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (that is, REFIN – 1 LSB) after the offset error has been adjusted out. Gain Error Match This is the difference in gain error between any two channels. Zero Code Error This applies when using the twos complement output coding option, in particular to the 2 × REFIN input range with −REFIN to +REFIN biased about the REFIN point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal VIN voltage, that is, REFIN − 1 LSB. Zero Code Error Match This is the difference in zero code error between any two channels. Positive Gain Error This applies when using the twos complement output coding option, in particular to the 2 × REFIN input range with −REFIN to +REFIN biased about the REFIN point. It is the deviation of the last code transition (011. . .110) to (011 . . . 111) from the ideal (that is, +REFIN − 1 LSB) after the zero code error has been adjusted out. Positive Gain Error Match This is the difference in positive gain error between any two channels. Negative Gain Error This applies when using the twos complement output coding option, in particular to the 2 × REFIN input range with −REFIN to +REFIN biased about the REFIN point. It is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (that is, −REFIN + 1 LSB) after the zero code error has been adjusted out. Negative Gain Error Match This is the difference in negative gain error between any two channels. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 400 kHz sine wave signal to all seven nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure is given worst case across all eight channels for the AD7908/AD7918/ AD7928. Power Supply Rejection (PSR) Variations in power supply affect the full-scale transition, but not the converter’s linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power-supply voltage from the nominal value (see the Performance Curves section). Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of conversion. Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB Thus for a 12-bit converter, this is 74 dB; for a 10-bit converter, this is 62 dB; and for an 8-bit converter, this is 50 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7908/AD7918/ AD7928, it is defined as: THD (dB ) = 20 log V2 2 + V 3 2 + V4 2 + V52 + V6 2 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Rev. D | Page 12 of 32 AD7908/AD7918/AD7928 TYPICAL PERFORMANCE CHARACTERISTICS Figure 6 shows the power supply rejection ratio vs. supply ripple frequency for the AD7928 when no decoupling is used. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC AVDD supply of frequency fS PSRR(dB) = 10 log(Pf/Pfs) Figure 7 shows a graph of total harmonic distortion vs. analog input frequency for various supply voltages, and Figure 8 shows a graph of total harmonic distortion vs. analog input frequency for various source impedances. See the Analog Input section. Figure 9 and Figure 10 show typical INL and DNL plots for the AD7928. 0 –20 –30 Pf is equal to the power at frequency f in ADC output; PfS is equal to the power at frequency fS coupled onto the ADC AVDD supply. Here a 200 mV p-p sine wave is coupled onto the AVDD supply. –40 –50 –60 –70 –80 –90 4096 POINT FFT AVDD = 5V fSAMPLE = 1MSPS fIN = 50kHz SINAD = 71.147dB THD = –87.229dB SFDR = –90.744dB –10 SNR (dB) –30 AVDD = 5V 200mV p-p SINEWAVE ON AVDD REFIN = 2.5V, 1µF CAPACITOR TA = 25°C –10 0 100 200 300 400 500 600 700 800 900 1000 SUPPLY RIPPLE FREQUENCY (kHz) 03089-006 Figure 4 shows a typical FFT plot for the AD7928 at 1 MSPS sample rate and 50 kHz input frequency. Figure 5 shows the signal-to-(noise + distortion) ratio performance vs. input frequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz. PSRR (dB) PERFORMANCE CURVES Figure 6. AD7928 PSRR vs. Supply Ripple Frequency –50 fSAMPLE = 1MSPS TA = 25°C RANGE = 0V TO REFIN –55 –50 AVDD = VDRIVE = 2.70V –60 –70 THD (dB) –65 –90 AVDD = VDRIVE = 3.60V –70 50 100 150 200 250 300 350 400 450 500 FREQUENCY (kHz) Figure 4. AD7928 Dynamic Performance at 1 MSPS –85 AVDD = VDRIVE = 5.25V Figure 7. AD7928 THD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS AVDD = VDRIVE = 4.75V 70 AVDD = VDRIVE = 3.60V 65 60 fSAMPLE = 1MSPS TA = 25°C RANGE = 0V TO REFIN 100 1000 03089-005 AVDD = VDRIVE = 2.70V INPUT FREQUENCY (kHz) 100 INPUT FREQUENCY (kHz) AVDD = VDRIVE = 5.25V SINAD (dB) AVDD = VDRIVE = 4.75V –90 10 75 55 10 –80 Figure 5. AD7928 SINAD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS Rev. D | Page 13 of 32 1000 03089-007 0 03089-004 –75 –110 AD7908/AD7918/AD7928 –50 fSAMPLE = 1MSPS TA = 25°C RANGE = 0V TO REFIN AVDD = 5.25V –55 1.0 RIN = 1000Ω AVDD = VDRIVE = 5V TEMPERATURE = 25°C 0.8 0.6 DNL ERROR (LSB) –60 THD (dB) –65 RIN = 100Ω –70 RIN = 50Ω –75 RIN = 10Ω –80 0.4 0.2 0 –0.2 –0.4 –0.6 –85 1000 INPUT FREQUENCY (kHz) Figure 8. AD7928 THD vs. Analog Input Frequency for Various Source Impedances AVDD = VDRIVE = 5V TEMPERATURE = 25°C 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 0 512 1024 1536 2048 2560 3072 CODE 3584 4096 03089-009 INL ERROR (LSB) 0.6 –1.0 0 512 1024 1536 2048 2560 3072 CODE Figure 10. AD7928 Typical DNL 1.0 0.8 –1.0 Figure 9. AD7928 Typical INL Rev. D | Page 14 of 32 3584 4096 03089-010 100 03089-008 –0.8 –90 10 AD7908/AD7918/AD7928 CONTROL REGISTER The control register on the AD7908/AD7918/AD7928 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line corresponds to the AD7908/AD7918/AD7928 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 7. MSB WRITE SEQ DON’TCARE ADD2 ADD1 ADD0 PM1 PM0 SHADOW DON’TCARE RANGE LSB CODING Table 7. Control Register Bit Functions Bit 11 Mnemonic WRITE 10 SEQ 9 8 to 6 DON’TCARE ADD2 to ADD0 5, 4 PM1, PM0 3 SHADOW 2 1 DON’TCARE RANGE 0 CODING Comment The value written to this bit of the control register determines whether or not the following 11 bits are loaded to the control register. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the remaining 11 bits are not loaded to the control register, and it remains unchanged. The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer function and access the SHADOW register (see the SHADOW register bit map). These three address bits are loaded at the end of the present conversion sequence and select which analog input channel is to be converted in the next serial transfer, or they can select the final channel in a consecutive sequence as described in Table 10. The selected input channel is decoded as shown in Table 8. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data, see the Serial Interface section. The next channel to be converted on is selected by the mux on the 14th SCLK falling edge. Power Management Bits. These two bits decode the mode of operation of the AD7908/AD7918/AD7928 as shown in Table 9. The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer function and access the SHADOW register (see Table 10). This bit selects the analog input range to be used on the AD7908/AD7918/AD7928. If it is set to 0, the analog input range extends from 0 V to 2 × REFIN. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next conversion). For 0 V to 2 × REFIN, AVDD = 4.75 V to 5.25 V. This bit selects the type of output coding the AD7908/AD7918/AD7928 uses for the conversion result. If this bit is set to 0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next conversion). Table 8. Channel Selection ADD2 0 0 0 0 1 1 1 1 ADD1 0 0 1 1 0 0 1 1 ADD0 0 1 0 1 0 1 0 1 Analog Input Channel VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 Rev. D | Page 15 of 32 AD7908/AD7918/AD7928 Table 9. Power Mode Selection PM1 1 PM0 1 1 0 0 1 0 0 Mode Normal Operation. In this mode, the AD7908/AD7918/AD7928 remain in full power mode regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7908/AD7918/AD7928. Full Shutdown. In this mode, the AD7908/ AD7918/AD7928 is in full shutdown mode with all circuitry powering down. The AD7908/AD7918/AD7928 retains the information in the control register while in full shutdown. The part remains in full shutdown until these bits are changed. Auto Shutdown. In this mode, the AD7908/AD7918/AD7928 automatically enters full shutdown mode at the end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 μs and the user should ensure that 1 μs has elapsed before attempting to perform a valid conversion on the part in this mode. Invalid Selection. This configuration is not allowed. SEQUENCER OPERATION The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table 10 outlines the four modes of operation of the sequencer. Table 10. Sequence Selection SEQ 0 SHADOW 0 0 1 1 0 1 1 Sequence Type This configuration means that the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of the ADD0 through ADD2 channel address bits in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7908/AD7918/AD7928 selects the next channel for conversion (see Figure 11). This configuration selects the SHADOW register for programming. The following write operation loads the contents of the SHADOW register. This programs the sequence of channels to be converted on continuously with each successive valid CS falling edge (see the SHADOW Register section, SHADOW register bit map, and Figure 12). The channels selected need not be consecutive. If the SEQ and SHADOW bits are set in this way, then the sequence functions are not interrupted upon completion of the write operation. This allows other bits in the control register to be altered between conversions while in a sequence, without terminating the cycle. This configuration is used in conjunction with the ADD2 to ADD0 channel address bits to program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address bits in the control register (see Figure 13). Rev. D | Page 16 of 32 AD7908/AD7918/AD7928 SHADOW REGISTER MSB LSB VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN0 VIN1 VIN2 Sequence One VIN3 VIN4 VIN5 VIN6 VIN7 Sequence Two The SHADOW register on the AD7908/AD7918/AD7928 is a 16-bit, write-only register. Data is loaded from the DIN pin of the AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that a conversion result is read from the part. This requires 16 serial clock falling edges for the data transfer. The information is clocked into the SHADOW register, provided that the SEQ and SHADOW bits were set to 0,1, respectively, in the previous write to the control register. MSB denotes the first bit in the data stream. Each bit represents an analog input from Channel 0 to Channel 7. Through programming the SHADOW register, two sequences of channels can be selected, through which the AD7908/AD7918/AD7928 cycle with each consecutive conversion after the write to the SHADOW register. POWER-ON DUMMY CONVERSION DIN = ALL 1s DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT A2 TO A0 FOR CONVERSION. SEQ = SHADOW = 0 CS DOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL A2 TO A0. CS WRITE BIT = 1, DIN: WRITE TO CONTROL REGISTER, SEQ = SHADOW = 0 WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT A2 TO A0 FOR CONVERSION. SEQ = SHADOW = 0 03089-011 VIN0 Figure 11. SEQ Bit = 0, SHADOW Bit = 0 Flowchart Sequence One is performed first and then Sequence Two. If the user does not wish to perform a second sequence option, then all 0s must be written to the last 8 LSBs of the SHADOW register. To select a sequence of channels, the associated channel bit must be set for each analog input. The AD7908/AD7918/ AD7928 continuously cycle through the selected channels in ascending order beginning with the lowest channel, until a write operation occurs (that is, the WRITE bit is set to 1) with the SEQ and SHADOW bits configured in any way except 1, 0, (see Table 10). The bit functions are outlined in the SHADOW register bit map. POWER-ON DUMMY CONVERSION DIN = ALL 1s CS Figure 11 reflects the traditional operation of a multichannel ADC, where each serial transfer selects the next channel for conversion. In this mode of operation the sequencer function is not used. DOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL A2 TO A0. DIN: WRITE TO SHADOW REGISTER, SELECTING WHICH CHANNELS TO CONVERT ON; CHANNELS SELECTED NEED NOT BE CONSECUTIVE CHANNELS WRITE BIT = 0 CS Rev. D | Page 17 of 32 CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS WRITE BIT = 0 WRITE BIT = 0 WRITE BIT = 1 SEQ = 1, SHADOW = 0 CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT WILL ALLOW RANGE, CODING, AND SO ON, TO CHANGE IN THE CONTROL REGISTER WITHOUT INTERRUPTING THE SEQUENCE, PROVIDED SEQ = 1 SHADOW = 0 WRITE BIT = 1 SEQ = 1, SHADOW = 0 Figure 12. SEQ Bit = 0, SHADOW Bit = 1 Flowchart 03089-012 Figure 12 shows how to program the AD7908/AD7918/AD7928 to continuously convert on a particular sequence of channels. To exit this mode of operation and revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 11), ensure that the WRITE bit = 1 and the SEQ = SHADOW = 0 on the next serial transfer. Figure 13 shows how a sequence of consecutive channels can be converted on without having to program the SHADOW register or write to the part on each serial transfer. Again, to exit this mode of operation and revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 11), ensure the WRITE bit = 1 and the SEQ = SHADOW = 0 on the next serial transfer. CS DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A2 TO A0 FOR CONVERSION. SEQ = 0 SHADOW = 1 AD7908/AD7918/AD7928 REFIN or 0 V to 2 × REFIN. Figure 14 and Figure 15 show simplified schematics of the ADC. The ADC is comprised of control logic, SAR, and a capacitive DAC, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 14 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected VIN channel. POWER-ON DUMMY CONVERSION DIN = ALL 1s DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A2 TO A0 FOR CONVERSION. SEQ = 1 SHADOW = 1 DOUT: CONVERSION RESULT FROM CHANNEL 0. CONTINUOUSLY CONVERTS ON A CONSECUTIVE SEQUENCE OF CHANNELS FROM CHANNEL 0 UP TO, AND INCLUDING, THE PREVIOUSLY SELECTED A2 TO A0 IN THE CONTROL REGISTER. CAPACITIVE DAC WRITE BIT = 0 A VIN0 SW1 4kΩ B VIN7 COMPARATOR AGND Figure 14. ADC Acquisition Phase WRITE BIT = 1 SEQ = 1, SHADOW = 0 03089-013 CS CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT WILL ALLOW RANGE, CODING, AND SO ON, TO CHANGE IN THE CONTROL REGISTER WITHOUT INTERRUPTING THE SEQUENCE, PROVIDED SEQ = 1 SHADOW = 0 CONTROL LOGIC SW2 03089-014 CS Figure 13. SEQ Bit = 1, SHADOW Bit = 1 Flowchart CIRCUIT INFORMATION The AD7908/AD7918/AD7928 are high speed, 8-channel, 8-bit, 10-bit, and 12-bit, single-supply ADCs, respectively. The parts can be operated from a 2.7 V to 5.25 V supply. When operated from either a 5 V or 3 V supply, the AD7908/AD7918/AD7928 are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock. The AD7908/AD7918/AD7928 provide the user with an onchip, track-and-hold ADC, and a serial interface housed in a 20-lead TSSOP package. The AD7908/AD7918/ AD7928 each have eight single-ended input channels with a channel sequencer, allowing the user to select a channel sequence that the ADC can cycle through with each consecutive CS falling edge. The serial clock input accesses data from the part, controls the transfer of data written to the ADC, and provides the clock source for the successive approximation ADC. The analog input range for the AD7908/AD7918/ AD7928 is 0 V to REFIN or 0 V to 2 × REFIN, depending on the status of Bit 1 in the control register. For the 0 to 2 × REFIN range, the part must be operated from a 4.75 V to 5.25 V supply. The AD7908/AD7918/AD7928 provide flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the PM1 and PM0 power management bits in the control register. CONVERTER OPERATION The AD7908/AD7918/AD7928 are 8-, 10-, and 12-bit successive approximation analog-to-digital converters based around a capacitive DAC, respectively. The AD7908/AD7918/ AD7928 can convert analog input signals in the range 0 V to When the ADC starts a conversion (see Figure 15), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 17 and Figure 18 show the ADC transfer functions. CAPACITIVE DAC A VIN0 SW1 VIN7 4kΩ B CONTROL LOGIC SW2 COMPARATOR AGND 03089-015 CS Figure 15. ADC Conversion Phase Analog Input Figure 16 shows an equivalent circuit of the analog input structure of the AD7908/AD7918/AD7928. The two diodes (D1 and D2) provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. This causes these diodes to become forward biased and start conducting current into the substrate. 10 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. The Capacitor C1 in Figure 16 is typically about 4 pF and can primarily be attributed to pin capacitance. The Resistor R1 is a lumped component made up of the on resistance of the trackand-hold switch and also includes the on resistance of the input multiplexer. The total resistance is typically about 400 Ω. The Capacitor C2 is the ADC sampling capacitor and has a capacitance of 30 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC lowpass filter on the relevant analog input pin. In applications where harmonic distortion Rev. D | Page 18 of 32 AD7908/AD7918/AD7928 When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases, and performance degrades (see Figure 8). –VREF + 1 LSB R1 Figure 19 shows how useful the combination of the 2 × REFIN input range and the twos complement output coding scheme is for handling bipolar input signals. If the bipolar input signal is biased about REFIN and twos complement output coding is selected, then REFIN becomes the zero code point, −REFIN is negative full scale and +REFIN becomes positive full scale, with a dynamic range of 2 × REFIN. 03089-016 CONVERSION PHASE: SWITCH OPEN TRACK PHASE: SWITCH CLOSED Figure 16. Equivalent Analog Input Circuit ADC TRANSFER FUNCTION 1LSB = VREF /256 AD7908 1LSB = VREF /1024 AD7918 1LSB = VREF /4096 AD7928 1 LSB +VREF – 1 LSB ANALOG INPUT NOTE 1. VREF IS EITHER REFIN OR 2 × REFIN. Figure 17. Straight Binary Transfer Characteristic 03089-017 ADC CODE The output coding of the AD7908/AD7918/AD7928 is either straight binary or twos complement, depending on the status of the LSB in the control register. The designed code transitions occur at successive LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size is REFIN/256 for the AD7908, REFIN/1024 for the AD7918, and REFIN/4096 for the AD7928. The ideal transfer characteristic for the AD7908/AD7918/AD7928 when straight binary coding is selected is shown in Figure 17, and the ideal transfer characteristic for the AD7908/AD7918/AD7928 when twos complement coding is selected is shown in Figure 18. 0V +VREF – 1 LSB HANDLING BIPOLAR INPUT SIGNALS C2 30pF VIN 111…111 111…110 • • 111…000 • 011…111 • • 000…010 000…001 000…000 VREF – 1 LSB Figure 18. Twos Complement Transfer Characteristic with REFIN ± REFIN Input Range D1 D2 1LSB = 2 × VREF /256 AD7908 1LSB = 2 × VREF /1024 AD7918 1LSB = 2 × VREF /4096 AD7928 ANALOG INPUT AVDD C1 4pF 011…111 011…110 • • 000…001 000…000 111…111 • • 100…010 100…001 100…000 03089-018 ADC CODE and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This can necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. TYPICAL CONNECTION DIAGRAM Figure 20 shows a typical connection diagram for the AD7908/AD7918/AD7928. In this setup, the AGND pin is connected to the analog ground plane of the system. In Figure 20, REFIN is connected to a decoupled 2.5 V supply from a reference source, the AD780, to provide an analog input range of 0 V to 2.5 V (if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). Although the AD7908/AD7918/AD7928 is connected to a VDD of 5 V, the serial interface is connected to a 3 V microprocessor. The VDRIVE pin of the AD7908/AD7918/ AD7928 is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section). The conversion result is output in a 16-bit word. This 16-bit data stream consists of a leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data for the AD7928 (10 bits of data for the AD7918 and 8 bits of data for the AD7908, each followed by two and four trailing zeros, respectively). For applications where power consumption is of concern, the power-down modes should be used between conversions or bursts of several conversions to improve power performance (see the Modes of Operation section). Rev. D | Page 19 of 32 AD7908/AD7918/AD7928 VDD VREF 0.1µF AVDD VDD VDRIVE AD7908/ AD7918/ AD7928 R4 V R3 V 0V VIN0 R2 DOUT DSP/µP TWOS COMPLEMENT • • R1 +REFIN VIN7 R1 = R2 = R3 = R4 (= 2 × REFIN) REFIN –REFIN 011…111 000…000 (= 0V) 100…000 03089-019 REFIN Figure 19. Handling Bipolar Signals 0.1µF SCLK AD7908/ AD7918/ AD7928 DOUT 0.1µF REFIN VDRIVE 2.5V AD780 µC/µP CS VIN7 AGND during the sequence, then it must be ensured that the SEQ and SHADOW bits are set to 1, 0 to avoid interrupting the automatic conversion sequence. This pattern continues until such time as the AD7908/AD7918/AD7928 is written to and the SEQ and SHADOW bits are configured with any bit combination except 1, 0. On completion of the sequence, the AD7908/ AD7918/AD7928 sequencer returns to the first selected channel in the SHADOW register and commence the sequence again. SERIAL INTERFACE DIN 0.1µF 10µF 3V SUPPLY NOTE 1. ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND. 03089-020 0V TO REFIN AVDD VIN0 • • 10µF 5V SUPPLY Figure 20. Typical Connection Diagram Analog Input Selection Any one of eight analog input channels can be selected for conversion by programming the multiplexer with the Address Bit ADD2 to Address Bit ADD0 in the control register. The channel configurations are shown in Table 8. The AD7908/ AD7918/AD7928 can also be configured to automatically cycle through a number of channels as selected. The sequencer feature is accessed via the SEQ and SHADOW bits in the control register (see Table 10). The AD7908/AD7918/AD7928 can be programmed to continuously convert on a selection of channels in ascending order. The analog input channels to be converted on are selected through programming the relevant bits in the SHADOW register (see the SHADOW Register section). The next serial transfer then acts on the sequence programmed by executing a conversion on the lowest channel in the selection. The next serial transfer results in a conversion on the next highest channel in the sequence, and so on. It is not necessary to write to the control register once a sequencer operation has been initiated. The WRITE bit must be set to zero or the DIN line tied low to ensure the control register is not accidentally overwritten, or the sequence operation interrupted. If the control register is written to at any time Rather than selecting a particular sequence of channels, a number of consecutive channels beginning with Channel 0 can also be programmed via the control register alone, without needing to write to the SHADOW register. This is possible if the SEQ and SHADOW bits are set to 1,1. The channel address bits ADD2 through ADD0 then determine the final channel in the consecutive sequence. The next conversion is on Channel 0, then Channel 1, and so on until the channel selected via the address bits ADD2 through ADD0 is reached. The cycle begins again on the next serial transfer, provided the WRITE bit is set to low, or if high, that the SEQ and SHADOW bits are set to 1, 0; then the ADC continues its preprogrammed automatic sequence uninterrupted. Regardless of which channel selection method is used, the 16-bit word output from the AD7928 during each conversion always contains a leading zero, three channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result. The AD7918 outputs a leading zero, three channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros; the AD7908 outputs a leading zero, three channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. (See the Serial Interface section.) Digital Inputs The digital inputs applied to the AD7908/AD7918/AD7928 are not limited by the maximum ratings that limit the analog Rev. D | Page 20 of 32 AD7908/AD7918/AD7928 Another advantage of SCLK, DIN, and CS not being restricted by the AVDD + 0.3 V limit is the fact that power supply sequencing issues are avoided. If CS, DIN, or SCLK are applied before AVDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to AVDD. VDRIVE The AD7908/AD7918/AD7928 also have the VDRIVE feature. VDRIVE controls the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7908/AD7918/AD7928 were operated with an AVDD of 5 V, the VDRIVE pin could be powered from a 3 V supply. The AD7908/AD7918/AD7928 have better dynamic performance with an AVDD of 5 V while still being able to interface to 3 V processors. Care should be taken to ensure VDRIVE does not exceed AVDD by more than 0.3 V. See the Absolute Maximum Ratings section. Reference An external reference source should be used to supply the 2.5 V reference to the AD7908/AD7918/AD7928. Errors in the reference source results in gain errors in the AD7908/ AD7918/AD7928 transfer function and adds to the specified full-scale errors of the part. A capacitor of at least 0.1 μF should be placed on the REFIN pin. Suitable reference sources for the AD7908/AD7918/AD7928 include the AD780, REF192, AD1582, ADR03, ADR381, ADR391, and ADR421. If 2.5 V is applied to the REFIN pin, the analog input range can either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of the RANGE bit in the control register. MODES OF OPERATION The AD7908/AD7918/AD7928 have a number of different modes of operation. These modes are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. The mode of operation of the AD7908/AD7918/AD7928 is controlled by the power management bits, PM1 and PM0, in the control register, as detailed in Table 9. When power supplies are first applied to the AD7908/AD7918/AD7928, care should be taken to ensure that the part is placed in the required mode of operation (see Powering Up the AD7908/AD7918/AD7928 section). Normal Mode (PM1 = PM0 = 1) This mode is intended for the fastest throughput rate performance, as the user does not have to worry about any power-up times with the AD7908/AD7918/AD7928 remaining fully powered at all times. Figure 21 shows the general diagram of the operation of the AD7908/AD7918/AD7928 in this mode. The conversion is initiated on the falling edge of CS and the track-and-hold enters hold mode as described in the Serial Interface section. The data presented to the AD7908/AD7918/ AD7928 on the DIN line during the first 12 clock cycles of the data transfer are loaded into the control register (provided WRITE bit is set to 1). If data is to be written to the SHADOW register (SEQ = 0, SHADOW = 1 on previous write), data presented on the DIN line during the first 16 SCLK cycles is loaded into the SHADOW register. The part remains fully powered up in normal mode at the end of the conversion as long as PM1 and PM0 are both loaded with 1 on every data transfer. Sixteen serial clock cycles are required to complete the conversion and access the conversion result. The track-andhold goes back into track on the 14th SCLK falling edge. CS can then idle high until the next conversion or can idle low until sometime prior to the next conversion, effectively idling CS low. Once a data transfer is complete (DOUT has returned to threestate), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. CS SCLK DOUT DIN 1 12 16 1 LEADING ZERO + 3 CHANNEL IDENTIFIER BITS + CONVERSION RESULT DATA IN TO CONTROL/SHADOW REGISTER NOTES 1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES. 2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES. 03089-021 inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the AVDD + 0.3 V limit as on the analog inputs. Figure 21. Normal Mode Operation Full Shutdown Mode (PM1 = 1, PM0 = 0) In this mode, all internal circuitry on the AD7908/AD7918/ AD7928 is powered down. The part retains information in the control register during full shutdown. The AD7908/AD7918/ AD7928 remains in full shutdown until the power management bits in the control register, PM1 and PM0, are changed. If a write to the control register occurs while the part is in full shutdown, with the power management bits changed to PM0 = PM1 = 1, normal mode, the part begins to power up on the CS rising edge. The track-and-hold that was in hold while the part was in full shutdown returns to track on the 14th SCLK falling edge. To ensure that the part is fully powered up, tPOWER UP, should have elapsed before the next CS falling edge. Figure 22 shows the general diagram for this sequence. Auto Shutdown Mode (PM1 = 0, PM0 = 1) In this mode, the AD7908/AD7918/AD7928 automatically enters shutdown at the end of each conversion when the control register is updated. When the part is in shutdown, the track and hold is in hold mode. Figure 23 shows the general diagram of Rev. D | Page 21 of 32 AD7908/AD7918/AD7928 other conversion result being valid. In this mode, the power consumption of the part is greatly reduced with the part entering shutdown at the end of each conversion. When the control register is programmed to move into auto shutdown, it does so at the end of the conversion. The user can move the ADC in and out of the low power state by controlling the CS signal. the operation of the AD7908/AD7918/AD7928 in this mode. In shutdown mode, all internal circuitry on the AD7908/AD7918/ AD7928 is powered down. The part retains information in the control register during shutdown. The AD7908/AD7918/ AD7928 remains in shutdown until the next CS falling edge it receives. On this CS falling edge, the track-and-hold that was in hold while the part was in shutdown returns to track. Wakeup time from auto shutdown is 1 μs, and the user should ensure that 1 μs has elapsed before attempting a valid conversion. When running the AD7908/AD7918/AD7928 with a 20 MHz clock, one dummy cycle should be sufficient to ensure the part is fully powered up. During this dummy cycle the contents of the control register should remain unchanged; therefore the WRITE bit should be 0 on the DIN line. This dummy cycle effectively halves the throughput rate of the part, with every PART IS IN FULL SHUTDOWN Powering Up the AD7908/AD7918/AD7928 When supplies are first applied to the AD7908/AD7918/ AD7928, the ADC can power up in any of the operating modes of the part. To ensure the part is placed into the required operating mode, the user should perform a dummy cycle operation as outlined in Figure 24. PART BEGINS TO POWER UP ON CS RISING EDGE AS PM1 = PM0 = 1 THE PART IS FULLY POWERED UP ONCE tPOWER UP HAS ELAPSED t12 CS 14 1 16 1 14 16 SCLK DOUT CHANNEL IDENTIFIER BITS + CONVERSION RESULT DATA IN TO CONTROL REGISTER DATA IN TO CONTROL/SHADOW REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 1 03089-022 DIN TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER Figure 22. Full Shutdown Mode Operation PART ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 = 0, PM0 = 1 PART BEGINS TO POWER UP ON CS FALLING EDGE CS DOUT DIN PART ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 = 0, PM0 = 1 DUMMY CONVERSION 1 12 16 CHANNEL IDENTIFIER BITS + CONVERSION RESULT 1 12 16 INVALID DATA DATA IN TO CONTROL/SHADOW REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS, PM1 = 0, PM0 = 1 1 12 16 CHANNEL IDENTIFIER BITS + CONVERSION RESULT DATA IN TO CONTROL/SHADOW REGISTER CONTROL REGISTER CONTENTS SHOULD NOT CHANGE. WRITE BIT = 0 Figure 23. Auto Shutdown Mode Operation Rev. D | Page 22 of 32 TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1 IN CONTROL REGISTER OR SET WRITE BIT = 0 03089-023 SCLK PART IS FULLY POWERED UP AD7908/AD7918/AD7928 CORRECT VALUE IN CONTROL REGISTER, VALID DATA FROM NEXT CONVERSION, USER CAN WRITE TO SHADOW REGISTER IN NEXT CONVERSION CS DUMMY CONVERSION 1 12 DUMMY CONVERSION 16 1 12 16 1 12 16 SCLK INVALID DATA INVALID DATA INVALID DATA DATA IN TO CONTROL REGISTER DIN 03089-024 DOUT CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCK EDGES KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS Figure 24. Placing AD7928 into the Required Operating Mode After Supplies are Applied POWER VS. THROUGHPUT RATE 10 AVDD = 5V AVDD = 3V 1 POWER (mW) 0.1 For example, if the AD7928 is operated in a continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz (AVDD = 5 V), and the device is placed in auto shutdown mode, that is, if PM1 = 0 and PM0 = 1, then the power consumption is calculated as follows: 0.01 0 50 100 150 200 250 300 THROUGHPUT (kSPS) The maximum power dissipation during normal operation is 13.5 mW (AVDD = 5 V). If the power-up time from auto shutdown is one dummy cycle, that is, 1 μs, and the remaining conversion time is another cycle, that is, 1 μs, then the AD7928 can be said to dissipate 13.5 mW for 2 μs during each conversion cycle. For the remainder of the conversion cycle, 8 μs, the part remains in auto shutdown mode. The AD7928 can be said to dissipate 2.5 μW for the remaining 8 μs of the conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs and the average power dissipated during each cycle is (2/10) × (13.5 mW) + (8 / 10) × (2.5 μW) = 2.702 mW Figure 25 shows the maximum power vs. throughput rate when using the auto shutdown mode with 3 V and 5 V supplies. 350 03089-025 By operating in auto shutdown mode on the AD7908/AD7918/ AD7928, the average power consumption of the ADC decreases at lower throughput rates. Figure 25 shows how as the throughput rate is reduced, the part remains in its shutdown state longer and the average power consumption over time drops accordingly. Figure 25. AD7928 Power vs. Throughput Rate SERIAL INTERFACE Figure 26, Figure 27, and Figure 28 show the detailed timing diagrams for serial interfacing to the AD7908, AD7918, and AD7928, respectively. The serial clock provides the conversion clock and also controls the transfer of information to and from the AD7908/AD7918/AD7928 during each conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state; the analog input is sampled at this point. The conversion is also initiated at this point and requires 16 SCLK cycles to complete. The track-and-hold goes back into track on the 14th SCLK falling edge as shown in Figure 26, Figure 27, and Figure 28 at Point B, except when the write is to the SHADOW register, in which case the track-andhold does not return to track until the rising edge of CS, that is, Point C in Figure 29. On the 16th SCLK falling edge, the DOUT line goes back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion is terminated, the DOUT line goes back into three-state, and the control register is not updated; otherwise DOUT returns to three-state on the 16th SCLK falling edge as shown in Figure 26, Figure 27, and Figure 28. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7908/ AD7918/AD7928. For the AD7908/AD7918/AD7928, the Rev. D | Page 23 of 32 AD7908/AD7918/AD7928 8/10/12 bits of data are preceded by a leading zero and the 3-channel address bits (ADD2 to ADD0) identify which channel the result corresponds to. CS going low provides the leading zero to be read in by the microcontroller or DSP. The three remaining address bits and data bits are then clocked out by subsequent SCLK falling edges beginning with the first address bit (ADD2). Thus the first falling clock edge on the serial clock has a leading zero provided and also clocks out Address Bit ADD2. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. Writing of information to the control register takes place on the first 12 falling edges of SCLK in a data transfer, assuming the MSB, that is, the WRITE bit, has been set to 1. If the control register is programmed to use the SHADOW register, then writing of information to the SHADOW register takes place on all 16 SCLK falling edges in the next serial transfer, as shown for example on the AD7928 in Figure 29. Two sequence options can be programmed in the SHADOW register. If the user does not want to program a second sequence, then the eight LSBs should be filled with zeros. The SHADOW register is updated upon the rising edge of CS and the track-and-hold begins to track the first channel selected in the sequence. The AD7908 outputs a leading zero and three channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. The AD7918 outputs a leading zero and three channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros. The 16-bit word read from the AD7928 always contains a leading zero and three channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result. MICROPROCESSOR INTERFACING The serial interface on the AD7908/AD7918/AD7928 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7908/AD7918/AD7928 with some of the more common microcontroller and DSP serial interface protocols. AD7908/AD7918/AD7928 to TMS320C541 The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7908/AD7918/AD7928. The CS input allows easy interfacing between the TMS320C541 and the AD7908/ AD7918/AD7928 without any glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode with internal CLKX0 (Tx serial clock on Serial Port 0) and FSX0 (Tx frame sync from Serial Port 0). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The connection diagram is shown in Figure 30. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C541 provides equidistant sampling. The VDRIVE pin of the AD7908/AD7918/AD7928 takes the same supply voltage as that of the TMS320C541. This allows the ADC to operate at a higher voltage than the serial interface, that is, TMS320C541, if necessary. Rev. D | Page 24 of 32 AD7908/AD7918/AD7928 CS t2 tCONVERT t6 2 3 4 t3 5 ADD2 ADD1 SEQ1 ADD0 DONTC 14 DB7 15 16 t11 t8 DB6 DB0 ZERO ZERO ZERO tQUIET ZERO FOUR TRAILING ZEROS THREE-STATE t10 t9 WRITE 13 t5 THREE IDENTIFICATION BITS ZERO DIN 12 t7 t4 DOUT THREE-STATE B 11 6 ADD2 ADD1 CODING DONTC ADD0 DONTC DONTC DONTC 15 16 03089-026 1 SCLK Figure 26. AD7908 Serial Interface Timing Diagram CS t2 tCONVERT t6 2 3 4 t3 5 ADD2 ADD1 SEQ ADD0 DONTC 14 DB7 t11 t8 DB6 DB2 DB1 DB0 ZERO tQUIET ZERO TWO TRAILING ZEROS THREE-STATE t10 t9 WRITE 13 t5 THREE IDENTIFICATION BITS ZERO ADD2 ADD1 CODING DONTC ADD0 DONTC DONTC DONTC Figure 27. AD7918 Serial Interface Timing Diagram CS tCONVERT t6 t2 2 3 4 t3 DOUT THREE-STATE ADD2 ADD1 ADD0 WRITE SEQ DONTC 14 DB11 DB10 16 15 t5 t7 t11 t8 DB2 DB1 DB0 THREE-STATE t10 9 DIN 13 6 t4 THREE IDENTIFICATION BITS ZERO t tQUIET B 5 ADD2 ADD1 ADD0 DONTC DONTC 03089-028 1 SCLK DONTC Figure 28. AD7928 Serial Interface Timing Diagram C CS tCONVERT t6 t2 1 SCLK 2 3 4 5 t3 ZERO DIN ADD1 ADD0 DB11 THREE IDENTIFICATION BITS VIN0 t9 VIN1 VIN2 VIN3 14 DB10 DB2 16 15 t5 t7 t4 ADD2 DOUT THREE-STATE 13 6 t11 t8 DB1 DB0 THREE-STATE t10 VIN4 VIN5 SEQUENCE 1 VIN6 SEQUENCE 2 Figure 29. AD7928 Writing to SHADOW Register Timing Diagram Rev. D | Page 25 of 32 VIN7 03089-029 DIN 12 t7 t4 DOUT THREE-STATE B 11 6 03089-027 1 SCLK AD7908/AD7918/AD7928 TMS320C5411 AD7908/ AD7918/ AD79281 CLKX SCLK CLKR DOUT DR DIN DT FSX VDRIVE 1ADDITIONAL PINS REMOVED FOR CLARITY. FSR VDD 03089-030 CS Figure 30. Interfacing to the TMS320C541 AD7908/AD7918/AD7928 to ADSP-21xx The ADSP-21xx family of DSPs are interfaced directly to the AD7908/AD7918/AD7928 without any glue logic required. The VDRIVE pin of the AD7908/AD7918/AD7928 takes the same supply voltage as that of the ADSP-21xx. This allows the ADC to operate at a higher voltage than the serial interface, that is, ADSP-21xx, if necessary. The SPORT0 control register should be set up as follows: TFSW = RFSW = 1, alternate framing INVRFS = INVTFS = 1, active low frame signal DTYPE = 00, right justify data SLEN = 1111, 16-bit data-words ISCLK = 1, internal serial clock TFSR = RFSR = 1, frame every word IRFS = 0 ITFS = 1 SCLK SCLK DR RFS CS TFS 1ADDITIONAL DT PINS REMOVED FOR CLARITY. VDD 03089-031 VDRIVE DIN The connection diagram in Figure 32 shows how the AD7908/AD7918/AD7928 can be connected to the synchronous serial interface (ESSI) of the DSP563xx family of DSPs from Motorola. Each ESSI (two on board) is operated in synchronous mode (SYN bit in CRB = 1) with internally generated word length frame sync for both Tx and Rx (Bit FSL1 = 0 and Bit FSL0 = 0 in CRB). Normal operation of the ESSI is selected by making MOD = 0 in the CRB. Set the word length to 16 by setting Bit WL1 = 1 and Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so the frame sync is negative. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP563xx provides equidistant sampling. In the example shown in Figure 32, the serial clock is taken from the ESSI so the SCK0 pin must be set as an output, SCKD = 1. The VDRIVE pin of the AD7908/AD7918/AD7928 takes the same supply voltage as that of the DSP563xx. This allows the ADC to operate at a higher voltage than the serial interface, that is, DSP563xx, if necessary. ADSP-21xx1 DOUT For example, if the ADSP-2189 had a 20 MHz crystal such that it had a master clock frequency of 40 MHz, then the master cycle time would be 25 ns. If the SCLKDIV register was loaded with the value 3, then an SCLK of 5 MHz is obtained, and eight master clock periods elapse for every one SCLK period. Depending on the throughput rate selected, if the timer register is loaded with the value, say 803 (803 + 1 = 804), 100.5 SCLKs occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, then equidistant sampling is implemented by the DSP. AD7908/AD7918/AD7928 to DSP563xx The connection diagram is shown in Figure 31. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS, as with all signal processing applications where equidistant sampling is necessary. However, in this example the timer interrupt is used to control the sampling rate of the ADC, and under certain conditions equidistant sampling cannot be achieved. AD7908/ AD7918/ AD79281 The timer register, for example, is loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and thus the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (that is, AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before transmission can start. If the timer and SCLK values are chosen, such that the instruction to transmit occurs on or near the rising edge of SCLK, then the data can be transmitted or it can wait until the next clock edge. Figure 31. Interfacing to the ADSP-21xx Rev. D | Page 26 of 32 AD7908/AD7918/AD7928 DSP563xx1 AD7908/ AD7918/ AD79281 SCLK SCK DOUT SRD DIN STD CS SC2 1ADDITIONAL PINS REMOVED FOR CLARITY. 03089-032 VDRIVE VDD Figure 32. Interfacing to the DSP563xx APPLICATION HINTS Grounding and Layout The AD7908/AD7918/AD7928 have very good immunity to noise on the power supplies, as can be seen by the PSRR vs. Supply Ripple Frequency plot, Figure 6. However, care should still be taken with regard to grounding and layout. The printed circuit board that houses the AD7908/AD7918/ AD7928 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. All four AGND pins of the AD7908/AD7918/AD7928 should be sunk in the AGND plane. If the AD7908/AD7918/AD7928 is in a system where multiple devices require an AGND to DGND connection, the connection should be made at only one point in the plane. Using a star ground point, the connection should be established as close as possible to the AD7908/ AD7918/AD7928. Avoid running digital lines under the device, as these couple noise onto the die. The analog ground plane should be allowed to run under the AD7908/AD7918/AD7928 to avoid noise coupling. The power supply lines to the AD7908/AD7918/ AD7928 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, like clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to AGND. To achieve the best performance from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 μF capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Evaluating the AD7908/AD7918/AD7928 Performance The recommended layout for the AD7908/AD7918/AD7928 is outlined in the AD7908/AD7918/AD7928 evaluation board. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the eval-board controller. The eval-board controller can be used in conjunction with the AD7908/AD7918/AD7928 evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7908/AD7918/AD7928. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7908/AD7918/AD7928. The software and documentation are on a CD shipped with the evaluation board. Rev. D | Page 27 of 32 AD7908/AD7918/AD7928 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 33. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters Rev. D | Page 28 of 32 0.75 0.60 0.45 AD7908/AD7918/AD7928 ORDERING GUIDE Model 1, 2, 3, 4 AD7908BRU-REEL AD7908BRU-REEL7 AD7908BRUZ AD7908BRUZ-REEL AD7908BRUZ-REEL7 AD7908WYRUZ-REEL7 AD7918BRU-REEL7 AD7918BRUZ AD7918BRUZ-REEL AD7918BRUZ-REEL7 AD7918WYRUZ-REEL7 AD7928BRU AD7928BRU-REEL AD7928BRUZ AD7928BRUZ-REEL AD7928BRUZ-REEL7 AD7928WYRUZ-REEL7 EVAL-AD79x8CBZ EVAL-CONTROL BRD Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C Linearity Error (LSB) 5 ±0.2 ±0.2 ±0.2 ±0.2 ±0.2 ±0.2 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±1 ±1 ±1 ±1 ±1 ±1 Package Description 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP Evaluation Board Controller Board Package Option RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 1 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. 3 The EVAL-AD79x8CBZ can be used as a standalone evaluation board or in conjunction with the evaluation controller board for evaluation/demonstration purposes. The board comes with one chip of each the AD7908, AD7918, and AD7928. 4 The EVAL-CONTROL BRD is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, order the particular ADC evaluation board, such as the EVAL-AD79x8CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant evaluation board technical note for more information. 5 Linearity error here refers to integral linearity error. 2 AUTOMOTIVE PRODUCTS The AD72x8W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. D | Page 29 of 32 AD7908/AD7918/AD7928 NOTES Rev. D | Page 30 of 32 AD7908/AD7918/AD7928 NOTES Rev. D | Page 31 of 32 AD7908/AD7918/AD7928 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03089-0-12/10(D) Rev. D | Page 32 of 32