Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors AD9943/AD9944 Data Sheet FEATURES GENERAL DESCRIPTION 25 MSPS correlated double sampler (CDS) 6 dB to 40 dB 10-bit variable gain amplifier (VGA) Low noise optical black clamp circuit Preblanking function 10-bit (AD9943), 12-bit (AD9944) 25 MSPS A/D converter No missing codes guaranteed 3-wire serial digital interface 3 V single-supply operation Space-saving 32-lead 5 mm × 5 mm LFCSP package The AD9943/AD9944 are complete analog signal processors for CCD applications. They feature a 25 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The signal chain for the AD9943/AD9944 consists of a correlated double sampler (CDS), a digitally controlled variable gain amplifier (VGA), and a black level clamp. The AD9943 offers 10-bit ADC resolution, while the AD9944 contains a true 12-bit ADC. APPLICATIONS Digital still cameras Digital video camcorders PC cameras Portable CCD imaging devices CCTV cameras The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input clock polarity, and power-down modes. The AD9943/AD9944 operate from a single 3 V power supply, typically dissipate 79 mW, and are packaged in space-saving 32-lead LFCSP packages. FUNCTIONAL BLOCK DIAGRAM REFT AD9943/AD9944 REFB PBLK DRVDD BAND GAP REFERENCE DRVSS 6dB–40dB 10/12 CCDIN 10-/12-BIT ADC VGA CDS DOUT CLP 10 AVDD CLPOB AVSS CONTROL REGISTERS SL SCK SDATA SHP SHD DATACLK DVDD DVSS 02905-B-001 INTERNAL TIMING DIGITAL INTERFACE Figure 1. Functional Block Diagram Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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Technical Support www.analog.com AD9943/AD9944 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Equivalent Input Circuits .............................................................. 10 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 11 General Description ......................................................................... 1 Internal Register Map .................................................................... 12 Functional Block Diagram .............................................................. 1 Serial Interface ................................................................................ 13 Revision History ............................................................................... 2 Circuit Description and Operation .............................................. 14 Specifications..................................................................................... 3 DC Restore .................................................................................. 14 General Specifications ................................................................. 3 Correlated Double Sampler ...................................................... 14 Digital Specifications ................................................................... 3 Optical Black Clamp .................................................................. 14 AD9943 System Specifications ................................................... 3 A/D Converter ............................................................................ 15 AD9944 System Specifications ................................................... 4 Variable Gain Amplifier ............................................................ 15 Timing Specifications .................................................................. 5 CCD Mode Timing ........................................................................ 16 Absolute Maximum Ratings............................................................ 6 Applications Information .............................................................. 17 Thermal Resistance ...................................................................... 6 Internal Power-On Reset Circuitry.......................................... 18 ESD Caution .................................................................................. 6 Grounding and Decoupling Recommendations .................... 18 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 19 Terminology ...................................................................................... 9 Ordering Guide............................................................................... 19 REVISION HISTORY 3/14—Rev. B to Rev. C Added Exposed Pad Notation, Figure 2 and Table 6 ................... 7 Added Exposed Pad Notation, Figure 3 and Table 7 ................... 8 Changes to Figure 17 ...................................................................... 17 Changes to Figure 18 ...................................................................... 18 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 5/04—Data Sheet Changed from Rev. A to Rev. B Updated Format .................................................................. Universal Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 5/03—Data Sheet changed from Rev. 0 to Rev. A Added AD9944 ................................................................... Universal Changes to Features Section............................................................ 1 Updated Ordering Guide ................................................................. 5 Replaced TPC 3................................................................................. 9 Added Figure 12.............................................................................. 15 Updated Outline Dimensions ....................................................... 16 Rev. C | Page 2 of 20 Data Sheet AD9943/AD9944 SPECIFICATIONS GENERAL SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted. Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Mode MAXIMUM CLOCK RATE Min Typ Max Unit −20 −65 +85 +150 °C °C 2.7 3.6 V 79 150 mW µW MHz 25 DIGITAL SPECIFICATIONS DRVDD = DVDD = 2.7 V, CL = 20 pF, unless otherwise noted. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA Symbol Min VIH VIL IIH IIL CIN 2.1 VOH VOL 2.2 Typ Max 0.6 10 10 10 0.5 Unit V V µA µA pF V V AD9943 SYSTEM SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted. Table 2. Parameter CDS Maximum Input Range before Saturation 1 Allowable CCD Reset Transient1 Maximum CCD Black Pixel Amplitude1 VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain Maximum Gain BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level Maximum Clamp Level Min 40 Typ Max Unit Conditions 1.0 500 100 V p-p mV mV See input waveform in footnote. 1024 Guaranteed Steps 5.3 41.5 dB dB 256 Steps 0 63.75 LSB LSB See Figure 13 for VGA gain curve. See Variable Gain Amplifier section for VGA gain equation. Measured at ADC output. Rev. C | Page 3 of 20 AD9943/AD9944 Data Sheet Parameter A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Data Output Coding Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Range Low Gain (VGA Code = 0) Maximum Gain (VGA Code = 1023) Gain Accuracy Peak Nonlinearity 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Typ Max 10 Unit Conditions Bits LSB ±0.3 Guaranteed Straight binary 2.0 V 2.0 1.0 V V Specifications include entire signal chain. 40 5.3 41.5 ±1 0.1 0.3 50 dB dB dB % LSB rms dB 12 dB gain applied. AC grounded input, 6 dB gain applied. Measured with step change on supply. Input signal characteristics defined as follows: 500mV TYP RESET TRANSIENT 100mV TYP OPTICAL BLACK PIXEL 1V TYP INPUT SIGNAL RANGE 02905-B-002 1 Min AD9944 SYSTEM SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted. Table 3. Parameter CDS Maximum Input Range before Saturation 1 Allowable CCD Reset Transient1 Maximum CCD Black Pixel Amplitude1 VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain Maximum Gain BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level Maximum Clamp Level A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Data Output Coding Full-Scale Input Voltage Min 40 Typ Max Unit Conditions 1.0 500 100 V p-p mV mV See input waveform in footnote. 1024 Guaranteed Steps 5.3 41.5 dB dB 256 Steps 0 255 LSB LSB See Figure 13 for VGA gain curve. See Variable Gain Amplifier section for VGA gain equation. Measured at ADC output. 12 ±0.4 Guaranteed Straight binary 2.0 Rev. C | Page 4 of 20 Bits LSB V Data Sheet AD9943/AD9944 Parameter VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Range Low Gain (VGA Code = 0) Maximum Gain (VGA Code = 1023) Gain Accuracy Peak Nonlinearity 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Typ Max 2.0 1.0 Unit Conditions V V Specifications include entire signal chain. 40 5.3 41.5 ±1 0.1 0.9 50 dB dB dB % LSB rms dB 12 dB gain applied. AC grounded input, 6 dB gain applied. Measured with step change on supply. Input signal characteristics defined as follows: 500mV TYP RESET TRANSIENT 100mV TYP OPTICAL BLACK PIXEL 1V TYP INPUT SIGNAL RANGE 02905-B-002 1 Min TIMING SPECIFICATIONS CL = 20 pF, fSAMP = 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11. Table 4. Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulse Width SHP Pulse Width SHD Pulse Width CLPOB Pulse Width 1 SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay DATA OUTPUTS Output Delay Pipeline Delay SERIAL INTERFACE Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold 1 Symbol Min tCONV tADC tSHP tSHD tCOB tS1 tS2 tID 40 16 2 16 tOD fSCLK tLS tLH tDS tDH Typ Max 20 10 10 20 10 20 3.0 ns ns ns ns Pixels ns ns ns 9.5 9 ns Cycles 10 10 10 10 10 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Rev. C | Page 5 of 20 Unit MHz ns ns ns ns AD9943/AD9944 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter (With Respect To) AVDD (AVSS) DVDD (DVSS) DRVDD (DRVSS) Digital Outputs (DRVSS) SHP, SHD, DATACLK (DVSS) CLPOB, PBLK (DVSS) SCK, SL, SDATA DVSS (AVSS) REFT, REFB, CCDIN Junction Temperature Lead Temperature (10 sec) Min −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 Max +3.9 +3.9 +3.9 DRVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 150 300 Unit V V V V V V V V °C °C The thermal resistance of a 32-lead LFCSP package (with the exposed bottom pad soldered to the board GND) is θJA = 27.7°C/W. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 6 of 20 Data Sheet AD9943/AD9944 32 31 30 29 28 27 26 25 NC2 NC2 NC1 NC1 NC1 SCK SDATA SL PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD9943 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 REFB REFT CCDIN AVSS AVDD SHD SHP CLPOB 1NC 2NC = NO CONNECT. INTERNALLY PULLED DOWN. FLOAT OR CONNECT TO GND. = NO CONNECT. INTERNALLY NOT CONNECTED. NOTES 1. SOLDER THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB. 02905-003 D8 D9 DRVDD DRVSS DVDD DATACLK DVSS PBLK 9 10 11 12 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 D7 Figure 2. AD9943 Pin Configuration Table 6. AD9943 Pin Function Descriptions Pin No. 1 to 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 to 30 31 to 32 1 Mnemonic D0 to D9 DRVDD DRVSS DVDD DATACLK DVSS PBLK CLPOB SHP SHD AVDD AVSS CCDIN REFT REFB SL SDATA SCK NC NC EPAD Type 1 DO P P P DI P DI DI DI DI P P AI AO AO DI DI DI NC NC Description Digital Data Outputs. Digital Output Driver Supply. Digital Output Driver Ground. Digital Supply. Digital Data Output Latch Clock. Digital Supply Ground. Preblanking Clock Input. Black Level Clamp Clock Input. CDS Sampling Clock for CCD Reference Level. CDS Sampling Clock for CCD Data Level. Analog Supply. Analog Ground. Analog Input for CCD Signal. A/D Converter Top Reference Voltage Decoupling. A/D Converter Bottom Reference Voltage Decoupling. Serial Digital Interface Load Pulse. Serial Digital Interface Data Input. Serial Digital Interface Clock Input. Internally pulled down. Float or connect to GND. Internally not connected. Exposed Pad. Solder the exposed pad to the ground plane of the PCB. Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect. Rev. C | Page 7 of 20 Data Sheet 32 31 30 29 28 27 26 25 D1 D0 NC NC NC SCK SDATA SL AD9943/AD9944 1 2 3 4 5 6 7 8 AD9944 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 REFB REFT CCDIN AVSS AVDD SHD SHP CLPOB NOTES 1. NC = NO CONNECT. INTERNALLY PULLED DOWN. FLOAT OR CONNECT TO GND. 2. SOLDER THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB. 02905-004 D10 D11 DRVDD DRVSS DVDD DATACLK DVSS PBLK 9 10 11 12 13 14 15 16 D2 D3 D4 D5 D6 D7 D8 D9 Figure 3. AD9944 Pin Configuration Table 7. AD9944 Pin Function Descriptions Pin No. 1 to 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 to 30 31 32 1 Mnemonic D2 to D11 DRVDD DRVSS DVDD DATACLK DVSS PBLK CLPOB SHP SHD AVDD AVSS CCDIN REFT REFB SL SDATA SCK NC D0 D1 EPAD Type 1 DO P P P DI P DI DI DI DI P P AI AO AO DI DI DI NC DO DO Description Digital Data Outputs. Digital Output Driver Supply. Digital Output Driver Ground. Digital Supply. Digital Data Output Latch Clock. Digital Supply Ground. Preblanking Clock Input. Black Level Clamp Clock Input. CDS Sampling Clock for CCD Reference Level. CDS Sampling Clock for CCD Data Level. Analog Supply. Analog Ground. Analog Input for CCD Signal. A/D Converter Top Reference Voltage Decoupling. A/D Converter Bottom Reference Voltage Decoupling. Serial Digital Interface Load Pulse. Serial Digital Interface Data Input. Serial Digital Interface Clock Input. Internally pulled down. Float or connect to GND. Digital Data Output. Digital Data Output. Exposed Pad. Solder the exposed pad to the ground plane of the PCB. Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect. Rev. C | Page 8 of 20 Data Sheet AD9943/AD9944 TERMINOLOGY Differential Nonlinearity (DNL) Power Supply Rejection (PSR) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating conditions. The PSR is measured with a step change applied to the supply pins. This represents a very high frequency disturbance on the AD9943/AD9944’s power supply. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. Peak Nonlinearity Internal Delay for SHP/SHD Peak nonlinearity, a full-signal chain specification, refers to the peak deviation of the output of the AD9943/AD9944 from a true straight line. The point used as zero scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC’s full-scale range. The internal delay (also called aperture delay) is the time delay that occurs from the time a sampling edge is applied to the AD9943/AD9944 until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transition from low to high, so the internal delay is measured from each clock’s rising edge to the instant the actual internal sample is taken. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale 2 N codes ) where N is the bit resolution of the ADC. For example, 1 LSB of the AD9943 is 1.95 mV. Rev. C | Page 9 of 20 AD9943/AD9944 Data Sheet EQUIVALENT INPUT CIRCUITS AVDD DVDD 60Ω 02905-B-005 AVSS DVSS Figure 6. CCDIN (Pin 22) Figure 4. Digital Inputs—SHP, SHD, DATACLK, CLOB, PBLK, SCK, SL DVDD DRVDD DATA THREESTATE DVSS DRVSS 02905-B-006 DOUT Figure 5. Data Outputs Rev. C | Page 10 of 20 AVSS 02095-B-007 330Ω INPUT Data Sheet AD9943/AD9944 TYPICAL PERFORMANCE CHARACTERISTICS 0.50 100 POWER DISSIPATION (mV) 90 VDD = 3.3V 0.25 80 VDD = 3.0V 70 0 VDD = 2.7V 60 –0.25 10 15 25 20 SAMPLE RATE (MHz) –0.50 0.50 0.25 0 –0.50 400 600 800 1000 02905-B-009 –0.25 200 800 1600 2400 3200 Figure 9. AD9944 Typical DNL Performance Figure 7. AD9943/AD9944 Power vs. Sample Rate 0 0 Figure 8. AD9943 Typical DNL Performance Rev. C | Page 11 of 20 4000 02905-B-010 40 02905-B-008 50 AD9943/AD9944 Data Sheet INTERNAL REGISTER MAP All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (AD9943 = 32 LSB clamp level, and AD9944 = 128 LSB clamp level). Table 8. Register Name Operation Address Bits A2 A1 A0 0 0 0 Control 0 0 1 Clamp Level 0 1 0 Data Bits D0 D2, D1 D3 D5, D4 D6 D8, D7 D11 to D9 D0 D1 D2 D3 D4 D5 D6 D11 to D7 D7 to D0 VGA Gain 0 1 1 D9 to D0 Function Software Reset (0 = normal operation, 1 = reset all registers to default). Power-Down Modes (00 = normal power, 01 = standby, 10 = total shutdown). OB Clamp Disable (0 = clamp on, 1 = clamp off ). Test Mode. Should always be set to 00. PBLK Blanking Level (0 = blank output to zero, 1 = blank to ob clamp level). Test Mode 1. Should always be set to 00. Test Mode 2. Should always be set to 000. SHP/SHD Input Polarity (0 = active low, 1 = active high). DATACLK Input Polarity (0 = active low, 1 = active high). CLPOB Input Polarity (0 = active low, 1 = active high). PBLK Input Polarity (0 = active low, 1 = active high). Three-State Data Outputs (0 = outputs active, 1 = outputs three-stated). Data Output Latching (0 = latched by DATACLK, 1 = latch is transparent). Data Output Coding (0 = binary output, 1 = gray code output). Test Mode. Should always be set to 00000. OB Clamp Level (AD9943: 0 = 0 LSB, 255 = 63.75 LSB, AD9944: 0 = 0 LSB, 255 = 255 LSB). VGA Gain (0 = 6 dB, 1023 = 40 dB). Rev. C | Page 12 of 20 Data Sheet AD9943/AD9944 SERIAL INTERFACE TEST BIT A0 SDATA A2 A1 tDS 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 tDH SCK tLS tLH SL 02905-B-011 NOTES 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE. 3. ALL 12 DATA BITS D0–D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE USED FOR THE UNDEFINED BITS. 4. TEST BIT IS FOR INTERNAL USE ONLY AND MUST BE SET LOW. Figure 10. Serial Write Operation DATA FOR STARTING REGISTER ADDRESS TEST BIT SCK A0 1 A1 2 A2 3 D0 0 4 5 D1 6 D2 7 D3 8 D4 9 D5 10 ... D10 15 D11 16 D0 17 D1 18 ... D10 D11 27 28 D0 29 D1 30 D2 31 ... ... ... SL NOTES 1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 12-BIT DATA-WORDS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 12-BIT DATA-WORD. (ALL 12 BITS MUST BE WRITTEN.) 4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. NEW DATA IS UPDATED AT THE NEXT SL RISING EDGE. Figure 11. Continuous Serial Write Operation to All Registers Rev. C | Page 13 of 20 02905-B-012 SDATA DATA FOR NEXT REGISTER ADDRESS AD9943/AD9944 Data Sheet CIRCUIT DESCRIPTION AND OPERATION DC RESTORE INTERNAL VREF 6dB TO 40dB CCDIN 2V FULL SCALE VGA CDS 10/12 10-/12-BIT ADC 10 CLPOB OPTICAL BLACK CLAMP 8-BIT DAC DOUT DIGITAL FILTERING VGA GAIN REGISTER 8 CLAMP LEVEL REGISTER 02905-B-013 0.1µF Figure 12. CCD Mode Block Diagram The AD9943/AD9944 signal processing chain is shown in Figure 12. Each processing step is essential for achieving a high quality image from the raw CCD pixel data. DC RESTORE To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 µF series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, which is compatible with the 3 V single supply of the AD9943/AD9944. CORRELATED DOUBLE SAMPLER The CDS circuit samples each CCD pixel twice to extract video information and reject low frequency noise. The timing shown in Figure 14 illustrates how the two CDS clocks, SHP and SHD, are used, respectively, to sample the reference level and data level of the CCD signal. The CCD signal is sampled on the rising edges of SHP and SHD. Placement of these two clock signals is critical for achieving the best performance from the CCD. An internal SHP/SHD delay (tID) of 3 ns is caused by internal propagation delays. OPTICAL BLACK CLAMP The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD’s black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with the fixed black level reference selected by the user in the clamp level register. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the post processing, the optical black clamping for the AD9943/AD9944 may be disabled using Bit D3 in the operation register. Refer to Table 8 and Figure 10 and Figure 11. When the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. Horizontal timing is shown in Figure 15. The CLPOB pulse should be placed during the CCD’s optical black pixels. It is recommended that the CLPOB pulse be used during valid CCD dark pixels. The CLPOB pulse should be a minimum of 20 pixels wide to minimize clamp noise. Shorter pulse widths may be used, but clamp noise may increase and the loop’s ability to track low frequency variations in the black level is reduced. Rev. C | Page 14 of 20 Data Sheet AD9943/AD9944 A/D CONVERTER 42 The VGA stage provides a gain range of 6 dB to 40 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. A plot of the VGA gain curve is shown in Figure 13. VGA Gain (dB ) = (VGA Code × 0.035 dB ) + 5.3 dB 30 34 18 12 6 0 127 255 383 511 639 767 VGA GAIN REGISTER MODE Figure 13. VGA Gain Curve Rev. C | Page 15 of 20 895 1023 02905-B-014 VARIABLE GAIN AMPLIFIER 36 VGA GAIN (dB) The ADC uses a 2 V input range. Better noise performance results from using a larger ADC full-scale range. The ADC uses a pipelined architecture with a 2 V full-scale input for low noise performance. AD9943/AD9944 Data Sheet CCD MODE TIMING CCD SIGNAL N+2 N+1 N tID N+9 N + 10 tID SHP tCP tS2 tS1 SHD DATACLK tOD N – 10 N–9 N–8 N–1 N 02905-B-015 OUTPUT DATA NOTES 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. Figure 14. CCD Mode Timing EFFECTIVE PIXELS OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS CCD SIGNAL CLPOB PBLK EFFECTIVE PIXEL DATA OB PIXEL DATA NOTES 1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB. 2. PBLK SIGNAL IS OPTIONAL. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES. Figure 15. Typical CCD Mode Line Clamp Timing Rev. C | Page 16 of 20 DUMMY BLACK EFFECTIVE DATA 02905-B-016 OUTPUT DATA Data Sheet AD9943/AD9944 APPLICATIONS INFORMATION output data is then processed by the image processing ASIC. The internal registers of the AD9943/AD9944—used to control gain, offset level, and other functions—are programmed by the ASIC or microprocessor through a 3-wire serial digital interface. A system timing generator provides the clock signals for both the CCD and the AFE. The AD9943/AD9944 are complete analog front end (AFE) products for digital still camera and camcorder applications. As shown in Figure 12, the CCD image (pixel) data is buffered and sent to the AD9943/AD9944 analog input through a series input capacitor. The AD9943/AD9944 perform the dc restoration, CDS, gain adjustment, black level correction, and analog-to-digital conversion. The AD9943/AD9944’s digital AD9943/AD9944 CCD VOUT ADCOUT 0.1µF CCDIN REGISTER DATA BUFFER DIGITAL OUTPUTS DIGITAL IMAGE PROCESSING ASIC SERIAL INTERFACE CCD TIMING 02905-B-017 CDS/CLAMP TIMING V-DRIVE TIMING GENERATOR Figure 16. System Applications Diagram SL SDTA SCK NC NC NC NC NC 3 SERIAL INTERFACE 32 31 30 29 28 27 26 25 D0 1 24 REFB 1.0µF D1 2 23 REFT 1.0µF D2 3 22 CCDIN D3 4 AD9943 21 AVSS D4 5 AVDD 6 TOP VIEW (Not to Scale) 20 D5 19 SHD D6 7 18 SHP D7 8 17 CLPOB 0.1µF CCDIN 3V ANALOG SUPPLY 0.1µF PBLK DVSS DATACLK DVDD DRVSS DRVDD 10 5 3V DRIVER SUPPLY CLOCK INPUTS 3V ANALOG SUPPLY 0.1µF 0.1µF 02905-018 DATA OUTPUTS D9 D8 9 10 11 12 13 14 15 16 NC = NO CONNECT Figure 17. AD9943 Recommended Circuit Configuration for CCD Mode Rev. C | Page 17 of 20 AD9943/AD9944 Data Sheet SL SCK NC NC D1 NC D0 SDTA 3 SERIAL INTERFACE 32 31 30 29 28 27 26 25 D2 1 24 REFB 1.0µF D3 2 23 REFT 1.0µF D4 3 22 CCDIN D5 4 AD9944 21 AVSS D6 5 AVDD 6 TOP VIEW (Not to Scale) 20 D7 19 SHD D8 7 18 SHP D9 8 17 CLPOB 0.1µF CCDIN 3V ANALOG SUPPLY 0.1µF DATA OUTPUTS PBLK DVSS DATACLK DVDD DRVSS D11 DRVDD D10 9 10 11 12 13 14 15 16 12 5 3V DRIVER SUPPLY CLOCK INPUTS 3V ANALOG SUPPLY 0.1µF 02905-019 0.1µF NC = NO CONNECT Figure 18. AD9944 Recommended Circuit Configuration for CCD Mode INTERNAL POWER-ON RESET CIRCUITRY After power-on, the AD9943/AD9944 automatically reset all internal registers and perform internal calibration procedures. This takes approximately 1 ms to complete. During this time, normal clock signals and serial write operations may occur. However, serial register writes are ignored until the internal reset operation is completed. GROUNDING AND DECOUPLING RECOMMENDATIONS As shown in Figure 17 and Figure 18, a single ground plane is recommended for the AD9943/AD9944. This ground plane should be as continuous as possible. This ensures that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All decoupling capacitors should be located as close as possible to the package pins. A single clean power supply is recommended for the AD9943 and AD9944, but a separate digital driver supply may be used for DRVDD (Pin 11). DRVDD should always be decoupled to DRVSS (Pin 12), which should be connected to the analog ground plane. Advantages of using a separate digital driver supply include using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing digital power dissipation and potential noise coupling. If the digital outputs must drive a load larger than 20 pF, buffering is the recommended method to reduce digital code transition noise. Alternatively, placing series resistors close to the digital output pins may also help reduce noise. Note: The exposed pad on the bottom of the AD9943/AD9944 should be soldered to the GND plane of the printed circuit board. Rev. C | Page 18 of 20 Data Sheet AD9943/AD9944 OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 19. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9943KCPZ AD9943KCPZRL AD9944KCPZ AD9944KCPZRL 1 Temperature Range −20°C to +85°C −20°C to +85°C −20°C to +85°C −20°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ] Z = RoHS Compliant Part. Rev. C | Page 19 of 20 Package Option CP-32-7 CP-32-7 CP-32-7 CP-32-7 AD9943/AD9944 Data Sheet NOTES ©2004–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02905-0-3/14(C) Rev. C | Page 20 of 20