AVAGO ACPM-7311-BLKR Low quiescent current Datasheet

ACPM-7311-OR1
UMTS800 4x4 Power Amplifier Module
(824-849 MHz)
Data Sheet
Description
Features
The ACPM-7311, a Wide-band Code Division Multiple
Access (WCDMA) Power Amplifier (PA), is a fully matched
10-pin surface mount module developed for WCDMA
handset applications. This power amplifier module
operates in the 824-849MHz bandwidth. The ACPM-7311
meets the stringent WCDMA linearity requirements for
output power of up to 28dBm. The ACPM-7311 is also
developed to meet HSDPA specs.
• Excellent Linearity
The ACPM-7311 is designed to enhance the efficiency at
low and medium output power range by using 3-mode
control scheme with 2 mode control pins. This provides
extended talk time.
The ACPM-7311 is self contained, incorporating 50ohm
input and output matching networks.
Order information
• Low quiescent current
• High Efficiency
PAE at 28dBm: 39.8%
PAE at 16dBm: 15.9%
PAE at 8dBm: 5.8%
• 10-pin surface mounting package
(4mmx4mmx1.1mm)
• Internal 50ohm matching networks for both RF input
and output
• RoHS Compliant
Applications
• WCDMA Handset (HSDPA)
Part Number
No. of Devices
Container
ACPM-7311-OR1
1000
7” Tape and Reel
ACPM-7311-BLKR
100
BULK
Functional Block Diagram
Ven (1)
Vmode0 (2)
Vmode1 (3)
MODULE
TR Switch
Bias Circuit & Control Logic
Vcc1
(5)
RF Input
(4)
Input
Match
DA
Inter
Stage
Match
Output
Match
PA
MMIC
Vcc2 (6)
RF Output
(8)
Table 1. Absolute Maximum Ratings [1]
Parameter
Symbol
Min
Nominal
Max
Unit
RF Input Power
Pin
–
–
10.0
dBm
DC Supply Voltage
Vcc
0
3.4
5.0
V
Enable Voltage
Ven
0
2.6
3.3
V
Mode Control Voltage
Vmode0
0
2.6
3.3
V
Vmode1
0
2.6
3.3
V
Tstg
-55
–
+125
°C
Storage Temperature
Table 2. Recommended Operating Condition
Parameter
Symbol
Min
Nominal
Max
Unit
DC Supply Voltage
Vcc
3.2
3.4
4.2
V
PA Enable
Ven
1.9
2.6
2.9
V
Vmode0
Vmode1
0
0
0
0
0.5
0.5
V
V
– Mid Power Mode
Vmode0
Vmode1
1.9
0
2.6
0
2.9
0.5
V
V
– Low Power Mode
Vmode0
Vmode1
1.9
1.9
1.9
1.9
2.9
2.9
V
V
Operating Frequency
Fo
824
849
MHz
Case Operating Temperature
To
-20
90
°C
Mode Control Voltage
– High Power Mode
25
Table 3. Power Range Truth Table 2]
Power Mode
Symbol
Ven
Vmode0
Vmode1
Range
High Power Mode
PR3
High
Low
Low
~ 28dBm
Mid Power Mode
PR2
High
High
Low
~ 16dBm
Low Power Mode
PR1
High
High
High
~ 8dBm
Shut Down Mode
–
Low
–
-
–
Notes:
1. No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value.
2. High (1.9–2.9V), Low (0.0V–0.5V).
Table 4. Electrical Characteristics for WCDMA Mode (Vcc=3.4V, Ven=2.6V, T=25°C, Zin/Zout=50ohm) [1]
Characteristics
Symbol
Operating Frequency Range
F
Gain
Gain_hi
Gain_mid
Min.
Typ.
Max.
Unit
824
–
849
MHz
High Power Mode, Pout=28.0 dBm
23.5
26
dB
Mid Power Mode, Pout=16.0 dBm
12.5
16
dB
Gain_low
Low Power Mode, Pout=8.0 dBm
11.5
15
dB
PAE_hi
High Power Mode, Pout=28.0 dBm
35.3
39.8
%
PAE_mid
Mid Power Mode, Pout=16.0 dBm
13.1
15.9
%
PAE_low
Low Power Mode, Pout=8.0 dBm
4.4
5.8
%
Icc_hi
High Power Mode, Pout=28.0 dBm
465
525
mA
Icc_mid
Mid Power Mode, Pout=16.0 dBm
72
87
mA
Icc_low
Low Power Mode, Pout=8.0 dBm
31
41
mA
Iq_hi
High Power Mode
97
120
mA
Iq_mid
Mid Power Mode
14
22
mA
Iq_low
Low Power Mode
11
18
mA
Ien_hi
High Power Mode
0.18
1
mA
Ien_mid
Mid Power Mode
0.18
1
mA
Ien_low
Low Power Mode
0.18
1
mA
Imode0_mid
Mid Power Mode
0.4
1
mA
Imode1_low
Low Power Mode
0.18
1
mA
Imode0_low
Low Power Mode
0.4
1
mA
Total Current in Power-down mode
Ipd
Ven=0V
0.2
5
µA
Adjacent Channel
Leakage Ratio [2]
5 MHz offset
10 MHz offset
ACLR1_hi
ACLR2_hi
High Power Mode, Pout=28.0 dBm
-42
-54
-37
-46
dBc
dBc
5 MHz offset
10 MHz offset
ACLR1_mid
ACLR2_mid
Mid Power Mode, Pout=16.0 dBm
-47
-57
-37
-46
dBc
dBc
5 MHz offset
10 MHz offset
ACLR1_low
ACLR2_low
Low Power Mode, Pout=8.0 dBm
-39
-57
-36
-46
dBc
dBc
Second
Third
2f0
3f0
High Power Mode, Pout=28.0 dBm
-36
-55
-31
-45
dBc
dBc
1.2:1
2.0:1
Power Added Efficiency
Total Supply Current
Quiescent Current
Enable Current
Control Current
Harmonic
Suppression
Condition
Input VSWR
VSWR
Stability (Spurious Output)
S
VSWR 6:1, All phase
Noise Power in Rx Band
RxBN
High Power Mode, Pout=28.0 dBm
Phase Discontinuity
PDlow_mid
PDmid_high
Ruggedness
Ru
-60
dBc
-133
dBm/Hz
low power mode<-->mid power mode, at
Pout=8dBm
mid power mode<-->high power mode, at
Pout=16dBm
10
Deg
45
deg
Pout<28.0dBm, Pin<10dBm, All phase
High Power Mode
10:1
VSWR
-136
Notes:
1. Electrical characteristics are specified under WCDMA modulated ( 3GPP Uplink DPCCH + 1DPDCH ) signal
2. ACP is expressed as a ratio of total adjacent power to signal power, both with 3.84MHz bandwidth at specified offsets.
Table 5. Electrical Characteristics for HSDPA Mode (Vcc=3.4V, Ven=2.6V, T=25°C, Zin/Zout=50ohm) [1]
Characteristics
Symbol
Operating Frequency Range
F
Gain
Gain_hih
Gain_midh
Min.
Typ.
Max.
Unit
824
–
849
MHz
High Power Mode, Pout=27.5 dBm
23.5
26
dB
Mid Power Mode, Pout=16.0 dBm
12.5
16
dB
Gain_lowh
Low Power Mode, Pout=8.0 dBm
11.5
15
dB
PAE_hih
High Power Mode, Pout=27.5 dBm
33.7
38.4
%
PAE_midh
Mid Power Mode, Pout=16.0 dBm
13.4
16.3
%
PAE_lowh
Low Power Mode, Pout=8.0 dBm
4.5
6.0
%
Icc_hih
High Power Mode, Pout=27.5 dBm
430
490
mA
Icc_midh
Mid Power Mode, Pout=16.0 dBm
70
85
mA
Icc_lowh
Low Power Mode, Pout=8.0 dBm
30
40
mA
ACLR1_hih
ACLR2_hih
High Power Mode, Pout=27.5 dBm
–
-39
-53
-37
-46
dBc
dBc
5 MHz offset
10 MHz offset
ACLR1_midh
ACLR2_midh
Mid Power Mode, Pout=16.0 dBm
–
-44
-57
-37
-46
dBc
dBc
5 MHz offset
10 MHz offset
ACLR1_lowh
ACLR2_lowh
Low Power Mode, Pout=8.0 dBm
–
-39
-56
-36
-46
dBc
dBc
Power Added Efficiency
Total Supply Current
Adjacent Channel 5 MHz offset
Leakage Ratio [2] 10 MHz offset
Condition
Notes:
1. Electrical characteristics are specified under HSDPA modulated Up-Link signal (DPCCH/DPDCH=12/15, HS-DPCCH/DPDCH=15/15)
2. ACP is expressed as a ratio of total adjacent power to signal power, both with 3.84MHz bandwidth at specified offsets
Characteristics Data (WCDMA, Vcc=3.4V, Ven=2.6V, T=25°C, Zin/Zout=50ohm)
35
500
30
Current (mA)
Gain (dB)
25
20
15
824MHz
-10
-5
0
5
10
15
Pout (dBm)
20
25
200
150
-5
0
5
10
15
Pout (dBm)
20
25
30
-30
824MHz
40
-35
837MHz
35
849MHz
-40
ACLR1 (dBc)
30
PAE (%)
250
Figure 2. Gain vs. Output Power
45
25
20
15
-45
-50
824MHz
10
-55
5
837MHz
849MHz
0
-10
-5
0
5
10
15
20
25
30
Pout (dBm)
Figure 3. Power Added Efficiency vs. Output Power
824MHz
-45
837MHz
849MHz
-50
-55
-60
-65
-70
-10
-5
0
5
10
15
Pout (dBm)
-60
-10
-5
0
5
10
15
Pout (dBm)
20
25
Figure 4. Adjacent Channel Leakage Ratio 1 vs. Output Power
-40
ACLR2 (dBc)
849MHz
300
0
-10
30
Figure 1. Total Current vs. Output Power
20
25
Figure 5. Adjacent Channel Leakage Ratio 2 vs. Output Power
837MHz
350
50
849MHz
5
824MHz
400
100
837MHz
10
450
30
30
Characteristics Data (HSDPA, Vcc=3.4V, Ven=2.6V, T=25°C, Zin/Zout=50ohm)
35
450
824MHz
400
837MHz
350
849MHz
30
25
300
Gain (dB)
Current (mA)
500
250
200
15
150
824MHz
100
10
50
0
-10
-5
0
5
10
15
Pout (dBm)
20
25
5
30
0
5
10
15
Pout (dBm)
20
25
30
-30
-35
837MHz
35
849MHz
-40
ACLR1 (dBc)
30
PAE (%)
-5
824MHz
40
25
20
15
-45
-50
824MHz
10
-55
5
837MHz
849MHz
-10
-5
0
5
10
15
Pout (dBm)
20
25
30
Figure 8. Power Added Efficiency vs. Output Power
824MHz
-45
837MHz
849MHz
-50
-55
-60
-65
-70
-10
-5
0
5
10
15
Pout (dBm)
-60
-10
-5
0
5
10
15
Pout (dBm)
20
25
Figure 9. Adjacent Channel Leakage Ratio 1 vs. Output Power
-40
ACLR2 (dBc)
-10
Figure 7. Gain vs. Output Power
45
20
25
Figure 10. Adjacent Channel Leakage Ratio 2 vs. Output Power
837MHz
849MHz
Figure 6. Total Current vs. Output Power
0
20
30
30
Evaluation Board Description
Ven
Vmode0
C1
100pF
Vmode1
C2
100pF
C3
100pF
RF In
1 Ven
GND 10
2 Vmode0
GND 9
3 Vmode1
RF Out 8
RF Out
4 RF In
GND 7
Vcc2
Vcc1
C5
2.2uF
5 Vcc1
C4
680pF
Vcc2 6
Figure 11. Evaluation Board Schematic
C3
C2
C1
○
AVAGO
ACPM -7311
TYYWW
OLXXXXXX
C4
C5
Figure 12. Evaluation Board Assembly Diagram
C6
C7
C6
680pF
C7
2.2uF
Package Dimensions and Pin Descriptions
0.70 TYP.
Pin 1 Mark
1
10
2
9
3
8
4
7
5
6
4.0 ± 0.1
1.1 ± 0.1
4.0 ± 0.1
TOP VIEW
SIDE VIEW
Pin #
Name
Description
1
Ven
Enable Voltage
2
Vmode0
Control Voltage
3
Vmode1
Control Voltage
4
RF In
RF Input
5
Vcc1
Supply Voltage
6
Vcc2
Supply Voltage
7
GND
Ground
8
RF Out
RF Output
9
GND
Ground
10
GND
Ground
PIN DESCRIPTIONS
X-RAY BOTTOM VIEW
Figure 13. Package Dimensional Drawing and Pin Descriptions (All dimensions are in millimeters)
Pin 1 Mark
AVAGO
ACPM-7311
TYYWW
OLXXXXXX
Figure 14. Marking Specifications
Manufacturing Part Number
Lot Number
T
YY
WW
OLXXXXXX
Manufacturing info
Manufacturing Year
Work Week
Assembly Lot Number
PCB Design Guidelines
Stencil Design Guidelines
The recommended ACPM-7311 PCB land pattern is shown
in Figure 15 and Figure 16. The substrate is coated with
solder mask between the I/O and conductive paddle to
protect the gold pads from short circuit that is caused by
solder bleeding/bridging.
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads. The recommended stencil layout is
shown in Figure 17. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil
openings larger than 100% will lead to excessive solder
paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Considering the fact
that solder paste thickness will directly affect the quality
of the solder joint, a good choice is to use laser cut stencil
composed of 0.10mm(4mils)or 0.127mm(5mils) thick
stainless steel which is capable of producing the required
fine stencil outline.
0.1
0.6
0.4
0.6
0.5
0.4
0.85
1.6
0.25
0.5
Ø 0.3mm
on 0.6mm pitch
Figure 15. Metallization
0.7
0.85
0.55
2.0
0.5
1.8
0.85
2.4
Figure 16. Solder Mask Opening
Figure 17. Solder Paste Stencil Aperture
Tape and Reel Information
AVAGO
ACPM-7311
TYYWW
OLXXXXXX
Dimension List
Dimension
Millimeter
Dimension
A0
4.40±0.10
P2
2.00±0.05
B0
4.40±0.10
P10
40.00±0.20
K0
1.70±0.10
E
1.75±0.10
D0
1.55±0.05
F
5.50±0.05
D1
1.60±0.10
W
12.00±0.30
P0
4.00±0.10
T
0.30±0.05
P1
8.00±0.10
Figure 18. Tape and Reel Format – 4 mm x 4 mm.
10
Millimeter
Reel Drawing
BACK VIEW
Shading indicates
thru slots
18.4 max.
178 +0.4
-0.2
50 min.
25
min wide (ref)
Slot for carrier tape
insertion for attachment
to reel hub (2 places 180° apart)
12.4 +2.0
-0.0
FRONT VIEW
1.5 min.
13.0 ± 0.2
21.0 ± 0.8
Figure 19. Plastic Reel Format (all dimensions are in millimeters)
11
NOTES:
1. Reel shall be labeled with the following
information (as a minimum).
a. manufacturers name or symbol
b. Avago Technologies part number
c. purchase order number
d. date code
e. quantity of units
2. A certificate of compliance (c of c) shall
be issued and accompany each shipment
of product.
3. Reel must not be made with or contain
ozone depleting materials.
4. All dimensions in millimeters (mm)
Handling and Storage
ESD (Electrostatic Discharge)
Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of
neutralization or discharge will be sought. If the acquired
discharge route is through a semiconductor device, destructive damage will result.
ESD countermeasure methods should be developed and
used to control potential ESD damage during handling in
a factory environment at each manufacturing site.
MSL (Moisture Sensitivity Level)
Plastic encapsulated surface mount package is sensitive
to damage induced by absorbed moisture and temperature.
Avago Technologies follows JEDEC Standard J-STD 020B.
Each component and package type is classified for
moisture sensitivity by soaking a known dry package at
various temperatures and relative humidity, and times.
After soak, the components are subjected to three consecutive simulated reflows.
The out of bag exposure time maximum limits are determined by the classification test describe below which corresponds to a MSL classification level 6 to 1 according to
the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033.
ACPM-7311 is MSL3. Thus, according to the J-STD-033
p.11 the maximum Manufacturers Exposure Time (MET)
for this part is 168 hours. After this time period, the part
would need to be removed from the reel, de-taped and
then re-baked. MSL classification reflow temperature for
the ACPM-7311 is targeted at 260°C +0/-5°C. Figure 20
and Table 8 show typical SMT profile for maximum temperature of 260 +0/-5°C.
Table 6. ESD Classification
Pin #
Name
Description
HBM
CDM
Classification
1
Ven
Enable Voltage
± 2000V
± 200V
Class 2
2
Vmode0
Mode Control
± 2000V
± 200V
Class 2
3
Vmode1
Mode Control
± 2000V
± 200V
Class 2
4
RF In
RF Input
± 2000V
± 200V
Class 2
5
Vcc1
Supply Voltage
± 2000V
± 200V
Class 2
6
Vcc2
Supply Voltage
± 2000V
± 200V
Class 2
7
GND
Ground
± 2000V
± 200V
Class 2
8
RF Out
RF Output
± 2000V
± 200V
Class 2
9
GND
Ground
± 2000V
± 200V
Class 2
10
GND
Ground
± 2000V
± 200V
Class 2
Note :
1. Module products should be considered extremely ESD sensitive.
Table 7. Moisture Classification Level and Floor Life
MSL
Level
Floor Life (out of bag) at factory ambient
=< 30°C/60% RH or as stated
1
Unlimited at =< 30°C/85% RH
2
1 year
2a
4 weeks
3
168 hours
4
72 hours
5
48 hours
5a
24 hours
6
Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label
Note :
1. The MSL Level is marked on the MSL Label on each shipping bag.
12
tp
Tp
Critical Zone
T L to Tp
Temperature
Ramp-up
TL
tL
Ts max
Ts min
Ramp-down
ts
Preheat
25
t 25oC to Peak
Time
Figure 20. Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C
Table 8. Typical SMT Reflow Profile for Maximum Temperature = 260+0 / -5°C
Profile Feature
Sn-Pb Solder
Pb-Free Solder
Average ramp-up rate (TL to TP)
3°C/sec max
3°C /sec max
100°C
150°C
60-120 sec
150°C
200°C
60-180 sec
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Tsmax to TL
- Ramp-up Rate
3°C /sec max
Time maintained above:
- Temperature (TL)
- Time (TL)
183°C
60-150 sec
217°C
60-150 sec
Peak temperature (Tp)
240 +0/-5°C
260 +0/-5°C
10-30 sec
20-40 sec
6°C /sec max
6°C /sec max
6 min max.
8 min max.
Time within 5°C of actual Peak Temperature (tp)
Ramp-down Rate
Time 25°C to Peak Temperature
13
Storage Condition
Baking of Populated Boards
Packages described in this document must be stored
in sealed moisture barrier, antistatic bags. Shelf life in a
sealed moisture barrier bag is 12 months at <40°C and
90% relative humidity (RH) J-STD-033 p.7.
After unpacking the device must be soldered to the PCB
within 168 hours as listed in the J-STD-020B p.11 with
factory conditions <30°C and 60% RH.
Some SMD packages and board materials are not able to
withstand long duration bakes at 125°C. Examples of this
are some FR-4 materials, which cannot withstand a 24 hr
bake at 125°C. Batteries and electrolytic capacitors are
also temperature sensitive. With component and board
temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the
appropriate bake duration based on the component to
be removed. For additional considerations see IPC-7711
andIPC-7721.
Baking
Derating due to Factory Environmental Conditions
Out-of-Bag Time Duration
It is not necessary to re-bake the part if both conditions
(storage conditions and out-of bag conditions) have been
satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125°C for 12 hours J-STD-033 p.8.
CAUTION
Tape and reel materials typically cannot be baked at the
temperature described above. If out-of-bag exposure
time is exceeded, parts must be baked for a longer time
at low temperatures, or the parts must be de-reeled, detaped, re-baked and then put back on tape and reel. (See
moisture sensitive warning label on each shipping bag for
information of baking).
Board Rework
Component Removal, Rework and Remount
If a component is to be removed from the board, it is
recommended that localized heating be used and the
maximum body temperatures of any surface mount
component on the board not exceed 200°C. This method
will minimize moisture related component damage. If any
component temperature exceeds 200°C, the board must
be baked dry per 4-2 prior to rework and/or component
removal. Component temperatures shall be measured at
the top center of the package body. Any SMD packages
that have not exceeded their floor life can be exposed to
a maximum body temperature as high as their specified
maximum reflow temperature.
Removal for Failure Analysis
Not following the above requirements may cause
moisture/reflow damage that could hinder or completely prevent the determination of the original failure
mechanism.
14
Factory floor life exposures for SMD packages removed
from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling
approach is to expose the SMD packages only up to the
maximum time limits for each moisture sensitivity level as
shown in Table 7. This approach, however, does not work
if the factory humidity or temperature is greater than the
testing conditions of 30°C/60% RH. A solution for addressing this problem is to derate the exposure times based on
the knowledge of moisture diffusion in the component
package materials ref. JESD22-A120). Recommended
equivalent total floor life exposures can be estimated for
a range of humidities and temperatures based on the
nominal plastic thickness for each device.
Table 9 lists equivalent derated floor lives for humidities
ranging from 20-90% RH for three temperature, 20°C,
25°C, and 30°C.
This table is applicable to SMDs molded with novolac,
biphenyl or multifunctional epoxy mold compounds. The
following assumptions were used in calculating Table 9:
1. Activation Energy for diffusion = 0.35eV (smallest
known value).
2. For ≤60% RH, use Diffusivity = 0.121exp ( -0.35eV/kT)
mm2/s (this used smallest known Diffusivity @ 30°C).
3. For >60% RH, use Diffusivity = 1.320exp ( -0.35eV/kT)
mm2/s (this used largest known Diffusivity @ 30°C).
Table 9. Recommended Equivalent Total Floor Life (days) @ 20 °C, 25 °C & 30 °C For ICs with Novolac, Biphenyl and Multifunctional Epoxies
(Reflow at same temperature at which the component was classified)
Maximum Percent Relative Humidity
Package Type and Body Thickness
Moisture Sensitivity Level
5%
10%
Body Thickness ≥3.1 mm
Including
PQFPs >84 pin,
PLCCs (square)
All MQFPs
or
All BGAs ≥1 mm
Level 2a
∞
∞
∞
∞
∞
∞
∞
∞
∞
60
78
103
41
53
69
33
42
57
28
36
47
10
14
19
7
10
13
6
8
10
30°
25°
20°
Level 3
∞
∞
∞
∞
∞
∞
10
13
17
9
11
14
8
10
13
7
9
12
7
9
12
5
7
10
4
6
8
4
5
7
30°
25°
20°
Level 4
∞
∞
∞
5
6
8
4
5
7
4
5
7
4
5
7
3
5
7
3
4
6
3
3
5
2
3
4
2
3
4
30°
25°
20°
Level 5
∞
∞
∞
4
5
7
3
5
7
3
4
6
2
4
5
2
3
5
2
3
4
2
2
3
1
2
2
1
2
3
30°
25°
20°
Level 5a
∞
∞
∞
2
3
5
1
2
4
1
2
3
1
2
3
1
2
3
1
2
2
1
1
2
1
1
2
1
1
2
30°
25°
20°
Level 2a
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
86
148
∞
39
51
69
28
37
49
4
6
8
3
4
5
2
3
4
30°
25°
20°
Level 3
∞
∞
∞
∞
∞
∞
19
25
32
12
15
19
9
12
15
8
10
13
7
9
12
3
5
7
2
3
5
2
3
4
30°
25°
20°
Level 4
∞
∞
∞
7
9
11
5
7
9
4
5
7
4
5
6
3
4
6
3
4
5
2
3
4
2
2
3
1
2
3
30°
25°
20°
Level 5
∞
∞
∞
4
5
6
3
4
5
3
3
5
2
3
4
2
3
4
2
3
4
1
2
3
1
1
3
1
1
2
30°
25°
20°
Level 5a
∞
∞
∞
2
2
3
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
1
2
0.5
1
2
0.5
1
1
30°
25°
20°
Level 2a
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
28
∞
∞
1
2
2
1
1
2
1
1
1
30°
25°
20°
Level 3
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
11
14
20
7
10
13
1
2
2
1
1
2
1
1
1
30°
25°
20°
Level 4
∞
∞
∞
∞
∞
∞
∞
∞
∞
9
12
17
5
7
9
4
5
7
3
4
6
1
2
2
1
1
2
1
1
1
30°
25°
20°
Level 5
∞
∞
∞
∞
∞
∞
13
18
26
5
6
8
3
4
6
2
3
5
2
3
4
1
2
2
1
1
2
1
1
1
30°
25°
20°
Level 5a
∞
∞
∞
10
13
18
3
5
6
2
3
4
1
2
3
1
2
2
1
2
2
1
1
2
1
1
2
0.5
1
1
30°
25°
20°
Body 2.1 mm
≤ Thickness
<3.1 mm including
PLCCs (rectangular)
18-32 pin
SOICs (wide body)
SOICs ≥20 pins,
PQFPs ≤80 pins
Body Thickness <2.1 mm
including
SOICs <18 pin
All TQFPs, TSOPs
or
All BGAs <1 mm body
thickness
15
20% 30% 40% 50%
60% 70% 80%
90%
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved.
AV01-0607EN - November 21, 2006