Intersil HMP8171CN Ntsc/pal video encoder Datasheet

HMP8170, HMP8171, HMP8172, HMP8173
Data Sheet
May 1999
File Number
4284.5
NTSC/PAL Video Encoder
Features
The HMP8170, HMP8171, HMP8172, and HMP8173 NTSC
and PAL encoders are designed for use in systems requiring
the generation of high-quality NTSC and PAL video.
• (M) NTSC and (B, D, G, H, I, M, N, NC) PAL Operation
YCbCr digital video data drive the P0-P15 inputs. The Y data
is optionally lowpass filtered to 6MHz and drives the Y analog
output. Cb and Cr are each lowpass filtered to 1.3MHz,
quadrature modulated, and added together. The result drives
the C analog output. The digital Y and C data are also added
together and drive the two composite analog outputs.
The DACs can drive doubly-terminated (37.5Ω) lines, and
run at a 2x oversampling rate to simplify the analog output
filter requirements.
Applications
• DVD Players
• BT.601 and Square Pixel Operation
• Digital Input Formats
- 8-bit, 16-bit 4:2:2 YCbCr
- 8-bit BT.656
• Analog Output Formats
- Y/C + Two Composite
- RGB + Composite
- YUV + Composite
• Flexible Video Timing Control
- Timing Master or Slave
- Selectable Polarity on Each Control Signal
- Programmable Blank Output Timing
• “Sliced” VBI Data Support
- Closed Captioning
- Widescreen Signalling (WSS)
- BT.653 System B and C Teletext
- NABTS (North American Broadcast Teletext)
- WST (World System Teletext)
• Video CD Players
• Digital VCRs
• Multimedia PCs
Related Products
• Four 2x Oversampling, 10-Bit DACs
• NTSC/PAL Encoders
- HMP8154, HMP8156A
• Fast I2C Interface
• NTSC/PAL Decoders
- HMP8115
Ordering Information
PART NUMBER
MACROVISION
v7.01
RGB / YUV
OUTPUTS
TEMP. RANGE
(oC)
PACKAGE
no
no
0 to 70
64 Ld PQFP (Note 2)
Q64.14x14
yes
no
0 to 70
64 Ld PQFP (Note 2)
Q64.14x14
no
yes
0 to 70
64 Ld PQFP (Note 2)
Q64.14x14
yes
yes
0 to 70
64 Ld PQFP (Note 2)
Q64.14x14
HMP8170CN
HMP8171CN
(Note 1)
HMP8172CN
HMP8173CN
(Note 1)
HMP817xEVAL1
PKG. NO.
Daughter Card Evaluation Platform, where x is replaced by 0, 1, 2, or 3 (Note 3).
NOTES:
1. The HMP8171 and HMP8173 may be purchased by Macrovision Authorized Buyers only. These devices are protected by U.S. patent numbers
4,631,603, 4,577,216, and 4,819,098, and other intellectual property rights. The use of Macrovision’s copy protection technology in the devices
must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing
by Macrovision. Reverse engineering or disassembly is prohibited.
2. PQFP is also known as QFP and MQFP.
3. Evaluation board descriptions are in the Applications section.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Intercast™ is a trademark of Intel Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
2
CLK2
CLK
BLANK
VSYNC
HSYNC
RESET
SDA
SCL
SA
P0 - P15
CONTROL
TIMING
VIDEO
HOST
INTERFACE
4:2:2 TO
4:4:4 SAMPLE
CONVERSION
FIELD
(4:4:4
TO
8:8:8)
2X
UPSAMPLE
Cb/Cr
Y
CHROMA
MODULATION
LP FILTER
LP FILTER
(OPTIONAL)
MACROVISION
PROCESSING
(HMP8171 AND
HMP8173 ONLY)
VBI
DATA
PROCESSING
DAC
DAC
DAC
DAC
INTERNAL
1.195V
REFERENCE
C
NTSC/
PAL 2
NTSC/
PAL 1
Y
FS
ADJUST
VREF
HMP8170, HMP8171, HMP8172, HMP8173
Functional Block Diagram
HMP8170, HMP8171, HMP8172, HMP8173
Functional Operation
The HMP8170 - HMP8173 are fully integrated digital
encoders. All accept YCbCr digital video input data and
generate analog video output signals. The four outputs are
two composite video signals and Y/C (S-Video). The
HMP8172 and HMP8173 can also be configured to output
one composite and component RGB or YUV video.
The HMP817x accepts pixel data in one of several formats and
transforms it into 4:4:4 sampled luminance and chrominance
(YCbCr) data. The encoder then interpolates the YCbCr data to
twice the pixel rate and low pass filters it to match the
bandwidth of the video output format. If enabled, the encoder
also adds vertical blanking interval (VBI) information to the Y
data. At the same time, the encoder modulates the
chrominance data with a digitally synthesized subcarrier.
Finally, the encoder outputs luminance, chrominance, and their
sum as analog signals using 10-bit D/A converters.
The HMP817x provides operating modes to support all
versions of the NTSC and PAL standards and accepts full
size input data with rectangular (BT.601) and square pixel
aspect ratios. It operates from a single clock at twice the
pixel clock rate determined by the operating mode.
The HMP817x’s video timing control is flexible. It may
operate as the master, generating the system’s video timing
control signals, or it may accept external timing controls. The
polarity of the timing controls and the number of active pixels
and lines are programmable.
Pixel Data Input
The HMP817x accepts BT.601 YCbCr pixel data via the
P0-P15 input pins. The definition of each pixel input pin is
determined by the input format selected in the input format
register. The definition for each mode is shown in Table 1.
The YCbCr luminance and color difference signals are each 8
bits, scaled 0 to 255. The nominal range for Y is 16 (black) to
235 (white). Y values less than 16 are clamped to 16; values
greater than 235 are processed normally. The nominal range
for Cb and Cr is 16 to 240 with 128 representing zero. Cb and
Cr values outside their nominal range are processed normally.
Note that when converted to the analog outputs, some
combinations of YCbCr outside their nominal ranges would
generate a composite video signal larger than the analog
output limit. The composite signal will be clipped, but the
S-video outputs (Y and C) will note be.
The color difference signals are time multiplexed into one
8-bit bus beginning with a Cb sample. The Y and CbCr
busses may be input in parallel (16-bit mode) or may be time
multiplexed and input as a single bus (8-bit mode). The
single bus may also contain SAV and EAV video timing
reference codes or ancillary data (BT.656 mode).
TABLE 1. PIXEL DATA INPUT FORMATS
16-BIT
4:2:2
YCBCR
PIN
NAME
8-BIT
4:2:2
YCBCR
P0
P1
P2
P3
P4
P5
P6
P7
Cb0, Cr0
Cb1, Cr1
Cb2, Cr2
Cb3, Cr3
Cb4, Cr4
Cb5, Cr5
Cb6, Cr6
Cb7, Cr7
Ignored
P8
P9
P10
P11
P12
P13
P14
P15
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y0, Cb0, Cr0
Y1, Cb1, Cr1
Y2, Cb2, Cr2
Y3, Cb3, Cr3
Y4, Cb4, Cr4
Y5, Cb5, Cr5
Y6, Cb6, Cr6
Y7, Cb7, Cr7
BT.656
YCbCr Data,
SAV and EAV
Sequences,
and
Ancillary Data
Pixel Input and Control Signal Timing
The pixel input timing and the video control signal
input/output timing of the HMP817x depend on the part’s
operating mode. The periods when the encoder samples its
inputs and generates its outputs are summarized in Table 2.
Figures 1, 2, and 3 show the timing of CLK, CLK2, BLANK,
and the pixel input data with respect to each other. BLANK
may be an input or an output; the figures show both. When it
is an input, BLANK must arrive coincident with the pixel input
data; all are sampled at the same time.
When BLANK is an output, its timing with respect to the pixel
inputs depends on the blank timing select bit in the
timing_I/O_1 register. If the bit is cleared, the HMP817x
negates BLANK one CLK cycle before it samples the pixel
inputs.
If the bit is set, the encoder negates BLANK during the same
CLK cycle in which it samples the input data. In effect, the
input data must arrive one CLK cycle earlier than when the
bit is cleared. This mode is not shown in the figures.
TABLE 2. PIXEL INPUT AND CONTROL SIGNAL I/O TIMING
VIDEO TIMING CONTROL (NOTE)
CLK FREQUENCY
INPUT PIXEL DATA
SAMPLE
INPUT SAMPLE
OUTPUT ON
INPUT
OUTPUT
Rising edge of CLK2 when CLK is low
Rising edge of CLK2
One-half CLK22
when CLK is high.
8-Bit YCbCr
Every rising edge of CLK2 Every rising edge of CLK2 Any rising edge of CLK2 Ignored
One-half CLK2
BT.656
Every rising edge of CLK2 Not Allowed
Any rising edge of CLK2 Ignored
One-half CLK2
NOTE: Video timing control signals include HSYNC, VSYNC, BLANK and FIELD. The sync and blanking I/O directions are independent; FIELD is
always an output.
INPUT FORMAT
16-Bit YCbCr
3
HMP8170, HMP8171, HMP8172, HMP8173
8-Bit YCbCr Format
8-Bit BT.656 Format
When 8-bit YCbCr format is selected, the data is latched on
each rising edge of CLK2. The pixel data must be [Cb Y Cr Y’
Cb Y Cr Y’ . . . ], with the first active data each scan line being
Cb data. The pixel input timing is shown in Figure 1.
When BT.656 format is selected, data is latched on each
rising edge of CLK2. The pixel input timing is shown in
Figure 3. The figure shows the EAV code at the end of the
line. The format of the SAV and EAV codes are shown in
Table 3.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency.
The BT.656 input may also include ancillary data to load the
VBI or RTCI data registers. The HMP817x will use the
ancillary data when enabled in the VBI data input and Timing
I/O registers. The ancillary data formats and the enable
registers are described later in this data sheet.
16-Bit YCbCr Format
As inputs, the BLANK, HSYNC, and VSYNC pins are
ignored since all timing is derived from the EAV and SAV
sequences within the data stream. As outputs, BLANK,
HSYNC and VSYNC are output following the rising edge of
CLK2. If the CLK pin is configured as an input, it is ignored. If
configured as an output, it is one-half the CLK2 frequency.
When 16-bit YCbCr format is selected, the pixel data is
latched on the rising edge of CLK2 while CLK is low. The
pixel input timing is shown in Figure 2.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In these modes of operation, CLK is
one-half the CLK2 frequency.
CLK2
Cb 0
P8-P15
Y0
Cr 0
Y1
Cb 2
Y2
YN
BLANK
(INPUT)
BLANK
(OUTPUT)
FIGURE 1. PIXEL INPUT TIMING - 8-BIT YCBCR
CLK2
CLK
P8-P15
Y0
Y1
Y2
Y3
Y4
Y5
YN
P0-P7
Cb 0
Cr 0
Cb 2
Cr 2
Cb 4
Cr 4
Cr N-1
BLANK
(INPUT)
BLANK
(OUTPUT)
FIGURE 2. PIXEL INPUT TIMING - 16-BIT YCBCR
4
HMP8170, HMP8171, HMP8172, HMP8173
CLK2
P8-P15
Cb 2
Y2
Cr 2
Y3
Cb 4
Y4
"FF"
"00"
"00"
EAV
"10"
"80"
"10"
BLANK
(OUTPUT)
FIGURE 3. PIXEL INPUT TIMING - BT.656
TABLE 3. BT.656 EAV AND SAV SEQUENCES
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble Word 1
1
1
1
1
1
1
1
1
Preamble Word 2
0
0
0
0
0
0
0
0
Preamble Word 3
0
0
0
0
0
0
0
0
Status Word
1
F
V
H
P3
P2
P1
P0
NOTES:
F: 0 = Field 1; 1 = Field 2
V: 0 = Active Line; 1 = Vertical Blanking
H: 0 = Start Active Video; 1 = End Active Video
P3 - P0: Protection bits; Ignored
Video Timing Control
The pixel input data and the output video timing of the
HMP817x are at 50 or 59.94 fields per second interlaced.
The timing is controlled by the BLANK, HSYNC, VSYNC,
FIELD, and CLK2 pins.
HSYNC, VSYNC, and Field Timing
The leading edge of HSYNC indicates the beginning of a
horizontal sync interval. If HSYNC is an output, it is asserted
for about 4.7µs. If HSYNC is an input, it must be active for at
least two CLK2 periods. The width of the analog horizontal
sync tip is determined from the video standard and does not
depend on the width of HSYNC.
The leading edge of VSYNC indicates the beginning of a
vertical sync interval. If VSYNC is an output, it is asserted for
3 scan lines in (MM) NTSC and (M, N) PAL modes or 2.5
scan lines in (B, D, G, H, I, NC) PAL modes. If VSYNC is an
input, it must be asserted for at least two CLK2 periods.
resets its vertical half-line counter to the value specified by
the field control register. This allows the input and output
syncs to be offset, although the data must still be aligned.
The FIELD signal is always an output and changes state
near each leading edge of VSYNC. The delay between the
syncs and FIELD depends on the encoder’s operating mode
as summarized in Table 4. In modes in which the encoder
uses CLK to gate its inputs and outputs, the FIELD signal
may be delayed 0-12 additional CLK2 periods.
TABLE 4. FIELD OUTPUT TIMING
OPERATING MODE
SYNC I/O
BLANK I/O
CLK2
DIRECTION DIRECTION DELAY
Input
Input
148
The HMP817x provides programmable timing for the
VSYNC input. At the active edge of VSYNC, the encoder
5
FIELD lags VSYNC
switching from odd to
even.
FIELD lags the earlier
of VSYNC and HSYNC
when syncs are aligned
when switching from
even to odd.
When HSYNC and VSYNC are configured as outputs, their
leading edges will occur simultaneously at the start of an
odd field. At the start of an even field, the leading edge of
VSYNC occurs in the middle of the line.
When HSYNC and VSYNC are configured as inputs, the
HMP817x provides a programmable HSYNC window for
determining FIELD. The window is specified with respect to
the leading or trailing edge of VSYNC. The edge is selected
in the field control register. When HSYNC is found inside the
window, then the encoder sets FIELD to the value specified
in the field control register.
COMMENTS
Input
Output
138
Output
Don’t Care 32
FIELD lags VSYNC.
FIELD leads VSYNC.
Figure 4 illustrates the HSYNC, VSYNC, and FIELD general
timing for (M) NTSC and (M, N) PAL. Figure 5 illustrates the
general timing for (B, D, G, H, I, NC) PAL. In the figures, all
the signals are shown active low (their reset state), and
FIELD is low during odd fields.
HMP8170, HMP8171, HMP8172, HMP8173
There must be an even number of active and total pixels per
line. In the 8-bit YCbCr modes, the number of active and
total pixels per line must be a multiple of four. Note that if
BLANK is an output, half-line blanking on the output video
cannot be done.
HSYNC
VSYNC
FIELD
FIGURE 4A. BEGINNING AN ODD FIELD
HSYNC
The HMP817x never adds a 7.5 IRE blanking setup during
the active line time on scan lines 1-21 and 263-284 for (M)
NTSC, scan lines 523-18 and 260-281 for (M) PAL, and scan
lines 623-22 and 311-335 for (B, D, G, H, I, N) PAL, allowing
the generation of video test signals, timecode, and other
information by controlling the pixel inputs appropriately.
The relative timing of BLANK, HSYNC, and the output video
depends on the blanking and sync I/O directions. The typical
timing relation is shown in Figure 6. The delays which vary
with operating mode are indicated. The width of the
composite sync tip and the location and duration of the color
burst are fixed based on the video format.
VSYNC
FIELD
FIGURE 4B. BEGINNING AN EVEN FIELD
.
FIGURE 4. HSYNC, VSYNC, AND FIELD TIMING FOR
(M) NTSC AND (M, N) PAL
COMPOSITE
VIDEO OUT
HSYNC
HSYNC
VSYNC
BLANK
FIELD
DATA PIPE
DELAY
FIGURE 5A. BEGINNING AN ODD FIELD
START H BLANK
SYNC DELAY
FIGURE 6. HSYNC, BLANK, AND OUTPUT VIDEO TIMING,
NORMAL MODE
HSYNC
VSYNC
FIELD
FIGURE 5B. BEGINNING AN EVEN FIELD
FIGURE 5. HSYNC, VSYNC, AND FIELD TIMING FOR
(B, D, G, H, I, NC) PAL
BLANK Timing
The encoder uses the HSYNC, VSYNC, FIELD signals to
generate a standard composite video waveform with no
active video (black burst). The signal includes only sync tips,
color burst, and optionally, a 7.5 IRE blanking setup. Based
on the BLANK signal, the encoder adds the pixel input data
to the video waveform.
The encoder ignores the pixel input data when BLANK is
asserted. Instead of the input data, the encoder generates
the blanking level. The encoder also ignores the pixel inputs
when generating VBI data on a specific line, even if BLANK
is negated.
6
When BLANK is an output, the encoder asserts it during the
inactive portions of active scan lines (horizontal blanking)
and for all of each inactive scan line (vertical blanking). The
inactive scan lines blanked each field are determined by the
start_v_blank and end_v_blank registers. The inactive
portion of active scan lines is determined by the
start_h_blank and end_h_blank registers.
The zero count for horizontal blanking is 32 CLK2 cycles
before the 50% point of the composite sync. From this zero
point, the HMP817x counts every other CLK2 cycle. When
the count reaches the value in the start_h_blank register, the
encoder negates BLANK. When the count reaches the value
in the end_h_blank register, BLANK is asserted. There may
be an additional 0-3 CLK2 delays in modes which use CLK.
The data pipeline delay through the HMP817x is 26 CLK2
cycles. In operating modes which use CLK to gate the
inputs into the encoder, the delay may be an additional 0-7
CLK2 cycles. The delay from BLANK to the start or end of
active video is an additional one-half CLK cycle when the
blank timing select bit is cleared. The active video may also
appear to end early or start late since the HMP817x
controls the blanking edge rates.
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 5. TYPICAL VIDEO TIMING PARAMETERS
PIXELS PER LINE
VIDEO STANDARD
HBLANK REGISTER VALUES
VBLANK REGISTER VALUES
ACTIVE
START
END
START
END
CLK2
(MHz)
858
864
858
864
864
720
720
720
720
720
842 (0x34a)
853 (0x355)
842 (0x34a)
853 (0x355)
853 (0x355)
122 (0x7a)
133 (0x85)
122 (0x7a)
133 (0x85)
133 (0x85)
259 (0x103)
310 (0x136)
259 (0x103)
309 (0x135)
310 (0x136)
19 (0x13)
22 (0x16)
19 (0x13)
21 (0x15)
22 (0x16)
27.0
27.0
27.0
27.0
27.0
780
944
780
944
944
640
768
640
768
768
758 (0x2f6)
923 (0x39b)
758 (0x2f6)
923 (0x39b)
923 (0x39b)
118 (0x76)
155 (0x9b)
118 (0x76)
155 (0x9b)
155 (0x9b)
259 (0x103)
310 (0x136)
259 (0x103)
309 (0x135)
310 (0x136)
19 (0x13)
22 (0x16)
19 (0x13)
21 (0x15)
22 (0x16)
24.54
29.5
24.54
29.5
29.5
TOTAL
RECTANGULAR PIXELS (BT.601)
(M) NTSC
(B, D, G, H, I) PAL
(M) PAL
(N) PAL
(NC) PAL
SQUARE PIXELS
(M) NTSC
(B, D, G, H, I) PAL
(M) PAL
(N) PAL
(NC) PAL
The delay from the active edge of HSYNC to the 50% point of
the composite sync is 4-39 CLK2 cycles depending on the
HMP817x operating mode. The delay is shortest when the
encoder is the timing master; it is longest when in slave mode.
CLK2 Input Timing
The CLK2 input clocks all of the HMP817x, including its
video timing counters. For proper operation, all of the
HMP817x inputs must be synchronous with CLK2. The
frequency of CLK2 depends on the device’s operating mode
and the total number of pixels per line. The standard clock
frequencies are shown in Table 5.
Note that the color subcarrier is derived from the CLK2 input.
Any jitter on CLK2 will be transferred to the color subcarrier,
resulting in color changes. Just 400ps of jitter on CLK2
causes up to a 1 degree color subcarrier phase shift. Thus,
CLK2 should be derived from a stable clock source, such as a
crystal. The use of a PLL to generate CLK2 is not
recommended.
Video Processing
Upsampling
The encoder begins the video processing with the pixel input
data. It converts the 4:2:2 YCbCr data to 4:4:4 data. The
conversion is done by 2x upsampling the Cb and Cr data.
The CbCr upsampling function uses linear interpolation. The
HMP817x then upsamples the 4:4:4 data to generate 8:8:8
data. Again, the encoder uses linear interpolation for the
upsampling.
Horizontal Filtering
Unless disabled, the HMP817x lowpass filters the Y data to
6.0MHz. Lowpass filtering Y removes any aliasing artifacts
due to the upsampling process, and simplifies the analog
output filters. The Y 6.0MHz lowpass filter response is
shown in Figure 7. At this point, the HMP817x also scales
the Y data to generate the proper output levels for the
various video standards.
The HMP817x lowpass filters the Cb and Cr data to 1.3MHz
prior to modulation. The lowpass filtering removes any
aliasing artifacts due to the upsampling process (simplifying
the analog output filters) and also properly bandwidth-limits
Cb and Cr prior to modulation. The chrominance filtering is
not optional like luminance filtering. The Cb and Cr 1.3MHz
lowpass filter response is shown in Figure 8.
7
HMP8170, HMP8171, HMP8172, HMP8173
0
-10
PAL SQUARE PIXEL
CLK2 = 29.50MHz
-20
NTSC OR PAL
RECTANGULAR PIXEL
CLK2 = 27.00MHz
-30
-0.5
ATTENUATION (dB)
ATTENUATION (dB)
0
NTSC SQUARE PIXEL
CLK2 = 24.54MHz
-40
-50
PAL SQUARE PIXEL
CLK2 = 29.50MHz
-1.0
NTSC OR PAL
RECTANGULAR PIXEL
CLK2 = 27.00MHz
-1.5
-2.0
NTSC SQUARE PIXEL
CLK2 = 24.54MHz
-2.5
-3.0
-60
0
2
4
6
8
10
12
14
0
1
2
FREQUENCY (MHz)
FIGURE 7A. FULL SPECTRUM
3
4
FREQUENCY (MHz)
5
6
7
FIGURE 7B. PASS BAND
FIGURE 7. Y LOWPASS FILTER RESPONSE
.
0
0
PAL SQUARE PIXEL
CLK2 = 29.50MHz
-0.5
NTSC OR PAL
RECTANGULAR PIXEL
CLK2 = 27.00MHz
-20
NTSC SQUARE PIXEL
CLK2 = 24.54MHz
-30
PAL SQUARE PIXEL
CLK2 = 29.50MHz
-1.0
ATTENUATION (dB)
ATTENUATION (dB)
-10
-40
-1.5
-2.0
NTSC OR PAL
RECTANGULAR PIXEL
CLK2 = 27.00MHz
-2.5
-3.0
-50
NTSC SQUARE PIXEL
CLK2 = 24.54MHz
-3.5
-60
0
2
4
6
8
FREQUENCY (MHz)
10
-4.0
12
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
FREQUENCY (MHz)
FIGURE 8A. FULL SPECTRUM
FIGURE 8B. PASS BAND
FIGURE 8. Cb AND Cr LOWPASS FILTER RESPONSE
Color Subcarrier Generation
The HMP817x uses a numerically controlled oscillator
(NCO) clocked by CLK2 and a sine look up ROM to generate
the color subcarrier. As shown in Figure 9, the phase
increment value (PHINC) of the NCO may come from the
encoder’s internal look up table, BT.656 ancillary data, or a
control register. The PHINC source is selected in timing I/O
register 2.
.
INTERNAL
BT.656
PHINC
+
D
Q
PHINT
I2C
CLK2
PHINC
SELECT
NCO RESET
FIGURE 9. COLOR SUBCARRIER GENERATION NCO.
8
HMP8170, HMP8171, HMP8172, HMP8173
The MSBs of the accumulated phase value (PHINT) are
used to address the encoder’s sine look up ROM. The sine
values from the ROM are pre-scaled to generate the proper
levels for the various video standards. Prescaling outside the
CbCr data path minimizes color processing artifacts. The
HMP817x modulates the filtered 8:8:8 chrominance data
with the synthesized subcarrier.
The SCH phase is 0 degrees after reset but then changes
monotonically over time due to residue in the NCO. In an ideal
system, zero SCH phase would be maintained forever. In
reality, this is impossible to achieve due to pixel clock frequency
tolerances and digital rounding errors. When the PHINC source
is BT.656 data, the SCH phase reset should be disabled.
If enabled, the HMP817x resets the NCO periodically to
avoid an accumulation of SCH phase error. The reset occurs
at the beginning of each field to burst phase sequence. The
sequence repeats every 4 fields for NTSC or 8 fields for PAL.
Resetting the SCH phase every four fields (NTSC) or eight
fields (PAL) avoids the accumulation of SCH phase error at
the expense of requiring any NTSC/PAL decoder after the
encoder be able to handle very minor “jumps” (up to 2
degrees) in the SCH phase at the beginning of each fourfield or eight-field sequence. Most NTSC/PAL decoders are
able to handle this due to video editing requirements.
Composite Video Limiting
The HMP817x adds the luminance and modulated
chrominance together with the sync, color burst, and
optional blanking pedestal to form the composite video data.
If enabled in the video processing register, the encoder limits
the active video so that it is always greater than one-eighth
of full scale. This corresponds to approximately one-half the
sync height. This allows the generation of “safe” video in the
event non-standard YCbCr values are input to the device.
Controlled Edges
The NTSC and PAL video standards specify edge rates and
rise and fall times for portions of the video waveform. The
HMP817x automatically implements controlled edge rates
and rise and fall times on these edges:
1. Analog Horizontal Sync (Rising and Falling Edges)
2. Analog Vertical Sync Interval (Rising and Falling Edges)
3. Color Burst Envelope
4. Blanking of Analog Active Video
5. Closed Captioning Information
6. WSS Information
7. Teletext Information
9
“Sliced” VBI Data
The HMP817x generates three types of vertical blanking
interval data: closed captioning, widescreen signalling, and
teletext data. The data is generated on the scan lines
specified by the selected output video standard which are
enabled in the VBI data control register. During scan lines
with VBI data, the pixel inputs are ignored.
Closed Captioning (CC)
The HMP817x captioning data output includes clock run-in and
start bits followed by the captioning data. During closed
captioning encoding, the pixel inputs are ignored on the scan
lines containing captioning information.
The HMP817x has two 16-bit registers containing the
captioning information. Each 16-bit register is organized as
two cascaded 8-bit registers. One 16-bit register (caption 21)
is read out serially during line 18, 21 or 22; the other 16-bit
register (WSS 284) is read out serially during line 281, 284
or 335. The data registers are shifted out LSB first.
The captioning output level is 50 IRE for a logic 1 and 0 IRE
for a logic 0. All transitions between levels are controlled to
have a raised-cosine shape. The rise or fall time of any
transition is 240-288ns.
The caption data registers may be loaded via the I2C interface
or as BT.656 ancillary data. Table 6 illustrates the format of the
caption data as BT.656 ancillary data. The transfer should
occur only once per field before the start of the SAV sequence
of the line containing the captioning output.
When written via the I2C interface, the bytes may be written
in any order but both must be written within one frame time
for proper operation. If the registers are not updated, the
encoder resends the previously loaded values.
The HMP817x provides a write status bit for each captioning
line. The encoder clears the write status bit to ‘0’ when
captioning is enabled and both bytes of the captioning data
register have been written. The encoder sets the write status
bit to ‘1’ after it outputs the data, indicating the registers are
ready to receive new data.
Captioning information may be enabled for either line, both
lines, or no lines. The captioning modes are summarized in
Table 7.
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 6. BT.656 ANCILLARY DATA FORMAT FOR CLOSED CAPTIONING DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble 1
0
0
0
0
0
0
0
0
Preamble 2
1
1
1
1
1
1
1
1
Preamble 3
1
1
1
1
1
1
1
1
Data ID
ep#
ep
1
1
0
0
0
Line
Data Block Number
ep#
ep
0
0
0
0
0
1
Data Word Count
ep#
ep
0
0
0
0
0
1
Caption Register Byte 3
ep#
ep
0
0
bit 15
bit 14
bit 13
bit 12
Caption Register Byte 1
ep#
ep
0
0
bit 11
bit 10
bit 9
bit 8
Caption Register Byte 1
ep#
ep
0
0
bit 7
bit 6
bit 5
bit 4
Caption Register Byte 0
ep#
ep
0
0
bit 3
bit 2
bit 1
bit 0
CRC
P14#
X
X
X
X
X
X
X
NOTES:
The even parity (EP and EP#) bits are ignored.
Line = Data Register Select: 0 = Line 21; 1 = 284.
X = Don’t Care.
TABLE 7. CLOSED CAPTIONING MODES
CAPTIONING REGISTER
CLOSED
CAPTIONING
ENABLE BITS
OUTPUT LINE(S)
WRITE STATUS BIT
284A
284B
21A
21B
284
21
00
None
Ignored
Ignored
Always 1
Always 1
01
21 (NTSC)
18 (M PAL)
22 (Other PAL)
Ignored
Caption Data
Always 1
0 = Loaded
1 = Output
10
284 (NTSC)
281 (M PAL)
335 (Other PAL)
Caption Data
Ignored
0 = Loaded
1 = Output
Always 1
11
21, 284 (NTSC)
18, 281 (M PAL)
22, 335 (Other PAL)
Caption Data
Caption Data
0 = Loaded
1 = Output
0 = Loaded
1 = Output
The HMP817x WSS data output includes clock run-in and
start codes followed by the WSS data. For NTSC operation,
the WSS data is followed by six bits of CRC data.
The WSS data registers may be loaded via the I2C interface
or as BT.656 ancillary data. Table 8 illustrates the format of
the WSS data as BT.656 ancillary data. The transfer should
occur only once per field before the start of the SAV
sequence of the line containing the WSS output.
The HMP817x has two 14-bit registers containing the WSS
information and two 6-bit registers containing the WSS CRC
data. Each 14-bit register is organized as a 6-bit register
cascaded with an 8-bit one. One 14-bit register (WSS 20) is
read out serially during line 17, 20 or 23; the other 14-bit
register (caption 283) is read out serially during line 280, 283
or 336. The data registers are shifted out LSB first.
When written via the I2C interface, the bytes may be written
in any order but all three bytes of each enabled line must be
written within one frame time for proper operation. If the
registers are not updated, the encoder resends the
previously loaded values.
Widescreen Signalling (WSS)
The WSS output level depends on the video format. For
NTSC operation (EIAJ CPX-1204), the WSS output level is 70
IRE for a logic 1 and 0 IRE for a logic 0. All transitions
between levels are controlled to have a raised-cosine shape
with a rise or fall time of 240ns. For PAL operation (ITU-R
BT.1119), the WSS output level is 71.5 IRE for a logic 1 and 0
IRE for a logic 0. All transitions between levels are controlled
to have a raised-cosine shape with a rise or fall time of 118ns.
10
The HMP817x provides a write status bit for each WSS line.
The encoder clears the write status bit to ‘0’ when WSS is
enabled and all bytes of the WSS data register have been
written. The encoder sets the write status bit to ‘1’ after it
outputs the data, indicating the registers are ready to receive
new data.
WSS information may be enabled for either line, both lines,
or no lines. The WSS modes are summarized in Table 9.
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 8. BT.656 ANCILLARY DATA FORMAT FOR WIDESCREEN SIGNALLING DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble 1
0
0
0
0
0
0
0
0
Preamble 2
1
1
1
1
1
1
1
1
Preamble 3
1
1
1
1
1
1
1
1
Data ID
ep#
ep
1
1
0
0
1
Line
Data Block Number
ep#
ep
0
0
0
0
0
1
Data Word Count
ep#
ep
0
0
0
0
1
0
WSS Data Nibble 3
ep#
ep
0
0
0
0
bit 13
bit 12
WSS Data Nibble 2
ep#
ep
0
0
bit 11
bit 10
bit 9
bit 8
WSS Data Nibble 1
ep#
ep
0
0
bit 7
bit 6
bit 5
bit 4
WSS Data Nibble 0
ep#
ep
0
0
bit 3
bit 2
bit 1
bit 0
WSS CRC Nibble 1
ep#
ep
0
0
0
0
bit 5
bit 4
WSS CRC Nibble 0
ep#
ep
0
0
bit 3
bit 2
bit 1
bit 0
Reserved
ep#
ep
0
0
0
0
0
0
Reserved
ep#
ep
0
0
0
0
0
0
CRC
P14#
X
X
X
X
X
X
X
NOTES:
The even parity (EP and EP#) bits are ignored.
Line = Data Register Select: 0 = Line 20; 1 = 283.
The WSS CRC data bits are ignored during PAL operation but must be included in the transfer.
X = Don’t Care.
TABLE 9. WIDESCREEN SIGNALLING MODES
WSS REGISTERS
WSS
ENABLE BITS
OUTPUT LINE(S)
WRITE STATUS BIT
283A, 283B,
CRC283
20A, 20B,
CRC20
283
20
00
None
Ignored
Ignored
Always 1
Always 1
01
20 (NTSC)
17 (M PAL)
23 (Other PAL)
Ignored
WSS Data
Always 1
0 = Loaded
1 = Output
10
283 (NTSC)
280 (M PAL)
336 (Other PAL)
WSS Data
Ignored
0 = Loaded
1 = Output
Always 1
11
20, 283 (NTSC)
17, 280 (M PAL)
23, 336 (Other PAL)
WSS Data
WSS Data
0 = Loaded
1 = Output
0 = Loaded
1 = Output
NOTE: The CRC registers are always ignored during PAL operation.
Teletext
The HMP817x supports ITU-R BT.653 625-line and 525-line
teletext system B and C generation. WST (World System
Teletext) is the same as BT.653 system B. NABTS (North
American Broadcast Teletext Specification) is the same as
BT.653 525-line system C. NABTS is also used to transmit
Intel Intercast information.
During the teletext encoding, the line’s pixel inputs are
ignored. The teletext information includes a 16-bit clock
synchronization code; the HMP817x automatically
generates it.
11
The teletext output level depends on the video format. For
system B teletext, the output level is 66 IRE for a logic 1 and 0
IRE for a logic 0. All transitions between levels are controlled to
have a raised-cosine shape with a rise or fall time of 200ns. For
system C teletext, the output level is 70 IRE for a logic 1 and 0
IRE for a logic 0. All transitions between levels are controlled to
have a raised-cosine shape with a rise or fall time of 200ns.
The HMP817x generates teletext output on any scan line
that includes teletext data in that line’s BT.656 ancillary data.
The encoder must receive the ancillary data before the SAV
sequence in order to output the teletext data. Table 10 shows
the BT.656 ancillary data format for loading the teletext data
registers.
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 10. BT.656 ANCILLARY DATA FORMAT FOR TELETEXT DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble 1
0
0
0
0
0
0
0
0
Preamble 2
1
1
1
1
1
1
1
1
Preamble 3
1
1
1
1
1
1
1
1
Data ID
ep#
ep
1
1
0
1
0
0
Data Block Number
ep#
ep
0
0
0
0
0
1
Data Word Count
ep#
ep
0
1
0
1
1
0
Teletext Register
Data
(86 Nibbles)
ep#
ep
Line
Sys
bit 343
bit 342
bit 341
bit 340
ep#
ep
0
0
bit 339
bit 338
bit 337
bit 336
...
ep#
ep
0
0
bit 7
bit 6
bit 5
bit 4
ep#
ep
0
0
bit 3
bit 2
bit 1
bit 0
Reserved
ep#
ep
0
0
0
0
0
0
Reserved
ep#
ep
0
0
0
0
0
0
CRC
P14#
X
X
X
X
X
X
X
NOTES:
The even parity (EP and EP#) bits are ignored.
Line = Standard Select: 0 = 525 Lines; 1 = 625 Lines
Sys = System Select: 0 = System B; 1 = System C.
625-line system B uses 43 bytes; all bits are used.
525-line system B uses 35 bytes; bits 343-280 are ignored.
525-line system C uses 34 bytes; bits 343-272 are ignored.
X = Don’t Care.
TABLE 11. BT.656 ANCILLARY DATA FORMAT FOR PHINC DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble 1
0
0
0
0
0
0
0
0
Preamble 2
1
1
1
1
1
1
1
1
Preamble 3
1
1
1
1
1
1
1
1
Data ID
ep#
ep
1
1
0
1
0
1
Data Block Number
ep#
ep
0
0
0
0
0
1
Data Word Count
ep#
ep
0
0
0
0
1
1
HPLL
Increment
(4 Nibbles)
ep#
ep
0
0
bit 15
bit 14
bit 13
bit 12
ep#
ep
0
0
bit 11
bit 10
bit 9
bit 8
ep#
ep
0
0
bit 7
bit 6
bit 5
bit 4
ep#
ep
0
0
bit 3
bit 2
bit 1
bit 0
ep#
ep
PSW
0
bit 31
bit 30
bit 29
bit 28
ep#
ep
F2
F1
bit 27
bit 26
bit 25
bit 24
FSCPLL
Increment
(8 Nibbles)
...
CRC
ep#
ep
0
0
bit 7
bit 6
bit 5
bit 4
ep#
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14#
X
X
X
X
X
X
X
NOTES:
The even parity (EP and EP#) bits are ignored.
HPLL, PSW, F2, and F1 are ignored.
X = Don’t Care.
12
HMP8170, HMP8171, HMP8172, HMP8173
Macrovision
Output DAC Filtering
The HMP8171 and HMP8173 provide the copy protection
system specified by the Macrovision Antitaping Process for
Digital Platforms document, revision 7.01, September 6, 1996.
Since the DACs run at 2x the pixel sample rate, the sin(x)/x
rolloff of the outputs is greatly reduced, and there are fewer
high frequency artifacts in the output spectrum. This allows
using simple analog output filters. The analog output filter
should be flat to Fs/4 and have good rejection at 3Fs/4.
Example filters are shown in the Applications section.
The devices are protected by U.S. patent numbers
4,631,603, 4,577,216, and 4,819,098 and other intellectual
property rights. The use of Macrovision’s copy protection
technology in the device must be authorized by Macrovision
and is intended for home and other limited pay-per-view
uses only, unless otherwise authorized in writing by
Macrovision. Reverse engineering or disassembly is
prohibited.
Additional information about Macrovision in the HMP8171
and HMP8173 is available to Macrovision Authorized Buyers
only. Tech Brief 359, HMP8171/HMP8173 Macrovision
Registers provides the details required.
Analog Outputs
The HMP817x converts the video data into analog signals
using four 10-bit DACs running at the CLK2 rate. The DACs
output a current proportional to the digital data. The full scale
output current is determined by the reference voltage VREF
and an external resistor RSET. The full scale output current
is given by:
IFULLSCALE (mA) = 3.9 * VREF (V)/RSET (kΩ)
(EQ 1.)
VREF must be chosen such that it is within the part’s
operating range; RSET must be chosen such that the
maximum output current is not exceeded.
If the VREF pin is not connected, the HMP817x uses the
internal reference voltage. Otherwise, the applied voltage
overdrives the internal reference. If an external reference is
used, it must decoupled from any power supply noise. An
example external reference circuit is shown in the
Applications section.
The HMP817x generates 1VP-P nominal video signals
across 37.5Ω loads, corresponding to doubly terminated
75Ω lines. The encoder may also drive larger loads. The full
scale output current and load must be chosen such that the
maximum output voltage is not exceeded.
Composite + Y/C Output Mode
The HMP817x provides composite with S-video output
mode. When S-video outputs are selected, the encoder
outputs the luminance, modulated chrominance, and two
copies of the composite video signals. All four outputs are
time aligned. The output pin assignments are summarized in
Table 12.
Composite + RGB Output Mode
The HMP8172/HMP8173 also provide composite with
component RGB output mode. When analog RGB video is
selected, the HMP817x transforms the filtered 8:8:8 YCbCr
data into 8:8:8 RGB data. The transform matrix uses
different coefficients to generate NTSC or PAL video levels.
The analog RGB outputs have a range of 0.3-1.0V with an
optional blanking pedestal. Composite sync information
(0.0-0.3V) may be optionally added to the green output. VBI
data is not included on the RGB outputs. The HMP817x also
generates composite video when in RGB output mode. All
four outputs are time aligned.
The HMP817x provides selectable pin outs for the RGB
outputs. When the SCART compatibility bit is cleared, the
analog composite video is output onto the NTSC/PAL 1 pin.
Red information is output onto the NTSC/PAL 2 pin, blue
information is output onto the C pin, and green information is
output onto the Y pin.
When the bit is set, the analog composite video is output
onto the Y pin. Red information is output onto the C pin, blue
video is output on the NTSC/PAL 2 pin, and the green signal
is output on the NTSC/PAL 1 pin. The output pin
assignments are summarized in Table 12.
TABLE 12. OUTPUT PIN ASSIGNMENTS
OUTPUT MODE (SCART SELECT BIT)
PIN NAME
PIN #
COMP. WITH Y/C
(X)
COMP. W/ RGB
(0)
COMP. W/ RGB
(1)
COMP. W/ YUV
(X)
Y
3
Luma
Green
Composite
Composite
C
7
Chroma
Blue
Red
V
NTSC/PAL 1
11
Composite
Composite
Green
Y
NTSC/PAL 2
15
Composite
Red
Blue
U
13
HMP8170, HMP8171, HMP8172, HMP8173
Composite + YUV Output Mode
The HMP8172/HMP8173 also provide composite with
component YUV output mode. When analog YUV video is
selected, the HMP817x scales the filtered YCbCr data to
match the levels required by its DACs. During the scaling,
values less than 16 are clamped to 16. The scaling factors
for Cb and Cr are the same, but the CbCr scaling factor is
different from the Y scaling factor. The encoder uses
different sets of scale factors for NTSC and PAL to
accommodate their different black levels.
I2C write cycle are written to the control registers, beginning
with the register specified by the address register. The 7-bit
address register is incremented after each data byte in the
I2C write cycle. Data written to reserved bits within registers
or reserved registers is ignored.
During I2C read cycles, data from the control register
specified by the address register is output. The address
register is incremented after each data byte in the I2C read
cycle. Reserved bits within registers return a value of “0”.
Reserved registers return a value of 00H .
The analog YUV outputs have a range of 0.3-1.0V with an
optional blanking pedestal. Composite sync information
(0.0-0.3V) may be optionally added to the Y output. VBI data
is included on the Y output. The HMP817x also generates
composite video when in YUV output mode. All four outputs
are time aligned. The output pin assignments are
summarized in Table 12.
The HMP817x’s operating modes are determined by the
contents of its internal registers which are accessed via the
I2C interface. All internal registers may be written or read by
the host processor at any time. However, some of the bits
and words are read only or reserved and data written to
these bits is ignored.
Power Down Modes
Table 13 lists the HMP817x’s internal registers. Their bit
descriptions are listed in Tables 14 through 45.
To reduce power dissipation, any of the four output DACs
may be turned off. Each DAC has an independent enable bit.
Each output may be disabled in the host control register.
When the power down mode is enabled, all of the DACs and
internal voltage reference are powered down (forcing their
outputs to zero) and the data pipeline registers are disabled.
The host processor may still read from and write to the
internal control registers.
Host Interfaces
Reset
The HMP817x resets to its default operating mode on power
up, when the reset pin is asserted for at least four CLK
cycles, or when the software reset bit of the host control
register is set. During the reset cycle, the encoder returns its
internal registers to their reset state and deactivates the I2C
interface.
I 2C Interface
The HMP817x provides a standard I2C interface and
supports fast-mode (up to 400Kbps) transfers. The device
acts as a slave for receiving and transmitting data only. It will
not respond to general calls or initiate a transfer. The
encoder’s slave address is either 0100 000xB when the SA
input pin is low or 0100 001xB when it is high. (The ‘x’ bit in
the address is the I2C read flag.)
The I2C interface consists of the SDA and SCL pins. When
the interface is not active, SCL and SDA must be pulled high
using external 4-6kΩ pull-up resistors. The I2C clock and
data timing is shown in Figures 10 and 11.
During I2C write cycles, the first data byte after the slave
address specifies the sub address, and is written into the
address register. Only the seven LSBs of the subaddress are
used; the MSB is ignored. Any remaining data bytes in the
14
TABLE 13. CONTROL REGISTER NAMES
SUB ADDRESS
(HEX)
CONTROL REGISTER
RESET
CONDITION
00
01
02
03
04
05
06
07
08-0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A-1F
20
21
22
23
24
25
26
27
28-2F
30-6A
6B-6F
70-7F
product ID
output format
input format
video processing
timing I/O 1
timing I/O 2
VBI data enable
VBI data input
reserved
host control 1
host control 2
caption_21A
caption_21B
caption_284A
caption_284B
WSS_20A
WSS_20B
WSS_283A
WSS_283B
CRC_20
CRC_283
reserved
start h_blank low
start h_blank high
end h_blank
start v_blank low
start v_blank high
end v_blank
field control 1
field control 2
reserved
test and unused
phase increment
test and unused
00H
06H
80H
00H
00H
00H
00H
1EH
00H
80H
80H
80H
80H
00H
00H
00H
00H
3FH
3FH
4AH
03H
7AH
03H
01H
13H
00H
00H
-
HMP8170, HMP8171, HMP8172, HMP8173
SDA
SCL
8
1-7
S
START
CONDITION
9
R/W
ADDRESS
1-7
8
ACK
DATA
9
P
ACK
STOP
CONDITION
FIGURE 10. I2C SERIAL TIMING FLOW
DATA WRITE
S
CHIP ADDR
A
SUB ADDR
0x40 OR
0x42
CHIP ADDR
DATA
A
REGISTER
POINTED
TO BY
SUBADDR
DATA READ
S
A
A
0x40 OR
0x42
SUB ADDR
A S
CHIP ADDR
0x41 OR
0x43
DATA
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
A P
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
A
DATA
REGISTER
POINTED
TO BY
SUBADDR
FROM MASTER
A
DATA
NA
P
FROM ENCODER
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
FIGURE 11. REGISTER WRITE PROGRAMMING FLOW
TABLE 14. PRODUCT ID REGISTER
SUB ADDRESS = 00H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Product ID
This 8-bit register specifies the last two digits of the product number. It is a read-only register.
Data written to it is ignored.
RESET
STATE
70H
71H
72H
73H
TABLE 15. OUTPUT FORMAT REGISTER
SUB ADDRESS = 01H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-5
Video Timing
Standard
000 = (M) NTSC
001 = reserved
010 = (B, D, G, H, I) PAL
011 = (M) PAL
100 = (N) PAL
101 = (NC) PAL
110 = reserved
111 = reserved
000B
4-3
Output Format
00 = Composite + Y/C
01 = Composite + YUV (HMP8172 and HMP8173 only)
10 = Composite + RGB without sync on green (HMP8172 and HMP8173 only)
11 = Composite + RGB with sync on green (HMP8172 and HMP8173 only)
00B
2-0
NTSC / PAL
Setup Select
These bits specify the blanking pedestal during active video, from 0 IRE (“000”) to 7.5 IRE
(“111”). Typically, these bits should be a “111” during (M) NTSC and (M, N) PAL operation.
Otherwise, they should be a “000”. These bits do not affect the analog RGB or YUV outputs.
111B
15
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 16. INPUT FORMAT REGISTER
SUB ADDRESS = 02H
BIT
NUMBER
FUNCTION
7-5
Input Format
4-0
Reserved
DESCRIPTION
000 = 16-bit 4:2:2 YCbCr
001 = 8-bit 4:2:2 YCbCr
010 = 8-bit BT.656
011 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
RESET
STATE
000B
00000B
TABLE 17. VIDEO PROCESSING REGISTER
SUB ADDRESS = 03H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7
Luminance
Processing
0 = None
1 = Y Lowpass filtering enabled
1B
6
Composite Video
Limiting
0 = None
1 = Lower limit of composite active video is about half the sync height
0B
5
SCH Phase
Mode
0 = Never reset SCH phase
1 = Reset SCH phase every 4 (NTSC) or 8 (PAL) fields
1B
4
RGB / YUV
Setup Select
This bits specifies the blanking pedestal on the analog RGB and YUV outputs during active
video. Typically, this bit should be a “1” during (M) NTSC and (M, N) PAL operation. Otherwise,
it should be a “0”. This bit does not affect the analog composite or Y/C outputs.
0 = 0 IRE
1 = 7.5 IRE
0B
3
RGB Output
Pins Select
This bit configures on what pins the analog RGB video is output.
0 = HMP8156 compatible
1 = SCART compatible
0B
2-0
Reserved
000B
TABLE 18. TIMING I/O REGISTER #1
SUB ADDRESS = 04H
BIT
NUMBER
FUNCTION
DESCRIPTION
This bit is ignored unless BLANK is configured to be an output.
0 = Data for the first active pixel of the scan line must arrive the CLK cycle after the encoder
negates BLANK.
1 = Data for the first active pixel of the scan line must arrive immediately after the encoder
negates BLANK.
RESET
STATE
7
BLANK
Timing Select
6
Reserved
5
BLANK Output
Control
0 = BLANK is an input
1 = BLANK is an output
0B
4
BLANK
Polarity
0 = Active low (low during blanking)
1 = Active high (high during blanking)
0B
3
HSYNC and
VSYNC Output
Control
0 = HSYNC and VSYNC are inputs
1 = HSYNC and VSYNC are outputs
0B
2
HSYNC
Polarity
0 = Active low (low during horizontal sync)
1 = Active high (high during horizontal sync)
0B
1
VSYNC
Polarity
0 = Active low (low during vertical sync)
1 = Active high (high during vertical sync)
0B
0
FIELD
Polarity
0 = Active low (low during odd fields)
1 = Active high (high during odd fields)
0B
0B
0B
16
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 19. TIMING I/O REGISTER #2
SUB ADDRESS = 05H
BIT
NUMBER
7-6
5
FUNCTION
Reserved
CLK Polarity Control
4
CLK Output Control
3
Aspect Ratio Mode
2
1-0
Reserved
Subcarrier PHINC
Select
DESCRIPTION
0 = Inputs are sampled when CLK is low (see Table 2).
1 = Inputs are sampled when CLK is high.
0 = CLK is an input
1 = CLK is an output
This bit must be set to “0” during BT.656 input mode.
0 = Rectangular (BT.601) pixels
1 = Square pixels
Selects the source of the color subcarrier NCO phase increment value.
00 = Internal (fixed) data.
01 = Reserved
10 = BT.656 RTCI ancillary data
11 = I2C interface PHINC register
RESET
STATE
00B
0B
0B
0B
0B
00B
TABLE 20. AUXILIARY DATA ENABLE REGISTER
SUB ADDRESS = 06H
BIT
NUMBER
7-6
5-4
3
1-0
FUNCTION
Closed Captioning
Enable
WSS Enable
Teletext Enable
DESCRIPTION
00 = Closed caption disabled
01 = Closed caption enabled for odd fields: line 21 for NTSC, line 18 for (M) PAL, or line 22 for
(B, D, G, H, I, N, NC) PAL
10 = Closed caption enabled for even fields: line 284 for NTSC, line 281 for (M) PAL, or line
335 for (B, D, G, H, I, N, NC) PAL
11 = Closed caption enabled for both odd and even fields
00 = WSS disabled
01 = WSS enabled for odd fields: line 20 for NTSC; line 17 for (M) PAL, or line 23 for (B, D, G,
H, I, N, NC) PAL
10 = WSS enabled for even fields: line 283 for NTSC, line 280 for (M) PAL, or line 336 for (B,
D, G, H, I, N, NC) PAL
11 = WSS enabled for both odd and even fields
00 = Teletext disabled
01 = System B teletext enabled
10 = System C teletext enabled
11 = reserved
Reserved
RESET
STATE
00B
00B
00B
00B
TABLE 21. VBI DATA INPUT REGISTER
SUB ADDRESS = 07H
BIT
NUMBER
7
FUNCTION
Closed Caption
Line 21
BT.656 Enable
DESCRIPTION
Setting this bit enables BT.656 ancillary data to be written into the closed caption line 21 data
registers. It is ignored unless in the BT.656 input mode.
0 = Ignore BT.656 ancillary data
1 = Use BT.656 ancillary data
6
Closed Caption
Line 284
BT.656 Enable
5
WSS Line 20
BT.656 Enable
4
WSS Line 283
BT.656 Enable
Setting this bit enables BT.656 ancillary data to be written into the closed caption line 284 data
registers. It is ignored unless in the BT.656 input mode.
0 = Ignore BT.656 ancillary data
1 = Use BT.656 ancillary data
Setting this bit enables BT.656 ancillary data to be written into the WSS line 20 data registers.
It is ignored unless in the BT.656 input mode.
0 = Ignore BT.656 ancillary data
1 = Use BT.656 ancillary data
Setting this bit enables BT.656 ancillary data to be written into the WSS line 283 data registers.
It is ignored unless in the BT.656 input mode.
0 = Ignore BT.656 ancillary data
1 = Use BT.656 ancillary data
3-0
Reserved
RESET
STATE
0B
0B
0B
0B
0000B
17
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 22. HOST CONTROL REGISTER 1
SUB ADDRESS = 0EH
BIT
NUMBER
7-5
FUNCTION
DESCRIPTION
Reserved
RESET
STATE
000B
4
Closed Caption
Line 21
Write Status
0 = Caption_21A and Caption_21B data registers contain unused data
1 = Data has been output, host processor may now write to the registers
1B
3
Closed Caption
Line 284
Write Status
0 = Caption_284A and Caption_284B data registers contain unused data
1 = Data has been output, host processor may now write to the registers
1B
2
WSS
Line 20
Write Status
0 = WSS_20A, WSS_20B, CRC_20A, and CRC_20B data registers contain
unused data
1 = Data has been output, host processor may now write to the registers
1B
1
WSS
Line 283
Write Status
0 = WSS_283A and WSS_283B data registers contain unused data
1 = Data has been output, host processor may now write to the registers
1B
0
Reserved
0B
TABLE 23. HOST CONTROL REGISTER 2
SUB ADDRESS = 0FH
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7
Software Reset
Setting this bit to “1” initiates a software reset. It is automatically reset to a “0” after the reset
sequence is complete.
0B
6
General
Power Down
This bit powers down all DAC outputs and most of the digital circuitry.
0 = Normal operation
1 = Power down mode
0B
5
Power Down
NTSC/PAL 1
Output DAC
This bit powers down only the NTSC/PAL 1 DAC output.
0 = Normal operation
1 = Power down mode
0B
4
Power Down
NTSC/PAL 2
Output DAC
This bit powers down only the NTSC/PAL 2 DAC output.
0 = Normal operation
1 = Power down mode
0B
3
Power Down
Y Output DAC
This bit powers down only the Y DAC output.
0 = Normal operation
1 = Power down mode
0B
2
Power Down
C Output DAC
This bit powers down only the C DAC output.
0 = Normal operation
1 = Power down mode
0B
1-0
Reserved
00B
TABLE 24. CLOSED CAPTION_21A DATA REGISTER
SUB ADDRESS = 10H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Line 21 Caption
LSB Data
This register is cascaded with the closed caption_21B data register and they are read out
serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A
data register is shifted out first.
RESET
STATE
80H
TABLE 25. CLOSED CAPTION_21B DATA REGISTER
SUB ADDRESS = 11H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Line 21 Caption
MSB Data
This register is cascaded with the closed caption_21A data register and they are read out
serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A
data register is shifted out first.
18
RESET
STATE
80H
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 26. CLOSED CAPTION_284A DATA REGISTER
SUB ADDRESS = 12H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Line 284 Caption
LSB Data
This register is cascaded with the closed caption_284B data register and they are read out
serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the
284A data register is shifted out first.
RESET
STATE
80H
TABLE 27. CLOSED CAPTION_284B DATA REGISTER
SUB ADDRESS = 13H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Line 284 Caption
MSB Data
This register is cascaded with the closed caption_284A data register and they are read out
serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the
284A data register is shifted out first.
RESET
STATE
80H
TABLE 28. WSS_20A DATA REGISTER
SUB ADDRESS = 14H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Line 20
WSS LSB Data
This register is cascaded with the WSS_20B data register and they are read out serially as 14
bits during line 17, 20, or 23 if WSS is enabled. Bit D0 of the WSS_20A data register is shifted
out first.
RESET
STATE
00H
TABLE 29. WSS_20B DATA REGISTER
SUB ADDRESS = 15H
BIT
NUMBER
FUNCTION
7-6
Reserved
5-0
Line 20
WSS MSB Data
DESCRIPTION
RESET
STATE
00B
This register is cascaded with the WSS_20A data register and they are read out serially as 14
bits during line 17, 20, or 23 if WSS is enabled. Bit D0 of the WSS_20A data register is shifted
out first.
000000B
TABLE 30. WSS_283A DATA REGISTER
SUB ADDRESS = 16H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Line 283
WSS LSB Data
This register is cascaded with the WSS_283B data register and they are read out serially as
14 bits during line 280, 283, or 336 if WSS is enabled. Bit D0 of the WSS_283A data register
is shifted out first.
RESET
STATE
00H
TABLE 31. WSS_283B DATA REGISTER
SUB ADDRESS = 17H
BIT
NUMBER
FUNCTION
7-6
Reserved
5-0
Line 283
WSS MSB Data
DESCRIPTION
RESET
STATE
00B
This register is cascaded with the WSS_283A data register and they are read out serially as
14 bits during line 280, 283, or 336 if WSS is enabled. Bit D0 of the WSS_283A data register
is shifted out first.
000000B
TABLE 32. CRC_20 REGISTER
SUB ADDRESS = 18H
BIT
NUMBER
FUNCTION
7-6
Reserved
5-0
Line 20
WSS CRC Data
DESCRIPTION
RESET
STATE
00B
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
19
111111B
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 33. CRC_283 REGISTER
SUB ADDRESS = 19H
BIT
NUMBER
FUNCTION
7-6
Reserved
5-0
Line 283
WSS CRC Data
DESCRIPTION
RESET
STATE
00B
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
111111B
TABLE 34. START H_BLANK LOW REGISTER
SUB ADDRESS = 20H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
LSB Assert BLANK
Output Signal
(Horizontal)
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This
register is ignored unless BLANK is configured as an output.
RESET
STATE
4AH
TABLE 35. START H_BLANK HIGH REGISTER
SUB ADDRESS = 21H
BIT
NUMBER
FUNCTION
DESCRIPTION
7-2
Reserved
1-0
MSB Assert BLANK
Output Signal
(Horizontal)
RESET
STATE
000000B
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This
register is ignored unless BLANK is configured as an output.
11B
TABLE 36. END H_BLANK REGISTER
SUB ADDRESS = 22H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Negate BLANK
Output Signal
(Horizontal)
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000H. This register is ignored
unless BLANK is configured as an output.
RESET
STATE
7AH
TABLE 37. START V_BLANK LOW REGISTER
SUB ADDRESS = 23H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
LSB Assert BLANK
Output Signal
(Vertical)
20
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000H (note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
RESET
STATE
03H
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 38. START V_BLANK HIGH REGISTER
SUB ADDRESS = 24H
BIT
NUMBER
7-1
0
FUNCTION
DESCRIPTION
Reserved
RESET
STATE
0000000B
MSB Assert BLANK
Output Signal
(Vertical)
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register. This register is ignored unless BLANK is configured as an output.
1B
TABLE 39. END V_BLANK REGISTER
SUB ADDRESS = 25H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Negate BLANK
Output Signal
(Vertical)
During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel
input data (and what line number to start generating active output video) each odd field; for
even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000H (note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
RESET
STATE
13H
TABLE 40. FIELD CONTROL REGISTER 1
SUB ADDRESS = 26H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Field Detect
Window Size Low
This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect
Window Size value. The value specifies the number of 1x clock cycles in the detection window
before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge
of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the
FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured
as inputs.
RESET
STATE
80H
TABLE 41. FIELD CONTROL REGISTER 2
SUB ADDRESS = 27H
BIT
NUMBER
7-4
FUNCTION
DESCRIPTION
RESET
STATE
Half Line Count
Reset Value
These bits specify the value to load to the vertical half line counter when the selected edge of
VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.
00000B
2
VSYNC Edge
Select
This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine
the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = leading edge
1 = trailing edge
0B
1
FIELD Detect
Select
This bit specifies whether an odd or even field is starting when the leading edge of HSYNC
occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = odd field
1 = even field
0B
0
Field Detect
Window Size High
This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window
Size value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.
0B
21
HMP8170, HMP8171, HMP8172, HMP8173
TABLE 42. PHASE INCREMENT REGISTER 0
SUB ADDRESS = 6BH
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
PHINC 0
(LSB)
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
RESET
STATE
00H
TABLE 43. PHASE INCREMENT REGISTER 1
SUB ADDRESS = 6CH
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
PHINC 1
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
RESET
STATE
00H
TABLE 44. PHASE INCREMENT REGISTER 2
SUB ADDRESS = 6DH
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
PHINC 2
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
RESET
STATE
00H
TABLE 45. PHASE INCREMENT REGISTER 1
SUB ADDRESS = 6EH
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
PHINC 3
(MSB)
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
22
RESET
STATE
00H
HMP8170, HMP8171, HMP8172, HMP8173
Pinout
P3
P4
P5
P6
P7
COMP 1
COMP 2
FS_ADJUST
VREF
GND
GND
P0
VAA
GND
P1
P2
HMP817X
(PQFP)
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VAA
VAA
Y
GND
VAA
GND
C
GND
VAA
GND
NTSC/PAL1
GND
VAA
GND
NTSC/PAL2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P8
P9
P10
P11
P12
P13
GND
CLK2
VAA
CLK
P14
P15
VSYNC
HSYNC
FIELD
BLANK
GND
SCL
SA
SDA
RESV
NC
NC
VAA
RESET
GND
NC
NC
NC
NC
NC
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin Descriptions
PIN
NAME
PIN
NUMBER
INPUT/
OUTPUT
P0-P15
58, 55-43,
38, 37
I
Pixel input pins. See Table 1. Any pixel inputs not used should be connected to GND.
NC
32-27, 23,
22
I
No connect pins. These pins are not used. They may be left floating or may be connected to
GND.
RESV
21
I
This pin is reserved and should be connected to GND.
FIELD
34
O
FIELD output. The field output indicates that the encoder is outputting the odd or even video
field. The polarity of FIELD is programmable.
HSYNC
35
I/O
Horizontal sync input/output. As an input, this pin must be asserted during the horizontal
sync intervals. If it occurs early, the line time will be shortened. If it occurs late, the line time
will be lengthened by holding the outputs at the front porch level. As an output, it is asserted
during the horizontal sync intervals. The polarity of HSYNC is programmable. If not driven,
the circuit for this pin should include a 4-12kΩ pull up resistor connected to VAA.
VSYNC
36
I/O
Vertical sync input/output. As an input, this pin must be asserted during the vertical sync
intervals. If it occurs early, the field time will be shortened. If it occurs late, the field time will
be lengthened by holding the outputs at the blanking level. As an output, it is asserted during
the vertical sync intervals. The polarity of VSYNC is programmable. If not driven, the circuit
for this pin should include a 4-12kΩ pull up resistor connected to VAA.
BLANK
33
I/O
Composite blanking input/output. As an input, this pin must be asserted during the horizontal
and vertical blanking intervals. As an output, it is asserted during the horizontal and vertical
blanking intervals. The polarity of BLANK is programmable. If not driven, the circuit for this
pin should include a 4-12kΩ pull up resistor connected to VAA.
23
DESCRIPTION
HMP8170, HMP8171, HMP8172, HMP8173
Pin Descriptions
(Continued)
PIN
NAME
PIN
NUMBER
INPUT/
OUTPUT
CLK
39
I/O
CLK2
41
I
2x pixel clock input. This clock must be a continuous, free-running clock.
SCL
18
I
I2C interface clock input. The circuit for this pin should include a 4-6kΩ pull-up resistor
connected to VAA.
SA
19
I
I2C interface address select input.
SDA
20
I/O
RESET
25
I
Reset control input. A logical zero for a minimum of four CLK cycles resets the device.
RESET must be a logical one for normal operation.
Y
3
O
Luminance analog current output. This output contains luminance video, sync, blanking, and
information. In analog YUV or RGB output mode, an alternate signal is generated (see Table
12). It is capable of driving a 37.5Ω load. If not used, it should be connected to GND.
C
7
O
Chrominance analog current output. This output contains chrominance video, and blanking
information. In analog YUV or RGB output mode, an alternate signal is generated (see Table
12). It is capable of driving a 37.5Ω load. If not used, it should be connected to GND.
NTSC/PAL 1
11
O
Composite video analog current output. This output contains composite video, sync,
blanking, and information. In analog YUV or RGB output mode, an alternate signal is
generated (see Table 12). It is capable of driving a 37.5Ω load. If not used, it should be
connected to GND.
NTSC/PAL 2
15
O
Composite video analog current output. This output contains composite video, sync,
blanking, and information. In analog YUV or RGB output mode, an alternate signal is
generated (see Table 12). It is capable of driving a 37.5Ω load. If not used, it should be
connected to GND.
VREF
61
I/O
Voltage reference. An optional external 1.235V reference may be used to drive this pin. If
left floating, the internal voltage reference is used.
FS_ADJUST
62
Full scale adjust control. A resistor (RSET) connected between this pin and GND sets the
full-scale output current of each of the DACs.
COMP 1
64
Compensation pin. A 0.1µF ceramic chip capacitor should be connected between this pin
and VAA, as close to the device as possible.
COMP 2
63
Compensation pin. A 0.1µF ceramic chip capacitor should be connected between this pin
and VAA as close to the device as possible.
DESCRIPTION
1x pixel clock input/output. As an input, this clock must be free-running and synchronous to
the clock signal on the CLK2 pin. As an output, this pin may drive a maximum of one LS TTL
load. CLK is generated by dividing CLK2 by two or four, depending on the mode. If not
driven, the circuit for this pin should include a 4-12kΩ pull up resistor connected to VAA.
I2C interface data input/output. The circuit for this pin should include a 4-6kΩ pull-up resistor
connected to VAA.
VAA
+5V power. A 0.1µF ceramic capacitor, in parallel with a 0.01µF chip capacitor, should be
used between each group of VAA pins and GND. These should be as close to the device as
possible.
GND
Ground
24
HMP8170, HMP8171, HMP8172, HMP8173
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VAA to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0V
All Signal Pins . . . . . . . . . . . . . . . . . . . . . (GND – 0.5V) to (VAA + 0.5V)
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2
Thermal Resistance (Typical, Note 4)
θJA oC/W
PQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Vapor Phase Soldering, 1 Minute . . . . . . . . . . . . . . . . . . . . . .220oC
(PQFP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operation section of this specification is not implied.
NOTE:
4. θJA is measured with the component mounted on an evaluation printed circuit board in free air. Dissipation rating assumes that the device is
mounted with all its leads soldered to the PCB.
Electrical Specifications
VAA = +5V ±5%, RSET = 133Ω, VREF Unconnected, TA = 25oC, Unless Otherwise Specified
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Input Logic Low Voltage, VIL
-
-
0.8
V
Input Logic High Voltage, VIH
2.0
-
-
V
DC PARAMETERS, DIGITAL INPUTS EXCEPT CLK2, SDA, SCL
Input Logic Low Current, IIL
VIN = 0.0V
-
-
-10
µA
Input Logic High Current, IIH
VIN = VAA
-
-
10
µA
-
8
-
pF
Input Capacitance, CIN
DC PARAMETERS, CLK2 INPUT
Input Logic Low Voltage, VIL
-
-
0.3 x VAA
V
Input Logic High Voltage, VIH
0.7 x VAA
-
-
V
Input Logic Low Current, IIL
VIN = 0.0V
-
-
-10
µA
Input Logic High Current, IIH
VIN = VAA
-
-
10
µA
-
8
-
pF
Input Capacitance, CIN
DC PARAMETERS, SDA AND SCL INPUTS
Input Logic Low Voltage, VIL
-
-
0.3 x VAA
V
Input Logic High Voltage, VIH
0.7 x VAA
-
-
V
-
-
± 10
µA
-
8
-
pF
-
0.4
V
Input Current, II
VIN = 0.0V – VAA
Input Capacitance, CIN
DC PARAMETERS, DIGITAL OUTPUTS, EXCEPT SDA
Output Logic Low Voltage, VOL
IOL = 2mA
-
Output Logic High Voltage, VOH
IOH = -2mA
2.4
-
-
V
-
8
-
pF
-
-
0.4
V
-
8
-
pF
Output Capacitance, COUT
DC PARAMETERS, SDA OUTPUT
Output Logic Low Voltage, VOL
IOL = 3mA
Output Capacitance, COUT
DC PARAMETERS, ANALOG OUTPUTS
DAC Resolution
-
10
-
Bits
Integral Nonlinearity, INL
-
0.5
±2
LSB
Differential Nonlinearity, DNL
-
0.5
±1
LSB
Output Current
-
-
34.8
mA
Output Impedance
Output Capacitance
IOUT = 0mA
-
2M
-
Ω
IOUT = 34mA
-
300K
-
Ω
-
15
-
pF
0
-
1.4
V
IOUT = 0mA, CLK = 13.5MHz
Output Compliance Range
25
HMP8170, HMP8171, HMP8172, HMP8173
Electrical Specifications
VAA = +5V ±5%, RSET = 133Ω, VREF Unconnected, TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
Video Level Error
Internal Voltage Reference
External Voltage Reference
MIN
TYP
MAX
UNITS
(Note 5)
VREF Unconnected, RSET = 133Ω
TEST CONDITION
-
-
±10
%
VREF = 1.230V (Figure 27), RSET = 140Ω
-
-
±10
%
-
-
5
%
1.13
1.19
1.32
V
-50
-
50
µA
DAC to DAC Matching
VREF Output Voltage
Pin not connected, using internal reference
VREF Output Current
VREF Input Voltage
Pin connected to external reference shown in
Figure 27.
VREF Input Current
1.11
1.23
1.36
V
-500
-
500
µA
-
1
-
%
AC PARAMETERS, ANALOG OUTPUTS
Differential Gain Error
Using analog output filter shown in Figure 28A.
Differential Phase Error
-
1
-
Degree
SNR (Weighted)
-
70
-
dB
Hue Accuracy
-
2
-
Degree
Color Saturation Accuracy
-
2
-
%
Luminance Nonlinearity
-
1
-
%
Residual Subcarrier
-
-60
-
dB
-
±1.5
-
Degree
Analog Output Skew, tASK
-
-
3
ns
Analog Output Delay, tAD
-
-
12
ns
DAC-DAC Crosstalk
-
-60
-
dB
-
35
-
pV-s
8
-
-
ns
SCH Phase
SCH Phase Reset enabled
Glitch Energy
Using analog output filter shown in Figure 28A.
Includes clock and data feedthrough
AC PARAMETERS, DIGITAL INPUTS AND OUTPUTS EXCEPT SCL AND SDA
Setup Time, tS
Note 6.
Hold Time, tH
0
-
-
ns
CLK2 to Output Delay, tD
3
-
15
ns
CLK2 Frequency
-
-
30.0
MHz
CLK2 High Time, CLK2H
13.6
-
20.3
ns
CLK2 Low Time, CLK2L
13.6
-
20.3
ns
4
-
-
CLK
Cycles
RESET* Pulse Width Low, tRES
AC PARAMETERS, SCL AND SDA (I2C INTERFACE)
All AC parameters meet the fast-mode I2C Bus Interface specification.
POWER SUPPLY CHARACTERISTICS
DAC PSRR at DC
Note 7
Power Supply Range, VAA
Normal Supply Current, IAA
Power-Down Supply Current, IAA
Note 8
Power Dissipation
-
64
-
dB
4.75
5.0
5.25
V
-
-
260
mA
-
-
750
µA
-
1100
1300
mW
NOTES:
5. Output level is dependent on the voltage on VREF, the value of RSET, and the load.
6. Test performed with CL= 40pF, IO = ± 2mA, VIH = 3.0V, VIL = 0.0V. Input reference level is 2.0V for all inputs.
7. The supply voltage rejection is the relative variation of the full-scale output driving a 37.5Ω load for a ±5% supply variation:
PSRR = 20 x log (∆VAA /∆VOUT).
8. If using an external voltage reference, it is not powered down. The internal voltage reference is powered down.
26
HMP8170, HMP8171, HMP8172, HMP8173
Typical Performance Curves
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
-45.0
-50.0
-55.0
-60.0
-65.0
-70.0
-75.0
-80.0
-85.0
-90.0
-95.0
-100.0
APL = 44.3%
FIELD = 1 LINE = 47
AMPLITUDE (0dB = 714mVP-P)
BANDWIDTH 10kHz TO FULL
Wfm ---> PEDESTAL
NOISE LEVEL = -79.9dB RMS
1.0
AVERAGE
2.0
3.0
4.0
5.0
(MHz)
FIGURE 12. NOISE SPECTRUM (NTSC)
SETUP 7.5%
FIGURE 13. NTSC COLOR BAR VECTOR SCOPE PLOT
FIGURE 14. NTSC FCC COLOR BAR
27
SYSTEM LINE L 47 F1
ANGLE (DEG) 0.0
GAIN x1.000
0.000dB
525 LINE NTSC
BURST FROM SOURCE
HMP8170, HMP8171, HMP8172, HMP8173
Typical Performance Curves
105.0
104.5
104.0
103.5
103.0
102.5
102.0
101.5
101.0
100.5
100.0
99.5
99.0
98.5
98.0
97.5
97.0
96.5
96.0
95.5
95.0
FIELD = 1 LINE = 47
LUMINANCE NON LINEARITY (%)
(Continued)
wfm ---> 5 STEP
PEAK-TO-PEAK = 2.1
LINE FREQUENCY ERROR
0.00 (%)
100.0
99.1
99.1
99.8
97.9
-0.4
1ST
2ND
3RD
4TH
5TH
-0.2
0.2
0.4
LINE FREQUENCY 15.734 (kHz)
FIELD FREQUENCY 59.94 (Hz)
AVERAGE OFF
AVERAGE
FIGURE 15. LUMINANCE NON LINEARITY (NTSC)
LINE
0.0
(%)
JITTER (LINE 20 TO 250)
FIGURE 16. LINE FREQUENCY (NTSC)
525 LINE NTSC
MEAN SCH
0.8 DEGREES
2nsP-P
AVERAGE
FIGURE 17. H SYNC JITTER IN A FRAME (NTSC)
FIGURE 18. SCH PHASE MEASUREMENT
APL = 40.0%
SYSTEM LINE L 72
ANGLE (DEG) 0.0
GAIN x1.000
0.000dB
625 LINE PAL
BURST FROM SOURCE
DISPLAY +V AND -V
AVERAGE
FIGURE 19. NOISE SPECTRUM (PAL)
28
FIGURE 20. PAL COLOR BAR VECTOR SCAPE PLOT
HMP8170, HMP8171, HMP8172, HMP8173
Typical Performance Curves
(Continued)
LINE = 72
Wfm ---> COLOR BAR
FIGURE 21. COLORBAR (PAL)
105.0
104.5
104.0
103.5
103.0
102.5
102.0
101.5
101.0
100.5
100.0
99.5
99.0
98.5
98.0
97.5
97.0
96.5
96.0
95.5
95.0
LINE = 72
LUMINANCE NON LINEARITY (%)
wfm ---> 5 STEP
PEAK-TO-PEAK = 1.4
LINE FREQUENCY ERROR
0.00 (%)
100.0
97.9
99.1
99.1
99.8
-0.4
-0.2
0.0
(%)
0.2
LINE FREQUENCY 15.625 (kHz)
FIELD FREQUENCY 50.00 (Hz)
AVERAGE OFF
1ST
2ND
3RD
4TH
5TH
AVERAGE
FIGURE 22. LUMINANCE NON LINEARITY (PAL)
29
FIGURE 23. LINE FREQUENCY (PAL)
0.4
HMP8170, HMP8171, HMP8172, HMP8173
Typical Performance Curves
(Continued)
FIGURE 24. H SYNC JITTER IN A FRAME (PAL)
Application Information
PCB Considerations
A PCB board with a minimum of 4 layers is recommended,
with layers 1 and 4 (top and bottom) for signals and layers 2
and 3 for power and ground. The PCB layout should
implement the lowest possible noise on the power and
ground planes by providing excellent decoupling. PCB trace
lengths between groups of VAA and GND pins should be as
short as possible.
Component Placement
The optimum layout places the HMP817x at the edge of the
PCB and as close as possible to the video output connector.
External components should be positioned as close as
possible to the appropriate pin, ideally such that traces can
be connected point to point. Chip capacitors are
recommended where possible, with radial lead ceramic
capacitors the second-best choice.
Traces containing digital signals should not be routed over,
under, or adjacent to the analog output traces to minimize
crosstalk. If this is not possible, coupling can be minimized
by routing the digital signals at a 90 degree angle to the
analog signals. The analog output traces should also not
cross over or under the VCC power plane to maximize highfrequency power supply rejection.
Power and Ground Planes
A common ground plane for all devices, including the
HMP817x, is recommended. However, placing the encoder
on an electrically connected GND peninsula reduces noise
levels. All GND pins on the HMP817x must be connected to
the ground plane. Typical power and ground planes are
shown in Figure 26.
30
FIGURE 25. SCH PHASE MEASUREMENT
The small connection between the ground areas should be
made wide enough so that most of the encoders digital
inputs can be routed over or under it. It is especially
important that the CLK and CLK2 signals cross through the
connection.
The HMP817x should have its own power plane that is
isolated from the common power plane of the board, with a
gap between the two power planes of at least 1/8 inch. All
VAA pins of the HMP817x must be connected to this isolated
power plane.
The HMP817x power plane should be connected to the
board’s normal VCC power plane at a single point though a
low-resistance ferrite bead, such as a Ferroxcube
5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. The
ferrite bead provides resistance to switching currents,
improving the performance of HMP817x. A single, large
capacitor should also be used between the HMP817x power
plane and the ground plane to control low-frequency power
supply ripple.
HMP8170, HMP8171, HMP8172, HMP8173
FERRITE
BEAD
BULK AREA
CAPACITOR
VCC
8154/8156A
817x
LP
FILTERS
ANALOG
CONN.
VAA
PCB
FIGURE 26A. VCC AND VAA PLANES
GND
8154/8156A
817x
LP
FILTERS
ANALOG
CONN.
PCB
FIGURE 26B. COMMON GROUND PLANE
FIGURE 26. EXAMPLE POWER AND GROUND PLANES
For proper operation, power supply decoupling is required. It
should be done using a 0.1µF ceramic capacitor in parallel
with a 0.01µF chip capacitor for each group of VAA pins to
ground. These capacitors should be located as close to the
VAA and GND pins as possible, using short, wide traces.
If a separate linear regulator is used to provide power to the
HMP817x power plane, the power-up sequence should be
designed to ensure latchup will not occur. A separate linear
regulator is recommended if the power supply noise on the
31
VAA pins exceeds 200mV. About 10% of the noise (that is
less than 1MHz) on the VAA pins will couple onto the analog
outputs.
External Reference Voltage
If an external reference voltage is used, its circuitry should
receive power from the same plane as the HMP817x. The
external VREF must also be stable and well decoupled from
the power plane. An example VREF circuit using a band gap
reference diode is shown in Figure 27.
HMP8170, HMP8171, HMP8172, HMP8173
Analog Output Filters
VAA
The various video standards specify the frequency response
of the video signal. The HMP817x uses 2X oversampling
DACs to simplify the reconstruction filter required. Example
post filters are shown in Figure 28. The analog output filters
should be as close as possible to the HMP817x.
6.8K
1.235V
ICL8069
+
4.7µF
0.01µF
FIGURE 27. EXTERNAL REFERENCE VOLTAGE CIRCUIT
1.0µH
1.0µH
2.2µH
75
82pF
330pF
330pF
39pF
RL
75
FIGURE 28A. HIGH QUALITY FILTER
2.7µH
75
560pF
560pF
RL
75
FIGURE 28B. LOW COST FILTER
FIGURE 28. EXAMPLE POST-FILTER CIRCUITS
Evaluation Kits
The HMP817xEVAL1 is a small (index card size) printed
circuit board containing the encoder, voltage references and
bypassing, analog output filters, and input/output
connectors. The board allows the encoder’s operation and
performance to be observed and measured.
The HMP817xEVAL1 board has a 50 pin, two row receptacle
which allows connection into an existing system. The
connector provides access to all of the encoder’s digital
inputs and outputs.
The HMP8156EVAL2 is the Intersil designed mother board
for the HMP817xEVAL1. The mother board is a standard
size PC add in card with an ISA bus interface and application
software. The HMP8156EVAL2 kit is a complete system
which allows demonstrating all of both encoders’ operating
modes. It has analog video inputs for composite, S-video,
and component RGB signals. The analog signals are
32
converted/decoded to the digital domain and input to the
encoder. The board also provides a 3 megabyte video RAM
for image capture and display and a BT.656 connector and
interface.
For simpler operation, the HMP817xEVAL1 may also be
driven by external power supplies, a BT.656 signal
generator, and a PC parallel port. The evaluation kit includes
application software to program the part using its I2C bus
connected to the printer port. The board includes the
standard 25 pin BT.656 connector and interface.
HMP8170, HMP8171, HMP8172, HMP8173
Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
Q64.14x14 (JEDEC MO-108BD-2 ISSUE A)
D
64 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.10
0.004
-C-
5o-16o
0.40
0.016 MIN
0.20
M C A-B S
0.008
0o MIN
A2 A1
0o-7o
L
MIN
MAX
MIN
MAX
NOTES
A
-
0.130
-
3.30
-
A1
0.004
0.010
0.10
0.25
-
A2
0.100
0.120
2.55
3.05
-
B
0.012
0.018
0.30
0.45
6
B1
0.012
0.016
0.30
0.40
-
D
0.667
0.687
16.95
17.45
3
D1
0.547
0.555
13.90
14.10
4, 5
E
0.667
0.687
16.95
17.45
3
E1
0.547
0.555
13.90
14.10
4, 5
L
0.026
0.037
0.65
0.95
N
64
64
e
0.032 BSC
0.80 BSC
7
Rev. 0 1/94
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
B
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
B1
BASE METAL
WITH PLATING
MILLIMETERS
D S
0.13/0.17
0.005/0.007
5o-16o
INCHES
SYMBOL
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
0.13/0.23
0.005/0.009
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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33
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