IDT ICS9DB803DFILFT Eight output differential buffer for pcie gen 2 Datasheet

DATASHEET
ICS9DB803DI
Eight Output Differential Buffer for PCIe Gen 2
Description
Features/Benefits
The 9DB803 is a DB800 Version 2.0 Yellow Cover part with PCI
Express Gen II support. It can be used in PC or embedded
systems to provide outputs that have low cycle-to-cycle jitter
(50ps), low output-to-output skew (100ps), and are PCI Express
Gen 2 compliant. The 9DB803 supports a 1 to 8 output
configuration, taking a spread or non spread differential HCSL
input from a CK410(B) main clock such as 954101 and
932S401, or any other differential HCSL pair. 9DB803 can
generate HCSL or LVDS outputs from 50 to 100MHz in PLL
mode or 50 to 400Mhz in bypass mode. There are two dejittering modes available selectable through the HIGH_BW#
input pin, high bandwidth mode provides de-jittering for spread
inputs and low bandwidth mode provides extra de-jittering for
non-spread inputs. The SRC_IN#, PD#, and individual OE realtime input pins provide completely programmable power
management control.
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
•
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Output Features
•
•
•
8 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
Key Specifications
•
•
•
•
•
•
•
•
Outputs cycle-cycle jitter < 50ps
Outputs skew: 50ps
50-100 MHz operation in PLL mode
50-400 MHz operation in Bypass mode
Phase jitter: PCIe Gen1 < 86ps peak to peak
Phase jitter: PCIe Gen2 < 3.1ps rms
48-pin SSOP/TSSOP package
Available in RoHS compliant packaging
Funtional Block Diagram
8
OE_(7:0)
SPREAD
COMPATIBLE
PLL
SRC_IN
SRC_IN#
M
U
X
STOP
LOGIC
8
DIF(7:0))
SRC_STOP#
HIGH_BW#
BYPASS#/PLL
PD#
CONTROL
LOGIC
IREF
SDATA
SCLK
LOCK
Note: Polarities shown for OE_INV = 0.
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
1
REV A 06/18/08
ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
LOCK
OE_7
OE_4
DIF_7
DIF_7#
OE_INV
VDD
DIF_6
DIF_6#
OE_6
OE_5
DIF_5
DIF_5#
GND
VDD
DIF_4
DIF_4#
HIGH_BW#
DIF_STOP#
PD#
GND
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE0#
OE3#
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE1#
OE2#
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
Polarity Inversion Pin List Table
1
6
OE_0
OE0#
7
OE_3
OE3#
14
OE_1
OE1#
15
OE_2
OE2#
26
PD#
PD
27
DIF_STOP#
DIF_STOP
35
OE_5
OE5#
36
OE_6
OE6#
43
OE_4
OE4#
44
OE_7
OE7#
VDDA
GNDA
IREF
LOCK
OE7#
OE4#
DIF_7
DIF_7#
OE_INV
VDD
DIF_6
DIF_6#
OE6#
OE5#
DIF_5
DIF_5#
GND
VDD
DIF_4
DIF_4#
HIGH_BW#
DIF_STOP
PD
GND
Power Groups
Pin Number
VDD
GND
2
3
6,11,19,
10,18, 25,32
31,39
N/A
47
48
47
OE_INV
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE_INV = 1
OE_INV = 0
Pins
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9DB803
(Same as ICS9DB801)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9DB803
(Same as ICS9DB108)
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
Description
SRC_IN/SRC_IN#
DIF(7:0)
IREF
Analog VDD & GND for PLL core
ICS9DB803DI
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ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Pin Description for OE_INV = 0
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
IN
Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
1
SRC_DIV#
2
VDD
PWR
Power supply, nominal 3.3V
3
GND
PWR
Ground pin.
4
SRC_IN
IN
0.7 V Differential SRC TRUE input
5
SRC_IN#
IN
6
OE_0
IN
7
OE_3
IN
8
9
10
DIF_0
DIF_0#
GND
OUT
OUT
PWR
0.7 V Differential SRC COMPLEMENTARY input
Active high input for enabling output 0.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling output 3.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
11
VDD
PWR
Power supply, nominal 3.3V
12
DIF_1
OUT
0.7V differential true clock output
13
DIF_1#
OUT
14
OE_1
IN
15
OE_2
IN
0.7V differential complement clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling output 2.
0 = tri-state outputs, 1= enable outputs
16
DIF_2
OUT
0.7V differential true clock output
17
18
DIF_2#
GND
OUT
PWR
0.7V differential complement clock output
Ground pin.
19
VDD
PWR
Power supply, nominal 3.3V
20
DIF_3
OUT
0.7V differential true clock output
21
DIF_3#
OUT
0.7V differential complement clock output
22
BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23
24
SCLK
SDATA
IN
I/O
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
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REV A 06/18/08
ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Pin Description for OE_INV = 0
PIN #
25
PIN NAME
GND
PIN TYPE
PWR
DESCRIPTION
Ground pin.
26
PD#
IN
27
DIF_STOP#
IN
28
HIGH_BW#
PWR
29
DIF_4#
OUT
Asynchronous active low input pin used to power down the device.
The internal clocks are disabled and the VCO and the crystal are
stopped.
Active low input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock output
30
DIF_4
OUT
0.7V differential true clock output
31
VDD
PWR
Power supply, nominal 3.3V
32
33
34
GND
DIF_5#
DIF_5
PWR
OUT
OUT
35
OE_5
IN
36
OE_6
IN
37
DIF_6#
OUT
Ground pin.
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 5.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
38
DIF_6
OUT
0.7V differential true clock output
39
VDD
PWR
Power supply, nominal 3.3V
40
OE_INV
IN
41
42
DIF_7#
DIF_7
OUT
OUT
43
OE_4
IN
44
OE_7
IN
45
LOCK
OUT
46
IREF
IN
47
48
GNDA
VDDA
PWR
PWR
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 4.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling output 7.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high when
lock is achieved.
This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
4
REV A 06/18/08
ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Pin Description for OE_INV = 1
PIN #
PIN NAME
PIN TYPE
IN
DESCRIPTION
Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
1
SRC_DIV#
2
VDD
PWR
Power supply, nominal 3.3V
3
GND
PWR
Ground pin.
4
SRC_IN
IN
0.7 V Differential SRC TRUE input
5
SRC_IN#
IN
6
OE0#
IN
7
OE3#
IN
8
9
10
DIF_0
DIF_0#
GND
OUT
OUT
PWR
0.7 V Differential SRC COMPLEMENTARY input
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
11
VDD
PWR
Power supply, nominal 3.3V
12
DIF_1
OUT
0.7V differential true clock output
13
DIF_1#
OUT
14
OE1#
IN
15
OE2#
IN
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
16
DIF_2
OUT
0.7V differential true clock output
17
18
DIF_2#
GND
OUT
PWR
0.7V differential complement clock output
Ground pin.
19
VDD
PWR
Power supply, nominal 3.3V
20
DIF_3
OUT
0.7V differential true clock output
21
DIF_3#
OUT
0.7V differential complement clock output
22
BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23
24
SCLK
SDATA
IN
I/O
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
5
REV A 06/18/08
ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Pin Description for OE_INV = 1
PIN #
PIN NAME
PIN TYPE
25
GND
PWR
26
PD
IN
27
DIF_STOP
IN
DESCRIPTION
Ground pin.
Asynchronous active high input pin used to power down the device.
The internal clocks are disabled and the VCO is stopped.
Active High input to stop differential output clocks.
28
HIGH_BW#
PWR
29
DIF_4#
OUT
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock output
30
DIF_4
OUT
0.7V differential true clock output
31
VDD
PWR
Power supply, nominal 3.3V
32
33
34
GND
DIF_5#
DIF_5
PWR
OUT
OUT
35
OE5#
IN
36
OE6#
IN
37
DIF_6#
OUT
Ground pin.
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
38
DIF_6
OUT
0.7V differential true clock output
39
VDD
PWR
Power supply, nominal 3.3V
40
OE_INV
IN
41
42
DIF_7#
DIF_7
OUT
OUT
43
OE4#
IN
44
OE7#
IN
45
LOCK
OUT
46
IREF
IN
47
48
GNDA
VDDA
PWR
PWR
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
3.3V output indicating PLL Lock Status. This pin goes high when lock
is achieved.
This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
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ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Absolute Max
Symbol
VDD_A
VDD_In
VIL
VIH
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
ESD prot
Min
Max
4.6
4.6
GND-0.5
VDD+0.5V
-65
-40
Units
V
V
V
V
150
85
115
2000
°
C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = -40 - 85°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
VIH
VIL
I IH
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
2
GND - 0.3
-5
I IL1
VIN = 0 V; Inputs with no pull-up resistors
-5
uA
I IL2
VIN = 0 V; Inputs with pull-up resistors
-200
uA
Operating Supply Current
I DD3.3OP
Full Active, CL = Full load;
200
mA
Powerdown Current
I DD3.3PD
all diff pairs driven
all differential pairs tri-stated
PLL Mode
Bypass Mode
60
6
110
400
7
5
6
4
1.4
mA
mA
MHz
MHz
nH
pF
pF
MHz
MHz
1
1
1
1
1
1
1
1
ms
1,2
33
kHz
1
10
ns
1,3
300
us
1,3
5
5
ns
ns
1
2
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Frequency
Pin Inductance
Capacitance
FiPLL
FiBYPASS
Lpin
CIN
COUT
PLL Bandwidth
BW
Clk Stabilization
TSTAB
Modulation Frequency
fMOD
Tdrive_SRC_STOP#
tDRVSTP
Tdrive_PD#
tDRVPD
Tfall
Trise
tF
tR
Logic Inputs
Output pin capacitance
PLL Bandwidth when PLL_BW=0
PLL Bandwidth when PLL_BW=1
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st
clock
Triangular Modulation
DIF output enable after
SRC_Stop# de-assertion
DIF output enable after
PD# de-assertion
Fall time of PD# and SRC_STOP#
Rise time of PD# and SRC_STOP#
VDD + 0.3
0.8
5
UNITS NOTES
50
50
1.5
2
0.7
30
3
1
V
V
uA
1
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
3
Time from deassertion until outputs are >200 mV
2
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
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REV A 06/18/08
ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Electrical Characteristics - Clock Input Parameters
TA = -40 - 85°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage DIF_IN
Input Low Voltage DIF_IN
Input Common Mode
Voltage - DIF_IN
SYMBOL
VIHDIF
VILDIF
CONDITIONS
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
MIN
TYP
MAX
UNITS NOTES
600
800
1150
mV
1
VSS - 300
0
300
mV
1
VCOM
Common Mode Input Voltage
300
1000
mV
1
Input Amplitude - DIF_IN
VSWING
Peak to Peak value
300
1450
mV
1
Input Slew Rate - DIF_IN
dv/dt
Measured differentially
0.4
8
V/ns
1,2
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to
Cycle
I IN
dtin
VIN = VDD , VIN = GND
Measurement from differential wavefrom
-5
45
5
55
uA
%
1
1
J DIFIn
Differential Measurement
0
125
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through Vswing min centered around differential zero
2
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
8
REV A 06/18/08
ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = -40 - 85°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, RREF=475Ω
PARAMETER
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
Skew
SYMBOL
1
Zo
CONDITIONS
MIN
VO = Vx
3000
TYP
MAX
UNITS NOTES
Ω
Statistical measurement on single ended signal 660
VHigh
850
mV
using oscilloscope math function.
VLow
-150
150
Measurement on single ended signal using
Vovs
1150
mV
absolute value.
Vuds
-300
Vcross(abs)
250
550
mV
d-Vcross
Variation of crossing over all edges
140
mV
ppm
see Tperiod min-max values
0
ppm
VOL = 0.175V, VOH = 0.525V
tr
175
700
ps
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
d-tr
125
ps
d-tf
125
ps
dt3
Measurement from differential wavefrom
45
50
55
%
tsk3
VT = 50%
60
ps
PLL mode
40
50
ps
tjcyc-cyc
Jitter, Cycle to cycle
BYPASS mode as additive jitter
15
50
ps
PCIe Gen 1 specs
30
86
ps
(pk to pk value)
tjphasebypass
PCIe Gen 2 specs
2.6
3.1
ps
(rms value)
Jitter, Phase
PCIe Gen 1 specs
40
86
ps
(pk to pk value)
tjphasePLL
PCIe Gen 2 specs
2.8
3.1
ps
(rms value)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK409/CK410/CK505
accuracy requirements. The 9DB403/803 itself does not contribute to ppm error.
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
4
Applies to Bypass Mode Only
5
Measured from differential waveform
6
See http://www.pcisig.com for complete specs
7
Device driven by HP81134A Pulse Generator
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
9
1
1,3
1,3
1
1
1
1
1,2
1
1
1
1
1
1
1,5
1,5
1,6,7
1,6,7
1,6,7
1,6,7
REV A 06/18/08
ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Clock Periods Differential Outputs with Spread Spectrum Enabled
Measurement
Window
Symbol
Signal Name
Definition
DIF 100
DIF 133
DIF 166
DIF 200
DIF 266
DIF 333
DIF 400
1 Clock
LgAbsolute
Period
Minimum
Absolute
Period
9.87400
7.41425
5.91440
4.91450
3.66463
2.91470
2.41475
1us
-SSC
Short-term
Average
Minimum
Absolute
Period
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
0.1s
-ppm error
Long-Term
Average
Minimum
Absolute
Period
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
0.1s
0ppm
Period
1 Clock
Lg+
Period
Nominal
Maximum
Maximum
Maximum
10.00000
7.50000
6.00000
5.00000
3.75000
3.00000
2.50000
10.00100
7.50075
6.00060
5.00050
3.75038
3.00030
2.50025
10.05130
7.53845
6.03076
5.02563
3.76922
3.01538
2.51282
10.17630
7.62345
6.11576
5.11063
3.85422
3.10038
2.59782
Signal Name
Clock Periods Differential Outputs with Spread Spectrum Disabled
Measurement
Window
1 Clock
1us
0.1s
0.1s
Symbol
Lg-SSC
-ppm error
0ppm
Absolute Short-term Long-Term
Period
Average
Period
Average
Definition
Minimum
Minimum
Minimum
Absolute
Absolute
Absolute
Nominal
Period
Period
Period
9.87400
9.99900
10.00000
DIF 100
7.41425
7.49925
7.50000
DIF 133
5.91440
5.99940
6.00000
DIF 166
4.91450
4.99950
5.00000
DIF 200
3.66463
3.74963
3.75000
DIF 266
2.91470
2.99970
3.00000
DIF 333
2.41475
2.49975
2.50000
DIF 400
1
0.1s
1us
+ ppm error
+SSC
Long-Term Short-term
Average
Average
0.1s
1us
+ ppm error
+SSC
Long-Term Short-term
Average
Average
Maximum
10.00100
7.50075
6.00060
5.00050
3.75038
3.00030
2.50025
Maximum
Units
ns
ns
ns
ns
ns
ns
ns
Notes
1,2,3
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
Units
ns
ns
ns
ns
ns
ns
ns
Notes
1,2,3
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1 Clock
Lg+
Period
Maximum
10.17630
7.62345
6.11576
5.11063
3.85422
3.10038
2.59782
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with
CK409/CK410/CK505 accuracy requirements. The 9DB403/803 itself does not contribute to ppm error.
3
4
Driven by SRC output of main clock, PLL or Bypass mode
Driven by CPU output of CK410/CK505 main clock, Bypass mode only
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
10
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ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
L3 length, Route as non-coupled 50 ohm trace.
0.2 max
Rs
33
Rt
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
Down Device Differential Routing
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit
inch
inch
Figure
1
1
Differential Routing to PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
Figure
2
2
Figure 1 Down device routing.
L1
L2
L4
Rs
L1’
L4’
L2’
Rs
Rt
HSCL Output
Buffer
L3’
Rt
PCI Ex Board
Down Device
REF_CLK Input
L3
Figure 1
Figure 2 PCI Express Connector Routing.
L1
L2
L4
Rs
L1’
L4’
L2’
Rs
HSCL Output
Buffer
Rt
L3’
Rt
L3
PCI Ex
Add In Board
REF_CLK Input
Figure 2
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
11
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ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff
Vp-p
0.45 v
0.22v
0.58
0.28
0.80
0.40
0.60
0.3
R1a = R1b = R1
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
150
78.7
78.7
174
R3
100
137
none
140
R4
100
100
100
100
Note
ICS874003i-02 input compatible
Standard LVDS
Figure_3.
L1
L2
R3
L4
R1a
L1’
L4’
L2’
R1b
R2a
HSCL Output
Buffer
R4
R2b
Down Device
REF_CLK Input
L3
L3’
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component
R5a,R5b
R6a,R6b
Cc
Vcm
Value
8.2K 5%
1K 5%
0.1 uF
0.350 volts
Note
3.3 Volts
R5a
R5b
L4
L4’
Cc
Cc
R6a
R6b
PCIe Device
REF_CLK Input
Figure_4.
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
12
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ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
General SMBus serial interface information for the ICS9DB803DI
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address DC (h)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address DC(h)
WRite
WR
Controller (host) will send start bit.
Controller (host) sends the write address DC (h)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD (h)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address DC(h)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address DD(h)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
Not acknowledge
stoP bit
ICS9DB803DI
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Eight Output Differential Buffer for PCIe for Gen 2
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Pin #
Name
Control Function
Type
Byte 0
PD_Mode
PD# drive mode
RW
Bit 7
STOP_Mode
SRC_Stop# drive mode
RW
Bit 6
PD_Polarity
Select PD polarity
RW
Bit 5
Reserved
Reserved
RW
Bit 4
Reserved
Reserved
RW
Bit 3
PLL_BW#
Select PLL BW
RW
Bit 2
BYPASS#
BYPASS#/PLL
RW
Bit 1
SRC_DIV#
SRC Divide by 2 Select
RW
Bit 0
0
1
driven
Hi-Z
driven
Hi-Z
Low
High
Reserved
Reserved
High BW Low BW
fan-out
ZDB
x/2
1x
PWD
0
0
0
X
X
1
1
1
SMBus Table: Output Control Register
Pin #
Name
Byte 1
42,41
DIF_7
Bit 7
38,37
DIF_6
Bit 6
34,33
DIF_5
Bit 5
DIF_4
30,29
Bit 4
DIF_3
20,21
Bit 3
DIF_2
16,17
Bit 2
DIF_1
12,13
Bit 1
8,9
DIF_0
Bit 0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBus Table: Output Control Register
Byte 2
Pin #
Name
42,41
DIF_7
Bit 7
38,37
DIF_6
Bit 6
34,33
DIF_5
Bit 5
30,29
DIF_4
Bit 4
20,21
DIF_3
Bit 3
16,17
DIF_2
Bit 2
12,13
DIF_1
Bit 1
8,9
DIF_0
Bit 0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
1
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
PWD
0
0
0
0
0
0
0
0
SMBus Table: Output Control Register
Pin #
Name
Byte 3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ICS9DB803DI
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ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
SMBus Table: Vendor & Revision ID Register
Byte 4
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBus Table: DEVICE ID
Byte 5
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
REVISION ID
VENDOR ID
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
X
X
X
X
0
0
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
0
X
X
0
0
0
1
1
Device ID is 83 Hex
for 9DB803 and 43
Hex for 9DB403
SMBus Table: Byte Count Register
Pin #
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Control
Function
Type
0
1
PWD
Writing to this register configures how
many bytes will be read back.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
0
1
1
1
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
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Eight Output Differential Buffer for PCIe for Gen 2
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
PD#, Power Down
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting
off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the
device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD#
drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PWRDWN#
DIF
DIF#
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
Tstable
<1mS
PWRDWN#
DIF
DIF#
Tdrive_PwrDwn#
<300uS, >200mV
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
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ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
SRC_STOP#
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP# - Assertion
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
SRC_STOP# - De-assertion (transition from '0' to '1')
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
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Eight Output Differential Buffer for PCIe for Gen 2
SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
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ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
c
N
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
N
α
L
E1
E
INDEX
AREA
1 2
α
h x 45°
D
A
N
A1
48
-C-
e
b
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
D (inch)
MIN
.620
MAX
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
SEATING
PLANE
.10 (.004) C
Ordering Information
ICS9DB803DFILFT
Example:
ICS XXXX D F I LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Industrial Temperature
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
19
REV A 06/18/08
ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP
c
N
(240 mil)
L
E1
INDEX
AREA
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
a
aaa
E
1 2
a
D
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-1.20
0.05
0.15
0.80
1.05
0.17
0.27
0.09
0.20
SEE VARIATIONS
8.10 BASIC
6.00
6.20
0.50 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
-0.10
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.011
.0035
.008
SEE VARIATIONS
0.319 BASIC
.236
.244
0.020 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
VARIATIONS
A
A2
(20 mil)
N
A1
48
-C-
D (inch)
D mm.
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
Reference Doc.: JEDEC Publication 95, MO-153
e
b
SEATING
PLANE
10-0039
aaa C
Ordering Information
ICS9DB803DGILFT
Example:
ICS XXXX D G I LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Industrial Temperature
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803DI
20
REV A 06/18/08
ICS9DB803DI
Eight Output Differential Buffer for PCIe Gen 2
Revision History
Rev.
0.1
Issue Date Description
6/18/2008 1. Initial Release
Page #
A
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+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
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21