TI1 DAC7562-Q1 Low-power, buffered, voltage-output dac Datasheet

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DAC7562-Q1, DAC7563-Q1
DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
SLAS950A – MAY 2013 – REVISED JUNE 2015
DACxx6x-Q1 Automotive Dual 16-, 14-, 12-Bit, Low-Power, Buffered,
Voltage-Output DACs With 2.5-V, 4-PPM/°C Internal Reference
1 Features
3 Description
•
•
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1
(DACxx6x-Q1) devices are low-power, voltage-output,
dual-channel, 12-, 14-, and 16-bit digital-to-analog
converters (DACs), respectively. These devices
include a 2.5-V, 4-ppm/°C internal reference, giving a
full-scale output voltage range of 2.5 V or 5 V. The
internal reference has an initial accuracy of ±5 mV
and can source or sink up to 20 mA at the
VREFIN/VREFOUT pin.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Relative Accuracy:
– DAC756x (12-Bit): 0.3 LSB INL
– DAC816x (14-Bit): 1 LSB INL
– DAC856x (16-Bit): 4 LSB INL
Glitch Impulse: 0.1 nV-s
Bidirectional Reference: Input or 2.5-V Output
– Output Disabled by Default
– ±5-mV Initial Accuracy (Max)
– 4-ppm/°C Temperature Drift (Typ)
– 10-ppm/°C Temperature Drift (Max)
– 20-mA Sink and Source Capability
Power-On Reset to Zero Scale or Mid-Scale
Low-Power: 4 mW (Typ, 5-V AVDD, Including
Internal Reference Current)
Wide Power-Supply Range: 2.7 V to 5.5 V
50-MHz SPI With Schmitt-Triggered Inputs
LDAC and CLR Functions
Output Buffer With Rail-to-Rail Operation
Package: VSSOP-10
These devices are monotonic, providing excellent
linearity and minimizing undesired code-to-code
transient voltages (glitch). They use a versatile threewire serial interface that operates at clock rates up to
50 MHz. The interface is compatible with standard
SPI™, QSPI™, Microwire, and digital signal
processor (DSP) interfaces. The DACxx62-Q1
devices incorporate a power-on-reset circuit that
ensures the DAC output powers up and remains at
zero scale until a valid code is written to the device,
whereas the DACxx63-Q1 devices similarly power up
at mid-scale. These devices contain a power-down
feature that reduces current consumption to typically
550 nA at 5 V. The low power consumption, internal
reference, and small footprint make these devices
ideal for portable, battery-operated equipment.
The DACxx62-Q1 devices are drop-in and functioncompatible with each device in this family, as are the
DACxx63-Q1 devices. The entire family is available in
a 10-pin VSSOP-10 (DGS) package.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
PACKAGE
BODY SIZE (NOM)
DAC7562-Q1
Portable Instrumentation
PLC Analog Output Module
Closed-Loop Servo Control
Voltage Controlled Oscillator Tuning
Data Acquisition Systems
Programmable Gain and Offset Adjustment
DAC7563-Q1
DAC8162-Q1
VSSOP (10)
DAC8163-Q1
3.00 mm × 3.00 mm
DAC8562-Q1
DAC8563-Q1
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Block Diagram
GND
AVDD
DIN
SCLK
SYNC
LDAC
CLR
Buffer Control
Register Control
Input Control Logic
Control Logic
DAC756x-Q1 (12-Bit)
DAC816x-Q1 (14-Bit)
DAC856x-Q1 (16-Bit)
VREFIN/VREFOUT
2.5-V
Reference
PowerDown
Control
Logic
Data Buffer B
DAC Register B
DAC
VOUTB
Data Buffer A
DAC Register A
DAC
VOUTA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC7562-Q1, DAC7563-Q1
DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
SLAS950A – MAY 2013 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 26
8.1 Overview ................................................................. 26
8.2 Functional Block Diagram ....................................... 26
8.3 Feature Description................................................. 26
8.4 Device Functional Modes........................................ 30
8.5 Programming........................................................... 34
9
Application and Implementation ........................ 37
9.1 Application Information............................................ 37
9.2 Typical Applications ................................................ 39
9.3 System Examples ................................................... 43
10 Power Supply Recommendations ..................... 44
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 45
12 Device and Documentation Support ................. 46
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
46
46
13 Mechanical, Packaging, and Orderable
Information ........................................................... 47
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2013) to Revision A
Page
•
Changed Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Released the DAC8563-Q1, DAC8162-Q1, DAC8163-Q1, DAC7562-Q1, and DAC7563-Q1 devices................................. 1
•
Added the code-change total glitch amplitude parameter to the Electrical Characteristics table ......................................... 5
2
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DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
www.ti.com
SLAS950A – MAY 2013 – REVISED JUNE 2015
5 Device Comparison Table
PART NUMBER
DAC7562-Q1
DAC7563-Q1
DAC8162-Q1
DAC8163-Q1
DAC8562-Q1
DAC8563-Q1
RESOLUTION
MAXIMUM RELATIVE
ACCURACY (LSB)
MAXIMUM DIFFERENTIAL
NONLINEARITY (LSB)
MAXIMUM REFERENCE
DRIFT (ppm/°C)
12-bit
±0.75
±0.25
10
14-bit
±3
±0.5
10
16-bit
±12
±1
10
RESET TO
Zero
Mid-scale
Zero
Mid-scale
Zero
Mid-scale
6 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
VOUTA
1
10
VOUTB
2
9
AVDD
GND
3
8
DIN
LDAC
4
7
SCLK
CLR
5
6
SYNC
VREFIN/VREFOUT
Pin Functions
PIN
NAME
AVDD
DESCRIPTION
NO.
9
Power-supply input, 2.7 V to 5.5 V
CLR
5
Asynchronous clear input. The CLR input is falling-edge sensitive. When CLR is activated, zero scale (DACxx62Q1) or mid-scale (DACxx63-Q1) is loaded to all input and DAC registers. This sets the DAC output voltages
accordingly. The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is
activated during a write sequence, the write is aborted.
DIN
8
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Schmitt-trigger logic input
GND
3
Ground reference point for all circuitry on the device
LDAC
4
In synchronous mode, data are updated with the falling edge of the 24th SCLK cycle, which follows a falling edge
of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND
permanently or asserted and held low before sending commands to the device.
In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC
updates. Multiple single-channel commands can be written in order to set different channel buffers to desired
values and then make a falling edge on LDAC pin to simultaneously update the DAC output registers.
SCLK
7
Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input
SYNC
6
Level-triggered control input (active-low). This input is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The
DAC output updates following the 24th clock falling edge. If SYNC is taken high before the 23rd clock edge, the
rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC756x-Q1, DAC816x-Q1,
DAC856x-Q1. Schmitt-trigger logic input
VOUTA
1
Analog output voltage from DAC-A
VOUTB
2
Analog output voltage from DAC-B
VREFIN/VREFOUT
10
Bidirectional voltage reference pin. If internal reference is used, 2.5-V output.
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SLAS950A – MAY 2013 – REVISED JUNE 2015
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
MIN
MAX
UNIT
AVDD to GND
–0.3
6
V
CLR, DIN, LDAC, SCLK and SYNC input voltage to GND
–0.3
AVDD + 0.3
V
VOUT[A, B] to GND
–0.3
AVDD + 0.3
V
VREFIN/VREFOUT to GND
–0.3
AVDD + 0.3
V
Operating temperature
–40
125
°C
150
°C
150
°C
Junction temperature, TJ max
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per All pins
AEC Q100-011
Corner pins (1, 5, 6, and 10)
±500
UNIT
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Supply voltage
AVDD to GND
2.7
5.5
V
0
AVDD
V
0
AVDD
V
–40
125
°C
DIGITAL INPUTS
Digital input voltage
CLR, DIN, LDAC, SCLK and SYNC
REFERENCE INPUT
VREFIN
Reference input voltage
TEMPERATURE RANGE
TA
Operating ambient temperature
7.4 Thermal Information
DACxx6x-Q1
THERMAL METRIC (1)
DGS (VSSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
173.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.5
°C/W
RθJB
Junction-to-board thermal resistance
79.9
°C/W
ψJT
Junction-to-top characterization parameter
1.7
°C/W
ψJB
Junction-to-board characterization parameter
68.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
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SLAS950A – MAY 2013 – REVISED JUNE 2015
7.5 Electrical Characteristics
At AVDD = 2.7 V to 5.5 V and TA = –40°C to 125°C (unless otherwise noted).
PARAMETER
STATIC PERFORMANCE
TEST CONDITIONS
Resolution
DAC856x-Q1
Relative accuracy
Differential nonlinearity
16-bit monotonic
MAX
UNIT
Relative accuracy
Using line passing through codes 128 and
16,256
Differential nonlinearity
14-bit monotonic
±4
±12
LSB
±0.2
±1
LSB
Bits
±1
±3
LSB
±0.1
±0.5
LSB
±0.3
±0.75
LSB
±0.05
±0.25
LSB
±1
±4
12
Relative accuracy
Using line passing through codes 32 and 4,064
Differential nonlinearity
12-bit monotonic
Extrapolated from two-point line (1), unloaded
Offset error
Bits
14
Resolution
DAC756x-Q1
TYP
16
Using line passing through codes 512 and
65,024
Resolution
DAC816x-Q1
MIN
(1)
Offset error drift
Bits
±2
Full-scale error
DAC register loaded with all 1s
±0.03
±0.2
Zero-code error
DAC register loaded with all 0s
1
4
Zero-code error drift
±2
Extrapolated from two-point line (1), unloaded
Gain error
±0.01
Gain temperature coefficient
mV
µV/°C
% FSR
mV
µV/°C
±0.15
±1
% FSR
ppm FSR/°C
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time (3)
0
DACs unloaded
RL = 1 MΩ
Measured between 20% - 80% of a full-scale
transition
Slew rate
Capacitive load stability
AVDD
7
10
0.75
RL = ∞
1
RL = 2 kΩ
3
V
µs
V/µs
nF
Code-change glitch impulse
1-LSB change around major carry
0.1
nV-s
Digital feedthrough
SCLK toggling, SYNC high
0.1
nV-s
Power-on glitch impulse
RL = 2 kΩ, CL = 470 pF, AVDD = 5.5 V
40
mV
Code-change total glitch amplitude
1-LSB change around major carry. Includes
glitch impulse and digital feedthrough.
RL = 2 kΩ, CL = 470 pF, AVDD = 5.5 V
3
mV
Full-scale swing on adjacent channel,
External reference
5
Full-scale swing on adjacent channel,
Internal reference
15
Channel-to-channel DC crosstalk
µV
5
Ω
DAC outputs at full-scale, DAC outputs shorted
to GND
40
mA
Coming out of power-down mode
50
µs
DC output impedance
At mid-scale input
Short-circuit current
Power-up time, including settling time
AC PERFORMANCE (2)
(1)
(2)
(3)
DAC output noise density
TA = 25°C, at mid-scale input, fOUT = 1 kHz
90
nV/√Hz
DAC output noise
TA = 25°C, at mid-scale input, 0.1 Hz to 10 Hz
2.6
µVPP
16-bit: codes 512 and 65,024; 14-bit: codes 128 and 16,256; 12-bit: codes 32 and 4,064
Specified by design or characterization
Transition time between ¼ scale and ¾ scale including settling to within ±0.024% FSR
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Electrical Characteristics (continued)
At AVDD = 2.7 V to 5.5 V and TA = –40°C to 125°C (unless otherwise noted).
PARAMETER
LOGIC INPUTS
TEST CONDITIONS
MIN
TYP
–1
±0.1
MAX
UNIT
(2)
Input pin Leakage current
Logic input LOW voltage VINL
Logic input HIGH voltage VINH
1
µA
0
0.8
V
0.7 ×
AVDD
AVDD
V
3
pF
Pin capacitance
REFERENCE
External reference current
Reference input impedance
External VREF = 2.5 V (when internal reference
is disabled), all channels active using gain = 1
15
Internal reference disabled, gain = 1
170
Internal reference disabled, gain = 2
85
µA
kΩ
REFERENCE OUTPUT
Output voltage
TA = 25°C
2.495
2.5
2.505
Initial accuracy
TA = 25°C
–5
±0.1
5
mV
4
10
ppm/°C
Output voltage temperature drift
Output voltage noise
f = 0.1 Hz to 10 Hz
12
TA = 25°C, f = 1 kHz, CL = 0 µF
Output voltage noise density (high-frequency
TA = 25°C, f = 1 MHz, CL = 0 µF
noise)
TA = 25°C, f = 1 MHz, CL = 4.7 µF
Load regulation, sourcing (4)
Load regulation, sinking
(4)
µVPP
250
30
nV/√Hz
10
TA = 25°C
20
µV/mA
TA = 25°C
185
µV/mA
Output current load capability (2)
±20
mA
50
µV/V
ppm
Line regulation
TA = 25°C
Long-term stability and drift (aging) (4)
TA = 25°C, time = 0 to 1900 hours
100
First cycle
200
Thermal hysteresis (4)
V
Additional cycles
ppm
50
POWER REQUIREMENTS (5)
AVDD = 3.6 V to 5.5 V
Normal mode, internal reference off
0.25
0.5
Normal mode, internal reference on
0.9
1.6
Power-down modes (6)
0.55
2
(7)
0.55
4
Normal mode, internal reference off
0.2
0.4
Normal mode, internal reference on
0.73
1.4
Power-down modes (6)
0.35
2
(7)
0.35
3
Normal mode, internal reference off
0.9
2.75
Normal mode, internal reference on
3.2
8.8
Power-down modes (6)
2
11
Power-down modes (7)
2
22
Normal mode, internal reference off
0.54
1.44
Normal mode, internal reference on
1.97
5
Power-down modes (6)
0.95
7.2
Power-down modes (7)
0.95
10.8
Power-down modes
IDD
AVDD = 2.7 V to 3.6 V
Power-down modes
AVDD = 3.6 V to 5.5 V
Power dissipation
AVDD = 2.7 V to 3.6 V
(4)
(5)
(6)
(7)
6
mA
µA
mA
µA
mW
µW
mW
µW
See the Application Information section of this data sheet.
Input code = mid-scale, no load, VINH = AVDD, and VINL = GND
Temperature range –40°C to 105°C
Temperature range –40°C to 125°C
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SLAS950A – MAY 2013 – REVISED JUNE 2015
7.6 Timing Requirements (1) (2)
At AVDD = 2.7 V to 5.5 V and over –40°C to 125°C (unless otherwise noted). See Figure 1.
MIN
NOM
MAX
UNIT
50
MHz
f(SCLK)
Serial clock frequency
t1
SCLK falling edge to SYNC falling edge (for successful write operation)
10
ns
t2
SCLK cycle time
20
ns
t3
SYNC rising edge to 23rd SCLK falling edge (for successful SYNC interrupt)
13
ns
t4
Minimum SYNC HIGH time
80
ns
t5
SYNC to SCLK falling edge setup time
13
ns
t6
SCLK LOW time
8
ns
t7
SCLK HIGH time
t8
SCLK falling edge to SYNC rising edge
t9
8
ns
10
ns
Data setup time
6
ns
t10
Data hold time
5
ns
t11
SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode
5
ns
t12
LDAC pulse duration, LOW time
10
ns
t13
CLR pulse duration, LOW time
80
ns
t14
CLR falling edge to start of VOUT transition
(1)
(2)
100
ns
All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VINL + VINH) / 2.
See the Serial Write Operation timing diagram (Figure 1).
t(1)
t(2)
SCLK
t(6)
t(5)
t(3)
t(7)
t(8)
t(4)
SYNC
t(10)
t(9)
DIN
DB23
DB0
t(12)
t(11)
LDAC(1)
LDAC(2)
t(13)
CLR
t(14)
VOUTx
(1)
Asynchronous LDAC update mode. For more information, see the LDAC Functionality section.
(2)
Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section.
Figure 1. Serial Write Operation
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7.7 Typical Characteristics
7.7.1 Tables of Graphs
Table 1. Typical Characteristics: Internal Reference Performance
POWER-SUPPLY
VOLTAGE
MEASUREMENT
Internal Reference Voltage vs Temperature
FIGURE NUMBER
Figure 2
Internal Reference Voltage Temperature Drift Histogram
Figure 3
Internal Reference Voltage vs Load Current
5.5 V
Internal Reference Voltage vs Time
Figure 4
Figure 5
Internal Reference Noise Density vs Frequency
Figure 6
Internal Reference Voltage vs Supply Voltage
2.7 V – 5.5 V
Figure 7
Table 2. Typical Characteristics: DAC Static Performance
POWER-SUPPLY
VOLTAGE
MEASUREMENT
FIGURE NUMBER
FULL-SCALE, GAIN, OFFSET AND ZERO-CODE ERRORS
Full-Scale Error vs Temperature
Figure 16
Gain Error vs Temperature
5.5 V
Offset Error vs Temperature
Figure 17
Figure 18
Zero-Code Error vs Temperature
Figure 19
Full-Scale Error vs Temperature
Figure 63
Gain Error vs Temperature
2.7 V
Offset Error vs Temperature
Zero-Code Error vs Temperature
Figure 64
Figure 65
Figure 66
LOAD REGULATION
DAC Output Voltage vs Load Current
5.5 V
Figure 30
2.7 V
Figure 74
DIFFERENTIAL NONLINEARITY ERROR
Differential Linearity Error vs Digital Input Code
T = –40°C
Figure 9
T = 25°C
Figure 11
T = 125°C
5.5 V
Differential Linearity Error vs Temperature
Figure 15
T = –40°C
Differential Linearity Error vs Digital Input Code
Figure 13
T = 25°C
T = 125°C
Figure 56
2.7 V
Differential Linearity Error vs Temperature
Figure 58
Figure 60
Figure 62
INTEGRAL NONLINEARITY ERROR (RELATIVE ACCURACY)
Linearity Error vs Digital Input Code
T = –40°C
Figure 8
T = 25°C
Figure 10
T = 125°C
5.5 V
Linearity Error vs Temperature
Figure 14
T = –40°C
Linearity Error vs Digital Input Code
T = 25°C
T = 125°C
Linearity Error vs Temperature
8
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Figure 12
Figure 55
2.7 V
Figure 57
Figure 59
Figure 61
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Table 2. Typical Characteristics: DAC Static Performance (continued)
MEASUREMENT
POWER-SUPPLY
VOLTAGE
FIGURE NUMBER
POWER-DOWN CURRENT
Power-Down Current vs Temperature
Power-Down Current vs Power-Supply Voltage
Power-Down Current vs Temperature
5.5 V
Figure 28
2.7 V – 5.5 V
Figure 29
2.7 V
Figure 73
POWER-SUPPLY CURRENT
Power-Supply Current vs Temperature
External VREF
Figure 20
Internal VREF
Figure 21
External VREF
Power-Supply Current vs Digital Input Code
5.5 V
Internal VREF
Power-Supply Current Histogram
Figure 24
Internal VREF
Figure 25
2.7 V – 5.5 V
Internal VREF
Power-Supply Current vs Temperature
Power-Supply Current vs Temperature
Figure 49
Figure 50
3.6 V
Figure 52
Figure 53
Internal VREF
Figure 54
External VREF
Figure 67
Internal VREF
Figure 68
2.7 V
Internal VREF
Power-Supply Current Histogram
Figure 51
External VREF
External VREF
Power-Supply Current vs Digital Input Code
Figure 27
Internal VREF
Internal VREF
Power-Supply Current Histogram
Figure 26
External VREF
External VREF
Power-Supply Current vs Digital Input Code
Figure 23
External VREF
External VREF
Power-Supply Current vs Power-Supply Voltage
Figure 22
Figure 69
Figure 70
External VREF
Figure 71
Internal VREF
Figure 72
Table 3. Typical Characteristics: DAC Dynamic Performance
POWER-SUPPLY
VOLTAGE
MEASUREMENT
FIGURE NUMBER
CHANNEL-TO-CHANNEL CROSSTALK
Channel-to-Channel Crosstalk
5-V Rising Edge
5.5 V
5-V Falling Edge
Figure 43
Figure 44
CLOCK FEEDTHROUGH
Clock Feedthrough
500 kHz, Mid-Scale
5.5 V
Figure 48
2.7 V
Figure 87
GLITCH IMPULSE
Glitch Impulse, 1-LSB Step
Glitch Impulse, 4-LSB Step
Glitch Impulse, 16-LSB Step
Rising Edge, Code 7FFFh to 8000h
Figure 37
Falling Edge, Code 8000h to 7FFFh
Figure 38
Rising Edge, Code 7FFCh to 8000h
Falling Edge, Code 8000h to 7FFCh
5.5 V
Figure 39
Figure 40
Rising Edge, Code 7FF0h to 8000h
Figure 41
Falling Edge, Code 8000h to 7FF0h
Figure 42
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Table 3. Typical Characteristics: DAC Dynamic Performance (continued)
POWER-SUPPLY
VOLTAGE
MEASUREMENT
Glitch Impulse, 1-LSB Step
Glitch Impulse, 4-LSB Step
Glitch Impulse, 16-LSB Step
FIGURE NUMBER
Rising Edge, Code 7FFFh to 8000h
Figure 79
Falling Edge, Code 8000h to 7FFFh
Figure 80
Rising Edge, Code 7FFCh to 8000h
Falling Edge, Code 8000h to 7FFCh
2.7 V
Figure 81
Figure 82
Rising Edge, Code 7FF0h to 8000h
Figure 83
Falling Edge, Code 8000h to 7FF0h
Figure 84
NOISE
DAC Output Noise Density vs
Frequency
External VREF
DAC Output Noise 0.1 Hz to 10 Hz
External VREF
Figure 45
Internal VREF
5.5 V
Figure 46
Figure 47
POWER-ON GLITCH
Reset to Zero Scale
Power-on Glitch
5.5 V
Reset to Mid-Scale
Reset to Zero Scale
2.7 V
Reset to Mid-Scale
Figure 35
Figure 36
Figure 85
Figure 86
SETTLING TIME
Full-Scale Settling Time
Half-Scale Settling Time
Full-Scale Settling Time
Half-Scale Settling Time
10
Rising Edge, Code 0h to FFFFh
Falling Edge, Code FFFFh to 0h
Rising Edge, Code 4000h to C000h
Figure 31
5.5 V
Figure 32
Figure 33
Falling Edge, Code C000h to 4000h
Figure 34
Rising Edge, Code 0h to FFFFh
Figure 75
Falling Edge, Code FFFFh to 0h
Rising Edge, Code 4000h to C000h
Falling Edge, Code C000h to 4000h
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2.7 V
Figure 76
Figure 77
Figure 78
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SLAS950A – MAY 2013 – REVISED JUNE 2015
7.7.2 Internal Reference
At TA = 25°C, AVDD = 5.5 V, gain = 2 and VREFOUT, unloaded unless otherwise noted.
30
Population (%)
25
20
15
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
5
Temperature Drift (ppm/ °C)
Figure 2. Internal Reference Voltage vs Temperature
Figure 3. Internal Reference Voltage Temperature Drift
Histogram
2.510
VREFOUT (V)
2.505
2.500
2.495
16 units shown
2.490
−20
−15
−10
−5
0
5
Load Current (mA)
10
15
20
Figure 5. Internal Reference Voltage vs Time
Figure 4. Internal Reference Voltage vs Load Current
400
2.505
No Load
4.7 µF Load
−40°C
+25°C
+125°C
2.504
2.503
300
2.502
250
VREFOUT (V)
Voltage Noise (nV/rt−Hz)
350
200
150
2.501
2.500
2.499
2.498
100
2.497
50
0
2.496
10
100
1k
10k
Frequency (Hz)
100k
1M
Figure 6. Internal Reference Noise Density vs Frequency
Copyright © 2013–2015, Texas Instruments Incorporated
2.495
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
AVDD (V)
Figure 7. Internal Reference Voltage vs Supply Voltage
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7.7.3 DAC at AVDD = 5.5 V
At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
12
1.0
9
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
6
3
0
−3
0.4
0.2
0.0
−0.2
−0.4
−6
−0.6
−9
−12
Typical channel shown
−40°C
0
Typical channel shown
−40°C
−0.8
−1.0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 8. Linearity Error vs Digital Input Code (–40°C)
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 9. Differential Linearity Error vs Digital Input Code
(–40°C)
12
1.0
9
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
6
3
0
−3
0.4
0.2
0.0
−0.2
−0.4
−6
−0.6
−9
−12
Typical channel shown
25°C
0
Typical channel shown
25°C
−0.8
−1.0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 10. Linearity Error vs Digital Input Code (25°C)
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 11. Differential Linearity Error vs Digital Input Code
(25°C)
12
1.0
9
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
6
3
0
−3
0.4
0.2
0.0
−0.2
−0.4
−6
−0.6
−9
−12
Typical channel shown
125°C
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 12. Linearity Error vs Digital Input Code (125°C)
12
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Typical channel shown
125°C
−0.8
−1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 13. Differential Linearity Error vs Digital Input Code
(125°C)
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SLAS950A – MAY 2013 – REVISED JUNE 2015
DAC at AVDD = 5.5 V (continued)
At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
12
1.0
INL Max
INL Min
9
DNL Max
DNL Min
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
6
3
0
−3
0.4
0.2
0.0
−0.2
−0.4
−6
−0.6
−9
Typical channel shown
−12
−40 −25 −10 5
20 35 50 65
Temperature (°C)
−0.8
80
95
Typical channel shown
−1.0
−40 −25 −10 5
20 35 50 65
Temperature (°C)
110 125
Figure 14. Linearity Error vs Temperature
95
110 125
Figure 15. Differential Linearity Error vs Temperature
0.20
0.15
Ch A
Ch B
0.15
Ch A
Ch B
0.10
0.10
Gain Error (%FSR)
Full−Scale Error (%FSR)
80
0.05
0.00
−0.05
0.05
0.00
−0.05
−0.10
−0.10
−0.15
−0.20
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
−0.15
−40 −25 −10
110 125
Figure 16. Full-Scale Error vs Temperature
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 17. Gain Error vs Temperature
4
4.0
Ch A
Ch B
3
1
0
−1
−2
−3
Ch A
Ch B
3.5
Zero−Code Error (mV)
2
Offset Error (mV)
5
3.0
2.5
2.0
1.5
1.0
0.5
−4
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
Figure 18. Offset Error vs Temperature
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110 125
0.0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 19. Zero-code Error vs Temperature
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DAC at AVDD = 5.5 V (continued)
0.50
1.3
0.45
1.2
Power−Supply Current (mA)
0.40
0.35
0.30
0.25
0.20
0.15
0.10
1.1
1.0
0.9
0.8
0.7
0.6
0.05
0.00
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
0.5
−40 −25 −10
110 125
0.50
1.3
0.45
1.2
0.40
0.35
0.30
0.25
0.20
0.15
0.10
80
95
110 125
1.1
1.0
0.9
0.8
0.7
Internal reference enabled, Gain = 2
0
0.5
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 23. Power-Supply Current vs Digital Input Code
30
30
25
25
20
20
Population (%)
Figure 22. Power-Supply Current vs Digital Input Code
15
10
10
0.45
0.43
0.41
0.39
0.37
0.35
0.33
0.31
0.29
0.27
0.25
0.23
0
0.21
0
0.19
5
0.17
Internal reference enabled
Gain = 2
15
5
0.15
Population (%)
20 35 50 65
Temperature (°C)
0.6
0.05
14
5
Figure 21. Power-supply Current vs Temperature
Power−Supply Current (mA)
Power−Supply Current (mA)
Figure 20. Power-supply Current vs Temperature
0.00
Internal reference enabled
DACs at midscale code, Gain = 2
DACs at midscale code
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
Power−Supply Current (mA)
At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
Power Supply Current (mA)
Power Supply Current (mA)
Figure 24. Power-Supply Current Histogram
Figure 25. Power-Supply Current Histogram
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SLAS950A – MAY 2013 – REVISED JUNE 2015
DAC at AVDD = 5.5 V (continued)
At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
0.50
1.3
VREFIN = 2.5 V
DACs at midscale code, Gain = 1
Internal reference enabled
DACs at midscale code, Gain = 1
1.2
Power−Supply Current (mA)
Power−Supply Current (mA)
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
1.1
1.0
0.9
0.8
0.7
0.6
0.05
0.00
2.7
3.1
3.5
3.9
4.3
4.7
5.1
0.5
2.7
5.5
3.1
3.5
AVDD (V)
4.3
4.7
5.1
5.5
AVDD (V)
Figure 26. Power-Supply Current vs Power-Supply Voltage
Figure 27. Power-Supply Current vs Power-Supply Voltage
4.0
0.60
Power−Down Current (µA)
3.5
Power−Down Current (µA)
3.9
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
G028
Figure 28. Power-Down Current vs Temperature
0.50
IDD (µA)
IREFIN (µA)
0.40
0.30
0.20
0.10
0.00
2.7
3.1
3.5
3.9
4.3
AVDD (V)
4.7
5.1
5.5
G029
Figure 29. Power-Down Current vs Power-Supply Voltage
7.0
Typical channel shown
Full scale
Mid scale
Zero scale
6.0
Large Signal VOUT (2 V/div)
5.0
Output Voltage (V)
LDAC Trigger (5 V/div)
4.0
3.0
2.0
Small Signal Settling
(1.22 mV/div = 0.024% FSR)
1.0
0.0
−1.0
−20
−15
−10
−5
0
5
10
15
ILOAD (mA)
Figure 30. DAC Output Voltage vs Load Current
Copyright © 2013–2015, Texas Instruments Incorporated
From Code: 0h
To Code: FFFFh
20
Time (5 μs/div)
Figure 31. Full-Scale Settling Time: Rising Edge
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DAC at AVDD = 5.5 V (continued)
At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
LDAC Trigger (5 V/div)
LDAC Trigger (5 V/div)
Large Signal VOUT (2 V/div)
Large Signal VOUT (2 V/div)
Small Signal Settling (1.22 mV/div = 0.024% FSR)
Small Signal Settling (1.22 mV/div = 0.024% FSR)
From Code: FFFFh
To Code: 0h
Time (5 μs/div)
From Code: 4000h
To Code: C000h
Time (5 μs/div)
Figure 32. Full-Scale Settling Time: Falling Edge
LDAC Trigger (5 V/div)
Figure 33. Half-Scale Settling Time: Rising Edge
AVDD (2 V/div)
Large Signal VOUT (2 V/div)
Small Signal Settling (1.22 mV/div = 0.024% FSR)
VOUTA (50 mV/div)
VOUTB (50 mV/div)
From Code: C000h
To Code: 4000h
Time (5 μs/div)
VREFIN shorted to AVDD
Time (1 ms/div)
Figure 34. Half-Scale Settling Time: Falling Edge
Figure 35. Power-On Glitch Reset to Zero Scale
LDAC Trigger (5 V/div)
AVDD (2 V/div)
Glitch Impulse » 0.1 nV-s
VOUTA (1 V/div)
VOUT (100 μV/div)
VOUTB (1 V/div)
LDAC Feedthrough
From Code: 7FFFh
To Code: 8000h
VREFIN shorted to AVDD
Time (1 ms/div)
Figure 36. Power-On Glitch Reset to Mid-Scale
16
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Time (5 μs/div)
Figure 37. Glitch Impulse Rising Edge, 1-LSB Step
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SLAS950A – MAY 2013 – REVISED JUNE 2015
DAC at AVDD = 5.5 V (continued)
At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
LDAC Trigger (5 V/div)
LDAC Trigger (5 V/div)
Glitch Impulse » 0.1 nV-s
LDAC Feedthrough
VOUT (100 μV/div)
VOUT (100 μV/div)
LDAC Feedthrough
Glitch Impulse » 0.12 nV-s
From Code: 8000h
To Code: 7FFFh
From Code: 7FFCh
To Code: 8000h
Time (5 μs/div)
Time (5 μs/div)
Figure 38. Glitch Impulse Falling Edge, 1-LSB Step
Figure 39. Glitch Impulse Rising Edge, 4-LSB Step
LDAC Trigger (5 V/div)
LDAC Trigger (5 V/div)
Glitch Impulse » 0.1 nV-s
VOUT (500 μV/div)
LDAC Feedthrough
VOUT (100 μV/div)
LDAC Feedthrough
Glitch Impulse » 0.14 nV-s
From Code: 8000h
To Code: 7FFCh
From Code: 7FF0h
To Code: 8000h
Time (5 μs/div)
Time (5 μs/div)
Figure 40. Glitch Impulse Falling Edge, 4-LSB Step
Figure 41. Glitch Impulse Rising Edge, 16-LSB Step
LDAC Trigger (5 V/div)
LDAC Trigger (5 V/div)
VOUTB (1 V/div)
LDAC Feedthrough
VOUTA (500 μV/div)
Glitch Area (Between Cursors) = 1.6 nV-s
Glitch Impulse » 0.1 nV-s
VOUT (500 μV/div)
7.3 μs
VOUTA at Midscale Code
Internal Reference Enabled
Gain = 2
From Code: 8000h
To Code: 7FF0h
Time (5 μs/div)
Figure 42. Glitch Impulse Falling Edge, 16-LSB Step
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Time (5 μs/div)
Figure 43. Channel-to-Channel Crosstalk 5-V Rising Edge
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DAC at AVDD = 5.5 V (continued)
At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
1400
Internal reference disabled
VREFIN = 5 V, Gain = 1
LDAC Trigger (5 V/div)
6.4 μs
Voltage Noise (nV/rt−Hz)
1200
Glitch Area (Between Cursors) = 2 nV-s
VOUTA (500 μV/div)
VOUTA at Midscale Code
Internal Reference Enabled
Gain = 2
Full Scale
Mid Scale
Zero Scale
1000
800
600
400
200
VOUTB (1 V/div)
0
10
100
Time (5 μs/div)
1k
Frequency (Hz)
10k
100k
Figure 45. DAC Output Noise Density vs Frequency
Figure 44. Channel-to-Channel Crosstalk 5-V Falling Edge
1400
Internal reference enabled
Gain = 2
Full Scale
Mid Scale
Zero Scale
1000
VNOISE (1 μV/div)
Voltage Noise (nV/rt−Hz)
1200
800
600
400
» 2.5 μVPP
200
0
10
100
1k
Frequency (Hz)
10k
100k
Figure 46. DAC Output Noise Density vs Frequency
DAC = Midscale
Figure 47. DAC Output Noise 0.1 Hz TO 10 Hz
SCLK (5 V/div)
VOUT (500 μV/div)
Clock Feedthrough Impulse » 0.06 nV-s
Time (500 ns/div)
Figure 48. Clock Feedthrough 500 kHz, Mid-Scale
18
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SLAS950A – MAY 2013 – REVISED JUNE 2015
7.7.4 Typical Characteristics: DAC at AVDD = 3.6 V
0.50
1.3
0.45
1.2
Power−Supply Current (mA)
0.40
0.35
0.30
0.25
0.20
0.15
0.10
1.1
1.0
0.9
0.8
0.7
0.6
0.05
0.00
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
0.5
−40 −25 −10
110 125
0.50
1.3
0.45
1.2
0.40
0.35
0.30
0.25
0.20
0.15
0.10
20 35 50 65
Temperature (°C)
80
95
110 125
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.05
Internal reference enabled, Gain = 1
0
0.4
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 52. Power-Supply Current vs Digital Input Code
30
30
25
25
20
20
Population (%)
Figure 51. Power-Supply Current vs Digital Input Code
15
10
10
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
0.18
0
0.16
0
0.14
5
0.12
Internal reference enabled
Gain = 1
15
5
0.10
Population (%)
5
Figure 50. Power-Supply Current vs Temperature
Power−Supply Current (mA)
Power−Supply Current (mA)
Figure 49. Power-Supply Current vs Temperature
0.00
Internal reference enabled
DACs at midscale code, Gain = 1
DACs at midscale code
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
Power−Supply Current (mA)
At TA = 25°C, 3.3-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
Power Supply Current (mA)
Power Supply Current (mA)
Figure 53. Power-Supply Current Histogram
Figure 54. Power-Supply Current Histogram
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7.7.5 Typical Characteristics: DAC at AVDD = 2.7 V
At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
12
1.0
9
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
6
3
0
−3
0.4
0.2
0.0
−0.2
−0.4
−6
−0.6
−9
−12
Typical channel shown
−40°C
0
Typical channel shown
−40°C
−0.8
−1.0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 55. Linearity Error vs Digital Input Code (–40°C)
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 56. Differential Linearity Error vs Digital Input Code
(–40°C)
12
1.0
9
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
6
3
0
−3
0.4
0.2
0.0
−0.2
−0.4
−6
−0.6
−9
−12
Typical channel shown
25°C
0
Typical channel shown
25°C
−0.8
−1.0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 57. Linearity Error vs Digital Input Code (25°C)
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 58. Differential Linearity Error vs Digital Input Code
(25°C)
12
1.0
9
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
6
3
0
−3
0.4
0.2
0.0
−0.2
−0.4
−6
−0.6
−9
−12
Typical channel shown
125°C
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 59. Linearity Error vs Digital Input Code (125°C)
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Typical channel shown
125°C
−0.8
−1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 60. Differential Linearity Error vs Digital Input Code
(125°C)
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Typical Characteristics: DAC at AVDD = 2.7 V (continued)
At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
12
1.0
INL Max
INL Min
9
DNL Max
DNL Min
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
6
3
0
−3
0.4
0.2
0.0
−0.2
−0.4
−6
−0.6
−9
Typical channel shown
−12
−40 −25 −10 5
20 35 50 65
Temperature (°C)
−0.8
80
95
Typical channel shown
−1.0
−40 −25 −10 5
20 35 50 65
Temperature (°C)
110 125
Figure 61. Linearity Error vs Temperature
95
110 125
Figure 62. Differential Linearity Error vs Temperature
0.20
0.15
Ch A
Ch B
0.15
Ch A
Ch B
0.10
0.10
Gain Error (%FSR)
Full−Scale Error (%FSR)
80
0.05
0.00
−0.05
0.05
0.00
−0.05
−0.10
−0.10
−0.15
−0.20
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
−0.15
−40 −25 −10
110 125
Figure 63. Full-Scale Error vs Temperature
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 64. Gain Error vs Temperature
4
4.0
Ch A
Ch B
3
1
0
−1
−2
−3
Ch A
Ch B
3.5
Zero−Code Error (mV)
2
Offset Error (mV)
5
3.0
2.5
2.0
1.5
1.0
0.5
−4
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
Figure 65. Offset Error vs Temperature
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110 125
0.0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 66. Zero-Code Error vs Temperature
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Typical Characteristics: DAC at AVDD = 2.7 V (continued)
0.40
1.3
0.35
1.2
Power−Supply Current (mA)
Power−Supply Current (mA)
At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
0.30
0.25
0.20
0.15
0.10
0.05
1.1
1.0
0.9
0.8
0.7
0.6
Internal reference enabled
DACs at midscale code, Gain = 1
DACs at midscale code
0.00
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
0.5
−40 −25 −10
110 125
0.40
1.3
0.35
1.2
0.30
0.25
0.20
0.15
0.10
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 68. Power-Supply Current vs Temperature
Power−Supply Current (mA)
Power−Supply Current (mA)
Figure 67. Power-Supply Current vs Temperature
5
0.05
1.1
1.0
0.9
0.8
0.7
0.6
0.5
Internal reference enabled, Gain = 1
22
0
0.4
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 70. Power-Supply Current vs Digital Input Code
30
30
25
25
20
20
15
10
15
10
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
0
0.18
0
0.16
5
0.14
5
0.12
Internal reference enabled
Gain = 1
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
Population (%)
Figure 69. Power-Supply Current vs Digital Input Code
0.10
Population (%)
0.00
Power Supply Current (mA)
Power Supply Current (mA)
Figure 71. Power-Supply Current Histogram
Figure 72. Power-Supply Current Histogram
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Typical Characteristics: DAC at AVDD = 2.7 V (continued)
At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
3.0
4
Full scale
Mid scale
Zero scale
3
Output Voltage (V)
Power−Down Current (µA)
Typical channel shown
2.5
2.0
1.5
1.0
2
1
0
0.5
0.0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
G073
Figure 73. Power-Down Current vs Temperature
LDAC Trigger (5 V/div)
−1
−20
−15
−10
−5
0
5
10
15
20
ILOAD (mA)
Figure 74. DAC Output Voltage vs Load Current
LDAC Trigger (5 V/div)
Large Signal VOUT (1 V/div)
Large Signal VOUT (1 V/div)
Small Signal Settling (0.61 mV/div = 0.024% FSR)
Small Signal Settling (0.61 mV/div = 0.024% FSR)
From Code: FFFFh
To Code: 0h
From Code: 0h
To Code: FFFFh
Time (5 μs/div)
Time (5 μs/div)
Figure 75. Full-Scale Settling Time: Rising Edge
LDAC Trigger (5 V/div)
Figure 76. Full-Scale Settling Time: Falling Edge
LDAC Trigger (5 V/div)
Large Signal VOUT (1 V/div)
Large Signal VOUT (1 V/div)
Small Signal Settling (0.61 mV/div = 0.024% FSR)
Small Signal Settling (0.61 mV/div = 0.024% FSR)
From Code: 4000h
To Code: C000h
Time (5 μs/div)
Figure 77. Half-Scale Settling Time: Rising Edge
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From Code: C000h
To Code: 4000h
Time (5 μs/div)
Figure 78. Half-Scale Settling Time: Falling Edge
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Typical Characteristics: DAC at AVDD = 2.7 V (continued)
At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
LDAC Trigger (5 V/div)
LDAC Trigger (5 V/div)
LDAC Feedthrough
Glitch Impulse » 0.1 nV-s
VOUT (100 μV/div)
VOUT (100 μV/div)
LDAC Feedthrough
Glitch Impulse » 0.1 nV-s
From Code: 7FFFh
To Code: 8000h
From Code: 8000h
To Code: 7FFFh
Time (5 μs/div)
Time (5 μs/div)
Figure 79. Glitch Impulse Rising Edge, 1-LSB Step
Figure 80. Glitch Impulse Falling Edge, 1-LSB Step
LDAC Trigger (5 V/div)
LDAC Trigger (5 V/div)
Glitch Impulse » 0.1 nV-s
LDAC Feedthrough
VOUT (100 μV/div)
VOUT (100 μV/div)
LDAC Feedthrough
Glitch Impulse » 0.1 nV-s
From Code: 7FFCh
To Code: 8000h
From Code: 8000h
To Code: 7FFCh
Time (5 μs/div)
Time (5 μs/div)
Figure 81. Glitch Impulse Rising Edge, 4-LSB Step
Figure 82. Glitch Impulse Falling Edge, 4-LSB Step
LDAC Trigger (5 V/div)
Glitch Impulse » 0.1 nV-s
VOUT (200 μV/div)
LDAC Trigger (5 V/div)
LDAC Feedthrough
LDAC Feedthrough
VOUT (200 μV/div)
Glitch Impulse » 0.1 nV-s
From Code: 7FF0h
To Code: 8000h
Time (5 μs/div)
Figure 83. Glitch Impulse Rising Edge, 16-LSB Step
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From Code: 8000h
To Code: 7FF0h
Time (5 μs/div)
Figure 84. Glitch Impulse Falling Edge, 16-LSB Step
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Typical Characteristics: DAC at AVDD = 2.7 V (continued)
At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
AVDD (2 V/div)
AVDD (2 V/div)
VOUTA (500 mV/div)
VOUTB (500 mV/div)
VOUTA (50 mV/div)
VOUTB (50 mV/div)
VREFIN shorted to AVDD
VREFIN shorted to AVDD
Time (1 ms/div)
Time (1 ms/div)
Figure 85. Power-On Glitch Reset to Zero Scale
Figure 86. Power-On Glitch Reset to Mid-Scale
SCLK (2 V/div)
Clock Feedthrough Impulse » 0.02 nV-s
VOUT (500 μV/div)
Time (500 ns/div)
Figure 87. Clock Feedthrough 500 kHz, Mid-Scale
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8 Detailed Description
8.1 Overview
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices are low-power, voltage-output, dual-channel, 12-,
14-, and 16-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 4-ppm/°C
internal reference, giving a full-scale output voltage range of 2.5 V or 5 V. The internal reference has an initial
accuracy of ±5 mV and can source or sink up to 20 mA at the VREFIN/VREFOUT pin.
8.2 Functional Block Diagram
GND
DIN
SCLK
SYNC
LDAC
CLR
Buffer Control
Register Control
AVDD
VREFIN/VREFOUT
2.5-V
Reference
Input Control Logic
Control Logic
DAC756x-Q1 (12-Bit)
DAC816x-Q1 (14-Bit)
DAC856x-Q1 (16-Bit)
PowerDown
Control
Logic
Data Buffer B
DAC Register B
DAC
VOUTB
Data Buffer A
DAC Register A
DAC
VOUTA
8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC)
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 architecture consists of two string DACs, each followed by
an output buffer amplifier. The devices include an internal 2.5-V reference with 4-ppm/°C temperature drift
performance. Figure 88 shows a principal block diagram of the DAC architecture.
Gain
Register
DIN
n
DAC
Register
VREFIN/
VREFOUT
150 kW
REF(+)
Resistor String
REF(-)
150 kW
VOUT
GND
Figure 88. DAC Architecture
The input coding to the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices is straight binary, so the ideal
output voltage is given by Equation 1:
æD ö
VO UT = ç IN
´ VREF ´ Gain
n ÷
è 2 ø
(1)
where:
n = resolution in bits; either 12 (DAC756x-Q1), 14 (DAC816x-Q1) or 16 (DAC856x-Q1)
DIN = decimal equivalent of the binary code that is loaded to the DAC register. DIN ranges from 0 to 2n – 1.
VREF = DAC reference voltage; either VREFOUT from the internal 2.5-V reference or VREFIN from an
aaa external reference.
Gain = 1 by default when internal reference is disabled (using external reference), and gain = 2 by default
aaa when using internal reference. Gain can also be manually set to either 1 or 2 using the gain register.
aaa See the Gain Function section for more information.
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Feature Description (continued)
8.3.1.1 Resistor String
The resistor string section is shown in Figure 89. It is simply a string of resistors, each of value R. The code
loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the
output amplifier by closing one of the switches connecting the string to the amplifier. The resistor string
architecture results in monotonicity. The RDIVIDER switch is controlled by the gain registers (see the Gain Function
section). Because the output amplifier has a gain of 2, RDIVIDER is not shorted when the DAC-n gain is set to 1
(default if internal reference is disabled), and is shorted when the DAC-n gain is set to 2 (default if internal
reference is enabled).
VREFIN/VREFOUT
RDIVIDER
VREF
2
R
R
To Output Amplifier
R
R
Figure 89. Resistor String
8.3.1.2 Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a maximum output
range of 0 V to AVDD. It is capable of driving a load of 2 kΩ in parallel with 3 nF to GND. The typical slew rate is
0.75 V/µs, with a typical full-scale settling time of 14 µs as shown in Figure 31, Figure 32, Figure 75 and
Figure 76.
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Feature Description (continued)
8.3.2 Internal Reference
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices include a 2.5-V internal reference that is disabled by
default. The internal reference is externally available at the VREFIN/VREFOUT pin. The internal reference output
voltage is 2.5 V and can sink and source up to 20 mA.
A minimum 150-nF capacitor is recommended between the reference output and GND for noise filtering.
The internal reference of the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices is a bipolar transistor-based
precision band-gap voltage reference. Figure 90 shows the basic band-gap topology. Transistors Q1 and Q2 are
biased such that the current density of Q1 is greater than that of Q2. The difference of the two base-emitter
voltages (VBE1 – VBE2) has a positive temperature coefficient and is forced across resistor R1. This voltage is
amplified and added to the base-emitter voltage of Q2, which has a negative temperature coefficient. The
resulting output voltage is virtually independent of temperature. The short-circuit current is limited by design to
approximately 100 mA.
VREFIN/VREFOUT
Reference
Enable
Q1
Q2
R1
R2
Figure 90. Band-Gap Reference Simplified Schematic
8.3.3 Power-On Reset
8.3.3.1 Power-On Reset to Zero-Scale
The DAC7562-Q1, DAC8162-Q1, and DAC8562-Q1 devices contain a power-on-reset circuit that controls the
output voltage during power up. All device registers are reset as shown in Table 4. At power up, all DAC
registers are filled with zeros and the output voltages of all DAC channels are set to zero volts. Each DAC
channel remains that way until a valid load command is written to it. The power-on reset is useful in applications
where it is important to know the state of the output of each DAC while the device is in the process of powering
up. No device pin should be brought high before applying power to the device. The internal reference is disabled
by default and remains that way until a valid reference-change command is executed.
8.3.3.2 Power-On Reset to Mid-Scale
The DAC7563-Q1, DAC8163-Q1, and DAC8563-Q1 devices contain a power-on reset circuit that controls the
output voltage during power up. At power up, all DAC registers are reset to mid-scale code and the output
voltages of all DAC channels are set to VREFIN / 2 V. Each DAC channel remains that way until a valid load
command is written to it. The power-on reset is useful in applications where it is important to know the state of
the output of each DAC while the device is in the process of powering up. No device pin should be brought high
before applying power to the device. The internal reference is powered off or down by default and remains that
way until a valid reference-change command is executed. If using an external reference, it is acceptable to power
on the VREFIN pin either at the same time as or after applying AVDD.
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Table 4. DACxx62-Q1 and DACxx63-Q1 Power-On Reset Values
REGISTER
DEFAULT SETTING
DAC and input registers
DACxx62-Q1
Zero-scale
DACxx63-Q1
Mid-scale
LDAC registers
LDAC pin enabled for both channels
Power-down registers
DACs powered up
Internal reference register
Internal reference disabled
Gain registers
Gain = 1 for both channels
8.3.3.3 Power-On Reset (POR) Levels
When the device powers up, a POR circuit sets the device in default mode as shown in Table 4. The POR circuit
requires specific AVDD levels, as indicated in Figure 91, to ensure discharging of internal capacitors and to reset
the device on power up. In order to ensure a power-on reset, AVDD must be below 0.7 V for at least 1 ms. When
AVDD drops below 2.2 V but remains above 0.7 V (shown as the undefined region), the device may or may not
reset under all specified temperature and power-supply conditions. In this case, TI recommends a power-on
reset. When AVDD remains above 2.2 V, a power-on reset does not occur.
AVDD (V)
5.50
No Power-On Reset
Specified Supply
Voltage Range
2.70
2.20
Undefined
0.70
Power-On Reset
0.00
Figure 91. Relevant Voltage Levels for POR Circuit
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8.4 Device Functional Modes
8.4.1 Power-Down Modes
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices have two separate sets of power-down commands.
One set is for the DAC channels and the other set is for the internal reference. The internal reference is forced to
a powered-down state while both DAC channels are powered down, and is only enabled if any DAC channel is
also in the normal mode of operation. For more information on the internal reference control, see the Internal
Reference Enable Register section.
8.4.1.1 DAC Power-Down Commands
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 DACs use four modes of operation. These modes are
accessed by setting the serial interface command bits to 100. Once the command bits are set correctly, the four
different power-down modes are software programmable by setting bits DB5 and DB4 in the shift register.
Table 5 and Table 6 show the different power-down options. For more information on how to set the DAC
operating mode see Table 17.
Table 5. DAC-n Operating Modes
DB5
DB4
0
0
Selected DACs power up (normal mode, default)
DAC MODES OF OPERATION
0
1
Selected DACs power down, output 1 kΩ to GND
1
0
Selected DACs power down, output 100 kΩ to GND
1
1
Selected DACs power down, output Hi-Z to GND
Table 6. DAC-n Selection for Operating Modes
DAC-B (DB1), DAC-A (DB0)
OPERATING MODE
0
DAC-n does not change operating mode
1
DAC-n operating mode set to value on PD1 and PD0
It is possible to write to the DAC register or buffer of the DAC channel that is powered down. When the DAC
channel is then powered up, it powers up to this new value.
The advantage of the available power-down modes is that the output impedance of the device is known while it is
in power-down mode. As described in Table 5, there are three different power-down options. VOUT can be
connected internally to GND through a 1-kΩ resistor, a 100-kΩ resistor, or open-circuited (Hi-Z). The DAC
power-down circuitry is shown in Figure 92.
Resistor
String
DAC
Amplifier
Power-Down
Circuitry
VOUTX
Resistor
Network
Figure 92. Output Stage
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8.4.2 Gain Function
The gain register controls the GAIN setting in the DAC transfer function:
æD ö
VO UT = ç IN
´ VREF ´ Gain
n ÷
è 2 ø
(2)
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices have a gain register for each channel. The gain for
each channel, in Equation 2, is either 1 or 2. This gain is automatically set to 2 when using the internal reference,
and is automatically set to 1 when the internal reference is disabled (default). However, each channel can have
either gain by setting the registers appropriately. The gain registers are accessible by setting the serial interface
command bits to 000, address bits to 010, and using DB1 for DAC-B and DB0 for DAC-A. See Table 7 and
Table 17 for the full command structure. The gain registers are automatically reset to provide either gain of 1 or 2
when the internal reference is powered off or on, respectively. After the reference is powered off or on, the gain
register is again accessible to change the gain.
Table 7. DAC-n Selection for Gain Register Command
DB1, DB0
VALUE
DB0
0
DAC-A uses gain = 2 (default with internal reference)
1
DAC-A uses gain = 1 (default with external reference)
0
DAC-B uses gain = 2 (default with internal reference)
1
DAC-B uses gain = 1 (default with external reference)
DB1
GAIN
8.4.3 Software Reset Function
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices contain a software reset feature. The software reset
function is accessed by setting the serial interface command bits to 101. The software reset command contains
two reset modes which are software-programmable by setting bit DB0 in the shift register. Table 8 and Table 17
show the available software reset commands.
Table 8. Software Reset
DB0
REGISTERS RESET TO DEFAULT VALUES
0
DAC registers
Input registers
1
DAC registers
Input registers
LDAC registers
Power-down registers
Internal reference register
Gain registers
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8.4.4 Internal Reference Enable Register
The internal reference in the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices is disabled by default for
debugging, evaluation purposes, or when using an external reference. The internal reference can be powered up
and powered down by setting the serial interface command bits to 111 and configuring DB0 (see Table 9). The
internal reference is forced to a powered down state while both DAC channels are powered down, and can only
be enabled if any DAC channel is in normal mode of operation. During the time that the internal reference is
disabled, the DAC functions normally using an external reference. At this point, the internal reference is
disconnected from the VREFIN/VREFOUT pin (Hi-Z output).
Table 9. Internal Reference
DB0
INTERNAL REFERENCE CONFIGURATION
0
Disable internal reference and reset DACs to gain = 1
1
Enable internal reference and reset DACs to gain = 2
8.4.4.1 Enabling Internal Reference
To enable the internal reference, refer to the command structure in Table 17. When performing a power cycle to
reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference
is powered down until a valid write sequence powers up the internal reference. However, the internal reference is
forced to a disabled state while both DAC channels are powered down, and remains disabled until either DAC
channel is returned to the normal mode of operation. See DAC Power-Down Commands for more information on
DAC channel modes of operation.
8.4.4.2 Disabling Internal Reference
To disable the internal reference, refer to the command structure in Table 17. When performing a power cycle to
reset the device, the internal reference is disabled (default mode).
8.4.5 CLR Functionality
The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 10.
When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output
voltages accordingly. The device exits clear mode on the 24th falling edge of the next write to the device. If the
CLR pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated
and changes the input and DAC registers immediately according to Table 10.
Table 10. Clear Mode Reset Values
32
DEVICE
DAC OUTPUT ENTERING CLEAR MODE
DAC8562-Q1, DAC8162-Q1, DAC7562-Q1
Zero-scale
DAC8563-Q1, DAC8163-Q1, DAC7563-Q1
Mid-scale
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8.4.6 LDAC Functionality
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices offer both a software and hardware simultaneous
update and control function. The DAC double-buffered architecture has been designed so that new data can be
entered for each DAC without disturbing the analog outputs.
DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 data updates can be performed either in synchronous or in
asynchronous mode.
In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC
updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values
and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. Data buffers of all
channels must be loaded with desired data before an LDAC falling edge. After a high-to-low LDAC transition, all
DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a
data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is triggered.
LDAC must be returned high before the next serial command is initiated.
In synchronous mode, data are updated with the falling edge of the 24th SCLK cycle, which follows a falling edge
of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND
permanently or asserted and held low before sending commands to the device.
Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The
LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be
updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 2-bit word
(DB1 and DB0) using command bits C2, C1, and C0 (see Table 17). The default value for each bit, and therefore
for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is
internally tied low for that particular DAC channel) and this DAC channel updates synchronously after the falling
edge of the 24th SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the
LDAC pin.
The combination of software and hardware simultaneous update functions is particularly useful in applications
when updating a DAC channel, while keeping the other channel unaffected; see Table 11 and Table 17 for more
information.
Table 11. DAC-n Selection for LDAC Register Command
DB1, DB0
VALUE
DB0
0
DAC-A uses LDAC pin
1
DAC-A operates in synchronous mode
0
DAC-B uses LDAC pin
1
DAC-B operates in synchronous mode
DB1
LDAC PIN FUNCTIONALITY
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8.5 Programming
The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices have a three-wire serial interface (SYNC, SCLK,
and DIN; see the table) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs.
See the Serial Write Operation timing diagram (Figure 1) for an example of a typical write sequence.
The DAC756x-Q1, DAC816x-Q1, or DAC856x-Q1 input shift register is 24 bits wide, consisting of two don’t care
bits (DB23 to DB22), three command bits (DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits
(DB15 to DB0). All 24 bits of data are loaded into the DAC under the control of the serial clock input, SCLK.
DB23 (MSB) is the first bit that is loaded into the DAC shift register. DB23 is followed by the rest of the 24-bit
word pattern, left-aligned. This configuration means that the first 24 bits of data are latched into the shift register,
and any further clocking of data is ignored.
The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 24-bit shift
register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the
DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices compatible with high-speed DSPs. On the 24th falling
edge of the serial clock, the last data bit is clocked into the shift register and the shift register locks. Further
clocking does not change the shift register data.
After receiving the 24th falling clock edge, the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices decode the
three command bits, three address bits and 16 data bits to perform the required function, without waiting for a
SYNC rising edge. After the 24th falling edge of SCLK is received, the SYNC line may be kept low or brought
high. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must
be met in order to begin the next cycle properly; see the Serial Write Operation timing diagram (Figure 1).
A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface; no data transfer occurs.
A new write sequence starts at the next falling edge of SYNC. To assure the lowest power consumption of the
device, care should be taken that the levels are as close to each rail as possible.
8.5.1 SYNC Interrupt
In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed
DAC register updates on the 24th falling edge. However, if SYNC is brought high before the 23rd falling edge, it
acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither
an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as
shown in Figure 93).
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB23
DB0
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the Falling Edge
DB0
Valid Write Sequence:
Output/Mode Updates on the Falling Edge
Figure 93. SYNC Interrupt Facility
34
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Programming (continued)
8.5.2 DAC Register Configuration
When the DAC registers are being written to, the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices receive
all 24 bits of data, ignore DB23 and DB22, and decode the next three bits (DB21 to DB19) in order to determine
the DAC operating or control mode (see Table 12). Bits DB18 to DB16 are used to address the DAC channels
(see Table 13).
Table 12. Commands for the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1
Devices
C2
(DB21)
C1
(DB20)
C0
(DB19)
0
0
0
Write to input register n (Table 13)
0
0
1
Software LDAC, update DAC register n (Table 13)
0
1
0
Write to input register n (Table 13) and update all DAC registers
0
1
1
Write to input register n and update DAC register n (Table 13)
1
0
0
Set DAC power-up or -down mode
1
0
1
Software reset
1
1
0
Set LDAC registers
1
1
1
Enable or disable the internal reference
COMMAND
Table 13. Address Select for the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1
Devices
A2
(DB18)
A1
(DB17)
A0
(DB16)
0
0
0
DAC-A
0
0
1
DAC-B
0
1
0
Gain (only use with command 000)
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
DAC-A and DAC-B
CHANNEL (n)
When writing to the DAC input registers the next 16, 14, or 12 bits of data that follow are decoded by the DAC to
determine the equivalent analog output (see Table 14 through Table 16). The data format is straight binary, with
all 0s corresponding to 0-V output and all 1s corresponding to full-scale output. For all documentation purposes,
the data format and representation used here is a true 16-bit pattern (that is, FFFFh data word for full scale) that
the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices require.
Table 14. DAC856x-Q1 Data Input Register Format
X (1) X
DB23
(1)
COMMAND
C2 C1 C0
ADDRESS
A2 A1 A0
D15 D14 D13 D12 D11 D10
D9
DATA
D8 D7
D6
D5
D4
D3
D2
D1
D0
DB0
D3
D2
D1
D0
X
X
DB0
X' denotes don't care bits.
Table 15. DAC816x-Q1 Data Input Register Format
X
X
DB23
COMMAND
C2 C1 C0
ADDRESS
A2 A1 A0
D13 D12 D11 D10
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D9
D8
DATA
D7 D6
D5
D4
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Table 16. DAC756x-Q1 Data Input Register Format
COMMAND
C2 C1 C0
X
X
DB23
ADDRESS
A2 A1 A0
D11 D10
D9
D8
DATA
D6 D5
D7
D4
D3
D2
D1
D0
X
X
X
X
DB0
In additon to DAC input register updates, the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices support a
number of functional mode commands (such as write to LDAC register, power down DACs and so on). The
complete set of functional mode commands is shown in Table 17.
Table 17. Command Matrix for the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 Devices
COMMAND
ADDRESS
DB23DB22
C2
C1
C0
X (1)
0
0
0
X
X
X
X
X
X
X
X
X
X
X
(1)
36
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
0
DATA
DB15DB6
A0
0
0
0
16-, 14-, or 12-bit DAC data
Write to DAC-A input register
0
0
1
16-, 14-, or 12-bit DAC data
Write to DAC-B input register
1
1
1
16-, 14-, or 12-bit DAC data
Write to DAC-A and DAC-B input registers
0
0
0
16-, 14-, or 12-bit DAC data
Write to DAC-A input register and update all DACs
0
0
1
16-, 14-, or 12-bit DAC data
Write to DAC-B input register and update all DACs
1
1
1
16-, 14-, or 12-bit DAC data
Write to DAC-A and DAC-B input register and update all DACs
0
0
0
16-, 14-, or 12-bit DAC data
Write to DAC-A input register and update DAC-A
0
0
1
16-, 14-, or 12-bit DAC data
Write to DAC-B input register and update DAC-B
1
1
1
16-, 14-, or 12-bit DAC data
Write to DAC-A and DAC-B input register and update all DACs
0
0
0
X
Update DAC-A
0
0
1
X
Update DAC-B
1
1
1
X
0
0
0
0
1
0
1
1
X
X
X
X
X
X
X
0
DB4
DESCRIPTION
A1
0
DB5
DB3DB2
A2
DB1
DB0
Update all DACs
0
0
Gain: DAC-B gain = 2, DAC-A gain = 2 (default with internal VREF)
0
1
Gain: DAC-B gain = 2, DAC-A gain = 1
1
0
Gain: DAC-B gain = 1, DAC-A gain = 2
1
1
Gain: DAC-B gain = 1, DAC-A gain = 1 (power-on default)
0
1
Power up DAC-A
1
0
Power up DAC-B
1
1
Power up DAC-A and DAC-B
0
1
Power down DAC-A; 1 kΩ to GND
1
0
Power down DAC-B; 1 kΩ to GND
1
1
Power down DAC-A and DAC-B; 1 kΩ to GND
0
1
Power down DAC-A; 100 kΩ to GND
1
0
Power down DAC-B; 100 kΩ to GND
1
1
Power down DAC-A and DAC-B; 100 kΩ to GND
0
1
Power down DAC-A; Hi-Z
1
0
Power down DAC-B; Hi-Z
1
1
Power down DAC-A and DAC-B; Hi-Z
X
0
Reset DAC-A and DAC-B input register and update all DACs
X
1
Reset all registers and update all DACs (Power-on-reset update)
0
0
LDAC pin active for DAC-B and DAC-A
0
1
LDAC pin active for DAC-B; inactive for DAC-A
1
0
LDAC pin inactive for DAC-B; active for DAC-A
1
1
LDAC pin inactive for DAC-B and DAC-A
X
0
Disable internal reference and reset DACs to gain = 1
X
1
Enable internal reference and reset DACs to gain = 2
X
X
X
X
X
0
0
0
1
1
0
1
1
X
X
X
X
X
X
X
X denotes don't care bits.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 DAC Internal Reference
The internal reference of the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices does not require an
external load capacitor for stability because it is stable without any capacitive load. However, for improved noise
performance, an external load capacitor of 150 nF or larger connected to the VREFIN/VREFOUT output is
recommended. Figure 94 shows the typical connections required for operation of the DAC756x-Q1, DAC816xQ1, and DAC856x-Q1 internal reference. A supply bypass capacitor at the AVDD input is also recommended.
DGS
150 nF
1
VOUTA
VREFIN/VREFOUT
10
2
VOUTB
AVDD
9
3
GND
DIN
8
4
LDAC
SCLK
7
5
CLR
SYNC
6
AVDD
1 mF
Figure 94. Typical Connection for Operating the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 Internal
Reference
9.1.1.1 Supply Voltage
The internal reference features an extremely low dropout voltage. It can be operated with a supply of only 5 mV
above the reference output voltage in an unloaded condition. For loaded conditions, see the Load Regulation
section. The stability of the internal reference with variations in supply voltage (line regulation, dc PSRR) is also
exceptional. Within the specified supply voltage range of 2.7 V to 5.5 V, the variation at VREFIN/VREFOUT is
typically 50 μV/V; see Figure 7.
9.1.1.2 Temperature Drift
The internal reference is designed to exhibit minimal drift error, defined as the change in reference output voltage
over varying temperature. The drift is calculated using the box method described by Equation 3:
æ VREF _ MAX - VREF _ MIN ö
6
Drift Error = çç
÷÷ ´ 10 (ppm / °C )
´
V
T
REF
RANGE
è
ø
(3)
where:
VREF_MAX = maximum reference voltage observed within temperature range TRANGE.
VREF_MIN = minimum reference voltage observed within temperature range TRANGE.
VREF = 2.5 V, target value for reference output voltage.
TRANGE = the characterized range from –40°C to 125°C (165°C range)
The internal reference features an exceptional typical drift coefficient of 4 ppm/°C from –40°C to 125°C.
Characterizing a large number of units, a maximum drift coefficient of 10 ppm/°C is observed. Temperature drift
results are summarized in Figure 3.
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Application Information (continued)
9.1.1.3 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise and noise spectral density performance are listed in the Electrical
Characteristics. Additional filtering can be used to improve output noise levels, although care should be taken to
ensure the output impedance does not degrade the ac performance. The output noise spectrum at the
VREFIN/VREFOUT pin, both unloaded and with an external 4.7-µF load capacitor, is shown in Figure 6. Internal
reference noise impacts the DAC output noise when the internal reference is used.
9.1.1.4 Load Regulation
Load regulation is defined as the change in reference output voltage as a result of changes in load current. The
load regulation of the internal reference is measured using force and sense contacts as shown in Figure 95. The
force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of
the load regulation contributed solely by the internal reference. Measurement results are shown in Figure 4.
Force and sense lines should be used for applications that require improved load regulation.
Output Pin
Contact and
Trace Resistance
VOUT
Force Line
IL
Sense Line
Meter
Load
Figure 95. Accurate Load Regulation of the DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 Internal
Reference
9.1.1.4.1 Long-Term Stability
Long-term stability or aging refers to the change of the output voltage of a reference over a period of months or
years. This effect lessens as time progresses. The typical drift value for the internal reference is listed in the
Electrical Characteristics and measurement results are shown in Figure 5. This parameter is characterized by
powering up multiple devices and measuring them at regular intervals.
9.1.1.5 Thermal Hysteresis
Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at 25°C,
cycling the device through the operating temperature range, and returning to 25°C. Hysteresis is expressed by
Equation 4:
é VREF_PRE - VREF_POST ù
6
VHYST = ê
ú ´ 10 (ppm/°C)
V
REF_NOM
ëê
ûú
(4)
where:
VHYST = thermal hysteresis.
VREF_PRE = output voltage measured at 25°C pre-temperature cycling.
VREF_POST = output voltage measured after the device cycles through the temperature range of –40°C to
aaa 125°C, and returns to 25°C.
VREF_NOM = 2.5 V, target value for reference output voltage.
9.1.2 DAC Noise Performance
Output noise spectral density at the VOUT-n pin versus frequency is depicted in Figure 45 and Figure 46 for fullscale, mid-scale, and zero-scale input codes. The typical noise density for mid-scale code is 90 nV/√Hz at 1 kHz.
High-frequency noise can be improved by filtering the reference noise. Integrated output noise between 0.1 Hz
and 10 Hz is close to 2.5 µVPP (mid-scale), as shown in Figure 47.
38
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9.2 Typical Applications
9.2.1 Combined Voltage and Current Analog Output Module Using the XTR300
The design features two independent outputs that can source and sink voltage and current over the standard
industrial output ranges. The possible outputs of the design include: –24 mA to 24 mA, 4 mA–20 mA, 0 mA to 24
mA, 0 V to 5 V, 0 V to 10 V, –5 V to5 V, and –10 V to 10 V.
VREF R
SET
CCOMP
5.5 V
15 V
0.1 µF
–15 V
0.1 µF
0.1 µF
4.7 µF
RIMON
AVDD
LDAC
SCLK
VDAC
DAC8563-Q1
DIN
XTR300
IMON
V+
V–
Current
Copy
ICOPY
RIN
IDRV DRV
VIN
VOUTA
OPA
SET
SYNC
VOUTB
GND
+
CH2
VREFIN/
VREFOUT
VREF
RIA
IAOUT
IIA
IA
IAIN+
RG1
RG2
V or I OUTA
0 V to 5 V, 0 V to 10 V, –5 to 5 V,
–10 V to 10 V, –24 mA to 24 mA,
0 mA to 24 mA, 4mA to 20 mA
RG
GND
DGND
IAIN–
0.022 µF
Figure 96. DAC8563-Q1 and XTR300 Discrete Analog Output Module
9.2.1.1 Design Requirements
The design uses a DAC and a current-or-voltage output driver to create a discrete analog output design that can
output either voltage or current from the same pin while focusing on high-accuracy specifications. The choice of
the DAC8563-Q1 device takes advantage of its 16-bit resolution as well as its low typical offset error of 1 mV and
gain error of 0.01% FSR. The choice of the XTR300 device is based on its strong dc performance, having a
typical error of 400 µV and 0.04% FSR gain error. The XTR300 device allows a variety of both current and
voltage outputs on the same pin while providing load monitoring and error status pins.
The power-on reset-to-midscale feature of the DAC8563-Q1 makes the bipolar output of the XTR300 power up at
0 V or 0 A. If using a unipolar output, the recommended device to achieve a system power-on output of 0 V, 0 A
or 4 mA is the DAC8562-Q1 device.
A recommendation for minimizing the introduction of errors into the system is to use ±0.01% tolerance RG and
RSET resistors. The bypass capacitors on AVDD, VREF, V+ and V– should have values between 100 nF and
10 µF. Smaller capacitors filter fast low-energy transients, whereas the large capacitors filter the slow highenergy transients. If there is an expectation of both types of signals in the system, the recommendation is to use
a pair of small and large values as shown on the AVDD pin of the DAC8563-Q1 device in Figure 96.
9.2.1.2 Detailed Design Procedure
When configured for voltage mode, the output of the instrumentation amplifier (IA), internal to the XTR300
device, is routed to the SET pin. The SET output provides feedback for the IA based on the IA input voltage. The
feedback from the IA provides high-impedance remote sensing of the voltage at the output load. Using the output
voltage can overcome errors from PCB traces and protection component impedances. The DAC provides a
unipolar input voltage to the VIN pin of the XTR300 device. The XTR300 device offsets the VDAC range by a
negative VREF and amplifies the difference by a value set by the RG and RSET resistors, as shown in Equation 5.
Copyright © 2013–2015, Texas Instruments Incorporated
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DAC8562-Q1, DAC8563-Q1
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www.ti.com
Typical Applications (continued)
VOUT =
æ VDAC - VREF
´ç
2 çè
R SET
RG
ö
÷
÷
ø
(5)
When configured for current mode, the XTR300 routes the internal output of its current copy circuitry to the SET
pin. This provides feedback for the internal OPA driver based on 1 / 10th of the output current, resulting in a
voltage-to-current transfer function. Generating bipolar current outputs from the single-ended DAC output
voltage, VDAC, requires the application of an offset to the XTR300 SET pin. Connect the RSET resistor from the
SET pin to VREF to apply the offset and obtain the transfer function shown in Equation 6.
æ VDAC - VREF ö
÷
I OUT = 10 ´ ç
ç
÷
R SET
è
ø
(6)
The desired output ranges for VDAC and VREF voltages determine the RSET and RG resistor values, calculated
using Equation 7 and Equation 8. The system design requires a VDAC voltage range of 0.04 V to 4.96 V in order
to operate the DAC8563-Q1 in the specified linear output range from codes 512 to 65 024.
æ V DAC - VREF ö
æ 4.96 V - 2.5 V ö
÷ = 10 ´ ç
RSET = 10 ´ ç
÷ = 1025 Ω
ç
÷
I OUT
0.024 A
è
ø
è
ø
(7)
2 ´ VOUT_MAX ´ R SET 2 ´ 10 V ´ 1020 Ω
RG =
=
= 8292 Ω
VDAC - VREF
4.96 V - 2.5 V
(8)
IMON and IAOUT accomplish load monitoring. The sizing of RIMON and RIA determine the monitoring output voltage
across the resistors. Size the resistors according to Equation 9 and Equation 10 and the expected output load
current IDRV.
10 ´ VIMON
R IMON =
IDRV
(9)
R IA =
10 ´ VIA
IIA
(10)
For more detailed information about the design procedure of this circuit and how to isolate it, see Two-Channel
Source/Sink Combined Voltage & Current Output, Isolated, EMC/EMI Tested Reference Design (TIDU434).
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DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
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SLAS950A – MAY 2013 – REVISED JUNE 2015
Typical Applications (continued)
9.2.1.3 Application Curves
Figure 97 shows the transfer function for the bipolar ±10 V voltage range. This design also supports output
voltage ranges of 0–5 V, 0–10 V and ±5 V. Figure 98 shows the transfer function for the unipolar 0–24 mA
current range. This design also supports output current ranges of ±24 mA and 4 mA–20 mA.
10
24
8
20
16
Output Current (mA )
Output Voltage (V )
6
4
2
0
-2
-4
-6
12
8
4
0
-4
-8
-12
-16
-8
-20
-24
-10
0
10k
20k
30k
40k
Input Code
50k
60k65535
Figure 97. Output Voltage vs Input Code
Copyright © 2013–2015, Texas Instruments Incorporated
D001
0
10k
20k
30k
40k
Input Code
50k
60k65535
D002
Figure 98. Output Current vs Input Code
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DAC7562-Q1, DAC7563-Q1
DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
SLAS950A – MAY 2013 – REVISED JUNE 2015
www.ti.com
Typical Applications (continued)
9.2.2 Up to ±15-V Bipolar Output Using the DAC8562-Q1
The DAC8562-Q1 is designed to be operate from a single power supply providing a maximum output range of
AVDD volts. However, the DAC can be placed in the configuration shown in Figure 99 in order to be designed into
bipolar systems. Depending on the ratio of the resistor values, the output of the circuit can range anywhere from
±5 V to ±15 V. The design example below shows that the DAC is configured to have its internal reference
enabled and the DAC8562-Q1 internal gain set to 2, however, an external 2.5-V reference could also be used
(with DAC8562-Q1 internal gain set to 2).
R
G´R
5.5 V
VREFOUT
18 V
R
+
DAC8562-Q1
VOUT
–
OPA140
G´R
–18 V
Figure 99. Bipolar Output Range Circuit Using DAC8562-Q1
The transfer function shown in Equation 5 can be used to calculate the output voltage as a function of the DAC
code, reference voltage and resistor ratio:
DIN
æ
ö
- 1÷
VOUT = G × VREFOUT ç 2 ×
65,536 ø
è
(11)
where:
DIN = decimal equivalent of the binary code that is loaded to the DAC register, ranging from 0 to 65,535 for
DAC8562-Q1 (16 bit).
VREFOUT = reference output voltage with the internal reference enabled from the DAC VREFIN/VREFOUT pin
G = ratio of the resistors
An example configuration to generate a ±10-V output range is shown below in Equation 6 with G = 4 and
VREFOUT = 2.5 V:
DIN
VOUT = 20 ×
- 10 V
65,536
(12)
In this example, the range is set to ±10 V by using a resistor ratio of four, VREFOUT of 2.5 V, and DAC8562-Q1
internal gain of 2. The resistor sizes must be selected keeping in mind the current sink or source capability of the
DAC8562-Q1 internal reference. Using larger resistor values, for example, R = 10 kΩ or larger, is recommended.
The op amp is selectable depending on the requirements of the system.
The DAC8562EVM and DAC7562EVM boards have the option to evaluate the bipolar output application by
installing the components on the pre-placed footprints. For more information see either the DAC8562EVM or
DAC7562EVM product folder.
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DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
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SLAS950A – MAY 2013 – REVISED JUNE 2015
9.3 System Examples
9.3.1 MSP430 Microprocessor Interfacing
Figure 100 shows a serial interface between the DAC756x-Q1, DAC816x-Q1, or DAC856x-Q1 device and a
typical MSP430 USI port such as the one found on the MSP430F2013. The port is configured in SPI master
mode by setting bits 3, 5, 6, and 7 in USICTL0. The USI counter interrupt is set in USICTL1 to provide an
efficient means of SPI communication with minimal software overhead. The serial clock polarity, source, and
speed are controlled by settings in the USI clock control register (USICKCTL). The SYNC signal is derived from
a bit-programmable pin on port 1; in this case, port line P1.4 is used. When data are to be transmitted to the
DAC756x-Q1, DAC816x-Q1, or DAC856x-Q1 device, P1.4 is taken low. The USI transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P1.4 is left low after the
first eight bits are transmitted; then, a second write cycle is initiated to transmit the second byte of data. P1.4 is
taken high following the completion of the third write cycle.
MSP430F2013
DAC
P1.4/GPIO
SYNC
P1.5/SCLK
SCLK
P1.6/SDO
DIN
NOTE: Additional pins omitted for clarity.
Figure 100. DAC756x-Q1, DAC816x-Q1, or DAC856x-Q1 Device to MSP430 Interface
9.3.2 TMS320 McBSP Microprocessor Interfacing
Figure 101 shows an interface between the DAC756x-Q1, DAC816x-Q1, or DAC856x-Q1 device and any
TMS320 series DSP from Texas Instruments with a multi-channel buffered serial port (McBSP). Serial data are
shifted out on the rising edge of the serial clock and are clocked into the DAC756x-Q1, DAC816x-Q1, or
DAC856x-Q1 device on the falling edge of the SCLK signal.
TMS320F28062
DAC
MFSxA
SYNC
MCLKxA
SCLK
MDxA
DIN
NOTE: Additional pins omitted for clarity.
Figure 101. DAC756x-Q1, DAC816x-Q1, or DAC856x-Q1 Device to TMS320 McBSP Interface
9.3.3 OMAP-L1x Processor Interfacing
Figure 102 shows a serial interface between the DAC756x-Q1, DAC816x-Q1, or DAC856x-Q1 device and the
OMAP-L138 processor. The transmit clock CLKx0 of the L138 drives SCLK of the DAC756x-Q1, DAC816x-Q1,
or DAC856x-Q1 device, and the data transmit (Dx0) output drives the serial data line of the DAC. The SYNC
signal is derived from the frame sync transmit (FSx0) line, similar to the TMS320 interface.
DAC
OMAP-L138
FSx0
SYNC
CLKx0
SCLK
Dx0
DIN
NOTE: Additional pins omitted for clarity.
Figure 102. DAC756x-Q1, DAC816x-Q1, or DAC856x-Q1 Device to OMAP-L1x Processor
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DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
SLAS950A – MAY 2013 – REVISED JUNE 2015
www.ti.com
10 Power Supply Recommendations
These devices can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to
AVDD should be well-regulated and low-noise. In order to further minimize noise from the power supplies, a
strong recommendation is to include a pair of 100-pF and 1-nF capacitors and a 0.1-μF to 1-μF bypass
capacitor. The current consumption of the AVDD pin, the short-circuit current limit, and the load current for these
devices are listed in the Electrical Characteristics table. Choose the power supplies for these devices to meet the
aforementioned current requirements.
11 Layout
11.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies. The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 devices offer single-supply operation, and are often
used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The
more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital
noise from appearing at the output. As a result of the single ground pin of the DAC756x-Q1, DAC816x-Q1, and
DAC856x-Q1 devices, all return currents (including digital and analog return currents for the DAC) must flow
through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be
separate from the ground connection for the digital components until they were connected at the power-entry
point of the system. The power applied to AVDD should be well-regulated and low noise. Switching power
supplies and dc-dc converters often have high-frequency glitches or spikes riding on the output voltage. In
addition, digital components can create similar high-frequency spikes as their internal logic switches states. This
noise can easily couple into the DAC output voltage through various paths between the power connections and
analog output. As with the GND connection, AVDD should be connected to a power-supply plane or trace that is
separate from the connection for digital logic until they are connected at the power-entry point. In addition, a pair
of 100-pF to 1-nF capacitors and a 0.1-µF to 1-µF bypass capacitor are strongly recommended. In some
situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a pi filter made
up of inductors and capacitors – all designed essentially to provide low-pass filtering for the supply and remove
the high-frequency noise.
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DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
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SLAS950A – MAY 2013 – REVISED JUNE 2015
11.2 Layout Example
0.1 µF
Bypass Capacitors
100 pF
AVDD
DIN
Digital Lines
VREFIN/VREFOUT
SCLK
SYNC
GND
VOUTA
VOUTB
Digital Lines
Analog Lines
LDAC
CLK
Figure 103. DACxx6x-Q1 Layout Example
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DAC7562-Q1, DAC7563-Q1
DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
SLAS950A – MAY 2013 – REVISED JUNE 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• DAC7562EVM, DAC8562EVM User's Guide (SBAU183) or go to either of the following tool folders:
– DAC8562EVM
– DAC7562EVM
• MSP430F2013, MIXED SIGNAL MICROCONTROLLER (SLAS491)
• OMAP-L138 C6000™ DSP+ ARM® Processor (SPRS586)
• TMS320F2806x Piccolo™ Microcontrollers (SPRS698)
• XTR111, Precision Voltage-to-Current Converter/Transmitter (SBOS375)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 18. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC8562-Q1
Click here
Click here
Click here
Click here
Click here
DAC8563-Q1
Click here
Click here
Click here
Click here
Click here
DAC8162-Q1
Click here
Click here
Click here
Click here
Click here
DAC8163-Q1
Click here
Click here
Click here
Click here
Click here
DAC7562-Q1
Click here
Click here
Click here
Click here
Click here
DAC7563-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola, Inc.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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DAC8162-Q1, DAC8163-Q1
DAC8562-Q1, DAC8563-Q1
www.ti.com
SLAS950A – MAY 2013 – REVISED JUNE 2015
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2013–2015, Texas Instruments Incorporated
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47
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC7562SQDGSRQ1
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ZADV
DAC7563SQDGSRQ1
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ZAIV
DAC8162SQDGSRQ1
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ZAGV
DAC8163SQDGSRQ1
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ZAHV
DAC8562SQDGSRQ1
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ZAAQ
DAC8563SQDGSRQ1
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ZAJV
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC7562-Q1, DAC7563-Q1, DAC8162-Q1, DAC8163-Q1, DAC8562-Q1, DAC8563-Q1 :
• Catalog: DAC7562, DAC7563, DAC8162, DAC8163, DAC8562, DAC8563
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC7562SQDGSRQ1
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
DAC7563SQDGSRQ1
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
DAC8162SQDGSRQ1
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
DAC8163SQDGSRQ1
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
DAC8562SQDGSRQ1
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
DAC8563SQDGSRQ1
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC7562SQDGSRQ1
VSSOP
DGS
10
2500
370.0
355.0
55.0
DAC7563SQDGSRQ1
VSSOP
DGS
10
2500
370.0
355.0
55.0
DAC8162SQDGSRQ1
VSSOP
DGS
10
2500
370.0
355.0
55.0
DAC8163SQDGSRQ1
VSSOP
DGS
10
2500
370.0
355.0
55.0
DAC8562SQDGSRQ1
VSSOP
DGS
10
2500
370.0
355.0
55.0
DAC8563SQDGSRQ1
VSSOP
DGS
10
2500
370.0
355.0
55.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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