Microchip MCP6546U-E/MS Open-drain output sub-microamp comparator Datasheet

MCP6546/6R/6U/7/8/9
Open-Drain Output Sub-Microamp Comparators
Features
Description
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The Microchip Technology Inc. MCP6546/7/8/9 family
of comparators is offered in single (MCP6546,
MCP6546R, MCP6546U), single with chip select
(MCP6548), dual (MCP6547) and quad (MCP6549)
configurations. The outputs are open-drain and are
capable of driving heavy DC or capacitive loads.
Low Quiescent Current: 600 nA/comparator (typ.)
Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
Open-Drain Output: VOUT ≤ 10V
Propagation Delay: 4 µs (typ., 100 mV Overdrive)
Wide Supply Voltage Range: 1.6V to 5.5V
Single available in SOT-23-5, SC-70-5 * packages
Available in Single, Dual and Quad
Chip Select (CS) with MCP6548
Low Switching Current
Internal Hysteresis: 3.3 mV (typ.)
Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Typical Applications
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Laptop Computers
Mobile Phones
Metering Systems
Hand-held Electronics
RC Timers
Alarm and Monitoring Circuits
Windowed Comparators
Multi-vibrators
These comparators are optimized for low power,
single-supply application with greater than rail-to-rail
input operation. The output limits supply current surges
and dynamic power consumption while switching. The
open-drain output of the MCP6546/7/8/9 family can be
used as a level-shifter for up to 10V using a pull-up
resistor. It can also be used as a wired-OR logic. The
internal Input hysteresis eliminates output switching
due to internal noise voltage, reducing current draw.
These comparators operate with a single-supply
voltage as low as 1.6V and draw a quiescent current of
less than 1 µA/comparator.
The related MCP6541/2/3/4 family of comparators from
Microchip has a push-pull output that supports rail-torail output swing and interfaces with CMOS/TTL logic.
* SC-70-5 E-Temp parts not avaliable at this release of
the data sheet.
MCP6546U SOT-23-5 is E-Temp only.
Related Devices
• CMOS/TTL-Compatible Output: MCP6541/2/3/4
Package Types
MCP6546
PDIP, SOIC, MSOP
+
NC
VDD
OUT
NC
OUT 1
VDD 2
VIN+ 3
5 VDD
-
+
OUT 1
VSS 2
VIN+ 3
4 VIN–
OUTA
VINA–
V
INA+
4 VIN–
VSS
MCP6546U
SOT-23-5
MCP6546
SOT-23-5, SC-70-5
VIN– 1
VSS 2
VIN+ 3
© 2006 Microchip Technology Inc.
MCP6547
PDIP, SOIC, MSOP
5 VSS
+
-
8
7
6
5
-
1
2
3
4
+
NC
VIN–
VIN+
VSS
MCP6546R
SOT-23-5
5 VDD
4 OUT
1
2
3
4
8
- +
7
+ - 6
5
OUTA 1
14 OUTD
OUTB VINA– 2
VINB– VINA+ 3
VINB+
VDD 4
- + + - 13 VIND–
VINB+ 5
VINB– 6
10 VINC+
- + +- 9 V –
INC
OUTB 7
8 OUTC
VDD
MCP6548
PDIP, SOIC, MSOP
NC
VIN–
VIN+
VSS
1
2
3
4
+
8
7
6
5
MCP6549
PDIP, SOIC, TSSOP
CS
VDD
12 VIND+
11 VSS
OUT
NC
DS21714E-page 1
MCP6546/6R/6U/7/8/9
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at those or any other conditions above those indicated
in the operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
Open-Drain output............................................... VSS + 10.5V
Analog Input (VIN+, VIN-)††............. VSS - 1.0V to VDD + 1.0V
All other inputs and outputs ........... VSS – 0.3V to VDD + 0.3V
†† See Section 4.1.2 “Input Voltage and Current
Limits”
Difference Input voltage ...................................... |VDD – VSS|
Output Short-Circuit Current .................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature (TJ) .......................... +150°C
ESD protection on all pins:
(HBM;MM) .....................................2 kV;200V (MCP6546U)
(HBM;MM) ................................ 4 kV; 200V (all other parts)
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS,
RPU = 2.74 kΩ to VPU = VDD (Refer to Figure 1-3).
Parameters
Sym
Min
Typ
Max
VDD
IQ
Input Voltage Range
VCMR
Common Mode Rejection Ratio
CMRR
Common Mode Rejection Ratio
Units
Conditions
1.6
—
5.5
V
VPU ≥ VDD
0.3
0.6
1
µA
IOUT = 0
VSS − 0.3
—
VDD + 0.3
V
55
70
—
dB
VDD = 5V, VCM = -0.3V to 5.3V
CMRR
50
65
—
dB
VDD = 5V, VCM = 2.5V to 5.3V
Common Mode Rejection Ratio
CMRR
55
70
—
dB
VDD = 5V, VCM = -0.3V to 2.5V
Power Supply Rejection Ratio
PSRR
63
80
—
dB
VCM = VSS
VOS
-7.0
±1.5
+7.0
mV
VCM = VSS (Note 1)
ΔVOS/ΔTA
—
±3
—
Power Supply
Supply Voltage
Quiescent Current
(per comparator)
Input
Input Offset Voltage
Drift with Temperature
Input Hysteresis Voltage
µV/°C TA = -40°C to +125°C, VCM = VSS
VHYST
1.5
3.3
6.5
Linear Temp. Co.
TC1
—
6.7
—
µV/°C TA = -40°C to +125°C, VCM = VSS (Note 2)
Quadratic Temp. Co.
TC2
—
-0.035
—
µV/°C2 TA = -40°C to +125°C, VCM = VSS (Note 2)
IB
—
1
—
At Temperature (I-Temp parts)
IB
—
25
100
pA
TA = +85°C, VCM = VSS (Note 3)
At Temperature (E-Temp parts)
IB
—
1200
5000
pA
TA = +125°C, VCM = VSS (Note 3)
VCM = VSS
Input Bias Current
mV
pA
Input Offset Current
IOS
—
±1
—
pA
Common Mode Input Impedance
ZCM
—
1013||4
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||2
—
Ω||pF
Note 1:
2:
3:
4:
VCM = VSS (Note 1)
VCM = VSS
The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
VHYST at differential temperatures is estimated using: VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.
Input bias current at temperature is not tested for the SC-70-5 package
Do not short the output above VSS + 10V. Limit the output current to Absolute Maximum Rating of 30 mA. The minimum
VPU test limit was VDD before Dec. 2004 (week code 52).
DS21714E-page 2
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS,
RPU = 2.74 kΩ to VPU = VDD (Refer to Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Open-Drain Output
Output Pull-Up Voltage
VPU
1.6
—
10
V
(Note 4)
High-Level Output Current
IOH
-100
—
—
nA
VDD = 1.6V to 5.5V, VPU = 10V (Note 4)
Low-Level Output Voltage
VOL
VSS
—
VSS + 0.2
V
ISC
—
±1.5
—
mA
VPU = VDD = 1.6V (Note 4)
ISC
–
30
—
mA
VPU = VDD = 5.5V (Note 4)
COUT
—
8
—
pF
Short-Circuit Current
Output Pin Capacitance
Note 1:
2:
3:
4:
IOUT = 2 mA, VPU = VDD = 5V
The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
VHYST at differential temperatures is estimated using: VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.
Input bias current at temperature is not tested for the SC-70-5 package
Do not short the output above VSS + 10V. Limit the output current to Absolute Maximum Rating of 30 mA. The minimum
VPU test limit was VDD before Dec. 2004 (week code 52).
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,
Step = 200 mV, Overdrive = 100 mV, RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF (Refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
tF
—
0.7
—
µs
Propagation Delay (High-to-Low)
tPHL
—
4.0
8.0
µs
Propagation Delay (Low-to-High)
tPLH
—
3.0
8.0
µs
Propagation Delay Skew
tPDS
—
-1.0
—
µs
Maximum Toggle Frequency
fMAX
—
225
—
kHz
VDD = 1.6V
fMAX
—
165
—
kHz
VDD = 5.5V
Eni
—
200
—
µVP-P
Fall Time
Input Noise Voltage
Note 1:
2:
(Note 1)
(Note 1)
(Notes 1 and 2)
10 Hz to 100 kHz
tR and tPLH depend on the load (RL and CL); these specifications are valid for the indicated load only.
Propagation Delay Skew is defined as: tPDS = tPLH - tPHL.
MCP6548 CHIP SELECT (CS) CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF (Refer to Figures 1-1 and 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
0.2 VDD
V
CS Input Current, Low
ICSL
—
5
—
pA
CS Logic Threshold, High
VIH
0.8 VDD
—
VDD
V
CS Input Current, High
ICSH
—
1
—
pA
CS = VDD
CS Input High, VDD Current
IDD
—
18
—
pA
CS = VDD
CS Input High, GND Current
ISS
—
-20
—
pA
CS = VDD
Comparator Output Leakage
IO(LEAK)
—
1
—
pA
VOUT = VSS+10V,
CS Low to Comparator Output Low
Turn-on Time
tON
—
2
50
ms
CS = 0.2VDD to VOUT = VDD/2,
VIN– = VDD
CS High to Comparator Output
High Z Turn-off Time
tOFF
—
10
—
µs
CS = 0.8VDD to VOUT = VDD/2,
VIN– = VDD
VCS_HYST
—
0.6
—
V
VDD = 5V
CS Low Specifications
CS = VSS
CS High Specifications
CS = VDD
CS Dynamic Specifications
CS Hysteresis
© 2006 Microchip Technology Inc.
DS21714E-page 3
MCP6546/6R/6U/7/8/9
VIL
CS
VIH
VIN–
tOFF
tON
VOUT High-Z
100 mV
VIN+ = VDD/2
100 mV
High-Z
ISS -20 pA (typ.)
-0.6 µA (typ.)
ICS 1 pA (typ.)
tPLH
VOUT
-20 pA (typ.)
5 pA (typ.)
1 pA (typ.)
VOH
VOL
FIGURE 1-2:
Diagram.
FIGURE 1-1:
Timing Diagram for the CS
pin on the MCP6548.
tPHL
VOL
Propagation Delay Timing
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5L-SC-70
θJA
—
331
—
°C/W
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Conditions
Temperature Ranges
Note
Thermal Package Resistances
Note:
1.1
The MCP6546/7/8/9 I-temp family operates over this extended temperature range, but with reduced
performance. In any case, the Junction Temperature (TJ) must not exceed the absolute maximum
specification of +150°C.
Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
VDD
VPU = VDD
200 kΩ
MCP654X
200 kΩ
100 kΩ
VIN = VSS
RPU =
(2 mA)/ VDD
VOUT
36 pF
VSS = 0V
FIGURE 1-3:
AC and DC Test Circuit for
the Open-Drain Output Comparators.
DS21714E-page 4
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
18%
1200 Samples
VCM = VSS
10%
8%
6%
4%
2%
0%
4
5
6
8%
6%
4%
2%
0%
7
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
Input Offset Voltage (mV)
FIGURE 2-4:
VCM = VSS.
14
3
2
1
VIN–
0
-1
0
1
2
3
4
5
6
7
Time (1 ms/div)
8
9
10
FIGURE 2-3:
The MCP6546/6R/6U/7/8/9
comparators show no phase reversal.
© 2006 Microchip Technology Inc.
9.4
9.0
8.6
8.2
VDD = 5.5V
VDD = 1.6V
-0.016
4
-0.020
VOUT
5
596 Samples
VCM = VSS
TA = -40°C to +125°C
-0.024
6
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-0.056
VDD = 5.5V
-0.060
Percentage of Occurrences
Inverting Input, Output
Voltage (V)
7
FIGURE 2-5:
Input Hysteresis Voltage
Linear Temp. Co. (TC1) at VCM = VSS.
-0.028
12
8
10
6
4
2
0
-2
-4
-6
-8
-10
-12
Input Hysteresis Voltage –
Linear Temp. Co.; TC1 (µV/°C)
Input Offset Voltage Drift (µV/°C)
Input Offset Voltage Drift at
7.8
0%
0%
FIGURE 2-2:
VCM = VSS.
VDD = 1.6V
5%
4.6
2%
VDD = 5.5V
7.4
4%
10%
-0.032
6%
7.0
8%
15%
-0.036
10%
596 Samples
VCM = VSS
TA = -40°C to +125°C
20%
6.6
12%
25%
-0.040
14%
Input Hysteresis Voltage at
6.2
1200 Samples
VCM = VSS
TA = -40°C to +125°C
5.0
Input Offset Voltage at
Percentage of Occurrences
16%
-14
Percentage of Occurrences
FIGURE 2-1:
VCM = VSS.
Input Hysteresis Voltage (mV)
-0.044
3
10%
5.8
2
12%
-0.048
1
14%
1200 Samples
VCM = VSS
5.4
-7 -6 -5 -4 -3 -2 -1 0
16%
-0.052
12%
Percentage of Occurrences
Percentage of Occurrences
14%
Input Hysteresis Voltage –
2
Quadratic Temp. Co.; TC2 (µV/°C )
FIGURE 2-6:
Input Hysteresis Voltage
Quadratic Temp. Co. (TC2) at VCM = VSS.
DS21714E-page 5
MCP6546/6R/6U/7/8/9
VCM = VSS
VDD = 1.6V
VDD = 5.5V
125
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
DS21714E-page 6
2.0
1.8
1.6
1.4
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-2.0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
2.0
-1.5
VDD = 5.5V
0.0
TA = +85°C
TA = +125°C
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
-0.5
0.0
-0.5
-1.0
FIGURE 2-11:
Input Hysteresis Voltage vs.
Common Mode Input Voltage at VDD = 1.6V.
Input Hysteresis Voltage (mV)
TA = -40°C
TA = +25°C
-0.5
Input Offset Voltage (mV)
VDD = 5.5V
0.5
1.2
Common Mode Input Voltage (V)
FIGURE 2-8:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 1.6V.
1.0
1.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-2.0
1.5
125
TA = +25°C
TA = -40°C
TA = +125°C
0.8
-1.5
2.0
100
TA = +125°C
TA = +85°C
1.5
TA = +125°C
-1.0
VDD = 1.6V
1.0
-0.5
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
0.6
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.0
0
25
50
75
Ambient Temperature (°C)
0.4
1.0
0.5
-25
0.2
Input Hysteresis Voltage (mV)
VDD = 1.6V
-0.4
Input Offset Voltage (mV)
1.5
-50
FIGURE 2-10:
Input Hysteresis Voltage vs.
Ambient Temperature at VCM = VSS.
FIGURE 2-7:
Input Offset Voltage vs.
Ambient Temperature at VCM = VSS.
2.0
VDD = 5.5V
0.0
0
25
50
75
100
Ambient Temperature (°C)
VDD = 1.6V
-0.2
-25
VCM = VSS
0.5
-50
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
-0.4
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
Input Hysteresis Voltage (mV)
Input Offset Voltage (mV)
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
Common Mode Input Voltage (V)
FIGURE 2-12:
Input Hysteresis Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
10n
10000
Input Referred
Input Bias, Offset Currents
(A)
90
CMRR, PSRR (dB)
85
100p
100
75
PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V
70
65
IB, TA = +85°C
10p
10
CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V
60
IOS, TA = +125°C
IOS, TA = +85°C
1
1p
100f
0.1
55
-50
-25
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-13:
Temperature.
1000
100
Common Mode Input Voltage (V)
CMRR,PSRR vs. Ambient
FIGURE 2-16:
Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
0.7
Quiescent Current
per Comparator (µA)
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
125
VDD = 5.5V
VCM = VDD
IB
10
| IOS |
1
0.1
0.6
0.5
0.4
0.2
0.1
65
75
85
95
105
115
125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Ambient Temperature (°C)
Power Supply Voltage (V)
FIGURE 2-14:
Input Bias Current, Input
Offset Current vs. Ambient Temperature.
0.7
0.6
0.8
IQ does not include pull-up resistor current
VDD = 1.6V
0.5
0.4
0.3
0.2
FIGURE 2-17:
Quiescent Current vs.
Power Supply Voltage.
Quiescent Current
per Comparator (µA)
0.8
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.3
0.0
55
Quiescent Current
per Comparator (µA)
VDD = 5.5V
1n
1000
80
Input Bias, Offset Currents
(pA)
IB, TA = +125°C
Sweep VIN+, VIN– = VDD/2
0.1
Sweep VIN–, VIN+ = VDD/2
0.0
0.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
Common Mode Input Voltage (V)
0.6
1.6
IQ does not include pull-up resistor current
VDD = 5.5V
0.5
0.4
0.3
0.2
0.1
0.0
FIGURE 2-15:
Quiescent Current vs.
Common Mode Input Voltage at VDD = 1.6V.
© 2006 Microchip Technology Inc.
0.7
Sweep VIN+, VIN– = VDD/2
Sweep VIN–, VIN+ = VDD/2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-18:
Quiescent Current vs.
Common Mode Input Voltage at VDD = 5.5V.
DS21714E-page 7
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
IDD spike near VPU = 1.3V
1
10
VDD = 2.1V
VDD = 2.6V
VDD = 3.6V
VDD = 4.6V
VDD = 5.6V
Supply Current
per Comparator (µA)
Supply Current
per Comparator (µA)
10
VDD = 1.6V
VDD = 1.6V
VDD = 2.1V
0.1
-4 -3 -2 -1
1
2
3 4 5 6 7 8
Pull-Up Voltage, VPU (V)
FIGURE 2-19:
Voltage.
Supply Current
per Comparator (µA)
10
9
10 11
Supply Current vs. Pull-Up
100 mV Overdrive
VCM = VDD/2
IDD does not include
pull-up resistor current
1
VDD = 5.5V
VDD = 1.6V
0.1
0.1
1
10
Toggle Frequency (kHz)
0.7
VDD = 1.6V
0.6
0.5
0.4
VOL–VSS:
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.3
0.2
0.1
0.0
0.0
0.2
0.4
0.6 0.8 1.0 1.2
Output Current (mA)
1.4
1.6
FIGURE 2-21:
Output Voltage Headroom
vs. Output Current at VDD = 1.6V.
DS21714E-page 8
2
3
4
5
6
7
8
9
35
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
30
25
20
15
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
100
Supply Current vs. Toggle
1
FIGURE 2-22:
Supply Current vs. Pull-Up
to Supply Voltage Difference.
FIGURE 2-23:
Output Short Circuit Current
Magnitude vs. Power Supply Voltage.
Output Voltage Headroom (V)
Output Voltage Headroom (V)
FIGURE 2-20:
Frequency.
0
Pull-up to Supply Voltage Difference,
VPU – VDD (V)
Output Short Circuit Current
Magnitude (mA)
0
VPU = 1.6V to 10.5V
1
0.1
0.8
VDD = 5.6V
VDD = 4.6V
VDD = 3.6V
VDD = 2.6V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VDD = 5.5V
VOL – VSS:
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
5
10
15
Output Current (mA)
20
25
FIGURE 2-24:
Output Voltage Headroom
vs. Output Current at VDD = 5.5V.
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
408 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 1.6V
0
1
Percentage of Occurrences
Percentage of Occurrences
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
VDD = 5.5V
2
3
4
5
6
7
65%
60%
55%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
8
408 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 1.6V
0
1
High-to-Low Propagation Delay (µs)
High-to-Low Propagation
408 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 5.5V
FIGURE 2-28:
Delay.
8
1.5
2.0
tPHL
tPLH
2.5
3.0
3.5
4.0
4.5
Power Supply Voltage (V)
5
5.0
7
8
Low-to-High Propagation
tPHL
VDD = 5.5V
tPLH
VDD = 1.6V
4
3
2
1
-25
0
25
50
75
Ambient Temperature (°C)
5.5
100
125
FIGURE 2-29:
Propagation Delay vs.
Ambient Temperature.
VCM = VDD/2
10
VDD = 5.5V
tPHL
VDD = 1.6V
1
FIGURE 2-27:
Propagation Delay vs.
Power Supply Voltage.
© 2006 Microchip Technology Inc.
6
100
10 mV Overdrive
100 mV Overdrive
5
6
-50
Propagation Delay (µs)
Propagation Delay (µs)
Propagation Delay Skew.
VCM = VDD/2
4
100 mV Overdrive
VCM = VDD/2
7
Propagation Delay Skew (µs)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
3
0
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
-0.8
-1.2
-1.6
VDD = 1.6V
FIGURE 2-26:
2
Low-to-High Propagation Delay (µs)
Propagation Delay (µs)
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
-2.0
Percentage of Occurrences
FIGURE 2-25:
Delay.
VDD = 5.5V
1
FIGURE 2-30:
Overdrive.
tPLH
10
100
Input Overdrive (mV)
1000
Propagation Delay vs. Input
DS21714E-page 9
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
8
VDD = 1.6V
100 mV Overdrive
7
Propagation Delay (µs)
Propagation Delay (µs)
8
6
5
4
tPHL
3
2
tPLH
1
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Common Mode Input Voltage (V)
1.6
FIGURE 2-31:
Propagation Delay vs.
Common Mode Input Voltage at VDD = 1.6V.
8
5
tPHL
4
tPLH
3
2
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-34:
Propagation Delay vs.
Common Mode Input Voltage at VDD = 5.5V.
VIN– = 100 mV Overdrive
7
VCM = VDD/2
VIN+ = VCM
6
Propagation Delay (µs)
Propagation Delay (µs)
6
0
0.0
tPLH
VDD = 5.5V
5
4
3
2
tPHL
VDD = 1.6V
1
0
0
10
20
30 40 50 60 70 80
Pull-up Resistor, RPU (k:)
FIGURE 2-32:
Pull-up Resistor.
8
Propagation Delay vs.
VDD = 5.5V
VDD = 1.6V
10
2
VDD = 1.6V
3
4
5
6
7
8
9
10
Pull-up Voltage (V)
DS21714E-page 10
Propagation Delay vs. Load
TA = +85°C
1.E+00
1p
tPLH
0
FIGURE 2-33:
Pull-up Voltage.
90
CS = VDD
VIN+ = VDD/2
VIN– = VSS
1.E+01
10p
3
2
80
TA = +125°C
100p
1.E+02
4
1
30 40 50 60 70
Load Capacitance (nF)
FIGURE 2-35:
Capacitance.
tPHL
VDD = 5.5V
0
20
tPHL
1n
1.E+03
5
1
tPLH
10n
1.E+04
VCM = VDD/2
VIN+ = VCM
6
100 mV Overdrive
VCM = VDD/2
0
90 100
VIN– = 100 mV Overdrive
7
200
180
160
140
120
100
80
60
40
20
0
Output Leakage Current (A)
Propagation Delay (µs)
VDD = 5.5V
100 mV Overdrive
7
Propagation Delay vs.
11
TA = +25°C
1.E-01
100f
0
1
2
3
4
5
6
7
8
Output Voltage (V)
9
10 11
FIGURE 2-36:
Output Leakage Current
(CS = VDD) vs. Output Voltage (MCP6548 only).
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
1m
1.E-03
Comparator
Turns On
Comparator
Shuts Off
10µ
1.E-05
Comparator
Turns On
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
1µ
1.E-06
CS Hysteresis
1.E-07
100n
1.E-08
10n
CS
High-to-Low
1.E-09
1n
VDD = 1.6V
1.E-11
10p
0.0 0.2 0.4
CS
Hysteresis
100n
1.E-07
10n
1.E-08
CS
Low-to-High
100p
1.E-10
0.6
0.8
1.0
1.2
1.4
VDD = 5.5V
10p
1.E-11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
1.6
Chip Select (CS) Voltage (V)
Chip Select (CS) Voltage (V)
1.6
VOUT
Supply Current (µA)
25
0.0
CS
20
-1.6
VDD = 1.6V
Charging output
capacitance
5
-3.2
Start-up
IDD
-4.9
-6.5
0
-8.1
FIGURE 2-40:
Supply Current (shoot
through current) vs. Chip Select (CS) Voltage at
VDD = 5.5V (MCP6548 only).
Supply Current
per Comparator (µA)
30
Output Voltage,
Chip Select Voltage (V),
FIGURE 2-37:
Supply Current (shoot
through current) vs. Chip Select (CS) Voltage at
VDD = 1.6V (MCP6548 only).
10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Time (1 ms/div)
VOUT
CS
1
2
3
4
5
6
Time (ms)
7
8
9
FIGURE 2-39:
Chip Select (CS) Step
Response (MCP6548 only).
© 2006 Microchip Technology Inc.
VOUT
10
6
3
0
-3
-6
-9
-12
-15
-18
-21
-24
CS
VDD = 5.5V
Start-up IDD
Charging output
capacitance
0.5
1.0 1.5 2.0 2.5
Time (0.5 ms/div)
3.0
3.5
FIGURE 2-41:
Supply Current (charging
current) vs. Chip Select (CS) pulse at VDD = 5.5V
(MCP6548 only).
Input Current Magnitude (A)
Chip Select, Output Voltage
(V)
VDD = 5.5V
0
200
180
160
140
120
100
80
60
40
20
0
0.0
FIGURE 2-38:
Supply Current (charging
current) vs. Chip Select (CS) pulse at VDD = 1.6V
(MCP6548 only).
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
CS
High-to-Low
CS
Low-to-High
1n
1.E-09
1.E-10
100p
15
Comparator
Shuts Off
Output Voltage,
Chip Select Voltage (V)
Supply Current
per Comparator (A)
1.E-04
100µ
Supply Current
per Comparator (A)
1.E-03
1m
1.E-02
10m
1.E-03
1m
1.E-04
100µ
1.E-05
10µ
1.E-06
1µ
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-42:
Voltage.
Input Bias Current vs. Input
DS21714E-page 11
MCP6546/6R/6U/7/8/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
MCP6546U
MCP6547
MCP6548
MCP6549
PIN FUNCTION TABLE
MCP6546R
TABLE 3-1:
6
1
1
4
1
6
1
2
4
4
1
2
2
2
VIN–, VINA– Inverting Input (comparator A)
3
3
3
3
3
3
3
VIN+, VINA+ Non-inverting Input (comparator A)
MCP6546
MCP6546
(PDIP,
(SOT-23-5,
SOIC,
SC-70-5)
MSOP)
Symbol
Description
OUT, OUTA Digital Output (comparator A)
7
5
2
5
8
7
4
VDD
—
—
—
—
5
—
5
VINB+
Non-inverting Input (comparator B)
—
—
—
—
6
—
6
VINB–
Inverting Input (comparator B)
—
—
—
—
7
—
7
OUTB
Digital Output (comparator B)
—
—
—
—
—
—
8
OUTC
Digital Output (comparator C)
—
—
—
—
—
—
9
VINC–
Inverting Input (comparator C)
—
—
—
—
—
—
10
VINC+
Non-inverting Input (comparator C)
4
2
5
2
4
4
11
VSS
—
—
—
—
—
—
12
VIND+
Non-inverting Input (comparator D)
—
—
—
—
—
—
13
VIND–
Inverting Input (comparator D)
—
—
—
—
—
—
14
OUTD
—
—
—
—
—
8
—
CS
Chip Select
1, 5, 8
—
—
—
—
1, 5
—
NC
No Internal Connection
3.1
Analog Inputs
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2
CS Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
3.3
Digital Outputs
The comparator outputs are CMOS, open-drain digital
outputs. They are designed to make level shifting and
wired-OR easy to implement.
DS21714E-page 12
3.4
Positive Power Supply
Negative Power Supply
Digital Output (comparator D)
Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.6V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD, except the output pins which
can be as high as 10V above VSS.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These can share a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
4.0
APPLICATIONS INFORMATION
The MCP6546/7/8/9 family of push-pull output
comparators are fabricated on Microchip’s state-of-theart CMOS process. They are suitable for a wide range
of applications requiring very low power consumption.
4.1
VDD
D1
R1
Comparator Inputs
4.1.1
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
VDD Bond
Pad
VIN+ Bond
Pad
Bond
Pad
VIN–
VSS Bond
Pad
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pin. Diodes D1 and D2 prevent the input
pin (VIN+ and VIN–) from going too far above VDD.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
© 2006 Microchip Technology Inc.
–
VOUT
V2
R2
R3
R1 ≥
VSS – (minimum expected V1)
2 mA
R2 ≥
VSS – (minimum expected V2)
2 mA
FIGURE 4-2:
Protecting the Analog Inputs.
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-42. Applications that are
high impedance may need to limit the useable voltage
range.
4.1.3
Input
Stage
MCP6G0X
D2
PHASE REVERSAL
The MCP6546/6R/6U/7/8/9 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
4.1.2
+
V1
NORMAL OPERATION
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages.
With this topology, the input voltage is 0.3V above VDD
and 0.3V below VSS. The input offset voltage is
measured at both VSS - 0.3V and VDD + 0.3V to ensure
proper operation.
The MCP6546/6R/6U/7/8/9 family has internally-set
hysteresis that is small enough to maintain input offset
accuracy (<7 mV), and large enough to eliminate
output chattering caused by the comparator’s own
input noise voltage (200 µVP-P). Figure 4-3 illustrates
this capability.
DS21714E-page 13
MCP6546/6R/6U/7/8/9
8
7
6
5
4
3
2
1
0
-1
-2
-3
VDD = 5.0V
VIN–
VOUT
Hysteresis
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
Input Voltage (10 mV/div)
Output Voltage (V)
4.4.1
Time (100 ms/div)
INVERTING CIRCUIT
Figure 4-4 shows an inverting circuit for a single-supply
application using three resistors, besides the pull-up
resistor. The resulting hysteresis diagram is shown in
Figure 4-5.
VDD
IPU
VIN
4.2
IRF
RF
R3
FIGURE 4-4:
hysteresis.
The internal CS circuitry is designed to minimize
glitches when cycling the CS pin. This helps conserve
power, which is especially important in battery-powered
applications.
Inverting circuit with
VOUT
VPU
VOH
MCP6548 Chip Select (CS)
The MCP6548 is a single comparator with a Chip
Select (CS) pin. When CS is pulled high, the total
current consumption drops to 20 pA (typ.). 1 pA (typ.)
flows through the CS pin, 1 pA (typ.) flows through the
output pin and 18 pA (typ.) flows through the VDD pin,
as shown in Figure 1-1. When this happens, the
comparator output is put into a high-impedance state.
By pulling CS low, the comparator is enabled. If the CS
pin is left floating, the comparator will not operate
properly. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
4.4
VOUT
IOL
Open-Drain Output
The open-drain output is designed to make levelshifting and wired-OR logic easy to implement. The
output can go as high as 10V for 9V battery-powered
applications. The output stage minimizes switching current (shoot-through current from supply-to-supply)
when the output changes state. See Figures 2-15, 2-18
and 2-37 through 2-41, for more information.
4.3
RPU
MCP654X
VDD
R2
FIGURE 4-3:
The MCP6546/7/8/9
comparators’ internal hysteresis eliminates
output chatter caused by input noise voltage.
VPU
Low-to-High
High-to-Low
VIN
VOL
VSS
VSS
VTLH VTHL
VDD
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
FIGURE 4-5:
inverting circuit.
Hysteresis diagram for the
In order to determine the trip voltages (VTHL and VTLH)
for the circuit shown in Figure 4-4, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-6.
VPU
Externally Set Hysteresis
Greater flexibility in selecting hysteresis, or input trip
points, is achieved by using external resistors.
Input offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points. Hysteresis reduces output
chattering when one input is slowly moving past the
other, thus reducing dynamic supply current. It also
helps in systems where it is best not to cycle between
states too frequently (e.g., air conditioner thermostatic
control).
DS21714E-page 14
RPU
MCP654X
+
VOUT
V23
R23
FIGURE 4-6:
RF
Thevenin Equivalent Circuit.
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
4.6
EQUATION 4-1:
R2 R3
R 23 = -----------------R2 + R3
R3
V 23 = ------------------ × V DD
R2 + R3
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
EQUATION 4-2:
R 23
R F + R PU
⎛
⎞
V THL = V PU ⎜ ----------------------------------------⎟ + V 23 ⎛ ---------------------------------------⎞
⎝
⎠
R
+
R
+
R
R
⎝ 23
PU⎠
23 + R F + R PU
F
RF
⎛ R 23 ⎞
V TLH = V OL ⎜ -----------------------⎟ + V 23 ⎛ ----------------------⎞
⎝
R 23 + R F⎠
⎝ R 23 + R F⎠
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
Figure 2-21 and Figure 2-24 can be used to determine
typical values for VOL. This voltage is dependent on the
output current IOL as shown in Figure 4-4. This current
can be determined using the equation below:
EQUATION 4-3:
I OL = I PU + I RF
V 23 – V OL
V PU – V OL
I OL = ⎛ --------------------------⎞ + ⎛ ------------------------⎞
⎝ R PU ⎠ ⎝ R 23 + R F ⎠
Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-27).
The supply current increases with increasing toggle
frequency (Figure 2-30), especially with higher
capacitive loads.
4.7
Battery Life
In order to maximize battery life in portable
applications, use large resistors and small capacitive
loads. Avoid toggling the output more than necessary.
Do not use Chip Select (CS) too frequently in order to
conserve power. Capacitive loads will draw additional
power at start-up.
4.8
PCB Surface Leakage
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low-humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference
would cause 5 pA of current to flow. This is greater
than the MCP6546/6R/6U/7/8/9 family’s bias current at
25°C (1 pA, typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
VIN-
VIN+
VSS
VOH can be calculated using the equation below:
EQUATION 4-4:
R 23 + R F
V OH = ( V PU – V 23 ) × ⎛⎝ --------------------------------------⎞⎠
R 23 + R F + R PU
As explained in Section 4.1 “Comparator Inputs”, it
is important to keep the non-inverting input below
VDD+0.3V when VPU > VDD.
4.5
Supply Bypass
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
© 2006 Microchip Technology Inc.
Guard Ring
FIGURE 4-7:
Example Guard Ring Layout
for Inverting Circuit.
1.
Inverting Configuration (Figures 4-4 and 4-7):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
pad without touching the guard ring.
DS21714E-page 15
MCP6546/6R/6U/7/8/9
4.9
Unused Comparators
An unused amplifier in a quad package (MCP6549)
should be configured as shown in Figure 4-8. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-18).
4.10
Typical Applications
4.10.1
PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041) to gain-up the input signal
before it reaches the comparator. Figure 4-9 shows an
example of this approach.
¼ MCP6549
VDD
VDD
VREF
MCP6041
VDD
–
+
FIGURE 4-8:
Unused Comparators.
VPU
RPU
VIN
R1
R2
VREF
FIGURE 4-9:
Comparator.
4.10.2
VOUT
MCP6546
Precise Inverting
WINDOWED COMPARATOR
Figure 4-10 shows one approach to designing a
windowed comparator. The wired-OR connection
produces a high output (logic 1) when the input voltage
is between VRB and VRT (where VRT > VRB ).
VRT
1/2
MCP6547
VPU
RPU
VOUT
VIN
VRB
FIGURE 4-10:
DS21714E-page 16
1/2
MCP6547
Windowed Comparator.
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
5-Lead SC-70 (MCP6546)
XXNN (Front)
YWW (Back)
Example: (I-temp)
Device
I-Temp
Code
E-Temp
Code
MCP6546
ACNN
Note 2
Note 1:
2:
I-Temp parts prior to March
2005 are marked “ACN”
SC-70-5 E-Temp parts not
available at this release of
the data sheet.
5-Lead SOT-23 (MCP6546, MCP6546R, MCP6546U)
XXNN
Device
I-Temp
Code
E-Temp
Code
MCP6546
ACNN
GWNN
MCP6546R
AHNN
GXNN
MCP6546U
—
AWNN
AC25(Front)
636 (Back)
Example: (I-temp)
AC25
Note: Applies to 5-Lead SOT-23
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
Example:
MCP6546
I/P256
0636
8-Lead SOIC (150 mil)
MCP6546I
e3
SN^^0636
256
OR
Example:
8-Lead MSOP
XXXXXX
6546I
YWWNNN
636256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
MCP6546
I/SN0636
256
XXXXXXXX
XXXXYYWW
NNN
MCP6546
e3
I/P^^256
0636
OR
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS21714E-page 17
MCP6546/6R/6U/7/8/9
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6549)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP6549-I/P
XXXXXXXXXXXXXX
0636256
OR
MCP6549E/P e3
0636256
MCP6549
I/P^^
e3
0636256
OR
14-Lead SOIC (150 mil) (MCP6549)
Example:
MCP6549ISL
XXXXXXXXXX
0636256
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
MCP6549
e3
E/SL^^
0636256
OR
14-Lead TSSOP (MCP6549)
XXXXXXXX
YYWW
NNN
DS21714E-page 18
Example:
MCP6549I
0636
256
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
5-Lead Plastic Package (LT) (SC-70)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
D
p
B
n
1
Q1
A2
c
A1
L
Units
Dimension Limits
A
MILLIMETERS*
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
Overall Height
A
.031
.043
0.80
Molded Package Thickness
A2
.031
.039
0.80
1.00
Standoff
A1
.000
.004
0.00
0.10
Number of Pins
5
5
.026 (BSC)
0.65 (BSC)
1.10
Overall Width
E
.071
.094
1.80
2.40
Molded Package Width
E1
.045
.053
1.15
1.35
Overall Length
D
.071
.087
1.80
2.20
Foot Length
L
.004
.012
0.10
0.30
Q1
.004
.016
0.10
0.40
Lead Thickness
c
.004
.007
0.10
0.18
Lead Width
B
.006
.012
0.15
0.30
Top of Molded Pkg to
Lead Shoulder
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (EIAJ) Standard: SC-70
Drawing No. C04-061
© 2006 Microchip Technology Inc.
Revised 07-19-05
DS21714E-page 19
MCP6546/6R/6U/7/8/9
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
B
p1
n
D
1
α
c
A
φ
β
A1
L
INCHES*
Units
Dimension Limits
MIN
Pitch
.038 BSC
Outside lead pitch
p1
.075 BSC
Overall Height
MILLIMETERS
NOM
n
p
Number of Pins
A2
MAX
MIN
NOM
6
MAX
6
0.95 BSC
1.90 BSC
A
.035
.046
.057
0.90
1.18
1.45
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
L
φ
.014
.022
0.35
Foot Angle
Lead Thickness
c
.004
Lead Width
B
α
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
β
.018
0
5
.006
.017
10
0.45
0
0.55
5
.008
0.09
0.15
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
DS21714E-page 20
Revised 09-12-05
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
INCHES*
NOM
8
.100
.155
.130
MAX
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MAX
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
4.32
Molded Package Thickness
A2
.115
.145
3.68
Base to Seating Plane
.015
A1
Shoulder to Shoulder Width
E
.300
.313
.325
8.26
Molded Package Width
E1
.240
.250
.260
6.60
Overall Length
D
.360
.373
.385
9.78
Tip to Seating Plane
L
.125
.130
.135
3.43
c
Lead Thickness
.008
.012
.015
0.38
Upper Lead Width
B1
.045
.058
.070
1.78
Lower Lead Width
B
.014
.018
.022
0.56
eB
Overall Row Spacing
§
.310
.370
.430
10.92
α
Mold Draft Angle Top
5
10
15
15
β
Mold Draft Angle Bottom
5
10
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2006 Microchip Technology Inc.
MIN
MIN
DS21714E-page 21
MCP6546/6R/6U/7/8/9
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.053
.069
1.75
Molded Package Thickness
A2
.052
.061
1.55
Standoff
§
.004
.010
0.25
A1
Overall Width
E
.228
.244
6.20
Molded Package Width
E1
.146
.157
3.99
Overall Length
D
.189
.197
5.00
Chamfer Distance
h
.010
.020
0.51
Foot Length
L
.019
.030
0.76
φ
Foot Angle
0
8
8
c
Lead Thickness
.008
.010
0.25
Lead Width
B
.013
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21714E-page 22
MIN
A1
MIN
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
α
c
φ
L
F
A2
A
A1
β
Units
INCHES
MILLIMETERS*
NOM
MIN
Dimension Limits
MAX
NOM
MIN
MAX
Number of Pins
n
Pitch
p
Overall Height
A
-
-
.043
-
-
1.10
Molded Package Thickness
A2
.030
.033
.037
0.75
0.85
0.95
Standoff
A1
.000
-
.006
0.00
-
0.15
Overall Width
E
.193 BSC
4.90 BSC
Molded Package Width
E1
.118 BSC
3.00 BSC
Overall Length
D
.118 BSC
Foot Length
L
0.60
0.80
Footprint (Reference)
Foot Angle
F
φ
Lead Thickness
c
.003
.006
.009
0.08
Lead Width
B
α
.009
.012
.016
0.22
Mold Draft Angle Top
Mold Draft Angle Bottom
β
8
8
.026 BSC
.016
0.65 BSC
3.00 BSC
.024
.031
0.40
.037 REF
0°
0.95 REF
-
8°
0°
-
8°
-
0.23
-
0.40
5°
-
15°
5°
-
15°
5°
-
15°
5°
-
15°
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-187
Drawing No. C04-111
© 2006 Microchip Technology Inc.
Revised 07-21-05
DS21714E-page 23
MCP6546/6R/6U/7/8/9
14-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
eB
B1
p
B
Units
Dimension Limits
n
p
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MAX
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
4.32
Molded Package Thickness
.115
.145
3.68
A2
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
8.26
Molded Package Width
E1
.240
.250
.260
6.60
Overall Length
D
.740
.750
.760
19.30
Tip to Seating Plane
L
.125
.130
.135
3.43
c
Lead Thickness
.008
.012
.015
0.38
Upper Lead Width
B1
.045
.058
.070
1.78
Lower Lead Width
B
.014
.018
.022
0.56
eB
Overall Row Spacing
§
.310
.370
.430
10.92
α
Mold Draft Angle Top
5
10
15
15
β
Mold Draft Angle Bottom
5
10
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS21714E-page 24
MIN
MIN
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
L
β
Units
Dimension Limits
n
p
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.053
.069
1.75
Molded Package Thickness
A2
.052
.061
1.55
Standoff
§
A1
.004
.010
0.25
Overall Width
E
.228
.244
6.20
Molded Package Width
E1
.150
.157
3.99
Overall Length
D
.337
.347
8.81
Chamfer Distance
h
.010
.020
0.51
Foot Length
L
.016
.050
1.27
φ
Foot Angle
0
8
8
c
Lead Thickness
.008
.010
0.25
Lead Width
B
.014
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
© 2006 Microchip Technology Inc.
MIN
A1
MIN
DS21714E-page 25
MCP6546/6R/6U/7/8/9
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
Units
Dimension Limits
A1
A2
MILLIMETERS*
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
Overall Height
A
.039
.041
.043
1.00
1.05
Molded Package Thickness
A2
.033
.035
.037
0.85
0.90
0.95
Standoff
A1
.002
.004
.006
0.05
0.10
0.15
Overall Width
E
.246
.251
.256
6.25
6.38
6.50
Molded Package Width
E1
.169
.173
.177
4.30
4.40
4.50
Molded Package Length
D
.193
.197
.201
4.90
5.00
5.10
Foot Length
L
φ
.020
.024
.028
0.50
0.60
0.70
Foot Angle
Lead Thickness
c
.004
Lead Width
B
α
.007
Mold Draft Angle Top
Mold Draft Angle Bottom
β
Number of Pins
14
14
.026 BSC
0.65 BSC
4°
0°
8°
0°
.006
.008
0.09
.010
.012
0.19
4°
1.10
8°
0.15
0.20
0.25
0.30
12° REF
12° REF
12° REF
12° REF
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
DS21714E-page 26
Revised: 08-17-05
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
APPENDIX A:
REVISION HISTORY
Revision E (September 2006)
The following is the list of modifications:
1.
2.
3.
4.
Added MCP6546U pinout for the SOT-23-5
package.
Clarified Absolute Maximum Analog Input
Voltage and Current Specifications.
Added applications writeups on unused
comparators.
Added disclaimer to package outline drawings.
Revision D (May 2006)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
7.
Added E-temp parts.
Changed minimum pull-up voltage specification
(VPU) to 1.6V for parts starting Dec. 2004 (week
code 52); previous parts are specified at a
minimum of VDD.
Changed VHYST temperature specifications to
linear and quadratic temperature coefficients.
Changed specifications and plots to include ETemp parts.
Added Section 3.0 “Pin Descriptions”.
Corrected package markings (Section 5.1
“Package Marking Information”).
Added Appendix A: “Revision History”.
Revision C (May 2003)
Revision B (December 2002)
Revision A (February 2002)
• Original Release of this Document.
© 2006 Microchip Technology Inc.
DS21714E-page 27
MCP6546/6R/6U/7/8/9
NOTES:
DS21714E-page 28
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
–X
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
Device:
Temperature Range:
MCP6546: Single Comparator
MCP6546T: Single Comparator (Tape and Reel)
(SC-70, SOT-23, SOIC, MSOP)
MCP6546RT: Single Comparator (Rotated - Tape and
Reel) (SOT-23 only)
MCP6546UT: Single Comparator (Tape and Reel)
(SOT-23-5 is E-Temp only)
MCP6547: Dual Comparator
MCP6547T: Dual Comparator
(Tape and Reel for SOIC and MSOP)
MCP6548: Single Comparator with CS
MCP6548T: Single Comparator with CS
(Tape and Reel for SOIC and MSOP)
MCP6549: Quad Comparator
MCP6549T: Quad Comparator
(Tape and Reel for SOIC and TSSOP)
I
= -40°C to +85°C
E * = -40°C to +125°C
* SC-70-5 E-Temp parts not available at this release of the
data sheet.
Package:
LT
OT
MS
P
SN
SL
ST
=
=
=
=
=
=
=
Plastic Package (SC-70), 5-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
Plastic MSOP, 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead (MCP6549)
Plastic TSSOP (4.4mm Body), 14-lead (MCP6549)
c)
d)
e)
f)
a)
b)
c)
d)
a)
b)
c)
d)
a)
b)
c)
d)
© 2006 Microchip Technology Inc.
MCP6546T-I/LT:
Tape and Reel,
Industrial Temperature,
5LD SC-70.
MCP6546T-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT-23.
MCP6546-E/P:
Extended Temperature,
8LD PDIP.
MCP6546RT-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT23.
MCP6546-E/SN: Extended Temperature,
8LD SOIC.
MCP6546UT-E/OT:Tape and Reel,
Extended Temperature,
5LD SOT23.
MCP6547-I/MS:
Industrial Temperature,
8LD MSOP.
MCP6547T-I/MS: Tape and Reel,
Industrial Temperature,
8LD MSOP.
MCP6547-I/P:
Industrial Temperature,
8LD PDIP.
MCP6547-E/SN: Extended Temperature,
8LD SOIC.
MCP6548-I/SN:
Industrial Temperature,
8LD SOIC.
MCP6548T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC.
MCP6548-I/P:
Industrial Temperature,
8LD PDIP.
MCP6548-E/SN: Extended Temperature,
8LD SOIC.
MCP6549T-I/SL:
Tape and Reel,
Industrial Temperature,
14LD SOIC.
MCP6549T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC.
MCP6549-I/P:
Industrial Temperature,
14LD PDIP.
MCP6549-E/ST: Extended Temperature,
14LD TSSOP.
DS21714E-page 29
MCP6546/6R/6U/7/8/9
NOTES:
DS21714E-page 30
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21714E-page 31
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
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08/29/06
DS21714E-page 32
© 2006 Microchip Technology Inc.