LTC1052/LTC7652
Zero-Drift
Operational Amplifier
U
FEATURES
■
■
■
■
■
■
■
■
DESCRIPTIO
Guaranteed Max Offset: 5µV
Guaranteed Max Offset Drift: 0.05µV/°C
Typ Offset Drift: 0.01µV/°C
Excellent Long Term Stability: 100nV/√Month
Guaranteed Max Input Bias Current: 30pA
Over Operating Temperature Range:
Guaranteed Min Gain: 120dB
Guaranteed Min CMRR: 120dB
Guaranteed Min PSRR: 120dB
Single Supply Operation: 4.75V to 16V
(Input Voltage Range Extends to Ground)
External Capacitors can be Returned to V – with No
Noise Degradation
■
■
■
Low frequency (1/f) noise is also improved by the
chopping technique. Instead of increasing continuously
at a 3dB/octave rate, the internal chopping causes noise to
decrease at low frequencies.
The chopper circuitry is entirely internal and completely
transparent to the user. Only two external capacitors
are required to alternately sample-and-hold the offset
correction voltage and the amplified input signal. Control
circuitry is brought out on the 14-pin and 16-pin versions
to allow the sampling of the LTC1052 to be synchronized
with an external frequency source.
U
APPLICATIO S
■
The LTC®1052 and LTC7652 are low noise zero-drift op
amps manufactured using Linear Technology’s enhanced
LTCMOSTM silicon gate process. Chopper-stabilization
constantly corrects offset voltage errors. Both initial offset
and changes in the offset due to time, temperature and
common mode voltage are corrected. This, coupled with
picoampere input currents, gives these amplifiers
unmatched performance.
Thermocouple Amplifiers
Strain Gauge Amplifiers
Low Level Signal Processing
Medical Instrumentation
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation.
Teflon is a trademark of DuPont.
U
TYPICAL APPLICATIO
Ultralow Noise, Low Drift Amplifier
Noise Spectrum
5V
160
7
+
6
LTC1052
2
8
–
4
1
0.1µF
0.1µF
0.1µF
–5V
5V
100k
INPUT
3K
3
+
1 5V
7
68k
LT 1007
VOS = 3µV
VOS∆T = 50nV/°C
NOISE = 0.06µVP-P 0.1Hz TO 10Hz
–
5V
8
®
2
1.5k
4
– 5V
6
OUTPUT
100k
VOLTAGE NOISE DENSITY (nV/√Hz)
3
140
120
100
80
60
40
20
0
0
100
200
300
400
500
FREQUENCY (Hz)
100Ω
LTC1052/7652 • TA02
LTC1052/7652 • TA01
1052fa
1
LTC1052/LTC7652
W W
W
AXI U
U
ABSOLUTE
RATI GS
(Notes 1 and 2)
Total Supply Voltage (V + to V –) ............................... 18V
Input Voltage ........................ (V + + 0.3V) to (V – – 0.3V)
Output Short Circuit Duration .......................... Indefinite
Storage Temperature Range .................. –55°C to 150°C
Operating Temperature Range
LTC1052C/LTC7652C ..........................–40°C to 85°C
LTC1052M (OBSOLETE).....................–55°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
U
W
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CEXTB
TOP VIEW
CEXTB
8
CEXTA
1
14 INT/EXT
1
CEXTA 2
+
7 V /CASE
13 CLK IN
NC (GUARD) 3
–
+
2
– IN
+ IN 3
6
12 CLK OUT
–
+
– IN 4
OUTPUT
+ IN 5
5
4
10 OUTPUT
9 OUTPUT CLAMP
8 CRETURN
NC (GUARD) 6
LTC1052 OUTPUT CLAMP
LTC7652 CRETURN
11 V +
V– 7
V–
N PACKAGE, 14-LEAD CERDIP
TJMAX = 110°C, θJA = 130°C/W
METAL CAN H PACKAGE
J PACKAGE, 14-LEAD CERDIP
OBSOLETE PACKAGE
OBSOLETE PACKAGE
Consider the N8 Package for Alternate Source
Consider the N14 Package for Alternate Source
ORDER PART NUMBER
REPLACES
ICL7652CTV
ICL7652ITV
ICL7650CTV-1
ICL7650ITV-1
ICL7650CTV
ICL7650ITV
ICL7650MTV
LTC7652CH
LTC1052CH
LTC1052MH
ORDER PART NUMBER
LTC1052CN
LTC1052CJ
LTC1052MJ
TOP VIEW
TOP VIEW
CEXTA
– IN
8 CEXTB
1
2
+N 3
V– 4
–
+
REPLACES
ICL7652CPD
ICL7650CPD
ICL7652IJD
ICL7650IJD
ICL7650MJD
7 V+
6 OUTPUT
OUTPUT
5
CLAMP
N8 PACKAGE
8-LEAD PDIP
TJMAX = 110°C, θJA = 150°C/W
J8 PACKAGE, 8-LEAD CERDIP
CEXTB
1
16 INT/EXT
CEXTA
2
15 CLK IN
NC (GUARD)
3
14 CLK OUT
– IN
4
13 V +
+ IN
5
12 OUTPUT
NC (GUARD)
6
11 OUTPUT CLAMP
V–
7
10 CRETURN
NC
8
9
NC
SW PACKAGE
16-LEAD PLASTIC (WIDE) SO
OBSOLETE PACKAGE
TJMAX = 110°C, θJA = 150°C/W
Consider the N8 Package for Alternate Source
ORDER PART NUMBER
REPLACES
ORDER PART NUMBER
REPLACES
LTC1052CN8
LTC1052CJ8
LTC1052MJ8
ICL7650CPA
ICL7650IJA
LTC1052CSW
LTC1052CS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
2
1052fa
LTC1052/LTC7652
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, test circuit TC1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
(Note 3)
∆VOS/∆Temp Average Input Offset Drift
MIN
(Note 3)
●
LTC1052M
TYP
MAX
LTC1052C/LTC7652C
MIN
TYP
MAX
±0.5
±5
±0.5
±5
±0.01
±0.05
±0.01
±0.05
µV
µV/°C
∆VOS/∆Time Long-Term Offset Voltage Stability
100
IOS
±30
±90
±2000
±30
±90
±350
pA
pA
±1
±30
±1000
±1
±30
±175
pA
pA
Input Offset Current
●
IB
Input Bias Current
●
RS = 100Ω, DC to 10HZ, TC3
RS = 100Ω, DC to 1HZ, TC3
100
UNITS
1.5
0.5
nV/√Month
enP-P
Input Noise Voltage
In
Input Noise Current
f = 10Hz (Note 5)
CMRR
Common Mode Rejection Ratio
VCM = V – to 2.7V
●
120
140
120
PSRR
Power Supply Rejection Ratio
VSUPPLY = ±2.375V to ±8V
●
120
150
120
150
dB
AVOL
Large-Signal Voltage Gain
RL = 10k, VOUT = ±4V
●
120
150
120
150
dB
VOUT
Maximum Output Voltage Swing
(Note 4)
RL = 10k
RL = 100k
●
±4.7
±4.85
±4.95
±4.7
±4.85
±4.95
V
V
SR
Slew Rate
RL = 10k, CL = 50pF
GBW
Gain Bandwidth Product
IS
Supply Current
0.6
No Load
RL = 100k
Clamp Off Current
–4V < VOUT < 4V
●
25
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Connecting any terminal to voltages greater than V +, or less than
V –, may cause destructive latch-up. It is recommended that no sources
operating from external supplies be applied prior to power-up of the
LTC1052/LTC7652.
Note 3: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of the voltage levels in high speed automatic
dB
4
V/µs
MHz
2.0
3.0
100
10
●
fA/√Hz
1.2
1.7
330
Clamp On Current
0.6
140
4
1.7
Internal Sampling Frequency
µVP-P
µVP-P
1.2
●
fS
1.5
0.5
25
100
2
2.0
3.0
mA
mA
330
Hz
100
µA
10
100
1
pA
nA
testing. VOS is measured to a limit determined by test equipment
capability. Voltages on CEXTA and CEXTB, AVOL, CMRR and PSRR are
measured to insure proper operation of the nulling loop to ensure meeting
the VOS and VOS drift specifications. See Package-Induced VOS in the
Applications Information section.
Note 4: Output clamp not connected.
Note 5: Current noise is calculated from the formula: in = (2q IB)1/2, where
q = 1.6 • 10 –19 coulomb.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Noise Voltage
VS = ±5V, TEST CIRCUIT (TC3)
5µV
DC TO 1Hz
0
5µV
DC TO 10Hz
0
10 SEC.
1052fa
3
LTC1052/LTC7652
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Offset Voltage vs Sampling
Frequency
1OHzP-P Noise vs Sampling
Frequency
5
12
6
4
2
900
INPUT BIAS CURRENT, IB (pA)
10Hz PEAK-TO-PEAK NOISE (µV)
VOS (µV)
8
1000
VSUPPLY= ± 5V
VSUPPLY= ±5V
10
Input Bias Current vs
Temperature
4
3
2
1
GUARANTEED
800
700
600
500
400
300
200
GUARANTEED
100
0
100
0
0
500
1000
1500
SAMPLING FREQUENCY, fS (Hz)
2000
1k
SAMPLING FREQUENCY, fS (Hz)
0
50
25
0
75 100
–50 –25
AMBIENT TEMPERATURE, TA(°C)
10k
125
LTC1052/7652 • TPC03
LTC1052/7652 • TPC01
LTC1052/7652 • TPC02
Common Mode Input Range vs
Supply Voltage
Aliasing Error
Overload Recovery
(Output Clamp Not Used)
VS = ±5V
6
fI–fS
fS
fI
4
IV/DIV
COMMON MODE RANGE (V)
OUTPUT SPECTRUM (dB)
(3Hz BANDWIDTH)
8
VS = ±5V
AV = –1
TEST CIRCUIT TC2
2
0
–2
VCM = V –
–4
OVERDRIVE
REMOVED
AV = –100
–6
50Hz/DIV
–8
0
1
2
4
5
3
6
SUPPLY VOLTAGE (±V)
7
50ms/DIV
8
LTC1052/7652 • TPC04
Small-Signal Transient Response*
Large-Signal Transient Response*
Gain Phase vs Frequency
60
100
OUTPUT VOLTAGE (2mV/DIV)
AV = 1
2µs/DIV
RL = 10k
CL = 100pF
VS = ±5V
*RESPONSE IS NOT DEPENDENT ON PHASE OF CLOCK
VS = ± 5V
CL= 100pF
100
VOLTAGE GAIN (dB)
80
AV = 1
RL = 10k
CL = 100pF
VS = ±5V
2µs/DIV
80
PHASE
120
60
GAIN
40
140
20
160
0
180
–20
200
–40
100
103
105
104
FREQUENCY (Hz)
106
PHASE SHIFT (DEGREES)
OUTPUT VOLTAGE (20mV/DIV)
120
220
107
LTC1052/LTC7652 • TPC06
1052fa
4
LTC1052/LTC7652
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Broadband Noise, CEXT = 0.1µF
Broadband Noise, CEXT = 1.0µF
Broadband Noise Test Circuit (TC2)
INPUT REFERRED NOISE
(5µV/DIV)
INPUT REFERRED NOISE
(5µV/DIV)
R2
1M
R1
1k
2
R3
1k
3
5V
7
–
6
LTC1052
8
+
4
1
CEXTA
AV = – 1000
1ms/DIV
AV = –1000
1ms/DIV
– 5V
SHORT-CIRCUIT OUTPUT CURRENT, IOUT (mA)
3.0
2.5
SUPPLY CURRENT, IS(mA)
SUPPLY CURRENT, IS(mA)
SUPPLY VOLTAGE = ± 5V
2.0
1.5
1.0
2.0
1.0
0.5
0
0
50
100
–50 –25
25
75
0
AMBIENT TEMPERATURE, TA (°C)
8
10
12
14
16
4 5 6
TOTAL SUPPLY VOLTAGE, V + TO V – (V)
LTC1052/LTC7652 • TPC08
Sampling Frequency vs
Temperature
ISOURCE VOUT = V –
4
2
0
– 10
ISINK VOUT = V +
– 20
– 30
12
16
4 5 6
10
14
8
TOTAL SUPPLY VOLTAGE, V + TO V – (V)
LTC1052/LTC7652 • TPC10
Comparator Operation
SUPPLY VOLTAGE = ± 5V
SAMPLING FREQUENCY, fS (Hz)
TA = 25°C
SAMPLING FREQUENCY, fS (Hz)
6
600
600
500
400
300
200
100
0
125
8
LTC1052/LTC7652 • TPC09
Sampling Frequency vs Voltage
LTC1052/7652 • TPC07
Output Short-Circuit Current vs
Supply Voltage
Supply Current vs Temperature
Supply Current vs Supply Voltage
CEXTB
14
16
8
10
12
4 5 6
TOTAL SUPPLY VOLTAGE, V + TO V – (V)
LTC1052/LTC7652 • TPC11
500
VREF*
1k
2
400
1k
VIN
300
5V
5
–
7
6
LTC1052
3
8
+
4
1
0.1µF
200
100
* – 5V ≤ VREF ≤ 2.7 V
0
50
100
– 50 – 25
25
75
0
AMBIENT TEMPERATURE, TA (°C)
0.1µF
– 5V
LTC1052/7652 • TPC13
125
LT1052/LTC7652 • TPC12
1052fa
5
LTC1052/LTC7652
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Response Time vs Overdrive
VREF + OVERDRIVE
INPUT
{
VREF – 1mV
10µV
OUTPUT
{
5V
50µV
5µV
–5V
20ms/DIV
TEST CIRCUITS
Electrical Characteristics Test Circuit (TC1)
DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3)
C2
C3
R2
1M
R1
1k
R2
V+
2
7
–
6
2
OUTPUT
8
+
RL
4
1
R1
–
3
+
C4
R3
7
LT1001
2
6
LTC1052
OUTPUT
(NOISE x 20,000)
–
34k
8
+
6
4
1
0.1µF
0.1µF
3
V+
LTC1052
3
R4
0.1µF
34k
0.1µF
V–
V–
LTC1052/7652 • TC01
BANDWIDTH
10Hz
1Hz
R1
16.2Ω
16.2Ω
R2
162k
162k
R3
16.2k
162k
R4
16.2k
162k
C2
0.1µF
1.0µF
C3
1.0µF
1.0µF
C4
1.0µF
1.0µF
LTC1052/7652 • TC02
U
THEORY OF OPERATIO
DC OPERATION
The shaded portion of the LTC1052 block diagram
(Figure 1a) entirely determines the amplifier’s DC
characteristics. During the auto zero portion of the cycle,
the gm1 inputs are shorted together and a feedback path is
closed around the input stage to null its offset. Switch S2
and capacitor CEXTA act as a sample-and-hold to store the
nulling voltage during the next step—the sampling cycle.
In the sampling cycle, the zeroed amplifier is used to
amplify the differential input voltage. Switch S2 connects
the amplified input voltage to CEXTB and the output gain
stage. CEXTB and S2 act as a sample-and-hold to store the
amplified input signal during the auto zero cycle.
By switching between these two states at a frequency
much higher than the signal frequency, a continuous
output results.
Notice that during the auto zero cycle the gm1 inputs are
not only shorted together, but are also shorted to the
inverting input. This forces nulling with the common mode
voltage present and accounts for the extremely high
CMRR of the LTC1052. In the same fashion, variations in
1052fa
6
LTC1052/LTC7652
U
THEORY OF OPERATIO
power supply are also nulled. For nulling to take place, the
offset voltage, common mode voltage and power supply
must not change at a frequency which is high compared to
the frequency response of the nulling loop.
For frequencies above this pole, I2 is:
I2 = VIN gm6 • 1 • SC1
SC2
and
C1
I1 – I2 = VIN gm1 – VIN gm6 •
C2
The LTC1052 is very carefully designed so that gm1 = gm6
and C1 = C2. Substituting these values in the above equation shows I1 – I2 = 0.
AC OPERATION AND ALIASING ERRORS
So far, the DC performance of the LTC1052 has been
explained. As the input signal frequency increases, the
problem of aliasing must be addressed. Aliasing is the
spurious formation of low and high frequency signals
caused by the mixing of the input signal with the sampling
frequency, fS. The frequency of the error signals, fE, is:
The gm6 input stage, with Cl and C2, not only filters the
input to the sampling loop, but also acts as a high
frequency path to give the LTC1052 good high frequency
response. The unity-gain cross frequencies for both the
DC path and high frequency path are identical
[f3dB = 1 (gm1/C1) = 1 (gm6/C2)]
2π
2π
thereby making the frequency response smooth and continuous while eliminating sampling noise in the output as
the loop transitions from the high gain DC loop to the high
frequency loop.
fE = fS ±fI
where fI = input signal frequency.
Normally it is the difference frequency (fS – fI ) which is of
concern because the high frequency (fS + fI) can be easily
filtered. As the input frequency approaches the sampling
frequency, the difference frequency approaches zero and
will cause DC errors—the exact problem that the zero-drift
amplifier is meant to eliminate.
The typical curves show just how well the amplifier works.
The output spectrum shows that the difference frequency
(fI –fS = 100Hz) is down by 80dB and the frequency
response curve shows no abnormalities or perturbations.
Also note the well-behaved small and large-signal step
responses and the absence of the sampling frequency in
the output spectrum. If the dynamics of the amplifier
(i.e., slew rate and overshoot), depend on the sampling
clock, the sampling frequency will appear in the output
spectrum.
The solution is simple; filter the input so the sampling loop
never sees any frequency near the sampling frequency.
At a frequency well below the sampling frequency, the
LTC1052 forces I1 to equal I2 (see Figure 1b). This makes
δ l zero, thus the gain of the sampling loop zero at this and
higher frequencies (i.e., a low pass filter). The corner
frequency of this low pass filter is set by the output stage
pole (1/RL4 gm5 RL5 C2).
C1
S3
VREF
C2
+ IN
S1
+
S2
gm1
– IN
–
–
+
–
gm2
RL1
gm4
RL2
VNULL
CEXT B
+
–
+
gm5
RL4
VOUT
RL5
CEXT A
gm3
–
V–
gm6
+
LTC1052/7652 • TPC13
Figure 1a. LTC1052 Block Diagram
Auto Zero Cycle
1052fa
7
LTC1052/LTC7652
U
THEORY OF OPERATIO
C1
S3
VREF
C2
l2
+ IN
S1
+
–
+
–
gm1
– IN
–
l1
S2
δl
gm2
gm4
RL2
RL1
CEXT B
+
–
+
gm5
RL4
VOUT
RL5
CEXT A
gm3
gm6
V–
l3
LTC1052/7652 • TO02
+
Figure 1b. LTC1052 Block Diagram
Sampling Cycle
U
–
W
U U
APPLICATIO S I FOR ATIO
EXTERNAL CAPACITORS
CEXTA and CEXTB are the holding elements of a sampleand-hold circuit. The important capacitor characteristics
are leakage current and dielectric absorption. A high
quality film-type capacitor such as mylar or polypropylene
provides excellent performance. However, low grade
capacitors such as ceramic are suitable in many
applications.
On competitive devices, connecting CEXTA and CEXTB to
V – causes an increase in amplifier noise. Design changes
have eliminated this problem on the LTC1052. On the
14-pin LTC1052 and 8-pin LTC7652, the capacitors can
be returned to V – or CRETURN with no change in noise
performance.
Capacitors with very high dielectric absorption (ceramic)
can take several seconds to settle after power is first
turned on. This settling appears as clock ripple on the
output and, as the capacitor settles, the ripple gradually
disappears. If fast settling after power turn-on is
important, mylar or polypropylene is recommended.
ACHIEVING PICOAMPERE/MICROVOLT PERFORMANCE
Above 85°C, leakage, both from the holding capacitors
and the printed circuit board, becomes important. To
maintain the capabilities of the LTC1052 it may be
necessary to use Teflon™ capacitors and Teflon standoffs
when operating at 125°C (see Achieving Picoampere/
Microvolt Performance).
CEXTA and CEXTB are normally in the range of 0.1µF
to 1.0µF. All specifications are guaranteed with 0.1µF and
the broadband noise (refer to Typical Performance Characteristics) is only very slightly degraded with 0.1µF.
Output clock ripple is not present for capacitors of 0.1µF
or greater at any temperature.
Picoamperes
In order to realize the picoampere level of accuracy of the
LTC1052, proper care must be exercised. Leakage
currents in circuitry external to the amplifier can
significantly degrade performance. High quality insulation
should be used (e.g., Teflon, Kel-F); cleaning of all
insulating surfaces to remove fluxes and other residues
will probably be necessary—particularly for high
temperature performance. Surface coating may be
necessary to provide a moisture barrier in high humidity
environments.
Board leakage can be minimized by encircling the input
connections with a guard ring operated at a potential
close to that of the inputs: in inverting configurations, the
guard ring should be tied to ground; in noninverting
Teflon is a trademark of Dupont.
1052fa
8
LTC1052/LTC7652
U
W
U U
APPLICATIO S I FOR ATIO
connections, to the inverting input. Guarding both sides
of the printed circuit board is required. Bulk leakage
reduction depends on the guard ring width.
Figure 2 is an example of the introduction of an
unnecessary resistor to promote differential thermal
balance. Maintaining compensating junctions in close
physical proximity will keep them at the same temperature
and reduce thermal EMF errors.
NOMINALLY UNNECESSARY
RESISTOR USED TO
THERMALLY BALANCE OTHER
INPUT RESISTOR
LEAD WIRE/SOLDER/COPPER
TRACE JUNCTION
+
OUTPUT
LTC1052
–
RESISTOR LEAD, SOLDER,
COPPER TRACE JUNCTION
Microvolts
Thermocouple effects must be considered if the LTC1052’s
ultralow drift is to be fully utilized. Any connection
of dissimilar metals forms a thermoelectric junction
producing an electric potential which varies with
temperature (Seebeck effect). As temperature sensors,
thermocouples exploit this phenomenon to produce
useful information. In low drift amplifier circuits the effect
is a primary source of error.
When connectors, switches, relays and/or sockets are
necessary they should be selected for low thermal EMF
activity. The same techniques of thermally balancing and
coupling the matching junctions are effective in reducing
the thermal EMF errors of these components.
Connectors, switches, relay contacts, sockets, resistors,
solder, and even copper wire are all candidates for
thermal EMF generation. Junctions of copper wire from
different manufacturers can generate thermal EMFs of
200nV/°C—4 times the maximum drift specification of
the LTC1052. The copper/kovar junction, formed when
wire or printed circuit traces contact a package lead, has
a thermal EMF of approximately 35µV/°C– 700 times the
maximum drift specification of the LTC1052.
Resistors are another source of thermal EMF errors.
Table 1 shows the thermal EMF generated for different
resistors. The temperature gradient across the resistor is
important, not the ambient temperature. There are two
junctions formed at each end of the resistor and if these
junctions are at the same temperature, their thermal EMFs
will cancel each other. The thermal EMF numbers are
approximate and vary with resistor value. High values give
higher thermal EMF.
Minimizing thermal EMF-induced errors is possible if
judicious attention is given to circuit board layout and
component selection. It is good practice to minimize the
number of junctions in the amplifier’s input signal path.
Avoid connectors, sockets, switches and relays where
possible. In instances where this is not possible, attempt
to balance the number and type of junctions so that
differential cancellation occurs. Doing this may involve
deliberately introducing junctions to offset unavoidable
junctions.
LTC1052/7652 • AI03
Figure 2
Table 1. Resistor Thermal EMF
RESISTOR TYPE
THERMAL EMF/°C GRADIENT
Tin Oxide
~mV/’C
Carbon Composition
~450µV/°C
Metal Film
~20µV/°C
Wire Wound
Evenohm
Manganin
~2µV/°C
~2µV/°C
1052fa
9
LTC1052/LTC7652
U
W
U U
APPLICATIO S I FOR ATIO
When all of these errors are considered, it may seem
impossible to take advantage of the extremely low drift
specifications of the LTC1052. To show that this is not the
case, examine the temperature test circuit of Figure 3. The
lead lengths of the resistors connected to the amplifier’s
inputs are identical. The thermal capacity and thermal
resistance each input sees is balanced because of the
symmetrical connection of resistors and their identical
size. Thermal EMF-induced shifts are equal in phase and
amplitude, thus cancellation occurs.
50k
2
5V
7
–
100Ω
+
1
0.1µF
6
LTC1052
3
50k
4
8
Very slight air currents can still affect even this
arrangement. Figure 5 shows strip charts of output noise
both with the circuit covered and with no cover in “still” air.
This data illustrates why it is often prudent to enclose the
LTC1052 and its attendant components inside some form
of thermal baffle.
VOS • 1000
0.1µF
0.1µF
–5V
LTC1052/7652 • AI04
Figure 3. Offset Drift Test Circuit
0 MIN
Figure 4 shows the response of this circuit under
temperature transient conditions. Metal film resistors and
an 8-pin DIP socket were used. Care was taken in the
construction to thermally balance the inputs to the
amplifier. The units were placed in an oven and allowed to
stabilize at 25°C. The recording was started and after
100 seconds the oven, preset to 125°C, was switched on.
The test was first performed on an 8-pin plastic package
and then was repeated for a TO-5 package plugged into the
same test board. It is significant that the change in VOS,
even under these severe thermal transient conditions,
is quite good. As temperature stabilizes, note that the
steady-state change of VOS is well within the maximum
±0.05µV/°C drift specification.
5 MIN
20 MIN
25 MIN
10
OFFSET VOLTAGE, VOS (10µV/DIV)
25°C TO 125°C
PLASTIC
±0.05µV/°C
0
10
25°C TO 125°C
METAL CAN
0
±0.05µV/°C
OVEN SWITCHED
ON (25°C)
OVEN STABILIZED
AT 12 MIN
100 SECONDS/IN
Figure 4. Transient Response of Offset Drift Test Circuit with 100°C Temperature Step
1052fa
10
LTC1052/LTC7652
U
W
U U
APPLICATIO S I FOR ATIO
#1 COVERED
1µV
#1 UNCOVERED
#2 UNCOVERED
20 SEC
Figure 5. DC to 1Hz (Test Circuit TC3)
PACKAGE-INDUCED OFFSET VOLTAGE
CLOCK
Since the LTC1052 is constantly fixing its own offset, it
may be asked why there is any error at all, even under
transient temperature conditions. The answer is simple.
The LTC1052 can only fix offsets inside its own nulling
loop. There are many thermal junctions outside this loop
that cannot be distinguished from legitimate signals.
The LTC1052 has an internal clock, setting the nominal
sampling frequency at 330Hz. On 8-pin devices, there is
no way to control the clock externally. In some applications it may be desirable to control the sampling clock and
this is the function of the 14-pin device.
Some have been discussed previously, but the package
thermal EMF effects are an important source of errors.
Notice the difference in the thermal response curves of
Figure 4. This can only be attributed to the package since
everything else is identical. In fact, the VOS specification is
set by the package-induced warm-up drift, not by the
LTC1052. TO-99 metal cans exhibit the worst warm-up
drift and Linear Technology sample tests TO-99 lots to
minimize this problem.
Two things make 100% screening costly: (1) The extreme
precision required on the LTC1052 and (2) the thermal
time constant of the package is 0.5 to 3 minutes, depending on package type. The first precludes the use of automatic handling equipment and the second takes a long
time. Bench test equipment is available to 100% test for
warmed-up drift if offsets of less than ±5µV are required.
CLK IN, CLK OUT and INT/EXT are provided to accomplish
this. With no external connection, an internal pull-up holds
INT/EXT at the V + supply and the 14-pin device selfoscillates at 330Hz. In this mode there is a signal on the
CLK IN pin of 660Hz (2 times sampling frequency) with a
30% duty cycle. A divide-by-two drives the CLK OUT pin
and sets the sampling frequency.
To use an external clock, connect INT/EXT to V – and the
external clock to CLK IN. The logic threshold of CLK IN is
2.5V below the positive supply; this allows CMOS logic to
drive it directly with logic supplies of V+ and ground. CLK
IN can be driven from V+ to V – if desired. The duty cycle of
the external clock is not particularly critical but should be
kept between 30% and 60%.
Capacitance between CLK IN and CLK OUT (pins 13 and
12) can cause the divide-by-two circuit to malfunction. To
avoid this, keep this capacitance below 5pF.
1052fa
11
LTC1052/LTC7652
U
W
U U
APPLICATIO S I FOR ATIO
OUTPUT CLAMP
If the LTC1052 is driven into saturation, the nulling loop,
attempting to force the differential input voltage to zero,
will drive CEXTA and CEXTB to a supply rail. After the
saturating drive is removed, the capacitors take a finite
time to recover—this is the overload recovery time. The
overload recovery is longest when the capacitors are
driven to the negative rail (refer to Overload Recovery in
the Typical Performance Characteristics section). The
overload recovery time in this case is typically 225ms. In
the opposite direction (i.e., CEXTA and CEXTB at positive
rail), it is about ten times faster (25ms). The overload
recovery time for the LTC1052 is much faster than competitive devices; however, if a faster overload recovery
time is necessary, the output clamp function can be used.
When the output clamp is connected to the negative input
it prevents the amplifier from saturating, thus keeping
CEXTA and CEXTB at their nominal voltages. The output
clamp is a switch that turns on when the output gets to
within approximately 1V of either supply rail. This switch
is in parallel with the amplifier’s feedback resistor. As the
output moves closer to the rail, the switch on
resistance decreases, reducing the closed loop gain. The
output swing is reduced when the clamp function is used.
How much current the output clamp leaks when off
is important because, when used, it is connected to the
amplifier’s negative input. Any current acts like input bias
current and will degrade accuracy. At the other extreme,
the maximum current the clamp conducts when on determines how much overdrive the clamp will take, and still
keep the amplifier from saturating. Both of these numbers
are guaranteed in the Electrical Characteristics section.
LOW SUPPLY OPERATION
The minimum supply voltage for proper operation of the
LTC1052 is typically 4.0V (±2.0V). In single supply
applications, PSRR is guaranteed down to 4.7V (±2.35V).
This assures proper operation down to the minimum TTL
specified voltage of 4.75V.
U
TYPICAL APPLICATIO S
5V Powered Ultraprecision Instrumentation Amplifier
Fast Precision Inverter
5V
5V
4
+ IN
3
8
7
6
LTC1052
2
11
C1
1µF
R1
100
13
6
8pF
1
1N4148
0.1µF
R2
100k
5V
2
0.22µF
5
10k 3
+
2
C3
1µF
1N914
2
5V
7
+
8
4
3
6
LTC1052
–
10k
+
7
LT318A
10k
1
C4
1µF
–
6
OUTPUT
4
–5V
0.1µF
0.1µF
3
– 5V
15
18
1000pF
300pF
43k
0.0047µF
17
10k
14
LTC1043
5V
–
0.1µF
12
– IN
VOUT
8
4
C2
1µF
10k*
10k*
INPUT
7
+
16
≈ – 0.5V
CIRCUITRY WITHIN DASHED LINES MAY BE DELETED IF OUTPUT
DOES NOT HAVE TO SWING ALL THE WAY TO GROUND
DRIFT = 50nV/°C
VOS = 3µV
GAIN = R2 + 1
R1
CMRR = >120dB DC – 20kHz
BANDWIDTH = 10Hz
*1% METAL FILM
FULL POWER BANDWIDTH = 2MHz
SLEW RATE = 40V/µs
SETTLING (10V STEP) = 12µs TO 0.01%
BIAS CURRENT DC = 30pA
OFFSET DRIFT = 50nV/°C
OFFSET VOLTAGE = 5µV
LTC1052/7652 • TA04
LTC1052/7652 • TA03
1052fa
12
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Offset Stabilized Comparator
5V
4
+
5V
14
13
2
12
COMPARATOR
INPUTS
330Ω
8
+
11
7
COMPARATOR
OUTPUT (± 5V)
5
–
1
4
10k
– 5V
–
GROUND OR
INPUT COMMONMODE VOLTAGE
2k
6
LT1011
3
150Ω
8
7
1µF
LTC1043
1M
2
6
5
5V
7
+
6
LTC1052
3
2
8
–
4
1
0.1µF
3
0.1µF
– 5V
5V
15
ZERO COMMAND
5V = ZERO
– 5V = COMPARE
16
STATUS OUTPUT
OV = ZERO
5V = COMPARE
18
17
–5V
LTC1052/7652 • TA05
1HZ to 1.25MHz Voltage-to-Frequency Converter (5V Supply)
470Ω
5V
3
7
+
6
3.3k
Q1
2N2907
LTC1052
2
0.01µF
470Ω
10k
–
4
8
NC
2N3904
1
0.1µF
5V
330pF
0.1µF
74C04
10k
OUTPUT
1H to 1.25MHz
0.01µF
VIN
OV TO 5V
10k
FULL-SCALE TRIM
(1.25MHz)
30.1k*
5V
2k
3.3pF
5V
10k
4
8
7
0.22µF
11
100pF**
LINEARITY
DYNAMIC RANGE
ZERO POINT DRIFT
GAIN DRIFT
0.1µF
12
*TRW MTR–5/ +1200ppm/°C
**POLYSTYRENE–WESCO #32–P/ – 120ppm/°C
± 0.05%
>120dB
0.01Hz/°C
20ppm/°C
LT1004-1.2V
14
13
1/2 LTC1043
16
LTC1052/7652 • TA06
17
1052fa
13
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
No VOS Adjust* CMOS DAC Buffer—Single Supply
Air Flow Detector
15V
CF *
RFB
5
1k
2
lOUT1
12–BIT CMOS DAC
10k
15V
+
7
6
LTC1052
3
lOUT2
–
43k
0.1µF
0.1µF
2
FOR HIGHER SPEED, REFER TO
“FAST PRECISION INVERTER”
UNDER TYPICAL APPLICATIONS
4
1
15V
100k
± 1%
VOUT
8
5V
LT1004-1.2
1k
5
+
43.2Ω
± 1%
–
AMBIENT –
TEMPERATURE
STILL AIR +
10k
5V = NO AIR FLOW
0V = AIR FLOW
4
0.1µF
0.1µF
5
6
8
1
4
6
7
LTC1052
3
–
11
1µF
NON POLARIZED
0.1µF
*OFFSET VOLTAGE CAUSES
NONLINEARITY ERRORS.
SEE: “APPLICATION GUIDE
TO CMOS MULTIPLYING D/A
CONVERTERS,”
ANALOG DEVICES, INC.
12
1pF
+
LTC1052/7652 • TA08
+
1N914
240Ω
TYPE K
≈ – 0.5V
15
15
AIR FLOW
LTC1052/7652 • TA07
16
1/2 LTC1043
17
1Hz to 30MHz Voltage-to-Frequency Converter
5V
120Ω
CURRENT
SOURCE
STABILIZING
AMP
3
0.1µF
120Ω
7
+
7.5k
6
LTC1052
2
12k
2N3906
8
–
1
RESET DIODE
2N3904
0.1µF
0.1µF
100pF
– 5V
IN
OV TO 3V
NC
FET BUFFER
2N5486
4
2k
30MHz
TRIM
16.2k*
50Ω
0.0.1µF
1Hz TO 30MHz
OUTPUT
5V
74S132
OUT
2N5486
10k
0.22µF
5V
TRIGGER
HP5082-2810
50Ω
CHARGE
PUMP
2k
5V
8
– 5V
7
100k
1000M
10k
1Hz TRIM
11
LT1004–1.2V
100pF †
100k
0.22µF
12
10
– 5V
*TRW MTR-5/ + 120ppm/°C
†WESCO #32-P/ – 120ppm/°C
14
13
1/2 LTC1043
16
5V
14
5V
5
11
7490
10 11 12
14 5
1/2 74S74
3
0.3Hz/°C ZERO-DRIFT
±0.08% LINEARITY
20ppm/°C GAIN DRIFT
150dB DYNAMIC RANGE
7
LTC1052/7652 • TA09
1052fa
14
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
±100mA Output Drive
VIN
Increasing Output Current
5V
100k
220pF
5V
2
7
–
1M
VOUT
LTC1010
8
+
4
2
INPUT
– 5V
7
–
3
RL
OUTPUT
6
LTC1052
±100mA
1
0.1µF
5V
10k
6
LTC1052
3
74C04
5V
100pF
8
+
4
1
0.1µF
0.1µF
0.1µF
– 5V
100k
VOS = 5µV
VOS/∆T = 50µV/°C
GAIN = 10
FULL POWER BANDWIDTH = 1kHz
LOAD
5k
2.5k
1k
220Ω
10k
LTC1052/7652 • TA10
100Ω
OUTPUT SWING
± 4.92V
± 4.84V
± 4.65V
± 3.65V
2000pF
LTC1052/7652 • TA11
Single 5V Thermocouple Amplifier with Cold Junction Compensation
5V
VT +
–
100k
LT1004-1.2
1690Ω
1k
R1
5V
5k AT 25°C†
5V
4
7
187Ω
3
8
7
–
2
11
( )
6
LTC1052
1820Ω
R
VOUT = VT 1 + F
Rl
8
+
4
1
1µF
1µF
0.1µF
0.1µF
RF
CF*
12
13
14
6
5
43k
5V
Rl
2
+
IN914
1µF
NONPOLARIZED
1µF
3
18
15
≈ – 0.5V
10k
LTC1052/7652 • TA12
16
0.0047µF
LTC1043
17
† YELLOW SPRINGS INST. CO. PART #44007
*CHOOSE CF TO FILTER NOISE
THERMOCOUPLE
TYPE
J
K
T
S
R1
232k
301k
301k
2.1M
1052fa
15
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Increasing Output Current and Voltage (VSUPPLY = ±15V)
DC Stabilized FET Probe
INPUT CAPACITANCE BOOTSTRAP
5V
7V
2N3904
15V
0.1µF
3k
INPUT
2
LT318A
4
2
1
0.1µF
7
+
8
+
33pF
–
4
0.1µF
2N3904
– 7V
6
10M
OUTPUT
±12V AT 20mA | LIMIT
DRAIN CURRENT SINK
10k
Q2
2N2222
0.01µF
100Ω
3k
–15V
6
0.1µF
– 5V
NC
V+
7
– 5V
1k
0.1µF
OUTPUT
LT1010
3
6
LTC1052
3
30k
NC
7
–
FAST SOURCE
FOLLOWER
Q1
2N5486
5V
1N4148
INPUT
10M
+
3
0.1µF
LTC1052
8
4
–
2
1
0.1µF
2000pF
DC STABILIZATION
STABLE FOR ALL GAINS, INVERTING
AND NONINVERTING, OBSERVE
LTC1052 COMMON MODE INPUT LIMITS
LTC1052/7652 • TA13
BANDWIDTH: 20MHz
†RISE: 100ns
DELAY: 5ns
LTC1052/7652 • TA14
1k
0.1µF
Precision Multiplexed Differential Thermocouple Amplifier
5V
COLD JUNCTION
COMPENSATOR
100k
4
R1
LT1004–1.2V
–
7
6
LTC1052
5k AT
25°C†
2
11
1690Ω
VOUT = 1001 • VTHERMOCOUPLE
8
+
4
1
1µF
1820Ω
187Ω
3
8
7
1µF
0.1µF
0.1µF
0.1µF
12
– 5V
13
14
6
5
1M
5V
16
12
13
1
3
1k
2
1µF
1µF
3
† YELLOW SPRINGS INST. CO. PART #44007
14
18
5
15
LTC1043
16
15
0.0047µF
17
2
THERMOCOUPLE
TYPE
J
K
T
S
R1
232k
301k
301k
2.1M
– 5V
11
9
4
10
ADDRESS
8
7
CD4052B
– 5V
LTC1052/7652 • TA15
1052fa
16
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Direct Thermocouple-to-Frequency Converter
RT
–
TYPE K
THERMOCOUPLE 41.4µV/°C
+
STABILIZING AMP
3
+
2
A
33k
6
4
10k
B
C
E
D
0.68µF
1
0.1µF
OPTIONAL INPUT
FILTER-AND-OVERLOAD
CLAMP
470Ω
74C04
8
–
1µF
1N4148
1.8k*
5V
7
LTC1052
1N914
100k
COLD JUNCTION TEMPERATURE TRACKING
0.1µF
820pF
– 5V
3300pF
150k**
5V
50k
60°C TRIM
74C04
5V
OUTPUT
0Hz TO 600Hz
0°C TO 60°C
F
5V
16
33k**
A†
– 5V
LTC1043
3k
74C903
4.75k*
5
6
1µF
0.1µF
1k*
*0.01% FILM-TRW MAR-6
**TRW/MTR/5/ + 120
RT = YELLOW SPRINGS INST. #44007
100pF = POLYSTYRENE
†
FOR GENERAL PURPOSE (1mV FULL-SCALE)
10-BIT A-TO-D, REMOVE THERMOCOUPLE—
COLD JUNCTION NETWORK, GROUND POINT A,
AND DRIVE LTC1052 POSITIVE INPUT
LT1004–1.2V
2
100pF
COLD JUNCTION BIAS
487Ω*
301k*
187Ω*
LTC1052/7652 • TA16
Direct 10-Bit Strain Gauge Digitizer
5V
74C00
5V
1000pF
20Ω
3
1
+
LM301A
2
STRAIN GAUGE
TRANSDUCER
ZIN = 350Ω
ZOUT = 350Ω
20Ω
8 6
1k
7
2N2905
1000pF
2
– 5V
5V
14 1
6
1/2 LTC1043
2
+
7
4
5
1N4148
1/2 74C903
FREQUENCY
OUT A
6
– 5V
OUTPUT
GATING
0.01µF
0.01µF
– 5V
OUT A = 1000 COUNTS FULL-SCALE
OUT B
*0.1% METAL FILM TRW MAR-5
SW1 = MAIN CURRENT SWITCH
SW2 = CURRENT LOADING COMPENSATION SWITCH
DATA OUTPUT =
1N4148
11
16
– 5V
5V
– 5V
8
SW1
FREQUENCY
OUT B
10k
4 3
1/2 74C74
8
1
3.3MΩ*
7
5V
LTC1052
3
BRIDGE DRIVE
0.003µF
INTEGRATOR
5V
7
–
470k*
5V
14k
CLOCK
4
–
– 5V
28k
3.3M
12
CONNECT DIRECTLY
ACROSS BRIDGE
DRIVE POINTS
SW2
13
14
100k
10k
CONNECT TO BRIDGE
END OF 470k RESISTOR
(OPTIONAL)
TRANSDUCER ZERO NETWORK
22.3k*
+
1k*
LTC1052/7652 • TA17
33µF
1052fa
17
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
16-Bit A/D Converter
74C00
28k
0.01µF
EIN
OV TO 5V
95k*
10k
FULL-SCALE
TRIM
2
–
5V
820pF
14k
CLOCK
BOUT
10k
5V
5V
7
1/3 74C903
14 1
4 2
6 2
1/2 74C74
A2
8 INTEGRATOR 7 5 6
10pF
LTC1052
3
+
4
5V
AOUT
1
– 5V
0.1µF
0.1µF
5V
5V
– 5V
7
6
2N4338
1k
+
4
16
3
14
13
LTC1052
8
4
–
2
12
1
0.1µF
0.1µF
1µF
LT1009
0.01µF
39pF
11
– 5V
20k
75k*
LINEARITY
TRIM
CURRENT SINK
7
8
18
15
– 5V
3
A
DATA OUTPUT = OUT
BOUT
100,000 COUNTS FULL-SCALE
NO ZERO TRIM
20ppm/°C GAIN DRIFT
*VISHAY S-102 RESISTOR
LTC1043
17
– 5V
CURRENT SWITCH
LTC1052/7652 • TA18
1052fa
18
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Precision Isolation Amplifier
1k*
INPUT SIDE OUTPUT SIDE
74C04
10k
10k
20k
ZERO TRIM
4
–
4
100k*
– 15V
1
2N5434
15V
30pF
2N5434
22M
LTC1052
14–PIN
10
5
2
7
5
INPUT
100k
2N5434
14
0.1µF
13
2N5434
6
0.1µF
11
12
74C90
÷10
10 1
1k GAIN TRIM
IN4148
100pF
12
2k
2k
68pF
330Ω
10M
(SELECT)
10k*
1.8k
2N3904
1k
– 15V
25mA
7
+
+
–
OUT
74C04
1N4148 1N4148
15V
25mA
4
13.3k*
10k
14
15V
2N3904
6
7 – 15V
15V
3
5
14 11
74C90
÷10
10 1
NC
8
10k
5
FLOATING
SUPPLY
OUTPUTS
1
+
LTC1052
1000pF
11
NC
3
2
1
+
100k
2
L2
STANCOR PCT-39
1
2.2µF
74C04
2N2222
11k
1N4148
L1
DALE TC–10–11
8
POWER
DRIVER
2.2µF
1000pF
15V
2
4.3k
– 15V
20k
20k
FLOATING COMMON
2N2222
9
250V ISOLATION
0.03% ACCURACY
*1% FILM RESISTOR
68pF
3
1.8k
1k
LTC1052/7652 • TA19
15V
1052fa
19
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
H Package
8-Lead TO-5 Metal Can (.200 Inch PCD)
(Reference LTC DWG # 05-08-1320)
.335 – .370
(8.509 – 9.398)
DIA
.305 – .335
(7.747 – 8.509)
.040
(1.016)
MAX
.050
(1.270)
MAX
SEATING
PLANE
.165 – .185
(4.191 – 4.699)
GAUGE
PLANE
.010 – .045*
(0.254 – 1.143)
REFERENCE
PLANE
.500 – .750
(12.700 – 19.050)
.016 – .021**
(0.406 – 0.533)
.027 – .045
(0.686 – 1.143)
PIN 1
45°TYP
.028 – .034
(0.711 – 0.864)
.200
(5.080)
TYP
.110 – .160
(2.794 – 4.064)
INSULATING
STANDOFF
*LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND THE SEATING PLANE
.016 – .024
**FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS
(0.406 – 0.610) H8(TO-5) 0.200 PCD 0801
OBSOLETE PACKAGE
1052fa
20
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
J Package
14-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.005
(0.127)
MIN
.785
(19.939)
MAX
14
13
12
11
10
9
8
.220 – .310
(5.588 – 7.874)
.025
(0.635)
RAD TYP
1
2
3
4
5
6
7
.300 BSC
(7.62 BSC)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.008 – .018
(0.203 – 0.457)
0° – 15°
.045 – .065
(1.143 – 1.651)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.014 – .026
(0.360 – 0.660)
.100
(2.54)
BSC
.125
(3.175)
MIN
J14 0801
OBSOLETE PACKAGE
1052fa
21
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
CORNER LEADS OPTION
(4 PLCS)
.405
(10.287)
MAX
.005
(0.127)
MIN
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
8
6
7
5
.025
(0.635)
RAD TYP
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.220 – .310
(5.588 – 7.874)
1
2
3
4
.300 BSC
(7.62 BSC)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.008 – .018
(0.203 – 0.457)
0° – 15°
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.045 – .065
(1.143 – 1.651)
.014 – .026
(0.360 – 0.660)
.125
3.175
MIN
.100
(2.54)
BSC
J8 0801
OBSOLETE PACKAGE
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
+.035
.325 –.015
(
8.255
+0.889
–0.381
)
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.065
(1.651)
TYP
.100
(2.54)
BSC
.120
(3.048) .020
MIN (0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
N8 1002
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1052fa
22
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
N Package
14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.770*
(19.558)
MAX
14
13
12
11
10
9
8
1
2
3
4
5
6
7
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
+.035
.325 –.015
(
+0.889
8.255
–0.381
NOTE:
1. DIMENSIONS ARE
)
.120
(3.048)
MIN
.005
(0.125) .100
MIN (2.54)
BSC
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.018 ± .003
(0.457 ± 0.076)
N14 1002
1052fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.398 – .413
(10.109 – 10.490)
NOTE 4
16
N
15
14
13
12
11 10
9
N
.325 ±.005
.420
MIN
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
1
.005
(0.127)
RAD MIN
.009 – .013
(0.229 – 0.330)
.291 – .299
(7.391 – 7.595)
NOTE 4
.010 – .029 × 45°
(0.254 – 0.737)
2
3
4
5
6
.093 – .104
(2.362 – 2.642)
7
8
.037 – .045
(0.940 – 1.143)
0° – 8° TYP
.050
(1.270)
BSC
NOTE 3
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
.004 – .012
(0.102 – 0.305)
.014 – .019
(0.356 – 0.482)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S16 (WIDE) 0502
1052fa
24
Linear Technology Corporation
LW/TP 1202 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 1985