Genesys Logic, Inc. GL811S USB 2.0 to ATA/ATAPI Bridge Controller Product Overview GL811S Product Overview Copyright Copyright © 2012 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Ownership and Title Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder. Disclaimer All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice. Genesys Logic, Inc. 12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231, New Taipei City, Taiwan Tel : (886-2) 8913-1888 Fax : (886-2) 6629-6168 http://www.genesyslogic.com ©2012 Genesys Logic, Inc. - All rights reserved. Page 2 GL811S Product Overview GENERAL DESCRIPTION The GL811S is a highly-compatible, low cost USB 2.0 to ATA / ATAPI bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and ATA / ATAPI-6 specification rev 1.0, the GL811S can support various kinds of ATA / ATAPI device. There are totally 4 endpoints in the GL811S controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL811S can support not only plug and play but also Windows XP/ 2000/ ME default driver. The GL811S uses 12MHz crystal and slew-rate controlled pads to reduce the EMI issue. With 48-pin LQFP (7mmX7mm) package, the GL811S is the best cost/ performance solution to fit different situations in the USB 2.0 high speed storage class applications such as Hard Disk, CD-ROM, CD-R / RW and DVD-ROM. ©2012 Genesys Logic, Inc. - All rights reserved. Page 3 GL811S Product Overview FEATURES · Complies with Universal Serial Bus specification rev. 2.0. · Complies with ATA/ATAPI-6 specification rev 1.0. · Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) · Operating system supported: Win XP / 2000 / Me / 98 / 98SE; Mac OS 9.X / 10.X. · Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE). · Support 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3). · 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint. · Support 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33 / 66). · Embedded Turbo 8051. · ROM size: 12k words; RAM size: 1280 bytes. (Bulk Buffer: 512 words, MC RAM: 256 bytes) · Supports Power Down mode and USB suspend indicator. · Supports USB 2.0 TEST mode features. · Supports 4 GPIOs for programmable AP (48 pin package). · Supports 8 GPIOs for programmable AP (64 pin package). · Supports device power control for power on/off when running suspend mode. · Supports 32 bit and 48 bit LBA hard disk. · Provides LED indicator for Full Speed and High Speed (only for 64 pin package). · Using 12 MHz external clock to provide better EMI. · 3.3V I/Os (5V tolerant) 5V tolerance pad for IDE interface. · Operates at 5V voltage (built-in 5V to 3.3V & 3.3V to 1.8V regulator) · Supports Wakeup ability. · Available in 48-pin/64-pin LQFP package types. · Provides SPI interface (only for 64 pin package). · Provides UART interface (only for 64 pin package). ©2012 Genesys Logic, Inc. - All rights reserved. Page 4 GL811S Product Overview BLOCK DIAGRAM GPIO Operation Register 8051 Core 2K ROM IDE Device IDE Interface Bulk FIFO SIE SPI Interface UTM SPI Device USB ©2012 Genesys Logic, Inc. - All rights reserved. EP0, EP3 FIFO Page 5