ON MT9J003I12STCV2-DP Cmos digital image sensor Datasheet

MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Features
1/2.3-Inch 10 Mp CMOS Digital Image Sensor
MT9J003 Datasheet, Rev. E
For the latest datasheet, please visit www.onsemi.com
Features
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Table 1:
1080p digital video mode
Simple two-wire serial interface
Auto black level calibration
Support for external mechanical shutter
Support for external LED or xenon flash
High frame rate preview mode with arbitrary downsize scaling from maximum resolution
Programmable controls: gain, horizontal and vertical
blanking, auto black level offset correction, frame
size/rate, exposure, left–right and top–bottom image
reversal, window size, and panning
Data interfaces: parallel or four-lane serial high-speed
pixel interface (HiSPi) differential signaling (subLVDS)
On-die phase-locked loop (PLL) oscillator
Bayer pattern downsize scaler
Integrated position-based color and lens shading
correction
One-time programmable memory (OTPM) for storing
module information
Key Performance Parameters
Parameter
Value
Optical format
1/2.3-inch (4:3)
6.440 mm (H) x 4.616 mm (V), 7.923 mm
diagonal (Entire sensor)
6.119 mm (H) x 4.589 mm (V), 7.649 mm
diagonal (Still mode)
6.413 mm (H) x 3.607 mm (V), 7.358 mm
diagonal (Video mode)
3856H x 2764V (Entire sensor)
3664H x 2748V (4:3, Still mode)
3840H x 2160V (16:9, Video mode)
1.67 x 1.67 m
0°, 13.4°
RGB Bayer pattern
Electronic rolling shutter (ERS) with
global reset release (GRR)
6–48 MHz
80 Mp/s at 80 MHz PIXCLK
Active imager size
Active pixels
Pixel size
Chief ray angle
Color filter array
Shutter type
Input clock frequency
Parallel
Maximum
data
HiSPi (4-lane)
rate
Still mode, 4:3
(3664H x 2748V)
Preview mode
Frame VGA
rate
1080p mode
(1920H x 1080V)
ADC resolution
Responsivity
Dynamic range
SNRMAX
Applications
• Digital video cameras
• Digital still cameras
General Description
The ON Semiconductor MT9J003 is a 1/2.3-inch CMOS
active-pixel digital imaging sensor with an active pixel
array of 3856H x 2764V including border pixels. It can
support 10 megapixel (3664H x 2748V) digital still
images and a 1080p (3840H x 2160V) digital video
mode. It incorporates sophisticated on-chip camera
functions such as windowing, mirroring, column and
row skip modes, and snapshot mode. It is programmable through a simple two-wire serial interface and has
very low power consumption.
I/O Digital
Supply Digital
voltage Analog
SLVS I/O
Still mode at 15
Power fps w/ serial I/F
Still mode at 7.5
Consump- fps w/ parallel I/F
tion
Preview
Standby
Package
Operating temperature
MT9J003-DS Rev. E 5/15 EN
1
2.8 Gbps
Programmable up to 15 fps serial I/F,
7.5 fps parallel I/F
30 fps with binning
60 fps with skip2bin2
60 fps using HiSPi I/F
30 fps using parallel I/F
12-bit, on-die
0.31 V/lux-sec (550nm)
65.2 dB
34 dB
1.7–1.9 V (1.8 V nominal)
or 2.4–3.1 V (2.8 V nominal)
1.7–1.9 V (1.8 V nominal)
2.4–3.1 V (2.8 V nominal)
0.4 - 0.8 V (0.4 or 0.8 V nominal)
638mW
388mW
250mW low power VGA
500W (typical, EXTCLK disabled)
48-pin iLCC (10mm x 10mm) Bare die,
48pin Tiny PLCC (12mm x 12mm)
–30°C to +70°C (at junction)
©Semiconductor Components Industries, LLC,2015
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Ordering Information
Ordering Information
Table 2:
Available Part Numbers
Part Number
Orderable Product Attribute Description
Product Description
MT9J003D00STMUC2CBC1-200
10 MP 1" CIS
Die Sales, 200m Thickness
MT9J003I12STCU-DP
10 MP 1/2.3" CIS
Dry Pack with Protective Film
MT9J003I12STCU-DR
10 MP 1/2.3" CIS
Dry Pack without Protective Film
MT9J003I12STCV2-DP
10 MP 1/2.3" CIS
Dry Pack with Protective Film
MT9J003I12STCV2-TP
10 MP 1/2.3" CIS
Tape & Reel with Protective Film
MT9J003I12STMU-DP
10 MP 1/2.3" CIS
Dry Pack with Protective Film
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Programming Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Control of the Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Sensor Readout Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Sensor Core Digital Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
List of Figures
List of Figures
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Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Typical Configuration: Serial Four-Lane HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Configuration: Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
HiSPi Package Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
48-Pin iLCC Parallel Package Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
HiSPi Transmitter and Receiver Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Diagram of DLL Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Delaying the clock_lane with Respect to data_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Delaying data_lane with Respect to the clock_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Steaming vs. Packetized Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Pixel Data Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Row Timing and FV/LV Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Single READ From Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Single READ From Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Sequential READ, Start From Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Sequential READ, Start From Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Effect of Limiter on the Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Timing of Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MT9J003 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Sequence for Programming the MT9J003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Effect of Horizontal Mirror on Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Effect of Vertical Flip on Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Pixel Array Readout Without Subsampling and With 2x2 Skipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Combinations of Pixel Skipping in the MT9J003 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Pixel Binning and Summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Pixel Skipping Combined with Summing or Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Xenon Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
LED Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
LED Flash Enabled Following Forced Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Overview of Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Entering and Leaving a Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Controlling the Reset and Integration Phases of the Global Reset Sequence . . . . . . . . . . . . . . . . . . . .53
Control of the Electromechanical Shutter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Controlling the SHUTTER Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Using FLASH With Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Global Reset Bulb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Entering Soft Standby During a Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Test Cursor Behavior With Image Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Hard Standby and Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Soft Standby and Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Two-WIre Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
HiSPi Eye Diagram for Both Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
HiSPi Skew Between Data Signals Within the PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
48-Pin iLCC Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
48-Pin tPLCC Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
List of Tables
List of Tables
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Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Row Timing with HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Row Timing with Parallel Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Row Timing with Parallel Interface Using Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Register Settings for Common Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Definitions for Programming Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Output Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Configuration of the Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
RESET_BAR and PLL in System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Signal State During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Streaming/STANDBY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Trigger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Subsampling Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Minimum Row Time and Blanking Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Minimum Frame Time and Blanking Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Fine_Integration_Time Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Fine_Correction Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Recommended Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
HiSPi Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
CRA (13.4°) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
DC Electrical Definitions and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Parallel Interface Configured to Use Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Two-Wire Serial Register Interface Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Two-Wire Serial Register Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
I/O Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
HiSPi Rise and Fall Times at 480 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
HiSPi Rise and Fall Times at 360 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Channel, PHY and intra-PHY Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Clock DLL Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Data DLL Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
48-Pin tPLCC Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
General Description
General Description
The MT9J003 digital image sensor features ON Semiconductor’s breakthrough low-noise
CMOS imaging technology that achieves near-CCD image quality (based on signal-tonoise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS.
When operated in its default 4:3 still-mode, the sensor generates a full resolution image
at 15 frames per second (fps) using the HiSPi serial interface. An on-chip analog-todigital converter (ADC) generates a 12-bit value for each pixel.
Functional Overview
The MT9J003 is a progressive-scan sensor that generates a stream of pixel data at a
constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal
clocks from a single master input clock running between 6 and 48 MHz. The maximum
output pixel rate is 80 Mp/s, corresponding to a pixel clock rate of 80 MHz. A block
diagram of the sensor is shown in Figure 1.
Figure 1:
Block Diagram
Active-Pixel
Sensor (APS)
Array
Analog Processing
Sync
Signals
Timing Control
Shading
Correction
ADC
Scaler
Control Registers
Limiter
FIFO
Data
Out
Two-wire
Serial
Interface
The core of the sensor is a 10Mp active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then reading each row in turn. In
the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between
reset and readout. Once a row has been read, the data from the columns is sequenced
through an analog signal chain (providing offset correction and gain), and then through
an ADC. The output from the ADC is a 12-bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain (which provides further data
path corrections and applies digital gain).
The pixel array contains optically active and light-shielded (“dark”) pixels. The dark
pixels are used to provide data for on-chip offset-correction algorithms (“black level”
control).
The sensor contains a set of control and status registers that can be used to control many
aspects of the sensor behavior including the frame size, exposure, and gain setting.
These registers can be accessed through a two-wire serial interface.
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Functional Overview
The output from the sensor is a Bayer pattern; alternate rows are a sequence of either
green and red pixels or blue and green pixels. The offset and gain stages of the analog
signal chain provide per-color control of the pixel data.
The control registers, timing and control, and digital processing functions shown in
Figure 1 on page 6 are partitioned into three logical parts:
• A sensor core that provides array control and data path corrections. The output of the
sensor core is a 12-bit parallel pixel data stream qualified by an output data clock
(PIXCLK), together with LINE_VALID (LV) and FRAME_VALID (FV) signals or a 4-lane
serial high-speed pixel interface (HiSPi).
• A digital shading correction block to compensate for color/brightness shading introduced by the lens or chief ray angle (CRA) curve mismatch.
• Additional functionality is provided. This includes a horizontal and vertical image
scaler, a limiter, a data compressor, an output FIFO, and a serializer.
The output FIFO is present to prevent data bursts by keeping the data rate continuous.
Programmable slew rates are also available to reduce the effect of electromagnetic interference from the output interface.
A flash output signal is provided to allow an external xenon or LED light source to
synchronize with the sensor exposure time. Additional I/O signals support the provision
of an external mechanical shutter.
Pixel Array
The sensor core uses a Bayer color pattern, as shown in Figure 2. The even-numbered
rows contain green and red pixels; odd-numbered rows contain blue and green pixels.
Even-numbered columns contain green and blue pixels; odd-numbered columns
contain red and green pixels.
Figure 2:
Pixel Color Pattern Detail (Top Right Corner)
Column Readout Direction
..
.
Row
Readout
Direction
...
Black Pixels
First clear
active pixel
(110, 52)
Gr R Gr R Gr
B Gb B Gb B
Gr R Gr R Gr
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Operating Modes
Operating Modes
By default, the MT9J003 powers up with the serial pixel data interface enabled. The
sensor can operate in serial HiSPi or parallel mode.
For low-noise operation, the MT9J003 requires separate power supplies for analog and
digital power. Incoming digital and analog ground conductors should be placed in such
a way that coupling between the two are minimized. Both power supply rails should also
be routed in such a way that noise coupling between the two supplies and ground is
minimized.
Caution
Typical Configuration: Serial Four-Lane HiSPi Interface
HiSPi
PHY I/O
power1
Master clock
(6–48 MHz)
VDD
VDD_SLVS
VDD_IO
1.5kΩ2, 3
1.5kΩ2
Digital Digital
Core
I/O
power1 power1
EXTCLK
VDD_SLVS_TX
Figure 3:
ON Semiconductor does not recommend the use of inductance filters on the power supplies
or output signals.
PLL
Analog Analog
power1 power1 power1
VDD_PLL
VAA
VAA_PIX
SLVS_0P
SLVS_0N
SLVS_1P
SLVS_1N
SLVS_2P
SLVS_2N
SLVS_3P
SDATA
SCLK
From
controller
SLVS_3N
SLVSC_P
SLVSC_N
GPI[3:0]4
RESET_BAR
SHUTTER
FLASH
TEST
GND_PLL
VDD_IO
VDD
VDD_SLVS_TX
VDD_PLL
VAA
DGND
MT9J003-DS Rev. E 5/15 EN
PIXGND
AGND
VAA_PIX
Digital
ground
Notes:
To
controlle
Analog
ground
1. All power supplies should be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire
speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. The GPI pins can be statically pulled HIGH or LOW to be used as module IDs, or they can be programmed to perform special functions (TRIGGER, OE_N, SADDR, STANDBY) to be dynamically controlled.
8
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Operating Modes
5. VPP, which can be used during the module manufacturing process, is not shown in Figure 3. This
pad is left unconnected during normal operation.
6. The parallel interface output pads can be left unconnected if the serial output interface is used.
7. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check the MT9J003 demo headboard schematics for circuit recommendations
8. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized.
9. The signal path between the HiSPi serial transmitter and receiver should be adequately designed to
minimize any trans-impedance mismatch and/or reflections on the data path.
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Operating Modes
Figure 4:
Typical Configuration: Parallel Pixel Data Interface
VDD_IO
1.5kΩ2, 3
1.5kΩ2
Digital Digital
core
I/O
power1 power1
Master clock
(6–48 MHz)
VDD
Analog Analog
PLL
power1 power1 power1
VDD_TX0
VDD_PLL
VAA_PIX
DOUT [11:0]
EXTCLK
PIXCLK
LINE_VALID
FRAME_VALID
SDATA
SCLK
From
Controller
VAA
SHUTTER
RESET_BAR
FLASH
GPI[3:0]4
TEST
VDD_IO
VDD
VDD_PLL
VAA
GND_PLL DGND
MT9J003-DS Rev. E 5/15 EN
PIX GND
AGND
VAA_PIX
Digital
ground
Notes:
To
controller
Analog
ground
1. All power supplies should be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire
speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. The GPI pins can be statically pulled HIGH or LOW to be used as module IDs, or they can be programmed to perform special functions (TRIGGER, OE_N, SADDR, STANDBY) to be dynamically controlled.
5. VPP, which can be used during the module manufacturing process, is not shown in Figure 4. This
pad is left unconnected during normal operation.
6. The serial interface output pads can be left unconnected if the parallel output interface is used.
7. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check the MT9J003 demo headboard schematics for circuit recommendations.
8. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized.
9. ON Semiconductor recommends that VDD_TX0 is tied to VDD when the sensor is using the parallel
interface.
10
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Signal Descriptions
Signal Descriptions
Table 1 provides signal descriptions for MT9J003 die. For pad location and aperture
information, refer to the MT9J003 die data sheet.
Table 1:
Signal Descriptions
Pad Name
Pad Type
Description
EXTCLK
Input
Master clock input, 6–48 MHz.
RESET_BAR
(XSHUTDOWN)
Input
Asynchronous active LOW reset. When asserted, data output stops and all internal registers are
restored to their factory default settings.
SCLK
Input
Serial clock for access to control and status registers.
Input
General purpose inputs. After reset, these pads are powered-down by default; this means that it is
not necessary to bond to these pads. Any of these pads can be configured to provide hardware
control of the standby, output enable, SADDR select, and shutter trigger functions.
Can be left floating if not used.
Input
Enable manufacturing test modes. It should not be left floating. It can be tied to ground or VDD_IO
when used in parallel or HiSPi. It should be connected to DGND for normal operation of the CCP2
configured sensor, or connected to VDD_IO power for the MIPI®-configured sensor.
GPI[3:0]
TEST
SDATA
I/O
Serial data from READs and WRITEs to control and status registers.
LINE_VALID
Output
LINE_VALID (LV) output. Qualified by PIXCLK.
FRAME_VALID
Output
FRAME_VALID (FV) output. Qualified by PIXCLK.
DOUT[11:0]
Output
Parallel pixel data output. Qualified by PIXCLK.
PIXCLK
Output
Pixel clock. Used to qualify the LV, FV, and DOUT[11:0] outputs.
FLASH
Output
Flash output. Synchronization pulse for external light source. Can be left floating if not used.
SHUTTER
Output
Control for external mechanical shutter. Can be left floating if not used.
Supply
Power supply used to program one-time programmable (OTP) memory. Disconnect pad when not
programming or when feature is not used.
Supply
PHY power supply. Digital power supply for the MIPI or CCP2 serial data interface. ON
Semiconductor recommends that VDD_TX0 is always tied to VDD when using an unpackaged
sensor.
VPP
VDD_TX0
VDD_SLVS
Supply
HiSPi power supply for data and clock output. This should be tied to VDD
VDD_SLVS_TX
Supply
Digital power supply for the HiSPi I/O.
VAA
Supply
Analog power supply.
VAA_PIX
Supply
Analog power supply for the pixel array.
AGND
Supply
Analog ground.
VDD
Supply
Digital power supply.
VDD_IO
Supply
I/O power supply.
DGND
Supply
Common ground for digital and I/O.
VDD_PLL
Supply
PLL power supply.
GND_PLL
Supply
PLL ground.
PIXGND
Supply
Pixel ground.
SLVS_0P
Output
Lane 1 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
SLVS_0N
Output
Lane 1 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
SLVS_1P
Output
Lane 2 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
SLVS_1N
Output
Lane 2 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
SLVS_2P
Output
Lane 3 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
SLVS_2N
Output
Lane 3 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Signal Descriptions
Table 1:
Signal Descriptions (continued)
Pad Name
Pad Type
Description
SLVS_3P
Output
Lane 4 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
SLVS_3N
Output
Lane 4 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
SLVS_CP
Output
Differential HiSPi (LVDS) serial clock (positive). Qualified by the SLVS serial clock.
SLVS_CN
Output
Differential HiSPi (LVDS) serial clock (positive). Qualified by the SLVS serial clock.
MT9J003-DS Rev. E 5/15 EN
1
GND
SLVSC_N
2
SLVS3_P
SLVS1_P
3
SLVS3_N
SLVS1_N
4
SLVS2_P
SLVS0_P
5
SLVS2_N
SLVS0_N
6
SLVSC_P
VDD_SLVS_TX
HiSPi Package Pinout Diagram
48
47
46
45
44
43
10
NC
EXTCLK
11
38
VAA
VDD
12
37
PIXGND
GND
13
36
VAA_PIX
VDD_IO
14
35
VAA_PIX
SDATA
15
34
NC
SCLK
16
33
NC
TEST
17
32
VAA
RESET_BAR
18
31
AGND
19
20
21
22
23
24
25
26
27
12
28
29
30
VPP
VDD
GND
NC
39
VDD_PLL
40
FLASH
9
SHUTTER
GND
GPI3
VAA
GPI2
41
GPI1
AGND
8
GPI0
42
VDD_IO
VDD_IO
7
GND
VDD_SLVS
VDD
Figure 5:
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Signal Descriptions
MT9J003-DS Rev. E 5/15 EN
GND
EXTCLK
VDD_PLL
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
GND
NC
48-Pin iLCC Parallel Package Pinout Diagram
6
5
4
3
2
1
48
47
46
45
44
43
10
39
AGND
DOUT11
11
38
VAA_PIX
VDD_IO
12
37
VAA_PIX
PIXCLK
13
36
VAA
VDD
14
35
AGND
SCLK
15
34
VAA
SDATA
16
33
VPP
RESET_BAR
17
32
NC
VDD_IO
18
31
NC
19
20
21
22
23
24
25
13
26
27
28
29
30
GND
DOUT10
LINE_VALID
VAA
FRAME_VALID
40
FLASH
9
SHUTTER
DOUT9
TEST
PIXGND
GND
41
GPI3
NC
8
GPI2
42
DOUT8
GPI1
7
GPI0
DOUT7
VDD
Figure 6:
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Output Data Format
Output Data Format
Serial Pixel Data Interface
The MT9J003 supports RAW8, RAW10, and RAW12 image data formats over a serial interface. The sensor supports a 1 and 2-lane MIPI as well as the HiSPi interface. These interfaces are not described in the data sheet.
High Speed Serial Pixel Interface
The High Speed Serial Pixel (HiSPi) interface uses four data and one clock low voltage
differential signaling (LVDS) outputs.
• SLVS_CP, SLVS_CN
• SLVS_[0:3]P, SLVS_[0:3]N
The HiSPi interface supports two protocols, streaming and packetized. The streaming
protocol conforms to a standard video application where each line of active or
intra-frame blanking provided by the sensor is transmitted at the same length. The packetized protocol will transmit only the active data ignoring line-to-line and
frame-to-frame blanking data.
The HiSPi interface building block is a unidirectional differential serial interface with
four data and one double data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple lanes. Figure 7 shows the
configuration between the HiSPi transmitter and the receiver.
Figure 7:
HiSPi Transmitter and Receiver Interface Block Diagram
A camera containing
the HiSPi transmitter
Tx
PHY0
MT9J003-DS Rev. E 5/15 EN
A host (DSP) containing
the HiSPi receiver
Dp0
Dp0
Dn0
Dn0
Dp1
Dp1
Dn1
Dn1
Dp2
Dp2
Dn2
Dn2
Dp3
Dp3
Dn3
Dn3
Cp0
Cp0
Cn0
Cn0
14
Rx
PHY0
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Output Data Format
HiSPi Physical Layer
The HiSPi physical layer is partitioned into blocks of four data lanes and an associated
clock lane. Any reference to the PHY in the remainder of this document is referring to
this minimum building block.
The PHY will serialize a 10-, 12-, 14- or 16-bit data word and transmit each bit of data
centered on a rising edge of the clock, the second on the following edge of clock. Figure 8
shows bit transmission. In this example, the word is transmitted in order of MSB to LSB.
The receiver latches data at the rising and falling edge of the clock.
Figure 8:
Timing Diagram
TxPost
cp
….
cn
TxPre
dp
….
MSB
dn
LSB
1 UI
DLL Timing Adjustment
The specification includes a DLL to compensate for differences in group delay for each
data lane. The DLL is connected to the clock lane and each data lane, which acts as a
control master for the output delay buffers. Once the DLL has gained phase lock, each
lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user
to increase the setup or hold time at the receiver circuits and can be used to compensate
for skew introduced in PCB design.
If the DLL timing adjustment is not required, the data and clock lane delay settings
should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation.
data _lane 0
delay
delay
del3[2:0]
del2[2:0]
del1[2:0]
delay
MT9J003-DS Rev. E 5/15 EN
delclock[2:0]
Block Diagram of DLL Timing Adjustment
del0[2:0]
Figure 9:
delay
delay
data _lane 1 clock _lane 0 data _lane 2 data _lane 3
15
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Output Data Format
Figure 10:
Delaying the clock_lane with Respect to data_lane
1 UI
dataN (de lN = 000)
cp (delclock = 000)
cp (delclock = 001)
cp (delclock = 010)
cp (de lclock = 011)
cp (delclock = 100)
cp (delcloc k = 101)
c p (delclock = 110)
cp (delclock =111)
increasing delclock_[2:0] increases clock delay
Figure 11:
Delaying data_lane with Respect to the clock_lane
cp (delclock = 000)
dataN (delN = 000)
dataN(delN = 001)
dataNdelN = 010)
dataN(delN = 011)
dataN(delN = 100)
dataN(delN = 101)
dataN(delN = 110)
dataN(delN = 111)
increasing delN_[2:0] increases data delay
t
DLLSTEP
1 UI
HiSPi Streaming Mode Protocol Layer
The protocol layer is positioned between the output data path of the sensor and the
physical layer. The main functions of the protocol layer are generating sync codes,
formatting pixel data, inserting horizontal/vertical blanking codes, and distributing
pixel data over defined data lanes.
The HiSPi interface can only be configured when the sensor is in standby. This includes
configuring the interface to transmit across 1, 2, or all 4 data lanes.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Output Data Format
Protocol Fundamentals
Referring to Figure 12, it can be seen that a SYNC code is inserted in the serial data
stream prior to each line of image data. The streaming protocol will insert a SYNC code
to transmit each active data line and vertical blanking lines.
The packetized protocol will transmit a SYNC code to note the start and end of each row.
The packetized protocol uses sync a “Start of Frame” (SOF) sync code at the start of a
frame and a “Start of Line” (SOL) sync code at the start of a line within the frame. The
protocol will also transmit an “End of Frame” (EOF) at the end of a frame and an “End of
Line” (EOL) sync code at the end of a row within the frame
Figure 12:
Steaming vs. Packetized Transmission
Parallel Pixel Data Interface
MT9J003 image data is read out in a progressive scan. Valid image data is surrounded by
horizontal blanking and vertical blanking, as shown in Figure 13. The amount of horizontal blanking and vertical blanking is programmable; LV is HIGH during the shaded
region of the figure. FV timing is described in the “Output Data Timing (Parallel Pixel
Data Interface)”.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Output Data Format
Figure 13:
Spatial Illustration of Image Readout
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
VERTICAL/HORIZONTAL
BLANKING
VERTICAL BLANKING
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
HORIZONTAL
BLANKING
VALID IMAGE
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n
Pm,0 Pm,1.....................................Pm,n-1 Pm,n
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00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Output Data Format
Output Data Timing (Parallel Pixel Data Interface)
MT9J003 output data is synchronized with the PIXCLK output. When LV is HIGH, one
pixel value is output on the 12-bit DOUT output every PIXCLK period. The pixel clock
frequency can be determined based on the sensor's master input clock and internal PLL
configuration. The rising edges on the PIXCLK signal occurs one-half of a pixel clock
period after transitions on LV, FV, and DOUT (see Figure 14). This allows PIXCLK to be
used as a clock to sample the data. PIXCLK is continuously enabled, even during the
blanking period. The MT9J003 can be programmed to delay the PIXCLK edge relative to
the DOUT transitions. This can be achieved by programming the corresponding bits in
the row_speed register. The parameters P, A, and Q in Figure 15 are defined in Table 2 on
page 19.
Figure 14:
Pixel Data Timing Example
LV
PIXCLK
P0 [11:0]
DOUT[11:0]
P1 [11:0]
P2 [11:0]
Blanking
Figure 15:
P3 [11:0]
P4 [11:0]
P5 Pn-2 Pn-1 [11:0]
Valid Image Data
Pn [11:0]
Blanking
Row Timing and FV/LV Signals
FV
LV
Number of
P
master clocks
A
Q
A
Q
A
P
The sensor timing (shown in Table 2 on page 19) is shown in terms of pixel clock and
master clock cycles (see Figure 14 on page 19). The default settings for the on-chip PLL
generate
a pixel array clock (vt_pix_clk) of 160 MHz and an output clock (op_pix_clk) of 40 MHz
given a 20 MHz input clock to the MT9J003. Equations for calculating the frame rate are
given in “Frame Rate Control” on page 47.
Table 2:
Row Timing with HiSPi Interface
Parameter
Name
PIXCLK_PERIOD Pixel clock period
MT9J003-DS Rev. E 5/15 EN
Equation
Default Timing
1/vt_pix_clk_freq_mhz
19
1 pixel clock
= 6.25ns
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Output Data Format
Table 2:
Row Timing with HiSPi Interface (continued)
Parameter
Name
S
For x_odd_inc = y_odd_inc = 3, S = 2.
For x_odd_inc = y_odd_inc = 7, S = 4.
otherwise, S = 1
For y_odd_inc = 3, S = 2
Skip (subsampling) factor
For y_odd_inc = 7, S = 4
For y_odd_inc = 15, S = 8
For y_odd_inc = 31, S = 16
For y_odd_inc = 63, S = 32
A
Active data time
P
Frame start/end blanking 6 * PIXCLK_PERIOD
Q
Horizontal blanking
(line_length_pck – A) * PIXCLK_PERIOD
= 3694 – 1832
1862 pixel clocks
= 11.63s
A+Q
Row time
line_length_pck * PIXCLK_PERIOD
3694 pixel clocks
= 23.09s
N
Number of rows
(y_addr_end - y_addr_start + y_odd_inc) / S = (2755 - 8 + 1)/1 2748 rows
V
Vertical blanking
((frame_length_lines - N) * (A + Q)) + Q – (2 * P)
= (2891 - 2748) *3694 + 1862 - 12
530092 pixel clocks
= 3.31ms
T
Frame valid time
(N * (A + Q)) - Q + (2 * P)
= 2748*3694 - 1862 + 12
10149262 pixel clocks
= 63.42ms
F
Total frame time
line_length_pck * frame_length_lines * PIXCLK_PERIOD
= 2891 *3694
10679354 pixel clocks
= 66.75ms
Table 3:
Equation
Default Timing
1
(x_addr_end – x_addr_start + x_odd_inc)*0.5
*PIXCLK_PERIOD/S = 3775 - 112 + 12
1832 pixel clocks
= 11.45s
6 pixel clocks
= 37.5ns
Row Timing with Parallel Interface
Parameter
Name
Equation
PIXCLK_PERIOD
Pixel clock period
1/vt_pix_clk_freq_mhz
1 pixel clock
= 6.25ns
S
Skip (subsampling) factor
For x_odd_inc = y_odd_inc = 3, S = 2.
For x_odd_inc = y_odd_inc = 7, S = 4.
otherwise, S = 1
For y_odd_inc = 3, S = 2
For y_odd_inc = 7, S = 4
For y_odd_inc = 15, S = 8
For y_odd_inc = 31, S = 16
For y_odd_inc = 63, S = 32
1
A
Active data time
(x_addr_end - x_addr_start +
x_odd_inc)*0.5*PIXCLK_PERIOD/S
= (3775-112+1)/2
1832 pixel clocks
= 11.45s
P
Frame start/end blanking
6 * PIXCLK_PERIOD
6 pixel clocks
= 75ns
Q
Array Horizontal blanking
(line_length_pck – A) * PIXCLK_PERIOD
= 7358 – 1832
5526 pixel clocks
= 34.5s
External horizontal blanking is 30
pixel clocks or 187ns.
A+Q
Row time limited by
output interface speed
x_output_size*clk_pixel/clk_op + 30
= 3664*160MHz/80MHz + 30
7358 pixel clocks
= 46.1s
N
Number of rows
(y_addr_end - y_addr_start + y_odd_inc) / S
2748 rows
= (2755 - 8 + 1)/1
MT9J003-DS Rev. E 5/15 EN
Default Timing
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Output Data Format
Table 3:
Row Timing with Parallel Interface (continued)
Parameter
Name
Equation
V
Vertical blanking
((frame_length_lines - N) * (A + Q)) + Q – (2 *
1054044 pixel clocks
P)
= 6.59ms
= (2891 - 2748)*7358 + 1862 - 12
T
Frame valid time
(N * (A + Q)) - Q + (2 * P)
= 2748*7358 - 1862 + 12
20217934 pixel clocks
= 126.36ms
F
Total frame time
line_length_pck * frame_length_lines *
PIXCLK_PERIOD
= 2891*37358
21271978pixel clocks
= 132.95ms
Table 4:
Default Timing
Row Timing with Parallel Interface Using Low Power Mode
Parameter
Name
Equation
Default Timing
Pixel clock period
1/vt_pix_clk_freq_mhz
1 pixel clock
= 12.5ns
S
Skip (subsampling) factor
For x_odd_inc = y_odd_inc = 3, S = 2.
For x_odd_inc = y_odd_inc = 7, S = 4.
otherwise, S = 1
For y_odd_inc = 3, S = 2
For y_odd_inc = 7, S = 4
For y_odd_inc = 15, S = 8
For y_odd_inc = 31, S = 16
For y_odd_inc = 63, S = 32
1
A
Active data time
(x_addr_end - x_addr_start +
x_odd_inc)*0.5*PIXCLK_PERIOD/S
= (3775-112+1)/2
1832 pixel clocks
= 22.9s
P
Frame start/end blanking
6 * PIXCLK_PERIOD
6 pixel clocks
= 75ns
Q
Array Horizontal blanking
(line_length_pck – A) * PIXCLK_PERIOD
= 3694 – 1832
1862 pixel clocks
= 23.2s
External horizontal blanking is 30
pixel clocks or 375ns.
A+Q
Row time limited by
output interface speed
x_output_size*clk_pixel/clk_op + 30
= 3664*80MHz/80MHz + 30
3694 pixel clocks
= 46.1s
N
Number of rows
(y_addr_end - y_addr_start + y_odd_inc) / S
2748 rows
= (2755 - 8 + 1)/1
V
Vertical blanking=
((frame_length_lines - N) * (A + Q)) + Q – (2 *
530092 pixel clocks
P)
= 6.63ms
= (2891 - 2748)*7358 + 1862 - 12
T
Frame valid time
(N * (A + Q)) - Q + (2 * P)
= 2748*3694 - 1862 + 12
10149262 pixel clocks
= 126.86ms
F
Total frame time
line_length_pck * frame_length_lines *
PIXCLK_PERIOD
= 2891*3694
10679354 pixel clocks
= 133.5ms
PIXCLK_PERIOD
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Output Data Format
Frame Rates at Common Resolutions
Table 5 shows examples of register settings to achieve common resolutions and their
frame rates.
Table 5:
Register Settings for Common Resolutions
Frame
Rate
Subsampling
Mode
x_addr_start
x_addr_end
y_addr_start
y_addr_end
HiSPi
Parallel
HiSPi
Parallel
HiSPi and
Parallel
HiSPi and
Parallel
14.7 fps
7.5 fps
59.94 fps
29.97 fps
59.94 fps
N/A
112
3775
8
2755
2x2 Summing
32
3873
296
2453
2x2 Summing
32
3873
296
2453
59.94 fps
2x2 Summing
624
3437
304
1885
HiSPi and
Parallel
29.97 fps
Sum2Skip2
112
3769
8
2753
Resolution
Interface
3664x2748
(Full Resolution)
1920x1080
(1080p HDTV)
1280x720
(720p HDTV)
1408x792 + 10% EIS
(720p HDTV + 10%
EIS)
640x480
(Low Power
Monitor)
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Two-Wire Serial Register Interface
The two-wire serial interface bus enables read/write access to control and status registers within the MT9J003. The interface protocol uses a master/slave model in which a
master controls one or more slave devices. The sensor acts as a slave device. The master
generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal
(SDATA). SDATA is pulled up to VDD off-chip by a 1.5k resistor. Either the slave or master
device can drive SDATA LOW—the interface protocol determines which device is allowed
to drive SDATA at any given time.
The protocols described in the two-wire serial interface specification allow the slave
device to drive SCLKLOW; the MT9J003 uses SCLK as an input only and therefore never
drives it LOW.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements:
1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no-) acknowledge bit
4. a message byte
5. a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with
a start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The
default slave addresses used by the MT9J003 for the MIPI configured sensor are 0x6C
(write address) and 0x6D (read address) in accordance with the MIPI specification. Alternate slave addresses of 0x6E(write address) and 0x6F(read address) can be selected by
enabling and asserting the SADDR signal through the GPI pad. But for the CCP2 configured sensor, the default slave addresses used are 0x20 (write address) and 0x21 (read
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
address) in accordance with the SMIA specification. Also, alternate slave addresses of
0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting
the SADDR signal through the GPI pad.
An alternate slave address can also be programmed through R0x31FC.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver does not drive SDATA LOW
during the SCLK clock period following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Typical Sequence
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave
device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
the WRITE should take place. This transfer takes place as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master then transfers the data as an 8-bit sequence; the slave sends an
acknowledge bit at the end of the sequence. The master stops writing by generating a
(re)start or stop condition.
If the request was a READ, the master sends the 8-bit write slave address/data direction
byte and 16-bit register address, the same way as with a WRITE request. The master then
generates a (re)start condition and the 8-bit read slave address/data direction byte, and
clocks out the register data, eight bits at a time. The master generates an acknowledge
bit after each 8-bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master
sends a no-acknowledge bit.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Single READ From Random Location
This sequence (Figure 16) starts with a dummy WRITE to the 16-bit address that is to be
used for the READ. The master terminates the WRITE by generating a restart condition.
The master then sends the 8-bit read slave address/data direction byte and clocks out
one byte of register data. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. Figure 16 shows how the internal register address
maintained by the MT9J003 is loaded and incremented as the sequence proceeds.
Figure 16:
Single READ From Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
A
Reg Address, M
Reg Address[7:0]
A Sr
Slave Address
M+1
1 A
Read Data
A P
slave to master
master to slave
Single READ From Current Location
This sequence (Figure 17) performs a read using the current value of the MT9J003
internal register address. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ
sequences.
Figure 17:
Single READ From Current Location
Previous Reg Address, N
S
MT9J003-DS Rev. E 5/15 EN
Slave Address
1 A
Reg Address, N+1
Read Data
A P
S
25
Slave Address
1 A
N+2
Read Data
A P
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Sequential READ, Start From Random Location
This sequence (Figure 18) starts in the same way as the single READ from random location (Figure 16). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 18:
Sequential READ, Start From Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
A
M+2
Read Data
A
Reg Address, M
Reg Address[7:0]
Slave Address
M+L-2
M+3
Read Data
A Sr
Read Data
M+L-1
Read Data
A
1 A
M+1
A
A
M+L
Read Data
A P
Sequential READ, Start From Current Location
This sequence (Figure 19) starts in the same way as the single READ from current location (Figure 17 on page 25). Instead of generating a no-acknowledge bit after the first
byte of data has been transferred, the master generates an acknowledge bit and
continues to perform byte READs until “L” bytes have been read.
Figure 19:
Sequential READ, Start From Current Location
Previous Reg Address, N
S
Slave Address
1 A
N+1
Read Data
A
N+2
Read Data
A
Read Data
N+L-1
A
Read Data
N+L
A P
Single WRITE to Random Location
This sequence (Figure 20) begins with the master generating a start condition. The slave
address/data direction byte signals a WRITE and is followed by the HIGH then LOW
bytes of the register address that is to be written. The master follows this with the byte of
write data. The WRITE is terminated by the master generating a stop condition.
Figure 20:
Single WRITE to Random Location
Previous Reg Address, N
S
MT9J003-DS Rev. E 5/15 EN
Slave Address
0 A Reg Address[15:8]
A
Reg Address, M
Reg Address[7:0]
26
A
Write Data
M+1
A P
A
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Sequential WRITE, Start at Random Location
This sequence (Figure 21) starts in the same way as the single WRITE to random location
(Figure 20 on page 26). Instead of generating a no-acknowledge bit after the first byte of
data has been transferred, the master generates an acknowledge bit and continues to
perform byte WRITEs until “L” bytes have been written. The WRITE is terminated by the
master generating a stop condition.
Figure 21:
Sequential WRITE, Start at Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8] A
M+1
Write Data
MT9J003-DS Rev. E 5/15 EN
M+2
A
Write Data
Reg Address, M
Reg Address[7:0]
M+3
A
Write Data
M+L-2
Write Data
A
27
M+1
A
M+L-1
A
Write Data
M+L
A
P
A
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Programming Restrictions
Programming Restrictions
The following sections list programming rules that must be adhered to for correct operation of the MT9J003.
Table 1:
Definitions for Programming Rules
Name
Definition
xskip
yskip
xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3; xskip = 4 if x_odd_inc = 7
yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3; yskip = 4 if y_odd_inc = 7;
yskip = 8 if y_odd_inc = 15; yskip = 16 if y_odd_inc = 31; yskip = 32 if y_odd_inc = 63
X Address Restrictions
The minimum column address available for the sensor is 24. The maximum value is
3879.
Effect of Scaler on Legal Range of Output Sizes
When the scaler is enabled, it is necessary to adjust the values of x_output_size and
y_output_size to match the image size generated by the scaler. The MT9J003 will operate
incorrectly if the x_output_size and y_output_size are significantly larger than the
output image. To understand the reason for this, consider the situation where the sensor
is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the
number of pixels in each direction). This situation is shown in Figure 1.
Figure 1:
Effect of Limiter on the Data Path
Core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1
LINE_VALID
PIXEL_VALID
Scaler output: scaled to half size
LINE_VALID
PIXEL_VALID
Limiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1
LINE_VALID
PIXEL_VALID
In Figure 1, three different stages in the data path (see “Timing Specifications” on
page 61) are shown. The first stage is the output of the sensor core. The core is running at
full resolution and x_output_size is set to match the active array size. The LV signal is
asserted once per row and remains asserted for N pixel times. The PIXEL_VALID signal
toggles with the same timing as LV, indicating that all pixels in the row are valid.
The second stage is the output of the scaler, when the scaler is set to reduce the image
size by one-half in each dimension. The effect of the scaler is to combine groups of
pixels. Therefore, the row time remains the same, but only half the pixels out of the
scaler are valid. This is signaled by transitions in PIXEL_VALID. Overall, PIXEL_VALID is
asserted for (N/2) pixel times per row.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Programming Restrictions
The third stage is the output of the limiter when the x_output_size is still set to match the
active array size. Because the scaler has reduced the amount of valid pixel data without
reducing the row time, the limiter attempts to pad the row with (N/2) additional pixels. If
this has the effect of extending LV across the whole of the horizontal blanking time, the
MT9J003 will cease to generate output frames.
A correct configuration is shown in Figure 2, in addition to showing the x_output_size
reduced to match the output size of the scaler. In this configuration, the output of the
limiter does not extend LV.
Figure 2 also shows the effect of the output FIFO, which forms the final stage in the data
path. The output FIFO merges the intermittent pixel data back into a contiguous stream.
Although not shown in this example, the output FIFO is also capable of operating with
an output clock that is at a different frequency from its input clock.
Figure 2:
Timing of Data Path
Core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1
LINE_VALID
PIXEL_VALID
Scaler output: scaled to half size
LINE_VALID
PIXEL_VALID
Limiter output: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2
LINE_VALID
PIXEL_VALID
Output FIFO: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2
LINE_VALID
PIXEL_VALID
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Programming Restrictions
Output Data Timing
The output FIFO acts as a boundary between two clock domains. Data is written to the
FIFO in the VT (video timing) clock domain. Data is read out of the FIFO in the OP
(output) clock domain.
When the scaler is disabled, the data rate in the VT clock domain is constant and
uniform during the active period of each pixel array row readout. When the scaler is
enabled, the data rate in the VT clock domain becomes intermittent, corresponding to
the data reduction performed by the scaler.
A key constraint when configuring the clock for the output FIFO is that the frame rate
out of the FIFO must exactly match the frame rate into the FIFO. When the scaler is
disabled, this constraint can be met by imposing the rule that the row time on the serial
data stream must be greater than or equal to the row time at the pixel array. The row time
on the serial data stream is calculated from the x_output_size and the data_format (8, 10,
or 12 bits per pixel), and must include the time taken in the serial data stream for start of
frame/row, end of row/frame and checksum symbols.
Caution
If this constraint is not met, the FIFO will either underrun or overrun. FIFO underrun or overrun is a fatal error condition that is signalled through the data path_status register
(R0x306A).
Changing Registers While Streaming
The following registers should only be reprogrammed while the sensor is in software
standby:
• vt_pix_clk_div
• vt_sys_clk_div
• pre_pll_clk_div
• pll_multiplier
• op_pix_clk_div
• op_sys_clk_div
Programming Restrictions When Using Global Reset
Interactions between the registers that control the global reset imposes some programming restrictions on the way in which they are used; these are discussed in "Global
Reset" on page 52.
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Control of the Signal Interface
Control of the Signal Interface
This section describes the operation of the signal interface in all functional modes.
Serial Register Interface
The serial register interface uses these signals:
• SCLK
• SDATA
• SADDR (through the GPI pad)
SCLK is an input-only signal and must always be driven to a valid logic level for correct
operation; if the driving device can place this signal in High-Z, an external pull-up
resistor should be connected on this signal.
SDATA is a bidirectional signal. An external pull-up resistor should be connected on this
signal.
SADDR is a signal, which can be optionally enabled and controlled by a GPI pad, to select
an alternate slave address. These slave addresses can also be programmed through
R0x31FC.
This interface is described in detail in "Two-Wire Serial Register Interface" on page 23.
Parallel Pixel Data Interface
The parallel pixel data interface uses these output-only signals:
• FV
• LV
• PIXCLK
• DOUT[11:0]
The parallel pixel data interface is disabled by default at power up and after reset. It can
be enabled by programming R0x301A. Table 3 on page 32 shows the recommended
settings.
When the parallel pixel data interface is in use, the serial data output signals can be left
unconnected. Set reset_register[12] to disable the serializer while in parallel output
mode.
Output Enable Control
When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High-Z under pin or register control, as shown in Table 2.
Selection of a pin to use for the OE_N function is described in "General Purpose Inputs"
on page 35.
Table 2:
Output Enable Control
MT9J003-DS Rev. E 5/15 EN
OE_N Pin
Drive Signals R0x301A–B[6]
Description
Disabled
Disabled
1
X
0
0
1
0
1
X
Interface High-Z
Interface driven
Interface High-Z
Interface driven
Interface driven
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Control of the Signal Interface
Configuration of the Pixel Data Interface
Fields in R0x301A are used to configure the operation of the pixel data interface. The
supported combinations are shown in Table 3.
Table 3:
Configuration of the Pixel Data Interface
Serializer
Disable
R0x301
A–B[12]
Parallel
Enable
R0x301A–B[7]
Standby
End-of-Frame
R0x301A–B[4]
0
0
1
Power up default.
Serial pixel data interface and its clocks are enabled. Transitions to soft
standby are synchronized to the end of frames on the serial pixel data
interface.
1
1
0
Parallel pixel data interface, sensor core data output. Serial pixel data
interface and its clocks disabled to save power. Transitions to soft standby
are synchronized to the end of the current row readout on the parallel pixel
data interface.
1
1
1
Parallel pixel data interface, sensor core data output. Serial pixel data
interface and its clocks disabled to save power. Transitions to soft standby
are synchronized to the end of frames in the parallel pixel data interface.
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Control of the Signal Interface
System States
The system states of the MT9J003 are represented as a state diagram in Figure 3 and
described in subsequent sections. The effect of RESET_BAR on the system state and the
configuration of the PLL in the different states are shown in Table 4 on page 34.
The sensor’s operation is broken down into three separate states: hardware standby,
software standby, and streaming. The transition between these states might take a
certain amount of clock cycles as outlined in Table 4.
Figure 3:
MT9J003 System States
Power supplies turned off
(asychronous from any state)
Powered Off
Powered On
POR =1
POR active
(only if POR is
on sensor)
POR = 0
RESET_BAR = 0
RESET _BAR transitions 1 -> 0
(asynchronous from any state )
Hardware
Standby
2400 EXTCLK
Cycles
RESET_BAR = 1
Software reset initiated
(synchronous from any state)
Internal
Initialization
Two-wire Serial
Interface Write
software_reset = 1
Initialization Timeout
Software
Standby
Two-wire Serial
Interface Write
mode_select = 1
PLL not locked
PLL Lock
Frame in
progress
PLL locked
Wait for Frame
End
Streaming
Two-wire Serial
Interface Write
mode_select = 0
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Control of the Signal Interface
Table 4:
RESET_BAR and PLL in System States
State
EXTCLKs
PLL
Powered off
POR active
Hardware standby
Internal initialization
Software standby
PLL Lock
Streaming
Wait for frame end
x
x
0
VCO powered down
1
Note:
VCO powering up and locking, PLL output bypassed
VCO running, PLL output active
VCO = voltage-controlled oscillator.
Power-On Reset Sequence
When power is applied to the MT9J003, it enters a low-power hardware standby state.
Exit from this state is controlled by the later of two events:
1. The negation of the RESET_BAR input.
2. A timeout of the internal power-on reset circuit.
It is possible to hold RESET_BAR permanently de-asserted and rely upon the internal
power-on reset circuit.
When RESET_BAR is asserted it asynchronously resets the sensor, truncating any frame
that is in progress.
When the sensor leaves the hardware standby state it performs an internal initialization
sequence that takes 2400 EXTCLK cycles. After this, it enters a low-power software
standby state. While the initialization sequence is in progress, the MT9J003 will not
respond to READ transactions on its two-wire serial interface. Therefore, a method to
determine when the initialization sequence has completed is to poll a sensor register; for
example, R0x0000. While the initialization sequence is in progress, the sensor will not
respond to its device address and READs from the sensor will result in a NACK on the
two-wire serial interface bus. When the sequence has completed, READs will return the
operational value for the register (0x2800 if R0x0000 is read).
When the sensor leaves software standby mode and enables the VCO, an internal delay
will keep the PLL disconnected for up to 1ms so that the PLL can lock. The VCO lock time
is 200µs(typical), 1ms (maximum).
Soft Reset Sequence
The MT9J003 can be reset under software control by writing “1” to software_reset
(R0x0103). A software reset asynchronously resets the sensor, truncating any frame that
is in progress. The sensor starts the internal initialization sequence, while the PLL and
analog blocks are turned off. At this point, the behavior is exactly the same as for the
power-on reset sequence.
Signal State During Reset
Table 5 on page 35 shows the state of the signal interface during hardware standby
(RESET_BAR asserted) and the default state during software standby. After exit from
hardware standby and before any registers within the sensor have been changed from
their default power-up values.
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Control of the Signal Interface
Table 5:
Signal State During Reset
Pad Name
Pad Type
EXTCLK
RESET_BAR
(XSHUTDOWN)
GPI[3:0]
Hardware Standby
Software Standby
Enabled. Must be driven to a valid logic level.
Input
Powered down. Can be left disconnected/floating.
TEST
Enabled. Must be driven to a logic 0 for a serial CCP2-configured sensor,
or 1 for a serial MIPI-configured sensor.
SCLK
Enabled. Must be pulled up or driven to a valid logic level.
SDATA
I/O
LINE_VALID
FRAME_VALID
DOUT[11:0]
PIXCLK
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
CLK_P
CLK_N
FLASH
SHUTTER
Enabled as an input. Must be pulled up or driven to a valid logic level.
High-Z. Can be left disconnected or floating.
Output
High-Z.
Logic 0.
General Purpose Inputs
The MT9J003 provides four general purpose inputs. After reset, the input pads associated with these signals are powered down by default, allowing the pads to be left disconnected/floating.
The general purpose inputs are enabled by setting reset_register[8] (R0x301A). Once
enabled, all four inputs must be driven to valid logic levels by external signals. The state
of the general purpose inputs can be read through gpi_status[3:0] (R0x3026).
In addition, each of the following functions can be associated with none, one, or more of
the general purpose inputs so that the function can be directly controlled by a hardware
input:
• Output enable (see “Output Enable Control” on page 31)
• Trigger (see the sections below)
• Standby functions
• SADDR selection (see “Serial Register Interface” on page 31)
The gpi_status register is used to associate a function with a general purpose input.
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Control of the Signal Interface
Streaming/Standby Control
The MT9J003 can be switched between its soft standby and streaming states under pin
or register control, as shown in Table 6. Selection of a pin to use for the STANDBY function is described in “General Purpose Inputs” on page 35. The state diagram for transitions between soft standby and streaming states is shown in Figure 3 on page 33.
Table 6:
Streaming/STANDBY
STANDBY
Streaming R0x301A–B[2]
Description
Disabled
Disabled
X
0
1
0
1
0
1
X
Soft standby
Streaming
Soft standby
Streaming
Soft standby
Trigger Control
When the global reset feature is in use, the trigger for the sequence can be initiated
either under pin or register control, as shown in Table 7. Selection of a pin to use for the
TRIGGER function is described in “General Purpose Inputs” on page 35.
Table 7:
Trigger Control
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Trigger
Global Trigger R0x3160–1[0]
Description
Disabled
Disabled
0
X
1
0
1
0
1
X
Idle
Trigger
Idle
Trigger
Trigger
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Control of the Signal Interface
PLL
The sensor contains a PLL for timing generation and control. The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler
output, and a set of dividers to generate the output clocks. The clocking structure is
shown in Figure 4.
Figure 4:
Clocking Structure
row _ speed
vt_pix_clk_div
3 (2, 3, 4, 5, 6,7, 8)
PLL output clock
clk _ pixel
PLL input clock
pll_ip_clk_freq
vt pix
PLL internal VCO
frequency
Divider
vt_pix_clk
clk
Divider
vt sys clk
Pre PLL
EXTCLK
clk_pixel
Divider
1(1, 2, 4, 6, 8)
External input clock
ext_clk_freq_mhz
[ 2: 0]
1 (1 , 2, 4)
vt_sys_clk
Divider
PLL
Multiplier
(m)
op_sys_clk
op sys clk
Divider
pre _ pll _ clk _ div
clk
1(1, 2, 4, 6, 8)
(m )
(n)
2 ( 1 - 64 )
op_pix_clk
op pix
pll _ multiplier
Divider
64 ( 32 - 128 )
clk_op
clk _ op
Divider
op _ pix _clk
12 (8, 10, 12)
_div
row _ speed
[10 :8 ]
1 (1 , 2 , 4 )
Figure 4 shows the different clocks and the register names. It also shows the default
setting for each divider/multiplier control register, and the range of legal values for each
divider/multiplier control register. The vt and op sys clk Divider is hardwired in the
design. The PLL default settings support the HiSPi interface.
From the diagram, the clock frequencies can be calculated for the HiSPi interface using a
15 MHz input clock as follows:
Internal pixel clock used to readout the pixel array:
ext_clk_freq_mhz x pll_multiplier
15 MHz x 64
clk_pixel_freq_mhz = ------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 160 MHz
pre_pll_clk_div x vt_pix_clk_div x row_speed [2:0]
2x3x1
(EQ 1)
External pixel clock used to output the data:
15 MHz x 64
ext_clk_freq_mhz x pll_multiplier
clk_op_freq_mhz = ---------------------------------------------------------------------------------------------------------------------------------- = --------------------------------- = 40 MHz
2x12x1
pre_pll_clk_div x op_pix_clk_div x row_speed [10:8]
(EQ 2)
Internal master clock:
vt_pix_clk_freq_mhz/2
(EQ 3)
The parameter limit register space contains registers that declare the minimum and
maximum allowable values for:
• The frequency allowable on each clock.
• The divisors that are used to control each clock.
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Control of the Signal Interface
The following factors determine what are valid values, or combinations of valid values,
for the divider/multiplier control registers:
• The minimum/maximum frequency limits for the associated clock must be met.
– pll_ip_clk_freq must be in the range 6–48 MHz. Higher frequencies are preferred.
• PLL internal VCO frequency must be in the range 384–768 MHz.
The minimum/maximum value for the divider/multiplier must be met.
– Range for m: 32–128.
– Range for (n): 1–64.
• The op_pix_clk must never run faster than the vt_pix_clk to ensure that the output
data stream is contiguous.
When using the HiSPi serial interface, the op_pix_clk must be 1/4 of the vt_pix_clk.
• The op_pix_clk_div divider must match the bit-depth of the image when using HiSPi.
For example, op_pix_clk_div must be set to 12 for a 12-bit HiSPi output. The is not
required when using the parallel interface.
• When using the parallel interface, the op_pix_clk must be half of the vt_pix_clk.
• The output line time (including the necessary blanking) must be output in a time
equal to or less than the time defined by line_length_pck.
Although the PLL VCO input frequency range is advertised as 6–48 MHz, superior
performance is obtained by keeping the VCO input frequency as high as possible.
The usage of the output clocks is shown below:
• clk_pixel is used by the sensor core to control the timing of the pixel array. The sensor
core produces one 12-bit pixel each vt_pix_clk period. The line length
(line_length_pck) and fine integration time (fine_integration_time) are controlled in
increments of the clk_pixel period.
• clk_op is used to load parallel pixel data from the output FIFO. The output FIFO
generates one pixel each op_pix_clk period.
An example of the parallel configuration for the PLL will uses an input clock of 10 MHz,
an internal pixel clock of 160 MHz, and an output clock of 80 MHz. In this configuration:
n=1
m = 64
vt_sys_clk_div = 2
op_sys_clk_div = 1
vt_pix_clk_div = 2
op_pix_clk_div = 8
Internal pixel clock used to readout the pixel array:
ext_clk_freq_mhz x pll_multiplier
10 MHz x 64
clk_pixel_freq_mhz = ------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 160 MHz
pre_pll_clk_div x vt_pix_clk_div x row_speed [2:0]
122
(EQ 4)
The external pixel clock used to output the data:
ext_clk_freq_mhz x pll_multiplier
10 MHz x 64
clk_op_freq_mhz = ---------------------------------------------------------------------------------------------------------------------------------- = --------------------------------- = 80 MHz
pre_pll_clk_div x op_pix_clk_div x row_speed [10:8]
1x1x8
Programming the PLL Divisors
The PLL divisors must be programmed while the MT9J003 is in the software standby
state. After programming the divisors, wait for the VCO lock time before enabling the
PLL. The PLL is enabled by entering the streaming state.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Features
An external timer will need to delay the entrance of the streaming mode by 1 millisecond
so that the PLL can lock.
The effect of programming the PLL divisors while the MT9J003 is in the streaming state
is undefined.
Clock Control
The MT9J003 uses an aggressive clock-gating methodology to reduce power consumption. The clocked logic is divided into a number of separate domains, each of which is
only clocked when required.
When the MT9J003 enters a low-power state, almost all of the internal clocks are
stopped. The only exception is that a small amount of logic is clocked so that the
two-wire serial interface continues to respond to READ and WRITE requests.
Features
Scaler
The MT9J003 sensor includes scaling capabilities. This allows the user to generate full
field-of-view, low resolution images. Scaling is advantageous because it uses all pixel
values to calculate the output image which helps to avoid aliasing. It is also more convenient than binning because the scale factor varies smoothly and the user is not limited to
certain ratios of size resolution.
The scaling factor is programmable in 1/16 steps.
scale_n
16
ScaleFactor = --------------------- = --------------------scale_m
scale_m
(EQ 5)
scale_n is fixed at 16.
scale_m is adjustable with R0x0404
Legal values for m are 16 through 128. The user has the ability to scale from
1:1 (m = 16) to 1:8 (m = 128).
Shading Correction
Lenses tend to produce images whose brightness is significantly attenuated near the
edges. There are also other factors causing color plane nonuniformity in images
captured by image sensors. The cumulative result of all these factors is known as image
shading. The MT9J003 has an embedded shading correction module that can be
programmed to counter the shading effects on each individual Red, GreenB, GreenR,
and Blue color signal.
The Correction Function
Color-dependent solutions are calibrated using the sensor, lens system and an image of
an evenly illuminated, featureless gray calibration field. From the resulting image,
register values for the color correction function (coefficients) can be derived.
The correction functions can then be applied to each pixel value to equalize the
response across the image as follows:
Pcorrected  row, col = Psensor(row,col) * f(row,col)
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Features
where P are the pixel values and f is the color dependent correction functions for each
color channel.
Each function includes a set of color-dependent coefficients defined by registers
R0x3600–3726. The function's origin is the center point of the function used in the calculation of the coefficients. Using an origin near the central point of symmetry of the
sensor response provides the best results. The center point of the function is determined
by ORIGIN_C (R0x3782) and ORIGIN_R (R0x3784) and can be used to counter an offset
in the system lens from the center of the sensor array.
One-Time Programmable Memory
The MT9J003 has a two-byte OTP memory that can be utilized during module manufacturing to store specific information about the module. This feature provides system integrators and module manufacturers the ability to label and distinguish various module
types based on lens, IR-cut filter, or other properties.
During the programming process, a dedicated pin for high voltage needs to be provided
to perform the anti-fusing operation. This voltage (VPP) would need to be 8.5V +3%.
Instantaneous VPP cannot exceed 9V at any time. The completion of the programming
process will be communicated by a register through the two-wire serial interface.
Because this programming pin needs to sustain a higher voltage than other input/
output pins, having a dedicated high voltage pin (VPP) minimizes the design risk. If the
module manufacturing process can probe the sensor at the die or PCB level (that is,
supply all the power rails, clocks, two-wire serial interface signals), then this dedicated
high voltage pin does not need to be assigned to the module connector pinout. However,
if the VPP pin needs to be bonded out as a pin on the module, the trace for VPP needs to
carry a maximum of 1mA is needed for programming only. This pin should be left
floating once the module is integrated to a design. If the VPP pin does not need to be
bonded-out as a pin on the module, it should be left floating inside the module.
The programming of the OTP memory requires the sensor to be fully powered and
remain in software standby with its clock input applied. The information will be
programmed through the use of the two-wire serial interface, and once the data is
written to an internal register, the programming host machine will apply a high voltage
to the programming pin, and send a program command to initiate the anti-fusing
process. After the sensor has finished programming the OTP memory, a status bit will be
set to indicate the end of the programming cycle, and the host machine can poll the
setting of the status bit through the two-wire serial interface. Only one programming
cycle for the 16-bit word can be performed.
Reading the OTP memory data requires the sensor to be fully powered and operational
with its clock input applied. The data can be read through a register from the two-wire
serial interface.
The steps below describe the process to program and verify the programmed data in the
OTP memory:
1. Apply power to all the power rails of the sensor (VDD, VDD_IO, VAA, VAA_PIX, VDD_PLL,
and VDD_TX0).
1a. Set VAA to 3.1V during OTP memory programming phase.
1b. VPP needs to be floated during this phase.
1c. Other supplies at nominal.
2. Provide 24 MHz EXTCLK clock input. The PLL settings are discussed at the end of the
document.
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3. Perform the proper reset sequence to the sensor.
4. Place the sensor in soft standby (sensor default state upon power-up) or ensure the
streaming is turned OFF when the part is in active mode.
5. VPP ramps to 8.5V in preparation to program. Power supply (VPP) slew rate should be
slower than 1V/µs.
6. Program R0x3052 to the value 0x045C.
7. Program R0x3054 to the value 0XEA99.
8. Write the 16 bit word data by programming R0x304C.
9. Initiate the OTP memory programming process by programming R0x304A[0] to the
value 0x0001.
10. Check R0x304A [2] = 1, until bit is set to “1” to check for program completion.
11. Repeat steps 9 and 10 two more times.
12. Remove high voltage and float VPP pin.
13. Power down the sensor.
14. Apply nominal power to all the power rails of the sensor VDD, VDD_IO, VAA, VAA_PIX
and VDD_PLL). VPP must be floated.
15. Set EXTCLK to normal or customer defined operating frequency.
16. Perform the proper reset sequence to the sensor.
17. Initiate the OTP memory reading process by setting R0x304A[4] to the value 0x0010.
18. Poll the register bit R0x304A[6] until bit set to “1” to check for read completion.
19. Read the 16 bit word data from the R0x304E.
Figure 5:
Sequence for Programming the MT9J003
Power Supplies
RESET_BAR
EXTCLK
SCLK/SDATA
VPP
Information to be
programmed to the register.
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Initiate programming
and poll status bit.
Read programmed
values for status.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
Sensor Readout Configuration
Image Acquisition Modes
The MT9J003 supports two image acquisition modes:
1. Electronic rolling shutter (ERS) mode
This is the normal mode of operation. When the MT9J003 is streaming; it generates
frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the
ERS is in use, timing and control logic within the sensor sequences through the rows
of the array, resetting and then reading each row in turn. In the time interval between
resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between
row reset and row readout. For each row in a frame, the time between row reset and
row readout is fixed, leading to a uniform integration time across the frame. When the
integration time is changed (by using the two-wire serial interface to change register
settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the MT9J003 switches
cleanly from the old integration time to the new while only generating frames with
uniform integration. See “Changes to Integration Time” in the MT9J003 Register Reference.
2. Global reset mode
This mode can be used to acquire a single image at the current resolution. In this
mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the MT9J003 provides control signals to interface to that
shutter. The operation of this mode is described in detail in "Global Reset" on page 52.
The benefit of using an external electromechanical shutter is that it eliminates the visual
artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel
array at a different point in time.
Window Control
The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. For both parallel and serial interfaces, the output
image size is controlled by the x_output_size and y_output_size registers.
Pixel Border
The default settings of the sensor provide a 3840H x 2748V image. A border of up to
8 pixels (4 in binning) on each edge can be enabled by reprogramming the x_addr_start,
y_addr_start, x_addr_end, y_addr_end, x_output_size, and y_output_size registers
accordingly. This provides a total active pixel array of 3856H x 2764V including border
pixels.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
Readout Modes
Horizontal Mirror
When the horizontal_mirror bit is set in the image_orientation register, the order of pixel
readout within a row is reversed, so that readout starts from x_addr_end and ends at
x_addr_start. Figure 6 shows a sequence of 6 pixels being read out with horizontal_mirror = 0 and horizontal_mirror = 1. Changing horizontal_mirror causes the Bayer
order of the output image to change; the new Bayer order is reflected in the value of the
pixel_order register.
Figure 6:
Effect of Horizontal Mirror on Readout Order
LINE_VALID
horizontal_mirror = 0
DOUT[11:0]
G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0]
horizontal_mirror = 1
DOUT[11:0]
R2[11:0] G2[11:0] R1[11:0] G1[11:0] R0[11:0] G0[11:0]
Vertical Flip
When the vertical_flip bit is set in the image_orientation register, the order in which
pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends
at y_addr_start. Figure 7 shows a sequence of 6 rows being read out with vertical_flip = 0
and vertical_flip = 1. Changing vertical_flip causes the Bayer order of the output image
to change; the new Bayer order is reflected in the value of the pixel_order register.
Figure 7:
Effect of Vertical Flip on Readout Order
FRAME_VALID
MT9J003-DS Rev. E 5/15 EN
vertical_flip = 0
DOUT[11:0]
Row0[11:0] Row1[11:0] Row2[11:0] Row3[11:0] Row4[11:0] Row5[11:0]
vertical_flip = 1
DOUT[11:0]
Row5[11:0] Row4[11:0] Row3[11:0] Row2[11:0] Row1[11:0] Row0[11:0]
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
Subsampling
The MT9J003 supports subsampling. This feature allows the sensor to read out a sample
of pixels available on the array. The most common subsampling used is either a 2x2 or
4x4 where every 2nd or 4th pixel is read in the x and y direction.
Figure 8:
Pixel Array Readout Without Subsampling and With 2x2 Skipping
2 x 2 skipping
Full Resolution
Pixel skipping can be configured up to 4x in the x-direction and 32x in the y-direction.
Skipping pixels in the x-direction will reduce the row-time while skipping in the y-direction will reduce the number of rows readout from the sensor. Skipping in both directions
will reduce the frame-time and is a common method used to increase the sensor framerate. Skipping will introduce image artifacts from aliasing.
Figure 9:
Combinations of Pixel Skipping in the MT9J003 Sensor
Skip 2x
Skip 32x, 16x, or 8x
Skip 4x
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
The subsampling feature can also bin or sum the skipped pixels. Pixel binning will
sample pixels and average the value together in the analog domain. Summing will add
the charge or voltage values of the neighboring pixels together.
Figure 10:
Pixel Binning and Summing
2 x2 B in n in g o r S u m m in g
B in n in g
S u m m in g
Σv
av g
av g
avg
av g
Σ e-
Σ e-
Σv
The pixel summing must be done with adjacent pixels within the same color plane. The
pixel binning can be configured to combine adjacent pixels or to combine every other
pixel.
The pixel subsampling can be configured as a combination of skipping and binning or
summing. This type of subsampling is typically used to achieve the best combination of
pixel responsivity and frame rate. The summing and skipping implementation will sum
neighboring pixels on the same color plane and skip over the adjacent group of pixels.
Figure 11 on page 46 shows that neighboring pixels are summed together. In the case
that a subsampling factor of 4x or greater is used with summing, the neighboring pixels
will also be summed together.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
Figure 11:
Pixel Skipping Combined with Summing or Binning
Table 8 shows the different combinations of subsampling available with the MT9J003
sensor. The sensor cannot combine pixels using two different methods in the same
direction. This means that bin-xy and sum-y are not valid combinations with the sensor.
As well, the bin-xy is limited to a skip of 4x in the vertical direction.
Table 8:
Subsampling Combinations
Skip Y
1
2
4
8
16
32
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Skip X
Bin X
Bin XY
Sum X
Sum XY
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
–
Y
Y
–
Y
Y
–
Y
Y
–
Y
Y
–
Y
Y
–
Y
Y
–
–
–
–
Y
Y
–
Y
Y
–
–
–
–
–
–
–
–
–
–
Y
Y
–
Y
Y
–
Y
Y
–
Y
Y
–
Y
Y
–
Y
Y
–
–
–
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
Frame Rate Control
The frame-time is calculated as the row-time multiplied by the number of rows
(frame_length_lines). The row-time is referred to in these calculations as the number of
pixel clocks read per row (line_length_pck) multiplied by the vt_pix_clk frequency.
The formulas for calculating the frame rate of the MT9J003 are shown below.
The line length is programmed in pixel clock periods through the register
line_length_pck. The minimum value can be determined as the largest value found in
Equation 7. These are the required values for either the array readout or the bandwidth
available to the parallel or serial interface.
Absolute Minimum Array Line Length Pck
minimum line_length_pck = min_line_length_pck (see Table 9, “Minimum Row Time
and Blanking Numbers,” on page 48)
Array Readout Line Length Pck
x_addr_end – x_addr_start + x_odd_inc
------------------------------------------------------------------------------------------------+ min_line_blanking_pck
x_odd_inc
+
1


2x  -----------------------------------
2
(EQ 7)
Interface Line Length Pck
op_pix_clk
x_output_size  -------------------------- + 30 (For parallel)
 vt_pix_clk 
(EQ 8)
 x_output_size
--------------------------------- op_pix_clk
-------------------------
 vt_pix_clk + 30 (For HiSPi)
4
(EQ 9)
Note that line_length_pck will be the maximum of the three equations. The second
equation describes the limitations from the readout of the pixel array while the third
determines the frame-rate of the output interface. The frame-rate using HiSPi will
always be higher than using the parallel interface. Values for min_line_blanking_pck are
provided in “Minimum Row Time” on page 48.
The frame length is programmed directly in number of lines in the register
frame_line_length. For a specific window size, the minimum frame length is shown in
Equation 10:
y_addr_end - y_addr_start + 1
minimum frame_length_lines =  ---------------------------------------------------------------------------- + min_frame_blanking_lines (EQ 10)


subsampling factor
The frame rate can be calculated from these variables and the pixel clock speed as
shown in Equation 11:
vt_pixel_clock_mhz x 1 x 10 6
frame rate = --------------------------------------------------------------------------------------------line_length_pck_x frame_length_lines
(EQ 11)
If coarse_integration_time is set larger than frame_length_lines the frame size will be
expanded to coarse_integration_time + 1.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
Minimum Row Time
The minimum row time and blanking values with default register settings are shown in
Table 9.
Table 9:
Minimum Row Time and Blanking Numbers
Register
No Row Binning
row_speed[2:0]
Row Binning
1
2
4
1
2
min_line_blanking_pck
0x046E
0x029A
min_line_length_pck
0x0670
0x03E0
4
0x01B0
0x0822
0x046C
0x0292
0x02F0
0x0CC0
0x0660
0x03D8
In addition, enough time must be given to the output FIFO so it can output all data at the
set frequency within one row time.
There are therefore three checks that must all be met when programming
line_length_pck:
1. line_length_pck> min_line_length_pck in Table 9.
2. line_length_pck > 0.5*(x_addr_end - x_addr_start + x_odd_inc)/((1+x_odd_inc)/2) +
min_line_blanking_pck in Table 9.
3. The row time must allow the FIFO to output all data during each row.
Parallel - line_length_pck > (x_output_size) * “vt_pix_clk period” / “op_pix_clk
period” + 0x005E.
HiSPi (4-lane) - line_length_pck > (1/4)*(x_output_size) * “vt_pix_clk period” /
“op_pix_clk period” + 0x005E.
Minimum Frame Time
The minimum number of rows in the image is 2, so min_frame_length_lines will always
equal (min_frame_blanking_lines + 2).
Table 10:
Minimum Frame Time and Blanking Numbers
Register
min_frame_blanking_lines
min_frame_length_lines
0x008F
0x0091
Fine Integration Time Limits
The limits for the fine_integration_time can be found from fine_integration_time_min
and fine_integration_time_max_margin. Values for different mode combinations are
shown in Table 11.
Table 11:
Fine_Integration_Time Limits
Register
No Row Binning
row_speed[2:0]
fine_integration_time_min
fine_integration_time_max_margin
1
0x03F2
0x027E
2
0x020A
0x012E
Row Binning
4
0x094
0x0108
1
0x07B2
0x050E
2
0x03AE
0x0276
4
0x010C
0x0224
Fine Correction
For the fine_integration_time limits, the fine_correction constant will change with the
pixel clock speed and binning mode. These values are shown in Table 12.
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Sensor Readout Configuration
Table 12:
Fine_Correction Values
Register
No Row Binning
row_speed[2:0]
fine_correction
1
0x09C
2
0x048
Row Binning
4
0x01E
1
0x0134
2
0x094
4
0x044
Low Power Mode
The MT9J003 sensor supports a low power mode, which can be entered by programming
register bit read_mode[9]. Setting this bit will do the following:
• Double the value of pc_speed[2:0] internally. This means halving the internal pixel
clock frequency.
• Lower currents in the analog domain. This can be done by setting a low power bit in
the static control register. The current will be halved where appropriate in the analog
domain.
Note that enabling the low power mode will not put the sensor in subsampling mode.
This will have to be programmed separately as described earlier in this document. Low
power is independent of the readout mode and can also be enabled in full resolution
mode. Because the pixel clock speed is halved, the frame rates that can be achieved with
low power mode are lower than in full power mode.
Because only internal pixel clock speeds of 1, 2, and 4 are supported, low power mode
combined with pc_speed[2:0] = 4 is an illegal combination.
Any limitations related to changing the internal pixel clock speed will also apply to low
power mode, because it automatically changes the pixel clock speed. Therefore, the
limiter registers need to be reprogrammed to match the new internal pixel clock
frequency.
Integration Time
The integration (exposure) time of the MT9J003 is controlled by the fine_integration_time and coarse_integration_time registers.
The limits for the fine integration time are defined by:
fine_integration_time_min < fine_integration_time < (line_length_pck –
(EQ 12)
fine_integration_time_max_margin
The limits for the coarse integration time are defined by:
coarse_integration_time_min < coarse_integration_time
(EQ 13)
The actual integration time is given by:
  coarse_integration_time * line_length_pck  + fine_integration_time 
integration_time = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- vt_pix_clk_freq_mhz*10 6 
(EQ 14)
It is required that:
coarse_integration_time < = (frame_length_lines - coarse_integration_time_max_margin)
(EQ 15)
If this limit is exceeded, the frame time will automatically be extended to (coarse_integration_time + coarse_integartion_time_max_margin) to accommodate the larger integration time.
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Sensor Readout Configuration
ON Semiconductor Gain Model
The ON Semiconductor gain model uses color-specific registers to control both analog
and digital gain to the sensor. These registers are:
• global_gain
• greenR_gain
• red_gain
• blue_gain
• greenB_gain
The registers provide three 2x and one 4x analog gain stages. The first analog gain stage
has a granularity of 64 steps over 2x gain. A digital gain from 1-7x can also be applied.
analog gain = (8/(8-g(colamp)<11:9>) x (1 + color_gain[8])(1 + color_gain[7])(color_gain[6:0]/64)
(EQ 16)
Bits 11 to 9 are also restricted to 0, 4, and 6. This limits the particular gain stage to 4x.
As a result of the different gain stages, analog gain levels can be achieved in different
ways. The recommended gain sequence is shown below in Table 13.
Table 13:
Recommended Gain Stages
Desired Gain
Recommended Gain Register Setting
1–1.98
2–3.97
4–7.94
8–15.875
16–31.75
0x1040–0x107F
0x1840–0x187F
0x1C40–0x1C7F
0x1CC0–0x1CFF
0x1DC0–0x1DFF
Flash Control
The MT9J003 supports both xenon and LED flash through the FLASH output signal. The
timing of the FLASH signal with the default settings is shown in Figure 12, and in
Figure 13 and Figure 14 on page 51. The flash and flash_count registers allow the timing
of the flash to be changed. The flash can be programmed to fire only once, delayed by a
few frames when asserted, and (for xenon flash) the flash duration can be programmed.
Enabling the LED flash will cause one bad frame, where several of the rows only have the
flash on for part of their integration time. This can be avoided either by first enabling
mask bad frames (write reset_register[9] = 1) before the enabling the flash or by forcing a
restart (write reset_register[1] = 1) immediately after enabling the flash; the first bad
frame will then be masked out, as shown in Figure 14 on page 51. Read-only bit flash[14]
is set during frames that are correctly integrated; the state of this bit is shown in
Figures 12, 13, and 14.
Figure 12:
Xenon Flash Enabled
FRAME_VALID
Flash STROBE
State of triggered bit
(R0x3046-7[14])
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
Figure 13:
LED Flash Enabled
FRAME_VALID
Flash STROBE
State of triggered bit
(R0x3046-7[14])
Bad frame
Flash enabled
during this frame
Notes:
Figure 14:
Bad frame
Good frame
Good frame Flash disabled
during this frame
1. Integration time = number of rows in a frame.
2. Bad frames will be masked during LED flash operation when mask bad frames bit field is set
(R0x301A[9] = 1).
3. An option to invert the flash output signal through R0x3046[7] is also available.
LED Flash Enabled Following Forced Restart
FRAME_VALID
Flash STROBE
State of triggered bit
(R0x3046-7[14])
Masked out
frame
Flash enabled
and a restart
triggered
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Masked out
frame
51
Good frame
Good frame
Flash disabled
and a restart
triggered
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
Global Reset
Global reset mode allows the integration time of the MT9J003 to be controlled by an
external electromechanical shutter. Global reset mode is generally used in conjunction
with ERS mode. The ERS mode is used to provide viewfinder information, the sensor is
switched into global reset mode to capture a single frame, and the sensor is then
returned to ERS mode to restore viewfinder operation.
Overview of Global Reset Sequence
The basic elements of the global reset sequence are:
1. By default, the sensor operates in ERS mode and the SHUTTER output signal is LOW.
The electromechanical shutter must be open to allow light to fall on the pixel array.
Integration time is controlled by the coarse_integration_time and fine_integration_time registers.
2. A global reset sequence is triggered.
3. All of the rows of the pixel array are placed in reset.
4. All of the rows of the pixel array are taken out of reset simultaneously. All rows start to
integrate incident light. The electromechanical shutter may be open or closed at this
time.
5. If the electromechanical shutter has been closed, it is opened.
6. After the desired integration time (controlled internally or externally to the MT9J003),
the electromechanical shutter is closed.
7. A single output frame is generated by the sensor with the usual LV, FV, PIXCLK, and
DOUT timing. As soon as the output frame has completed (FV de-asserts), the electromechanical shutter may be opened again.
8. The sensor automatically resumes operation in ERS mode.
This sequence is shown in Figure 15. The following sections expand to show how the
timing of this sequence is controlled.
Figure 15:
Overview of Global Reset Sequence
ERS
Row Reset
Integration
Readout
ERS
Entering and Leaving the Global Reset Sequence
A global reset sequence can be triggered by a register write to global_seq_trigger[0]
(global trigger, to transition this bit from a 0 to a 1) or by a rising edge on a suitably-configured GPI input (see “Trigger Control” on page 36).
When a global reset sequence is triggered, the sensor waits for the end of the current row.
When LV de-asserts for that row, FV is de-asserted 6 PIXCLK periods later, potentially
truncating the frame that was in progress.
The global reset sequence completes with a frame readout. At the end of this readout
phase, the sensor automatically resumes operation in ERS mode. The first frame integrated with ERS will be generated after a delay of approximately:
((13 + coarse_integration_time) * line_length_pck).
This sequence is shown in Figure 16.
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Sensor Readout Configuration
While operating in ERS mode, double-buffered registers are updated at the start of each
frame in the usual way. During the global reset sequence, double-buffered registers are
updated just before the start of the readout phase.
Figure 16:
Entering and Leaving a Global Reset Sequence
Trigger
Wait for end of current row
ERS
Row Reset
Automatic at end of frame readout
Integration
Readout
ERS
Programmable Settings
The registers global_rst_end and global_read_start allow the duration of the row reset
phase and the integration phase to be controlled, as shown in Figure 17. The duration of
the readout phase is determined by the active image size.
As soon as the global_rst_end count has expired, all rows in the pixel array are simultaneously taken out of reset and the pixel array begins to integrate incident light.
Figure 17:
Controlling the Reset and Integration Phases of the Global Reset Sequence
Trigger
Wait for end of current row
ERS
Row Reset
Automatic at end of frame readout
Integration
Readout
ERS
global_rst_end
global_read_start
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Sensor Readout Configuration
Control of the Electromechanical Shutter
Figure 18 shows two different ways in which a shutter can be controlled during the
global reset sequence. In both cases, the maximum integration time is set by the difference between global_read_start and global_rst_end. In shutter example 1, the shutter is
open during the initial ERS sequence and during the row reset phase. The shutter closes
during the integration phase. The pixel array is integrating incident light from the start
of the integration phase to the point at which the shutter closes. Finally, the shutter
opens again after the end of the readout phase. In shutter example 2, the shutter is open
during the initial ERS sequence and closes sometime during the row reset phase. The
shutter both opens and closes during the integration phase. The pixel array is integrating
incident light for the part of the integration phase during which the shutter is open. As
for the previous example, the shutter opens again after the end of the readout phase.
Figure 18:
Control of the Electromechanical Shutter
Trigger
Wait for end of current row
ERS
Row Reset
Automatic at end of frame readout
Integration
Readout
ERS
global_rst_end
global_read_start
maximum integration time
actual integration time
SHUTTER Example 1
shutter open
shutter closed
shutter open
shutter closed
shutter open
actual integration time
SHUTTER Example 2
shutter open
closed
shutter open
It is essential that the shutter remains closed during the entire row readout phase (that
is, until FV has de-asserted for the frame readout); otherwise, some rows of data will be
corrupted (over-integrated).
It is essential that the shutter closes before the end of the integration phase. If the row
readout phase is allowed to start before the shutter closes, each row in turn will be integrated for one row-time longer than the previous row.
After FV de-asserts to signal the completion of the readout phase, there is a time delay of
approximately 10 * line_length_pck before the sensor starts to integrate light-sensitive
rows for the next ERS frame. It is essential that the shutter be opened at some point in
this time window; otherwise, the first ERS frame will not be uniformly integrated.
The MT9J003 provides a SHUTTER output signal to control (or help the host system
control) the electromechanical shutter. The timing of the SHUTTER output is shown in
Figure 19 on page 55. SHUTTER is de-asserted by default. The point at which it asserts is
controlled by the programming of global_shutter_start. At the end of the global reset
readout phase, SHUTTER de-asserts approximately 2 * line_length_pck after the deassertion of FV.
This programming restriction must be met for correct operation:
global_read_start > global_shutter_start
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
Figure 19:
Controlling the SHUTTER Output
Trigger
Wait for end of current row
ERS
Row Reset
Automatic at end of frame readout
Integration
Readout
ERS
global_rst_end
~2*line_length_pck
global_read_start
global_shutter_start
SHUTTER
Using FLASH with Global Reset
If global_seq_trigger[2] = 1 (global flash enabled) when a global reset sequence is triggered, the FLASH output signal will be pulsed during the integration phase of the global
reset sequence. The FLASH output will assert a fixed number of cycles after the start of
the integration phase and will remain asserted for a time that is controlled by the value
of the flash_count register, as shown in Figure 20.
Figure 20:
Using FLASH With Global Reset
Trigger
Wait for end of current row
ERS
Row Reset
Automatic at end of frame readout
Integration
Readout
ERS
global_rst_end
(fixed)
flash_count
FLASH
External Control of Integration Time
If global_seq_trigger[1] = 1 (global bulb enabled) when a global reset sequence is triggered, the end of the integration phase is controlled by the level of trigger (global_seq_trigger[0] or the associated GPI input). This allows the integration time to be
controlled directly by an input to the sensor.
This operation corresponds to the shutter “B” setting on a traditional camera, where “B”
originally stood for “Bulb” (the shutter setting used for synchronization with a magnesium foil flash bulb) and was later considered to stand for “Brief” (an exposure that was
longer than the shutter could automatically accommodate).
When the trigger is de-asserted to end integration, the integration phase is extended by a
further time given by global_read_start – global_shutter_start. Usually this means that
global_read_start should be set to global_shutter_start + 1.
The operation of this mode is shown in Figure 21 on page 56. The figure shows the global
reset sequence being triggered by the GPI2 input, but it could be triggered by any of the
GPI inputs or by the setting and subsequence clearing of the global_seq_trigger[0] under
software control.
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Readout Configuration
The integration time of the GRR sequence is defined as:
global_scale  [global_read_start – global_shutter_start – global_rst_end]
Integration Time = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- (EQ 17)
vt_pix_clk_freq_mhz
Where:
global_read_start =  2
16
global_shutter_start =  2
 global_read_start2  7:0  + global_read_start1  15:0  
16
(EQ 18)
 global_shutter_start2  7:0  + global_shutter_start1  15:0   (EQ 19)
The integration equation allows for 24-bit precision when calculating both the shutter
and readout of the image. The global_rst_end has only 16-bit as the array reset function
and requires a short amount of time.
The integration time can also be scaled using global_scale. The variable can be set to
0–512, 1–2048, 2–128, and 3–32.
These programming restrictions must be met for correct operation of bulb exposures:
• global_read_start > global_shutter_start
• global_shutter_start > global_rst_end
• global_shutter_start must be smaller than the exposure time (that is, this counter
must expire before the trigger is de-asserted)
Figure 21:
Global Reset Bulb
Trigger
Wait for end of current row
ERS
Row Reset
Automatic at end of frame readout
Integration
global_rst_end
Readout
ERS
global_read_start - global_shutter_start
GPI2
Retriggering the Global Reset Sequence
The trigger for the global reset sequence is edge-sensitive; the global reset sequence
cannot be retriggered until the global trigger bit (in the global_seq_trigger register) has
been returned to “0,” and the GPI (if any) associated with the trigger function has been
de-asserted.
The earliest time that the global reset sequence can be retriggered is the point at which
the SHUTTER output de-asserts; this occurs approximately 2 * line_length_pck after the
negation of FV for the global reset readout phase.
The frame that is read out of the sensor during the global reset readout phase has exactly
the same format as any other frame out of the serial pixel data interface, including the
addition of two lines of embedded data. The values of the coarse_integration_time and
fine_integration_time registers within the embedded data match the programmed
values of those registers and do not reflect the integration time used during the global
reset sequence.
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Sensor Readout Configuration
Global Reset and Soft Standby
If the mode_select[stream] bit is cleared while a global reset sequence is in progress, the
MT9J003 will remain in streaming state until the global reset sequence (including frame
readout) has completed, as shown in Figure 22.
Figure 22:
Entering Soft Standby During a Global Reset Sequence
ERS
Row Reset
Integration
Readout
ERS
mode_select[streaming]
system state
MT9J003-DS Rev. E 5/15 EN
Streaming
57
Software
Standby
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
Sensor Core Digital Data Path
Test Patterns
The MT9J003 supports a number of test patterns to facilitate system debug. Test patterns
are enabled using test_pattern_mode (R0x0600–1). The test patterns are listed in
Table 14.
Table 14:
Test Patterns
test_pattern_mode
Description
0
1
2
3
4
Normal operation: no test pattern
Solid color
100% color bars
Fade-to-gray color bars
PN9 link integrity pattern (only on sensors with serial
interface)
Walking 1s (12-bit value)
Walking 1s (10-bit value)
Walking 1s (8-bit value)
256
257
258
Test patterns 0–3 replace pixel data in the output image (the embedded data rows are
still present). Test pattern 4 replaces all data in the output image (the embedded data
rows are omitted and test pattern data replaces the pixel data).
HiSPi Test Patterns
Test patterns specific to the HiSPi are also generated. The test patterns are enabled by
using test_enable (R0x31C6 - 7) and controlled by test_mode (R0x31C6[6:4]).
Table 15:
HiSPi Test Patterns
test_mode
Description
0
Transmit a constant 0 on all enabled data lanes.
1
Transmit a constant 1 on all enabled data lanes.
2
Transmit a square wave at half the serial data rate on all enabled data lanes.
3
Transmit a square wave at the pixel rate on all enabled data lanes.
4
Transmit a continuous sequence of pseudo random data, with no SAV code, copied on all enabled data
lanes.
5
Replace data from the sensor with a known sequence copied on all enabled data lanes.
For all of the test patterns, the MT9J003 registers must be set appropriately to control the
frame rate and output timing. This includes:
• All clock divisors
• x_addr_start
• x_addr_end
• y_addr_start
• y_addr_end
• frame_length_lines
• line_length_pck
• x_output_size
• y_output_size
MT9J003-DS Rev. E 5/15 EN
58
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
Test Cursors
The MT9J003 supports one horizontal and one vertical cursor, allowing a crosshair to be
superimposed on the image or on test patterns 1–3. The position and width of each
cursor are programmable in R0x31E8–R0x31EE. Both even and odd cursor positions and
widths are supported.
Each cursor can be inhibited by setting its width to “0.” The programmed cursor position
corresponds to the x and y addresses of the pixel array. For example, setting horizontal_cursor_position to the same value as y_addr_start would result in a horizontal cursor
being drawn starting on the first row of the image. The cursors are opaque (they replace
data from the imaged scene or test pattern). The color of each cursor is set by the values
of the Bayer components in the test_data_red, test_data_greenR, test_data_blue and
test_data_greenB registers. As a consequence, the cursors are the same color as test
pattern 1 and are therefore invisible when test pattern 1 is selected.
When vertical_cursor_position = 0x0FFF, the vertical cursor operates in an automatic
mode in which its position advances every frame. In this mode the cursor starts at the
column associated with x_addr_start = 0 and advances by a step-size of 8 columns each
frame, until it reaches the column associated with x_addr_start = 2040, after which it
wraps (256 steps). The width and color of the cursor in this automatic mode are
controlled in the usual way.
The effect of enabling the test cursors when the image_orientation register is non-zero is
not defined by the design specification. The behavior of the MT9J003 is shown in
Figure 23 on page 60 and the test cursors are shown as translucent, for clarity. In practice, they are opaque (they overlay the imaged scene). The manner in which the test
cursors are affected by the value of image_orientation can be understood from these
implementation details:
• The test cursors are inserted last in the data path, the cursor is applied with out any
sensor corrections.
• The drawing of a cursor starts when the pixel array row or column address is within
the address range of cursor start to cursor start + width.
• The cursor is independent of image orientation.
MT9J003-DS Rev. E 5/15 EN
59
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
Figure 23:
Test Cursor Behavior With Image Orientation
Horizontal mirror = 0, Vertical flip = 0
Readout
Direction
Vertical cursor start
Horizontal mirror = 1, Vertical flip = 0
Readout
Direction
Vertical cursor start
Horizontal cursor start
Horizontal cursor start
Readout
Direction
Horizontal mirror = 1, Vertical flip = 1
Horizontal cursor start
Horizontal mirror = 0, Vertical flip = 1
Horizontal cursor start
Readout
Direction
Vertical cursor start
MT9J003-DS Rev. E 5/15 EN
60
Vertical cursor start
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Timing Specifications
Timing Specifications
Power-Up Sequence
The recommended power-up sequence for the MT9J003 is shown in Figure 24. The available power supplies—VDD_IO, VDD, VDD_TX, VDD_PLL, VAA, VAA_PIX, VDD_SLVS,
VDD_SLVS_TX—can be turned on at the same time or have the separation specified below.
1. Turn on VDD_IO power supply.
2. After 1–500ms, turn on VDD and VDD_TX power supply.
3. After 1–500ms, turn on VDD_PLL and VAA/VAA_PIX power supplies.
4. After the last power supply is stable, enable EXTCLK.
5. Assert RESET_BAR for at least 1ms.
6. Wait 2400 EXTCLKs for internal initialization into software standby.
7. Configure PLL, output, and image settings to desired values
8. Set mode_select = 1 (R0x0100).
9. Wait 1ms for the PLL to lock before streaming state is reached.
Figure 24:
Power-Up Sequence
VDD_IO
t1
VDD, VDD_SLVS, VDD_TX
t2
VDD_PLL
t3
VAA, VAA_PIX
t4
VDD_SLVS_TX
EXTCLK
t5
RESET_BAR
t6
Hard
Reset
Table 16:
Internal
INIT
t7
Software
Standby
PLL
Lock
Streaming
Power-Up Sequence
Definition
Min
Typ
Max
Unit
VDD_IO to VDD, VDD_TX time
t
1
0
–
500
ms
VDD, VDD_TX to VDD_PLL time
t2
0
–
500
ms
VDD, VDD_TX to VAA/VAA_PIX time
t3
0
–
500
ms
VAA, VAA_PIX to VDD_SLVS_TX
t
–
–
500
ms
Active hard reset
t5
1
–
–
ms
Internal initialization
t6
2400
–
–
EXTCLKs
PLL lock time
t7
1
–
–
ms
Note:
MT9J003-DS Rev. E 5/15 EN
Symbol
4
Digital supplies must be turned on before analog supplies.
61
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Timing Specifications
Power-Down Sequence
The recommended power-down sequence for the MT9J003 is shown in Figure 25. The
available power supplies—VDD_IO, VDD, VDD_TX0, VDD_PLL, VAA, VAA_PIX, VDD_SLVS,
VDD_SLVS_TX—can be turned off at the same time or have the separation specified
below.
1. Disable streaming if output is active by setting mode_select = 0 (R0x0100).
2. The soft standby state is reached after the current row or frame, depending on configuration, has ended.
3. Assert hard reset by setting RESET_BAR to a logic “0.”
4. Turn off the VAA/VAA_PIX and VDD_PLL power supplies.
5. After 1–500ms, turn off VDD and VDD_TX0 power supply.
6. After 1–500ms, turn off VDD_IO power supply.
Figure 25:
Power-Down Sequence
t5
VDD_IO
VDD,VDD_TX, VDD_SLVS
t4
VDD_PLL
t3
VAA, VAA_PIX
t2
VDD_SLVS_TX
EXTCLK
RESET_BAR
t1
Software
Standby
Streaming
Table 17:
Hard
Reset
Turning Off Power Supplies
Power-Down Sequence
Definition
Min
Typ
Max
Unit
Hard reset
t
1
1
–
–
ms
VDD_SLVS_TX to VDD time
t2
0
–
500
ms
VDD/VAA/VAA_PIX to VDD time
t3
0
–
500
ms
VDD_PLL to VDD time
t
4
0
–
500
ms
VDD to VDD_IO time
t5
0
–
500
ms
MT9J003-DS Rev. E 5/15 EN
Symbol
62
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Timing Specifications
Hard Standby and Hard Reset
The hard standby state is reached by the assertion of the RESET_BAR pad (hard reset).
Register values are not retained by this action, and will be returned to their default
values once hard reset is completed. The minimum power consumption is achieved by
the hard standby state. The details of the sequence are described below and shown in
Figure 26 on page 63.
1. Disable streaming if output is active by setting mode_select = 0 (R0x0100).
2. The soft standby state is reached after the current row or frame, depending on configuration, has ended.
3. Assert RESET_BAR (active LOW) to reset the sensor.
4. The sensor remains in hard standby state if RESET_BAR remains in the logic “0” state.
Figure 26:
Hard Standby and Hard Reset
EXTCLK
mode_select
R0x0100
next row/frame
Logic “1”
Logic “0”
RESET_BAR
Streaming
MT9J003-DS Rev. E 5/15 EN
Soft Standby
63
Hard Standby from Hard Reset
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Timing Specifications
Soft Standby and Soft Reset
The MT9J003 can reduce power consumption by switching to the soft standby state
when the output is not needed. Register values are retained in the soft standby state.
Once this state is reached, soft reset can be enabled optionally to return all register
values back to the default. The details of the sequence are described below and shown in
Figure 27.
Soft Standby
1. Disable streaming if output is active by setting mode_select = 0 (R0x0100).
2. The soft standby state is reached after the current row or frame, depending on configuration, has ended.
Soft Reset
1. Follow the soft standby sequence listed above.
2. Set software_reset = 1 (R0x0103) to start the internal initialization sequence.
3. After 2400 EXTCLKs, the internal initialization sequence is completed and the current
state returns to soft standby automatically. All registers, including software_reset,
return to their default values.
Figure 27:
Soft Standby and Soft Reset
EXTCLK
next row/frame
mode_select
R0x0100
Logic “1”
Logic “0”
Logic “0”
Logic “0”
software_reset
R0x0103
Logic “0”
Logic “0”
Logic “1”
Logic “0”
2400 EXTCLKs
Streaming
MT9J003-DS Rev. E 5/15 EN
Soft Standby
64
Soft Reset
Soft Standby
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Spectral Characteristics
Spectral Characteristics
Figure 28:
Quantum Efficiency
50
B lu e
45
G re e n
40
Re d
Quantum Efficiency (%)
35
30
25
20
15
10
5
0
350
400
450
500
550
600
650
700
750
Wavelength (nm)
MT9J003-DS Rev. E 5/15 EN
65
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Spectral Characteristics
Table 18:
CRA (13.4°)
Image Height
20
18
16
14
CRA (deg)
12
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
Image Height (%)
MT9J003-DS Rev. E 5/15 EN
66
90
100
110
CRA
%
mm
0
0
deg
0
5
0.191
0.67
10
0.382
1.34
15
0.574
2.01
20
0.765
2.68
25
0.956
3.35
30
1.147
4.03
35
1.339
4.70
40
1.530
5.37
45
1.721
6.04
50
1.912
6.71
55
2.103
7.38
60
2.295
8.05
65
2.486
8.72
70
2.677
9.39
75
2.868
10.06
80
3.059
10.73
85
3.251
11.41
90
3.442
12.08
95
3.633
12.75
100
3.824
13.42
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Electrical Characteristics
Electrical Characteristics
Table 19:
DC Electrical Definitions and Characteristics
f
EXTCLK = 15 MHz; VDD = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_SLVS = 1.8V,
VDD_SLVS_TX = 0.8V; Output load = 68.5pF; TJ = 60°C; Data Rate = 480 MHz,; DLL set to 0, 10Mp frame-rate at 14.7 fps
Definition
Condition
Core digital voltage
I/O digital voltage
Parallel pixel data interface
Analog voltage
Symbol
Min
Typ
Max
Unit
VDD
1.7
1.8
1.9
V
VDD_IO
1.7
1.8
1.9
V
VAA
2.4
2.8
3.1
V
Pixel supply voltage
VAA_PIX
2.4
2.8
3.1
V
PLL supply voltage
VDD_PLL
2.4
2.8
3.1
V
VDD_SLVS
1.7
1.8
1.9
V
VDD_SLVS_TX
0.3
0.4
0.9
V
HiSPi digital voltage
HiSPi I/O digital voltage
Digital operating current
Streaming, full resolution
35
41
45
mA
I/O digital operating current
Streaming, full resolution
0
0
0
mA
Analog operating current
Streaming, full resolution
132
169
190
mA
Pixel supply current
Streaming, full resolution
2.7
7.6
13.3
mA
PLL supply current
Streaming, full resolution
6.5
7
7.5
mA
HiSPi digital operating current
Streaming, full resolution
n/a
20
n/a
mA
HiSPi I/O digital operating current
Streaming, full resolution
13
13.5
14
mA
1.3
1.5
1.9
mW
Soft standby (clock on)
Caution
Table 20:
Stresses greater than those listed in Table 20 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Absolute Maximum Ratings
Symbol
Definition
VDD_MAX
VDD_IO_MAX
VAA_MAX
VAA_PIX
VDD_PLL
VDD_SLVS_MAX
VDD_SLVS_TX_MAX
IDD
IDD_IO
IAA_MAX
IAA_PIX
IDD_PLL
tOP
tST
Core digital voltage
I/O digital voltage
Analog voltage
Pixel supply voltage
PLL supply voltage
HiSPi digital voltage
HiSPi I/O digital voltage
Digital operating current
I/O digital operating current
Analog operating current
Pixel supply current
PLL supply current
Operating temperature
Storage temperature
Notes:
MT9J003-DS Rev. E 5/15 EN
Condition
Measure at junction
Min
Max
Unit
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–
–
–
–6
–
–30
–40
1.9
3.1
3.5
3.5
3.5
1.9
1.2
90
100
225
25
25
70
85
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
1. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
67
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Electrical Characteristics
2. To keep dark current and shot noise artifacts from impacting image quality, care should be taken to
keep tOP at a minimum.
Table 21:
Parallel Interface Configured to Use Low Power Mode
f
EXTCLK = 15 MHz; VDD = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; TJ = 60°C;
Parallel Data Rate = 80Mp/s
10MP
720p60
1080p30
VGA60
Monitor
Frame Rate
IAA
IDDPLL
IDD
IDDIO
IAAPIX
7.5 fps
59.94 fps
29.97 fps
59.94 fps
29.97 fps
103.29
122.78
114.67
82.66
69.22
10.26
10.25
10.26
10.27
10.28
23.93
23.85
22.89
18.5
16.3
11.53
11.21
4.49
4.51
6.35
2.33
5.39
4.14
5.25
2.76
Note:
Figure 29:
388 mW
451 mW
411 mW
316 mW
271 mW
Monitor is a low power VGA preview mode. The power consumption values in this table represent
a small sample of MT9J003 sensors. The IDDIO current will double if the VDD_IO voltage is raised to
2.8V.
Two-WIre Serial Bus Timing Parameters
tr_clk
t SRTH
SCLK
t SDH
t SCLK
t SDS
t SHAW
tf_clk
tr_sdat
tf_sdat
90%
90%
10%
10%
t AHSW
t STPS
t STPH
SDATA
Write Address
Bit 7
Write Address
Bit 0
Register Address
Bit 7
Write Start
Register Value
Bit 0
ACK
t AHSR
t SHAR
SCLK
Stop
t SDHR t SDSR
SDATA
Read Address
Bit 7
Read Address
Bit 0
Read Start
Register Value
Bit 0
ACK
Note:
Table 22:
Register Value
Bit 7
Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register
address are issued.
Two-Wire Serial Register Interface Electrical Characteristics
fEXTCLK = 15 MHz; VDD = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_SLVS = 1.8V,
VDD_SLVS_TX = 0.4V; Output load = 68.5pF; TJ = 60°C; Data Rate = 480 MHz,; DLL set to 0
Symbol
VIL
IIN
VOL
MT9J003-DS Rev. E 5/15 EN
Parameter
Condition
Input LOW voltage
Input leakage current
No pull up resistor;
VIN = VDD_IO or DGND
Output LOW voltage
At specified 2 mA
68
Min
Typ
Max
Unit
–0.5
0.73
0.3 x VDD_IO
V
2
A
0.035
V
–2
0.031
0.032
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Electrical Characteristics
Table 22:
Two-Wire Serial Register Interface Electrical Characteristics (continued)
f
EXTCLK = 15 MHz; VDD = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_SLVS = 1.8V,
VDD_SLVS_TX = 0.4V; Output load = 68.5pF; TJ = 60°C; Data Rate = 480 MHz,; DLL set to 0
Symbol
Parameter
Condition
IOL
Output LOW current
At specified VOL 0.1V
CIN
Input pad capacitance
CLOAD
Table 23:
Min
Typ
Max
Unit
3
mA
6
pF
Load capacitance
pF
Two-Wire Serial Register Interface Timing Specification
f
EXTCLK = 15 MHz; VDD = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_SLVS = 1.8V,
VDD_SLVS_TX = 0.4V; Output load = 68.5pF; TJ = 60°C; Data Rate = 480 MHz,; DLL set to 0
Symbol
Parameter
fSCLK
Serial interface input clock
SCLK duty cycle
Condition
Min
Typ
Max
Unit
–
0
100
400
kHz
VOD
45
50
60
%
300
s
tR
SCLK/SDATA rise time
tSRTS
Start setup time
Master WRITE to slave
0.6
s
tSRTH
Start hold time
Master WRITE to slave
0.4
s
s
tSDH
SDATA hold
Master WRITE to slave
0.3
tSDS
SDATA setup
Master WRITE to slave
0.3
tSHAW
SDATA hold to ACK
Master READ to slave
0.15
0.65
s
tAHSW
ACK hold to SDATA
Master WRITE to slave
0.15
0.70
s
tSTPS
Stop setup time
Master WRITE to slave
0.3
s
tSTPH
Stop hold time
Master WRITE to slave
0.6
s
tSHAR
SDATA hold to ACK
Master WRITE to slave
0.3
1.65
s
tAHSR
ACK hold to SDATA
Master WRITE to slave
0.3
0.65
s
0.70
s
tSDHR
SDATA hold
Master READ from slave
.012
tSDSR
SDATA setup
Master READ from slave
0.3
MT9J003-DS Rev. E 5/15 EN
69
0.65
s
s
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Electrical Characteristics
Figure 30:
I/O Timing Diagram
tR
tRP
tF
tFP
90%
90%
10%
10%
tEXTCLK
EXTCLK
tCP
PIXCLK
tPD
tPD
Data[11:0]
Pxl _0
Pxl _1
Pxl _2
Pxl _n
tPFH
tPFL
tPLH
FRAME_VALID/
LINE_VALID
Table 24:
tPLL
FRAME_VALID trails
LINE_VALID by 6 PIXCLKs.
FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
I/O Parameters
fEXTCLK = 15 MHz; VDD = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_SLVS = 1.8V, VDD_SLVS_TX = 0.4V;
Output load = 68.5pF; TJ = 60°C; Data Rate = 480 MHz,; DLL set to 0
Symbol
Definition
Conditions
Min
Max
VIH
Input HIGH voltage
VIL
Input LOW voltage
IIN
Input leakage current
VOH
Output HIGH voltage
VOL
IOH
VDD_IO = 1.8V
VDD_IO = 2.8V
VDD_IO = 1.8V
VDD_IO = 2.8V
No pull-up resistor; VIN = VDD OR
DGND
At specified IOH
1.4
2.4
GND – 0.3
GND – 0.3
– 20
VDD_IO + 0.3
0.4
0.8
20
A
VDD_IO - 0.4V
–
V
Output LOW voltage
At specified IOL
–
0.4
V
Output HIGH current
At specified VOH
–
–12
mA
IOL
Output LOW current
At specified VOL
–
9
mA
IOZ
Tri-state output leakage
current
–
10
A
Table 25:
Units
V
I/O Timing
f
EXTCLK = 15 MHz; VDD = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_SLVS = 1.8V,
VDD_SLVS_TX = 0.4V; Output load = 68.5pF; TJ = 60°C; Data Rate = 480 MHz,; DLL set to 0
Symbol
Definition
Conditions
fEXTCLK
Input clock frequency
PLL enabled
6
tEXTCLK
Input clock period
PLL enabled
166
tR
Input clock rise time
0.1
tF
Input clock fall time
0.1
MT9J003-DS Rev. E 5/15 EN
70
Min
Typ
Max
Units
24
48
MHz
41
20
ns
–
1
V/ns
–
1
V/ns
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Electrical Characteristics
Table 25:
I/O Timing
f
EXTCLK = 15 MHz; VDD = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_SLVS = 1.8V,
VDD_SLVS_TX = 0.4V; Output load = 68.5pF; TJ = 60°C; Data Rate = 480 MHz,; DLL set to 0
Symbol
t
JITTER
Definition
Conditions
Min
Typ
Max
Units
Clock duty cycle
45
50
55
%
Input clock jitter
–
–
0.3
ns
Output pin slew
Fastest
CLOAD = 15pF
–
0.7
–
V/ns
f
PIXCLK frequency
Default
–
80
–
MHz
PIXCLK
t
PD
PIXCLK to data valid
Default
–
–
3
ns
t
PFH
PIXCLK to FRAME_VALID HIGH
Default
–
–
3
ns
t
PLH
PIXCLK to LINE_VALID HIGH
Default
–
–
3
ns
tPFL
PIXCLK to FRAME_VALID LOW
Default
–
–
3
ns
tPLL
PIXCLK to LINE_VALID LOW
Default
–
–
3
ns
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Electrical Characteristics
Figure 31:
HiSPi Eye Diagram for Both Clock and Data Signals
t
RISE
80%
DATA MASK
20%
Vdiff
TxPost
TxPre
t
FALL
UI/2
UI/2
CLOCK MASK
Max Vdiff
Vdiff
Trigger/Reference
CLKJITTER
Table 26:
HiSPi Rise and Fall Times at 480 MHz
Measurement Conditions: PHY Supply 1.8V, HiSPi Power Supply 0.8V, Data Rate 480MHz, DLL set to 0
Table 27:
Parameter
Name
Value
Unit
Max Setup Time from Transmitter
Max Hold Time from Transmitter
Rise time t
Fall time t
Output impedance
TxPRE
TxPost
tRISE
tFALL
0.44
0.44
350
350
66
UI
UI
ps
ps

HiSPi Rise and Fall Times at 360 MHz
Measurement Conditions: PHY Supply 1.8V, HiSPi Power Supply 0.8V, Data Rate 480MHz, DLL set to 0
MT9J003-DS Rev. E 5/15 EN
Parameter
Name
Value
Unit
Max Setup Time from Transmitter
Max Hold Time from Transmitter
Rise time t
Fall time t
Output impedance
TxPRE
TxPost
tRISE
tFALL
0.48
0.42
350
350
66
UI
UI
ps
ps

72
©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Electrical Characteristics
Figure 32:
HiSPi Skew Between Data Signals Within the PHY
tCHSKEW1PHY
Table 28:
Channel, PHY and intra-PHY Skew
Measurement Conditions: PHY Supply 1.8V, HiSPi Power Supply 0.8V, Data Rate 480MHz, DLL set to zero
Data Lane Skew in Reference to Clock
Table 29:
tCHSKEW1PHY
-150
ps
Clock DLL Steps
Measurement Conditions: PHY Supply 1.8V, HiSPi Power Supply 0.8V, Data DLL set to zero
Clock DLL Step
1
2
3
4
5
Step
Delay @ 480MHz
Eye_opening@ 480 MHz
Eye_opening@ 360 MHz
0.25
0.85
0.89
0.375
0.78
0.83
0.5
0.71
0.81
0.625
0.71
0.60
0.75
0.69
046
UI
UI
UI
Note:
Table 30:
The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the MT9J003 Rev. 2.
Data DLL Steps
Measurement Conditions: PHY Supply 1.8V, HiSPi Power Supply 0.8V, Clock DLL set to 0
Data DLL Step
1
2
4
6
Step
Delay @ 480MHz
Eye opening@ 480 MHz
Eye opening@ 360 MHz
0.25
0.79
0.85
0.375
0.84
0.83
0.625
0.71
0.82
0.875
0.61
0.77
UI
UI
UI
Note:
MT9J003-DS Rev. E 5/15 EN
The Data DLL Steps 3, 5, and 7 are not recommended by ON Semiconductor for the MT9J003 Rev. 2.
73
©Semiconductor Components Industries, LLC,2015.
MT9J003-DS Rev. E 5/15 EN
Package Dimensions
Figure 33:
48-Pin iLCC Package Outline Drawing
(0, 2)
0.1 A
(1, 25)
Seating plane
0.1 A
A
10±0.075
7.7
0.7 Typ.
1.4±0.5
0.15 A B C
3.85
C
0.725±0.075
5.014±0.075
Encapsulant2
First Clear Pixel
Substrate3
47X 0.8±0.05
0.15 A B C
4.2
5.082±0.075
4.5
Lid4
(4.589 CTR)
74
Optical Area7
3.85
0.7 Typ.
Optical Center8
48X 0.4±0.05
0.15 A B C
0.525±0.05
4.5
(0.125)
9
(6.413 CTR)
8±0.10
CTR
Section A - A
Notes:
©Semiconductor Components Industries, LLC,2015
1.
2.
3.
4.
5.
6.
7.
Dimensions in mm. Dimensions in () are for reference only.
Encapsulant: Epoxy
Substrate material: Plastic laminate 0.5 thickness
List material: Borosilicate glass 0.4 thickness. Refractive index at 20°C = 1.5255 @ 546nm and 1.5231 @ 588nm.
Lead finish: Gold plating, 0.5 microns minimum thickness.
Image sensor die 0.2 thickness.
Maximum rotation of optical area relative to seating plane A: 25 microns.
Maximum tilt of optical area relative to top of cover glass: 20 microns.
Maximum tilt of optical area relative to top of cover glass: 50 microns.
8. Die center = package center; optical center offset from package center: X = 0.01356, Y = -0.081705
7.5±0.10
CTR
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Package Dimensions
Image sensor die6
10±0.075
7.7
MT9J003-DS Rev. E 5/15 EN
Figure 34:
48-Pin tPLCC Package Outline Drawing
8.00±0.05
Primary datum
B
4.00±0.1
0.00
Ø0.60 -0.03
3 - 0.65±0.05
3 - 0.05±0.05
0.00
Ø0.60 -0.03
B
1 48
4.00±0.1
Sensor center
Die pad 1
First clear pixel
8.00±0.05
6.20±0.05
10.30±0.05
6.40±0.05
4 -R0.30
B
0.00
Ø0.55 -0.03
7.20±0.05
8.00±0.05
B 3 - Ø1.85
B 3 - Ø1.60
Capture direction with lens
Top view (see-through)
8.20±0.05
Side view
0.55±0.1
0.85±0.1
Glass
0.25±0.05
1.05±0.10
4 - 0.41
4 - 0.30
Housing
Substrate
12±0.075
7.7
3.85
0.7 Typ.
0.7 Typ.
47*0.8±0.05
12±0.075
©Semiconductor Components Industries, LLC,2015
7.7
3.85
4.2 4.5
48*0.4±0.05
1 48
1.4±0.05
4.5
9.0
Bottom view
Notes:
1. Die thi ck ness: 203 mm ty p.
2. Gloss thickness: 300mm typ.
3. PCB thi ckness: 300 mm typ.
4. Tilt of sensor relative to substrat e: 0.3 max.
5. Tilt of sensor optical area relative t o three seating pads
l ocat ed on the sensor housing: 0.7 max.
6. Rot ation of sensor optical area relative to the two of the
horizontal ly located F0.60 pi ns: 1.0 max.
7. Optical cent er offset from housing center: ±100mm max.
8. Optical cent er = pack age center = housing center
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Package Dimensions
75
1.35±0.15
0.30±0.05
10.30±0.05
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Package Dimensions
Table 31:
48-Pin tPLCC Pin Assignment
Pin
Number
Name
Pin
Number
Name
Pin
Number
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SLVSC_N
SLVS_1_P
SLVS_1_N
SLVS_0_P
SLVS_0_N
VDD_SLVS_TX
VDD_SLVS
VDD_IO
GND
VDD
EXTCLK
VDD
GND
VDD_IO
SDATA
SCLK
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TEST
RESET_BAR
VDD
GND
VDD_IO
GPI0
GPI1
GPI2
GPI3
SHUTTER
FLASH
GND
VDD_PLL
VPP
AGND
VAA
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
ATEST1_BTM
ATEST2_BTM
VAA_PIX
VAA_PIX
PIXGND
VAA
ATEST2_TOP
ATEST1_TOP
VAA
AGND
GND
SLVS3_P
SLVS3_N
SLVS2_P
SLVS2_N
SLVSC_P
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Revision History
Revision History
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/15
• Updated “Ordering Information” on page 2
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/26/15
• Converted to ON Semiconductor template
• Removed Confidential marking
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/10/12
• Updated trademarks
• Updated section on “PLL” on page 37
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/18/10
• Updated Table 2, “Available Part Numbers,” on page 2
• Updated Table 1, “Key Performance Parameters,” on page 1
• Added Table 18, “CRA (13.4°),” on page 66
• Updated Figure 33: “48-Pin iLCC Package Outline Drawing,” on page 74
• Added Figure 34: “48-Pin tPLCC Package Outline Drawing,” on page 75
• Added Table 31, “48-Pin tPLCC Pin Assignment,” on page 76
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/25/09
• Initial release
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the
rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/
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products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey
any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
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This literature is subject to all applicable copyright laws and is not for resale in any manner.
MT9J003-DS Rev. E 5/15 EN
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©Semiconductor Components Industries, LLC,2015 .