IRF IRF7832 Synchronous mosfet for notebook processor power Datasheet

PD - 94594E
IRF7832
HEXFET® Power MOSFET
Applications
l Synchronous MOSFET for Notebook
Processor Power
l Synchronous Rectifier MOSFET for
Isolated DC-DC Converters in
Networking Systems
VDSS
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
l 20V VGS Max. Gate Rating
l 100% tested for Rg
RDS(on) max
4.0m:@VGS = 10V
30V
Qg
34nC
A
A
D
S
1
8
S
2
7
D
S
3
6
D
G
4
5
D
SO-8
Top View
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
30
V
VGS
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
± 20
ID @ TA = 25°C
20
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
160
PD @TA = 25°C
Power Dissipation
2.5
PD @TA = 70°C
Power Dissipation
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
ID @ TA = 70°C
16
c
A
W
1.6
W/°C
°C
0.02
-55 to + 155
Thermal Resistance
Parameter
RθJL
RθJA
Junction-to-Drain Lead
Junction-to-Ambient
f
Typ.
Max.
Units
–––
20
°C/W
–––
50
Notes  through „ are on page 10
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1
06/30/05
IRF7832
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
∆ΒVDSS/∆TJ
RDS(on)
Drain-to-Source Breakdown Voltage
30
–––
–––
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
–––
–––
0.023
3.1
–––
4.0
VGS(th)
∆VGS(th)
Gate Threshold Voltage
–––
1.39
3.7
–––
4.8
2.32
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
5.7
–––
–––
1.0
IGSS
Gate-to-Source Forward Leakage
–––
–––
–––
–––
150
100
nA
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = 20V
Gate-to-Source Reverse Leakage
Forward Transconductance
–––
77
–––
–––
-100
–––
S
VGS = -20V
VDS = 15V, ID = 16A
Total Gate Charge
Pre-Vth Gate-to-Source Charge
–––
–––
34
8.6
51
–––
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
–––
–––
2.9
12
–––
–––
Qgodr
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
10.5
14.9
–––
–––
Qoss
Rg
Output Charge
Gate Resistance
–––
–––
23
1.2
–––
2.4
td(on)
tr
Turn-On Delay Time
Rise Time
–––
–––
12
6.7
–––
–––
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
21
13
–––
–––
Ciss
Coss
Input Capacitance
Output Capacitance
–––
–––
4310
990
–––
–––
Crss
Reverse Transfer Capacitance
–––
450
–––
gfs
Qg
Qgs1
Qgs2
Qgd
V
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 20A
V
e
= 16A e
VGS = 4.5V, ID
VDS = VGS, ID = 250µA
mV/°C
µA VDS = 24V, VGS = 0V
VDS = 15V
nC
VGS = 4.5V
ID = 16A
See Fig. 16
nC
Ω
VDS = 16V, VGS = 0V
VDD = 15V, VGS = 4.5V
ID = 16A
ns
Clamped Inductive Load
pF
VGS = 0V
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
c
d
Typ.
–––
Max.
260
Units
mJ
–––
16
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
3.1
ISM
(Body Diode)
Pulsed Source Current
–––
–––
160
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
V
p-n junction diode.
TJ = 25°C, IS = 16A, VGS = 0V
trr
Qrr
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
41
39
62
59
ns
nC
TJ = 25°C, IF = 16A, VDD = 10V
di/dt = 100A/µs
ton
Forward Turn-On Time
2
c
MOSFET symbol
A
D
showing the
integral reverse
G
S
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRF7832
1000
1000
100
BOTTOM
10
1
2.25V
0.1
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
2.25V
100
BOTTOM
10
2.25V
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.01
1
0.1
1
10
100
1000
0.1
VDS, Drain-to-Source Voltage (V)
TJ = 150°C
10
T J = 25°C
1
VDS = 15V
20µs PULSE WIDTH
0
3.0
3.5
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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100
1000
4.0
2.0
ID = 16A
VGS = 4.5V
1.5
(Normalized)
RDS(on) , Drain-to -Source On Resistance
100
2.5
10
Fig 2. Typical Output Characteristics
1000
2.0
1
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
ID, Drain-to-Source Current (Α)
VGS
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
2.25V
1.0
0.5
0.0
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J, Junction Temperature (°C )
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF7832
100000
6
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
Coss = Cds + Cgd
10000
Ciss
1000
Coss
Crss
100
ID= 16A
VDS= 24V
VDS= 15V
5
4
3
2
1
0
1
10
100
0
VDS, Drain-to-Source Voltage (V)
20
30
40
50
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
ID, Drain-to-Source Current (A)
1000
ISD , Reverse Drain Current ( Α)
10
100
100
T J = 150°C
10
T J = 25°C
1
VGS = 0V
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
100µsec
10
1msec
Tc = 25°C
Tj = 150°C
Single Pulse
1
1.6
1
10msec
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7832
24
VGS(th) , Gate Threshold Voltage (V)
2.5
ID, Drain Current (A)
20
16
12
8
4
2.0
1.5
ID = 250µA
1.0
0.5
0
25
50
75
100
125
-60 -40 -20
150
0
20
40
60
80 100 120 140 160
T J , Temperature (°C)
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
100
Thermal Response ( Z thJA )
D = 0.50
10
0.20
0.10
0.05
0.02
1
0.01
0.1
SINGLE PULSE
( THERMAL RESPONSE )
0.01
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
10
600
EAS , Single Pulse Avalanche Energy (mJ)
RDS(on), Drain-to -Source On Resistance (m Ω)
IRF7832
ID = 20A
8
6
TJ = 125°C
4
TJ = 25°C
2
0
ID
7.0A
13A
BOTTOM 16A
500
TOP
400
300
200
100
0
2
3
4
5
6
7
8
9
10
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
V GS, Gate -to -Source Voltage (V)
Fig 13. Maximum Avalanche Energy
vs. Drain Current
Fig 12. On-Resistance vs. Gate Voltage
Current Regulator
Same Type as D.U.T.
V(BR)DSS
tp
15V
50KΩ
12V
.3µF
DRIVER
L
VDS
.2µF
D.U.T.
D.U.T
RG
+
- VDD
IAS
20V
VGS
tp
A
0.01Ω
+
V
- DS
VGS
I AS
3mA
IG
Fig 14. Unclamped Inductive Test Circuit
and Waveform
ID
Current Sampling Resistors
Fig 15. Gate Charge Test Circuit
LD
VDS
VDS
+
90%
VDD D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 16. Switching Time Test Circuit
6
10%
VGS
td(on)
tr
td(off)
tf
Fig 17. Switching Time Waveforms
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IRF7832
D.U.T
Driver Gate Drive
ƒ
+
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 18. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 19. Gate Charge Waveform
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IRF7832
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgs 2
Qgd
⎞ ⎛
⎞
+⎜I ×
× Vin × f ⎟ + ⎜ I ×
× Vin × f ⎟
ig
ig
⎝
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
8
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
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IRF7832
SO-8 Package Details
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IRF7832
SO-8 Tape and Reel
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
‚ Starting TJ = 25°C, L = 2.0mH, RG = 25Ω, IAS = 16A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/05
10
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