1CY 7C28 7 CY7C287 64K x 8 Reprogrammable Registered PROM Features put enable that can be programmed to be synchronous (ES) or asynchronous (E). It is available in a 28-pin, 300-mil package. The address set-up time is 45 ns and the time from clock HIGH to output valid is 15 ns. • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — tSA = 45 ns — tCO = 15 ns • Low power — 120 mA • On-chip, edge-triggered output registers • Programmable synchronous or asynchronous output enable • EPROM technology, 100% programmable • 5V ±10% VCC, commercial and military • TTL-compatible I/O • Slim 300-mil package • Capable of withstanding >2001V static discharge Functional Description The CY7C287 is a high-performance 64K x 8 CMOS PROM. The CY7C287 is equipped with an output register and an out- The CY7C287 is available in a cerDIP package equipped with an erasure window to provide reprogrammability. When exposed to UV light, the PROM is erased and can be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms. The CY7C287 offers the advantage of low power, superior performance, and programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each memory location to be 100% tested with each cell being programmed, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that the product will meet DC and AC specification limits after customer programming. Reading the CY7C287 is accomplished by placing an active LOW signal on E/E S. The contents of the memory location addressed by the address lines (A0 − A 15) will become available on the output lines (O0 − O 7) on the next rising of CP. Logic Block Diagram Pin Configurations CerDIP Top View A15 A14 A13 A12 A11 A10 A9 A8 O7 X 512x 1024 PROGRAMMABLE ARRAY ROW ADDRESS 8 x 1 of 128 MULTIPLEXER 8 SENSE AMPS 8-BIT EDGETRIGGERED REGISTER O6 O5 O4 ADDRESS DECODER A7 A6 A5 A4 A3 O3 COLUMN ADDRESS O2 Y O1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 28 2 27 3 26 4 25 5 24 6 7C287 23 22 7 21 8 9 20 10 19 11 18 12 17 13 16 14 15 VCC A10 A11 A12 A13 A14 A15 CP E/ES O7 O6 O5 O4 O3 A2 A1 A0 C287-3 O0 LCC/PLCC Top View E/ES CP OE REGISTER PROGRAMMABLE MULTIPLEXER C287-1 A5 A4 A3 NC A2 A1 A0 GND O0 4 3 2 1 32 31 30 29 5 28 6 7C287 27 7 26 8 25 9 24 10 23 11 22 12 21 13 14151617 181920 A12 A13 A14 A15 NC CP E/ES O7 GND C287-2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 September 1994 – Revised December 1994 CY7C287 Selection Guide 7C287−45 7C287−55 7C287−65 Maximum Set-Up Time (ns) 45 55 65 Maximum Clock to Output (ns) 15 20 25 120 120 120 150 150 Maximum Operating Current (mA) Com’l Mil UV Exposure ................................................ 7258 Wsec/cm 2 Maximum Ratings Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015.2) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................−65°C to +150°C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied..................................................−55°C to +125°C Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Industrial[1] −40°C to +85°C 5V ± 10% Military[2] −55°C to +125°C 5V ± 10% Supply Voltage to Ground Potential .................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V DC Input Voltage .................................................−3.0V to +7.0V DC Program Voltage .....................................................13.0V Electrical Characteristics Over the Operating Range[3] 7C287−45 Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage 7C287−55 Test Conditions Min. Max. Min. VCC = Min., IOH = −2.0 mA VCC = Min., IOL = 8.0 mA Com’l 2.4 2.4 0.4 Mil VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for Inputs VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for Inputs IIX Input Load Current GND < VIN < VCC VCD Input Diode Clamp Voltage IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled −40 +40 −40 IOS Output Short Circuit Current VCC = Max., VOUT = GND[5] −20 −90 −20 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA VPP Programming Supply Voltage IPP Programming Supply Current VIHP Input HIGH Programming Voltage VILP Input LOW Programming Voltage 2.0 VCC 2.0 0.8 −10 +10 Max. 7C287−65 Min. V 0.4 0.4 0.4 0.4 VCC 2.0 V VCC V 0.8 V −10 +10 µA +40 −40 +40 µA −90 −20 −90 mA 120 120 mA 150 150 0.8 −10 Max. Unit 2.4 +10 Note 4 Com’l 120 Mil 12 13 12 50 3.0 2 12 50 3.0 0.4 Notes: 1. Contact a Cypress representative for industrial temperature range specifications. 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. See Introduction to CMOS PROMs for general information on testing. 5. Short circuit test should not exceed 30 seconds. 13 13 V 50 mA 3.0 0.4 V 0.4 V CY7C287 Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 10 pF 10 pF TA = 25°C, f = 1 MHz, VCC = 5.0V AC Test Loads and Waveform[4] R1 500Ω (658Ω MIL) R1 500Ω (658Ω MIL) 5V 5V OUTPUT ALL INPUT PULSES OUTPUT R2 333Ω (403Ω MIL) 30 pF 5 pF INCLUDING JIG AND C287-4 SCOPE INCLUDING JIG AND SCOPE (a) Normal Load Equivalent to: 3.0V R2 333Ω (403Ω MIL) 90% 10% 90% 10% GND ≤ 5 ns ≤ 5 ns C287-6 C287-5 (b) High Z Load THÉVENIN EQUIVALENT OUTPUT 200Ω 250Ω OUTPUT 2.0V 1.9V Military Commercial C287-7 Switching Characteristics Over the Operating Range[3,4] 7C287−45 Parameter Description Min. Max. 7C287−55 Min. Max. 7C287−65 Min. Max. Unit tSA Address Set-Up to Clock HIGH 45 55 65 ns tHA Address Hold from Clock HIGH 0 0 0 ns tCO Clock HIGH to Output Valid 15 20 25 ns tHZE Output High Z from E 15 20 25 ns tDOE Output Valid from E 15 20 25 ns tPWC Clock Pulse Width 15 20 25 ns tSEs[6] tHEs[6] tHZC[6] tCOs[6] ES Set-Up to Clock HIGH 12 15 18 ns ES Hold from Clock HIGH 5 8 10 ns Output High Z from CLK/ES 20 25 30 ns Output Valid from CLK/ES 20 25 30 ns Notes: 6. Parameters with synchronous ES option. 3 CY7C287 Switching Waveform A0 − A15 tSA tHA tHA ES tSEs tHEs tSEs tPWC CP tPWC tCO tHZC O0 − O7 tCOs VALID HIGH Z tHZE tDOE E be within 1 inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dosage. Erasure Characteristics Wavelengths of light less than 4000 Angstroms begin to erase the CY7C287 in the windowed package. For this reason, an opaque label should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time. Programming Modes Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating, the exposure time would be approximately 35 minutes. The CY7C287 needs to Table 1. CY7C287 Mode Selection Pin Function[7] CP A14 E, ES A15 O 7 − O0 VIL/VIH A14 VIL A15 O7 − O0 Output Disable – Asynchronous X A14 VIH A15 High Z Output Disable – Synchronous VIL/VIH A14 VIH A15 High Z Mode: Other PGM LATCH VFY VPP D7 − D0 Program VILP VILP VIHP VPP D7 − D0 Program Verify VIHP VILP VILP VPP O7 − O0 Program Inhibit VIHP VILP VIHP VPP High Z Blank Check VIHP VILP VILP VPP Zeros Mode: Read or Output Disable Synchronous Read Notes: 7. X = “don’t care” but not to exceed VCC ±5%. X can be VIL ir VIH. 4 CY7C287 DIP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND LCC 1 2 3 4 5 6 7C287 7 8 9 10 11 12 13 28 27 26 14 15 VCC A10 A11 A12 /A14 A13 /A15 25 24 23 22 21 A5 A4 A3 NC A2 A1 A0 GND D0 LATCH VPP PGM VFY D7 D6 D5 D4 D3 C287-9 20 19 18 17 16 4 3 2 1 32 31 30 29 5 28 6 7C287 27 7 26 8 25 9 24 10 23 11 22 12 21 13 14 15 16 17 18 19 20 A12 /A14 A13 /A15 LATCH VPP NC PGM VFY D7 GND C287-10 Figure 1. Programming Pinouts Architecture Configuration Bits Architecture Bit E/ES Architecture Verify D0 Device 7C287 D0 Function 0 = Erased Asynchronous Output Enable (Pin 20 = E) 1 = PGMED Synchronous Output Enable (Pin 20 = ES) Bit Map Programmer Address (Hex.) RAM Data 0000 . . FFFF 10000 Data . . Data Control Byte Architecture Byte (10000H) D7 D0 C7 C6 C5 C4 C3 C2 C1C0 5 CY7C287 Ordering Information[8] Speed (ns) Ordering Code 45 55 65 Package Name Operating Range Package Type CY7C287−45JC J65 32-Lead Plastic Leaded Chip Carrier CY7C287−45PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C287−45WC W22 28-Lead (300-Mil) Windowed CerDIP CY7C287−55JC J65 32-Lead Plastic Leaded Chip Carrier CY7C287−55PC P21 28-Lead (300-Mil) Molded DIP CY7C287−55WC W22 28-Lead (300-Mil) Windowed CerDIP CY7C287−55DMB D22 28-Lead (300-Mil) CerDIP CY7C287−55LMB L55 32-Pin Rectangular Leadless Chip Carrier CY7C287−55QMB Q55 32-Pin Windowed Rectangular Leadless Chip Carrier CY7C287−55WMB W22 28-Lead (300-Mil) Windowed CerDIP CY7C287−65JC J65 32-Lead Plastic Leaded Chip Carrier CY7C287−65PC P21 28-Lead (300-Mil) Molded DIP CY7C287−65WC W22 28-Lead (300-Mil) Windowed CerDIP CY7C287−65DMB D22 28-Lead (300-Mil) CerDIP CY7C287−65LMB L55 32-Pin Rectangular Leadless Chip Carrier CY7C287−65QMB Q55 32-Pin Windowed Rectangular Leadless Chip Carrier CY7C287−65WMB W22 28-Lead (300-Mil) Windowed CerDIP Commercial Military Commercial Military Notes: 8. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability. MILITARY SPECIFICATIONS Group A Subgroup Testing Switching Characteristics DC Characteristics Parameter Subgroups tSA 7, 8, 9, 10, 11 Parameter Subgroups tHA 7, 8, 9, 10, 11 VOH 1, 2, 3 tCO 7, 8, 9, 10, 11 VOL 1, 2, 3 tDOE 7, 8, 9, 10, 11 VIH 1, 2, 3 tPWC 7, 8, 9, 10, 11 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Document #: 38−00363 6 CY7C287 Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 32-Lead Plastic Leaded Chip Carrier J65 D-15 Config.A 32-Pin Rectangular Leadless Chip Carrier L55 32-Pin Windowed Rectangular Leadless Chip Carrier Q55 MIL-STD-1835 C-12 MIL-STD-1835 C-12 7 CY7C287 Package Diagrams 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D-15 Config.A © Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.