AD AD7686 16-bit, 500 ksps pulsar adc in msop Datasheet

Data Sheet
16-Bit, 500 kSPS PulSAR
ADC in MSOP
AD7686
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Process controls
IN+
IN–
1.8V TO VDD
REF VDD VIO
SDI
AD7686
SCK
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
SDO
GND
CNV
Figure 2.
Table 1. MSOP, LFCSP/SOT-23 14-/16-/18-Bit PulSAR ADC
Type
18-Bit True
Differential
16-Bit True
Differential
16-Bit Pseudo
Differential
14-Bit Pseudo
Differential
100
kSPS
250
kSPS
AD7691
AD7684
AD7687
AD7680
AD7683
AD7940
AD7685
AD7694
AD7942
400 kSPS
to
500 kSPS
AD7690
AD7982
AD7688
AD7693
AD7686
1000
kSPS
AD7982
AD7980
AD7946
ADC
Driver
ADA4941
ADA4941
ADA4941
ADA4841
ADA4941
ADA4941
The AD76861 is a 16-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5 V power supply, VDD. It contains a low power,
high speed, 16-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
the AD7686 samples an analog input IN+ between 0 V to REF
with respect to a ground sense IN−. The reference voltage, REF,
is applied externally and can be set up to the supply voltage.
POSITIVE INL = +0.52LSB
NEGATIVE INL = –0.38LSB
1.5
1.0
0.5
INL (LSB)
0 TO VREF
5V
GENERAL DESCRIPTION
2.0
0
Power dissipation scales linearly with throughput.
–0.5
–1.0
02969-007
–1.5
–2.0
0
16384
32768
CODE
49152
65535
Figure 1. Integral Nonlinearity vs. Code
1.
0.5V TO 5V
02969-002
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR)
SINAD: 92.5 dB at 20 kHz
THD: −110 dB at 20 kHz
Pseudo differential analog input range
0 V to VREF with VREF up to VDD
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Proprietary serial interface: SPI-/QSPI™-/MICROWIRE™-/DSPcompatible
Daisy-chain multiple ADCs and busy indicator
Power dissipation
3.75 µW at 5 V/100 SPS
3.75 mW at 5 V/100 kSPS
Standby current: 1 nA
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm, 10-lead LFCSP (SOT-23 size)
Pin-for-pin-compatible with 10-lead MSOP/PulSAR® ADCs
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus or provides an optional busy indicator. This device is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7686 is housed in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°C.
Protected by U.S. Patent 6,703,961.
Rev. C
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DOCUMENTATION
Application Notes
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• AD7686 Material Declaration
• AN-932: Power Supply Sequencing
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Data Sheet
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Data Sheet
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User Guides
TECHNICAL SUPPORT
• UG-340: Evaluation Board for the 10-Lead Family 14-/16-/
18-Bit PulSAR ADCs
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Family of 14-/16-/18-Bit PulSAR ADC Evaluation Boards
SOFTWARE AND SYSTEMS REQUIREMENTS
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AD7686
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 15
Applications ....................................................................................... 1
Voltage Reference Input ............................................................ 15
Functional Block Diagram .............................................................. 1
Power Supply............................................................................... 15
General Description ......................................................................... 1
Supplying the ADC from the Reference.................................. 16
Revision History ............................................................................... 2
Digital Interface .......................................................................... 16
Specifications..................................................................................... 3
CS MODE 3-Wire, No Busy Indicator .................................... 17
Timing Specifications....................................................................... 5
CS Mode 3-Wire with Busy Indicator ..................................... 18
Absolute Maximum Ratings ............................................................ 6
CS Mode 4-Wire, No Busy Indicator ....................................... 19
ESD Caution .................................................................................. 6
CS Mode 4-Wire with Busy Indicator ..................................... 20
Pin Configurations and Function Descriptions ........................... 7
Chain Mode, No Busy Indicator .............................................. 21
Terminology ...................................................................................... 8
Chain Mode with Busy Indicator ............................................. 22
Typical Performance Characteristics ............................................. 9
Application Hints ........................................................................... 23
Theory of Operation ...................................................................... 12
Layout .......................................................................................... 23
Circuit Information .................................................................... 12
Evaluating the Performance of the AD7686............................ 23
Converter Operation .................................................................. 12
True 16-Bit Isolated Application Example .............................. 24
Typical Connection Diagram.................................................... 13
Outline Dimensions ....................................................................... 25
Analog Input ............................................................................... 14
Ordering Guide .......................................................................... 26
REVISION HISTORY
8/14—Rev. B to Rev. C
Deleted QFN .................................................................. Throughout
Change to Features Section ............................................................. 1
Added Patent Note, Note 1 .............................................................. 1
Added EPAD Notation to Figure 6 and Table 6............................ 7
Changes to Evaluating the Performance of the AD7686
Section .............................................................................................. 23
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26
4/06—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26
4/05—Revision 0: Initial Version
3/07—Rev. A to Rev. B
Changes to Features and Table 1..................................................... 1
Changes to Table 3 ............................................................................ 4
Moved Figure 3 and Figure 4 to Page............................................. 5
Changes to Figure 13 and Figure 15............................................. 10
Changes to Figure 26 ...................................................................... 13
Changes to Table 8 .......................................................................... 15
Changes to Figure 31 ...................................................................... 16
Changes to Figure 42 ...................................................................... 21
Changes to Figure 44 ...................................................................... 22
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26
Rev. C | Page 2 of 28
Data Sheet
AD7686
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current at 25°
C Input Impedance
ACCURACY
No Missing Codes
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error 2, TMIN to TMAX
Gain Error Temperature Drift
Offset Error2, TMIN to TMAX
Offset Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Test Conditions/Comments
Min
16
IN+ − IN−
IN+
IN−
fIN = 200 kHz
Acquisition phase
0
−0.1
−0.1
B Grade
Typ
Max
VREF
VDD + 0.1
+0.1
Min
16
0
−0.1
−0.1
65
1
See the Analog Input
section
16
−1
−3
REF = VDD = 5 V
VDD = 5 V ± 5%
±0.7
±1
0.5
±2
±0.3
±0.1
±0.3
±0.05
0
89
89
Intermodulation Distortion 4
92
87.5
−106
−106
92
32
−110
VREF
VDD + 0.1
+0.1
65
1
See the Analog Input
section
16
−1
−2
±8
±1.6
500
400
Full-scale step
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz
fIN = 20 kHz
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 5 V, −60 dB input
+3
C Grade
Typ
Max
±0.5
±0.6
0.45
±2
±0.3
±0.1
±0.3
±0.05
0
91
91
+1.5
+2
±6
±1.6
500
400
92.7
88
−110
−110
92.5
33.5
−115
Unit
Bits
V
V
V
dB
nA
Bits
LSB 1
LSB1
LSB1
LSB1
ppm/°C
mV
ppm/°C
LSB1
kSPS
ns
dB 3
dB2
dB2
dB2
dB2
dB2
dB2
LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.
See the Terminology section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full scale.
1
2
Rev. C | Page 3 of 28
AD7686
Data Sheet
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Test Conditions/Comments
VOL
VOH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current 1, 2
Power Dissipation
ISINK = +500 µA
ISOURCE = −500 µA
TEMPERATURE RANGE 3
Specified Performance
1
2
3
Min
Typ
0.5
Max
Unit
VDD + 0.3
500 kSPS, REF = 5 V
100
V
µA
VDD = 5 V
9
2.5
MHz
ns
–0.3
0.7 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+1
+1
Serial 16 bits straight binary
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
Specified performance
Specified performance
4.5
2.3
1.8
VDD and VIO = 5 V, 25°C
VDD = 5 V, 100 SPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 500 kSPS throughput
TMIN to TMAX
1
3.75
3.75
15
−40
With all digital inputs forced to VIO or GND as required.
During acquisition phase.
Contact sales for extended temperature range.
Rev. C | Page 4 of 28
5.5
VDD + 0.3
VDD + 0.3
50
V
V
µA
µA
V
V
4.3
21.5
V
V
V
nA
µW
mW
mW
+85
°C
Data Sheet
AD7686
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width ( CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
tSCKL
tSCKH
tHSDO
tDSDO
Min
0.5
400
2
10
15
17
18
19
20
7
7
5
ns
ns
ns
ns
ns
ns
ns
14
15
16
17
ns
ns
ns
ns
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
26
ns
ns
15
0
5
5
3
4
30% VIO
tDELAY
2V OR VIO – 0.5V1
0.8V OR 0.5V2
1.4V
CL
50pF
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO
02969-003
IOH
Unit
µs
ns
µs
ns
ns
tEN
tDELAY
500µA
Max
1.6
70% VIO
IOL
TO SDO
Typ
2V OR VIO – 0.5V1
0.8V OR 0.5V2
VIO BELOW 2.5V.
BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Figure 3. Load Circuit for Digital Interface Timing
Rev. C | Page 5 of 28
02969-004
500µA
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
AD7686
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs
IN+ 1, IN−1
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature
1
Rating
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
GND − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
±7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
200°C/W (MSOP-10)
44°C/W (MSOP-10)
JEDEC J-STD-20
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
See the Analog Input section.
Rev. C | Page 6 of 28
Data Sheet
AD7686
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
SCK
7
SDO
GND 5
6
CNV
9
SDI
IN+ 3
TOP VIEW
(Not to Scale)
8
SCK
7
SDO
6
CNV
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO GROUND. THIS CONNECTION IS NOT REQUIRED TO
MEET ELECTRICAL PERFORMANCES.
Figure 5. 10-Lead MSOP Pin Configuration
02969-006
SDI
8
IN– 4
AD7686
IN– 4
9
TOP VIEW
(Not to Scale)
VIO
VDD 2
GND 5
AD7686
IN+ 3
10
02969-005
REF 1
10 VIO
VDD 2
Figure 6. 10-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type 1
AI
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
AI
AI
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
EPAD
N/A
Description
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 µF capacitor.
Power Supply.
Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to VREF.
Analog Input Ground Sense. It is connected to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode, chain, or CS. In CS mode, it enables the SDO pin when low. In chain mode,
the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low. If SDI or CNV is low when the conversion is completed,
the busy indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
Exposed Pad. The exposed pad must be connected to ground. This connection is not required to meet
electrical performances.
AI = analog input, DI = digital input, DO = digital output, and P = power.
1
Rev. C | Page 7 of 28
AD7686
Data Sheet
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111 . . . 10 to 111 . . . 11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset is adjusted out.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion), SINAD
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Aperture Delay
It is the measure of the acquisition performance and is the time
between the rising edge of the CNV input and when the input
signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Rev. C | Page 8 of 28
Data Sheet
AD7686
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
2.0
POSITIVE INL = +0.52LSB
NEGATIVE INL = –0.38LSB
1.0
1.0
0.5
0.5
0
–0.5
–1.0
–1.0
–1.5
–1.5
02969-007
–0.5
0
16384
32768
CODE
49152
02969-010
0
–2.0
POSITIVE DNL = +0.35LSB
NEGATIVE DNL = –0.36LSB
1.5
DNL (LSB)
INL (LSB)
1.5
–2.0
16384
0
65535
Figure 7. Integral Nonlinearity vs. Code
32768
CODE
49152
65535
Figure 10. Differential Nonlinearity vs. Code
250000
160000
VDD = REF = 5V
VDD = REF = 5V
140000
202719
133575
124164
200000
120000
100000
COUNTS
COUNTS
150000
100000
80000
60000
40000
0
22
26
0
0
0
8026
8027
8028
8029 802A 802B 802C 802D
CODE IN HEX
20000
0
8024
802E
Figure 8. Histogram of a DC Input at the Code Center
0
–60
8025
8026
1678
0
0
8028
8027
CODE IN HEX
8029
802A
802B
95
–105
–108
94
THD
93
SNR (dB)
–80
–100
–111
SNR
92
–114
91
–117
–140
–160
–180
0
20
40
60
80
90
–10
100 120 140 160 180 200 220 240
FREQUENCY (kHz)
Figure 9. FFT Plot
–120
–8
–6
–4
INPUT LEVEL (dB)
–2
Figure 12. SNR and THD vs. Input Level
Rev. C | Page 9 of 28
0
02969-012
–120
02969-009
AMPLITUDE (dB OF FULL SCALE)
–40
1703
Figure 11. Histogram of a DC Input at the Code Transition
8192 POINT FFT
VDD = REF = 5V
fS = 500kSPS
fIN = 19.99kHz
SNR = 92.8dB
THD = –108.7dB
SECOND HARMONIC = –110.1dB
THIRD HARMONIC = –119.2dB
–20
0
0
THD (dB)
0
30770
02969-008
27583
02969-011
50000
AD7686
Data Sheet
100
17.0
–90
–95
16.0
95
–100
THD
70
2.3
2.7
3.1
3.5
3.9
4.3
4.7
REFERENCE VOLTAGE (V)
13.0
5.5
5.1
SFDR
–110
–115
–120
14.0
85
–105
–125
–130
2.3
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
02969-016
ENOB
THD, SFDR (dB)
15.0
90
ENOB (Bits)
SINAD
02969-013
SNR, SINAD (dB)
SNR
2.7
3.1
3.5
4.3
3.9
4.7
REFERENCE VOLTAGE (V)
5.5
Figure 16. THD, SFDR vs. Reference Voltage
–90
100
VREF = 5V
VREF = 5V
–100
THD (dB)
95
90
–120
80
–55
02969-014
85
–110
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
–130
–55
125
Figure 14. SNR vs. Temperature
02969-017
SNR (dB)
5.1
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
Figure 17. THD vs. Temperature
100
–60
–70
95
VREF = 5V, –10dB
–80
VREF = 5V, –1dB
–90
80
–100
75
–110
70
0
50
100
FREQUENCY (kHz)
150
200
VREF = 5V, –10dB
02969-018
THD (dB)
VREF = 5V, –1dB
85
02969-015
SINAD (dB)
90
–120
0
Figure 15. SINAD vs. Frequency
50
100
FREQUENCY (kHz)
Figure 18. THD vs. Frequency
Rev. C | Page 10 of 28
150
200
Data Sheet
AD7686
1000
4
fS = 100kSPS
OFFSET, GAIN ERROR (LSB)
500
250
VIO
0
4.50
4.75
5.00
SUPPLY (V)
5.25
2
OFFSET ERROR
1
–0
GAIN ERROR
–1
–2
–3
–4
–55
5.50
Figure 19. Operating Currents vs. Supply
–15
5
45
25
65
TEMPERATURE (°C)
85
105
125
25
20
750
TDSDO DELAY (ns)
500
15
VDD = 5V, 85°C
10
VDD = 5V, 25°C
250
5
0
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
02969-020
VDD + VIO
105
125
Figure 20. Power-Down Currents vs. Temperature
fS = 100kSPS
VDD = 5V
750
500
02969-021
250
VIO
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
0
0
20
40
60
80
SDO CAPACITIVE LOAD (pF)
100
120
Figure 23. tDSDO Delay vs. Capacitance Load and Supply
1000
0
–55
02969-023
POWER-DOWN CURRENTS (nA)
–35
Figure 22. Offset and Gain Error vs. Temperature
1000
OPERATING CURRENTS (µA)
02969-022
750
02969-019
OPERATING CURRENTS (µA)
3
VDD
125
Figure 21. Operating Currents vs. Temperature
Rev. C | Page 11 of 28
AD7686
Data Sheet
THEORY OF OPERATION
IN+
SWITCHES CONTROL
MSB
LSB
32,768C 16,384C
4C
2C
C
SW+
C
BUSY
REF
COMP
GND
32,768C 16,384C
4C
2C
C
MSB
CONTROL
LOGIC
OUTPUT CODE
C
LSB
SW–
02969-024
CNV
IN–
Figure 24. ADC Simplified Schematic
CIRCUIT INFORMATION
CONVERTER OPERATION
The AD7686 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7686 is a successive approximation ADC based on a
charge redistribution DAC. Figure 24 shows a simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to two comparator inputs.
The AD7686 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
For example, when operating at 100 SPS, the device consumes
3.75 µW typically, which is ideal for battery-powered
applications.
The AD7686 provides the user with on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7686 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead LFCSP that
combines space savings and allows flexible configurations.
This device is pin-for-pin-compatible with the AD7685,
AD7687, and AD7688.
During the acquisition phase, terminals of the array tied to the
comparator input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase initiates. When the conversion phase begins,
SW+ and SW− are opened first.
The two capacitor arrays are then disconnected from the inputs
and connected to the GND input. Therefore, the differential
voltage between the inputs IN+ and IN−, captured at the end of
the acquisition phase, is applied to the comparator inputs,
causing the comparator to become unbalanced.
By switching each element of the capacitor array between GND
and REF, the comparator input varies by binary weighted
voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic
toggles these switches, starting with the MSB, to bring the
comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code and
a busy signal indicator. Because the AD7686 has an on-board
conversion clock, the serial clock, SCK, is not required for the
conversion process.
Rev. C | Page 12 of 28
Data Sheet
AD7686
Transfer Functions
Table 7. Output Codes and Ideal Input Voltages
Description
FSR – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
111...111
111...110
111...101
Analog Input
VREF = 5 V
4.999924 V
2.500076 V
2.5 V
2.499924 V
76.3 µV
0V
Digital Output Code
Hexadecimal
FFFF 1
8001
8000
7FFF
0001
0000 2
TYPICAL CONNECTION DIAGRAM
Figure 26 shows an example of the recommended connection
diagram for the AD7686 when multiple supplies are available.
000...010
000...001
000...000
–FSR
–FSR + 1 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
–FSR + 0.5 LSB
ANALOG INPUT
1
2
02969-025
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
Figure 25. ADC Ideal Transfer Function
≥7V
REF1
5V
10µF2
100nF
1.8V TO VDD
≥7V
100nF
33Ω
REF
VDD
IN+
VIO
SDI
0 TO VREF
SCK
3
≤–2V
AD7686
2.7nF
4
IN–
3- OR 4-WIRE INTERFACE5
SDO
CNV
GND
1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3SEE DRIVER AMPLIFIER CHOICE SECTION.
4OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5SEE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE.
Figure 26. Typical Application Diagram with Multiple Supplies
Rev. C | Page 13 of 28
02969-026
ADC CODE (STRAIGHT BINARY)
The ideal transfer characteristic for the AD7686 is shown in
Figure 25 and Table 7.
AD7686
Data Sheet
Figure 27 shows an equivalent circuit of the input structure
of the AD7686. The two diodes, D1 and D2, provide ESD
protection for the analog inputs IN+ and IN−. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 0.3 V because this causes these
diodes to begin to forward-bias and start conducting current.
These diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the input buffer’s (U1) supplies are different from
VDD. In such a case, an input buffer with a short-circuit
current limitation can be used to protect the part.
VDD
D1
IN+
OR IN–
CPIN
CIN
RIN
02969-027
D2
GND
Figure 27. Equivalent Analog Input Circuit
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 600 Ω and is a lumped component made up of
some serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits the noise.
When the source impedance of the driving circuit is low, the
AD7686 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency, as shown
in Figure 29.
The analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected, as shown in Figure 28, which represents the typical
CMRR over frequency. For instance, by using IN− to sense a
remote signal ground, ground potential differences between
the sensor and the local ADC ground are eliminated.
80
–80
–85
–90
THD (dB)
ANALOG INPUT
–95
RS = 250Ω
–100
–105
0
60
25
50
FREQUENCY (kHz)
75
100
Figure 29. THD vs. Analog Input Frequency and Source Resistance
50
02969-028
CMRR (dB)
RS = 50Ω
RS = 33Ω
–110
VDD = 5V
02969-030
RS = 100Ω
70
40
1
10
100
FREQUENCY (kHz)
1000
10000
Figure 28. Analog Input CMRR vs. Frequency
Rev. C | Page 14 of 28
Data Sheet
AD7686
DRIVER AMPLIFIER CHOICE
VOLTAGE REFERENCE INPUT
Although the AD7686 is easy to drive, the driver amplifier
should meet the following requirements:
The AD7686 voltage reference input, REF, has a dynamic input
impedance and should, therefore, be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7686. Note that the AD7686
has a noise much lower than most of the other 16-bit
ADCs and, therefore, can be driven by a noisier amplifier
to meet a given system noise specification. The noise
coming from the amplifier is filtered by the AD7686 analog
input circuit 1-pole, low-pass filter made by RIN and CIN or
by the external filter, if one is used. Because the typical
noise of the AD7686 is 37 µV rms, the SNR degradation
due to the amplifier is






If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor, such as 100 nF, between the REF
and GND pins.
where:
POWER SUPPLY
f–3dB is the input bandwidth in MHz of the AD7686
(9 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
•
For ac applications, the driver should have a THD
performance commensurate with the AD7686. Figure 18
shows the THD vs. frequency that the driver should exceed.
•
For multichannel multiplexed applications, the driver
amplifier and the AD7686 analog input circuit must settle a
full-scale step onto the capacitor array at a 16-bit level
(0.0015%). In the data sheet for the amplifier, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
The AD7686 is specified at 4.5 V to 5.5 V. The device uses two
power supply pins: a core supply VDD and a digital input/
output interface supply VIO. VIO allows direct interface with
any logic between 1.8 V and VDD. To reduce the supplies
needed, the VIO and VDD can be tied together.
The AD7686 is independent of power supply sequencing
between VIO and VDD. Additionally, it is very insensitive to
power supply variations over a wide frequency range, as shown
in Figure 30, which represents PSRR over frequency.
Table 8. Recommended Driver Amplifiers
Amplifier
ADA4841-x
AD8605, AD8615
AD8655
OP184
AD8021
AD8022
AD8519
AD8031
110
100
90
80
VDD = 5V
70
60
50
Typical Application
Very low noise and low power
5 V single-supply, low power
5 V single-supply, low power
Low power, low noise, and low frequency
Very low noise and high frequency
Very low noise and high frequency
Small, low power and low frequency
High frequency and low power
Rev. C | Page 15 of 28
40
02969-031
SNRLOSS


37
= 20log 

π
2
2
 37 + f − 3dB (NeN )
2

When REF is driven by a very low impedance source, such as a
reference buffer using the AD8031 or the AD8605, a 10 µF
(X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
PSRR (dB)
•
30
1
10
100
FREQUENCY (kHz)
Figure 30. PSRR vs. Frequency
1000
10000
AD7686
Data Sheet
The AD7686 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 31. This makes the part
ideal for low sampling rates (even a few Hz) and low batterypowered applications.
10000
OPERATING CURRENTS (µA)
1000
VDD = 5V
100
10
VIO
1
Though the AD7686 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7686, when in CS mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, such as Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals
minimizes wiring connections useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
The AD7686, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
0.1
0.001
10
100
1000
10000
SAMPLING RATE (SPS)
100000
1000000
02969-032
0.01
Figure 31. Operating Currents vs. Sampling Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7686, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 32. The reference line can be driven by either:
•
The system power supply directly.
•
A reference voltage with enough current output capability,
such as the ADR43x.
•
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 32.
5V
5V
DIGITAL INTERFACE
1µ F
10Ω
AD8031
In either mode, the AD7686 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must timeout the maximum conversion time prior to
readback.
The busy indicator feature is enabled as follows:
• In CS mode, if CNV or SDI is low when the ADC conversion
ends (see Figure 36 and Figure 40).
• In chain mode, if SCK is high during the CNV rising edge
(see Figure 44).
5V
10kΩ
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
10µF
1µ F
1
REF
VDD
VIO
1OPTIONAL
REFERENCE BUFFER AND FILTER.
02969-033
AD7686
Figure 32. Example of Application Circuit
Rev. C | Page 16 of 28
Data Sheet
AD7686
CS MODE 3-WIRE, NO BUSY INDICATOR
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate provided it has an
acceptable hold time. After the 16th SCK falling edge, or when
CNV goes high, whichever occurs first, SDO returns to high
impedance.
This mode is most often used when a single AD7686 is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 33, and the corresponding timing is
provided in Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers. However, CNV must be returned
high before the minimum conversion time and held high until
the maximum conversion time to avoid generating the busy
signal indicator. When the conversion is complete, the AD7686
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges.
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7686
DATA IN
SDO
02969-034
SCK
CLK
Figure 33. CS Mode 3-Wire, No Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
14
tHSDO
16
tSCKH
tDSDO
tEN
SDO
15
D15
D14
D13
tDIS
D1
D0
Figure 34. CS Mode 3-Wire, No Busy Indicator Serial Interface Timing (SDI High)
Rev. C | Page 17 of 28
02969-035
SCK
AD7686
Data Sheet
CS MODE 3-WIRE WITH BUSY INDICATOR
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or when CNV goes high, whichever
occurs first, SDO returns to high impedance.
This mode is generally used when a single AD7686 is connected
to an SPI-compatible digital host having an interrupt input. The
connection diagram is shown in Figure 35, and the corresponding timing is provided in Figure 36.
If multiple AD7686s are selected at the same time, the SDO
output pin handles this connection without damage or induced
latch-up. Meanwhile, it is recommended to keep this connection as
short as possible to limit extra power dissipation.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion, irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers. However,
CNV must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7686 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK edges.
CONVERT
VIO
DIGITAL HOST
CNV
VIO
47kΩ
AD7686
DATA IN
SDO
SCK
IRQ
02969-036
SDI
CLK
Figure 35. CS Mode 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
tHSDO
15
16
17
tSCKH
tDSDO
SDO
tDIS
D15
D14
D1
D0
Figure 36. CS Mode 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Rev. C | Page 18 of 28
02969-037
SCK
Data Sheet
AD7686
CS MODE 4-WIRE, NO BUSY INDICATOR
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7686 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th
SCK falling edge or when SDI goes high, whichever occurs first,
SDO returns to high impedance and another AD7686 can
be read.
This mode is generally used when multiple AD7686s are
connected to an SPI-compatible digital host. A connection
diagram example using two AD7686 devices is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers.
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
CS2
CS1
CONVERT
CNV
AD7686
SDO
SDI
AD7686
SCK
SDO
SCK
02969-038
SDI
DIGITAL HOST
CNV
DATA IN
CLK
Figure 37. CS Mode 4-Wire, No Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
SCK
1
2
14
3
tHSDO
16
17
18
D1
D0
D15
D14
30
31
32
D1
D0
tSCKH
tDSDO
tEN
D15
D14
D13
tDIS
02969-039
SDO
15
Figure 38. CS Mode 4-Wire, No Busy Indicator Serial Interface Timing
Rev. C | Page 19 of 28
AD7686
Data Sheet
CS MODE 4-WIRE WITH BUSY INDICATOR
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7686 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or SDI going high, whichever occurs first,
the SDO returns to high impedance.
This mode is usually used when a single AD7686 is connected
to an SPI-compatible digital host, which has an interrupt input,
and when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in applications
where low jitter on CNV is desired. The connection diagram is
shown in Figure 39, and the corresponding timing is provided
in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When
conversion is complete, SDO goes from high impedance to low.
CS1
CONVERT
VIO
DIGITAL HOST
CNV
47kΩ
AD7686
DATA IN
SDO
SCK
IRQ
02969-040
SDI
CLK
Figure 39. CS Mode 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
1
2
3
tHSDO
15
16
17
tSCKH
tDIS
tDSDO
tEN
SDO
D15
D14
D1
Figure 40. CS Mode 4-Wire with Busy Indicator Serial Interface Timing
Rev. C | Page 20 of 28
D0
02969-041
SCK
Data Sheet
AD7686
CHAIN MODE, NO BUSY INDICATOR
When the conversion is complete, the MSB is output onto SDO,
and the AD7686 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
then clocked by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 16 × N clocks are required to read back the N
ADCs. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate and, consequently,
more AD7686s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate can be
reduced due to the total readback time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to four AD7686s
running at a conversion rate of 360 kSPS can be daisy-chained
on a 3-wire port.
This mode can be used to daisy-chain multiple AD7686s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7686s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
CONVERT
CNV
SDI
AD7686
AD7686
SDI
SDO
DIGITAL HOST
A
B
SCK
SCK
SDO
DATA IN
02969-042
CNV
CLK
Figure 41. Chain Mode, No Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
14
15
tSSDISCK
tHSCKCNV
16
17
18
DA15
DA14
30
31
32
DA1
DA0
tSCKH
SDOA = SDIB
DA15
DA14
DA13
DA1
DA0
DB15
DB14
DB13
DB1
DB 0
tHSDO
tDSDO
SDOB
Figure 42. Chain Mode, No Busy Indicator Serial Interface Timing
Rev. C | Page 21 of 28
02969-043
tHSDISCK
tEN
AD7686
Data Sheet
CHAIN MODE WITH BUSY INDICATOR
This transition on SDO can be used as a busy indicator to
trigger the data readback controlled by the digital host. The
AD7686 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are then
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs.
This mode can be used to daisy-chain multiple AD7686s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and
wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register. A
connection diagram example using three AD7686s is shown in
Figure 43, and the corresponding timing is given in Figure 44.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7686s in the chain, provided
the digital host has an acceptable hold time. For instance,
with a 3 ns digital host setup time and 3 V interface, up to four
AD7686s running at a conversion rate of 360 kSPS can be daisy
chained to a single 3-wire port.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near-end ADC (ADC C in
Figure 43) SDO is driven high.
CONVERT
SDI
AD7686
SDO
SDI
AD7686
DIGITAL HOST
CNV
CNV
SDI
SDO
AD7686
A
B
C
SCK
SCK
SCK
DATA IN
SDO
IRQ
02969-044
CNV
CLK
Figure 43. Chain Mode with Busy Indicator Connection Diagram
tCYC
ACQUISITION
tCONV
tACQ
ACQUISITION
CONVERSION
tSSCKCNV
SCK
tSCKH
1
tHSCKCNV
2
tSSDISCK
tEN
SDOA = SDIB
3
4
tSCK
15
16
18
19
31
32
33
34
35
tSCKL
tHSDISCK
DA15 DA14 DA13
17
DA 1
SDOB = SDIC
49
tDSDOSDI
tDSDOSDI
DB15 DB14 DB13
DB1
DB0 DA15 DA14
DA 1
DA 0
DC15 DC14 DC13
DC1
DC0 DB15 DB14
DB1
DB0 DA15 DA14
tDSDOSDI
SDOC
48
DA 0
tHSDO
tDSDO
tDSDOSDI
47
tDSDOSDI
Figure 44. Chain Mode with Busy Indicator Serial Interface Timing
Rev. C | Page 22 of 28
DA 1
DA0
02969-045
CNV = SDIA
Data Sheet
AD7686
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7686
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The
pinout of the AD7686, with all its analog signals on the left side
and all its digital signals on the right side, eases this task.
Avoid running digital lines under the device because doing so
couples noise onto the die, unless a ground plane under the
AD7686 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
The AD7686 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connecting it with wide, low impedance
traces.
02969-046
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the devices.
Figure 45. Example of Layout of the AD7686 (Top Layer)
Finally, the AD7686 power supplies VDD and VIO should be
decoupled with ceramic capacitors (typically 100 nF) placed
close to the AD7686 and connected using short and wide traces.
This provides low impedance paths and reduces the effect of
glitches on the power supply lines. Examples of layouts that
follow these rules are shown in Figure 45 and Figure 46.
Other recommended layouts for the AD7686 are outlined in
the documentation of the EVAL-AD7686SBZ evaluation board.
The EVAL-AD7686SBZ evaluation board package includes a
fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the EVALSDP-CB1Z.
Rev. C | Page 23 of 28
02969-047
EVALUATING THE PERFORMANCE OF THE AD7686
Figure 46. Example of Layout of the AD7686 (Bottom Layer)
AD7686
Data Sheet
TRUE 16-BIT ISOLATED APPLICATION EXAMPLE
This skew is the channel-to-channel matching propagation
delay of the digital isolator (tPSKCD). This allows running the
serial interface at the maximum speed of the digital isolator
(45 Mbps for the ADuM1402C), which would have been
otherwise limited by the cascade of the propagation delays of
the digital isolator. For instance, four AD7686 devices running
at 330 kSPS can be chained together.
In applications where high accuracy and isolation are required,
such as power monitoring, motor control, and some medical
equipment, the circuit shown in Figure 47, using the AD7686
and the ADuM1402C digital isolator, provides a compact and
high performance solution.
Multiple AD7686 devices are daisy-chained to reduce the
number of signals to isolate. Note that the SCKOUT, which is a
readback of the AD7686 clock, has a very short skew with the
DATA signal.
The complete analog chain runs on a single 5 V supply using
the ADR391 low dropout reference voltage and the rail-to-rail
CMOS AD8618 amplifier while offering true bipolar input range.
5V
100nF
5V REF
±10V INPUT
4kΩ
GND2
VIA
VOA
SDO
VIB
VOB
SCK
CNV
VOC
VIC
VOD
VID
100nF
1kΩ
5V
REF VDD VIO
IN+
AD7686
2V REF
IN– GND
SDI
1/4 AD8618
5V REF
±10V INPUT
2.7V TO 5V
100nF
DATA
SCKOUT
SCKIN
CONVERT
5V
10µF
4kΩ
VDD2 , VE2
GND1
5V
10µF
VDD1 , VE1
100nF
ADuM1402C
1kΩ
5V
REF VDD VIO
IN+
SDO
AD7686
2V REF
SCK
CNV
SDI
IN– GND
1/4 AD8618
5V REF
5V
10µF
4kΩ
1kΩ
5V
REF VDD VIO
IN+
SDO
AD7686
2V REF
SCK
CNV
IN– GND
1kΩ
1kΩ
5V
SDI
1/4 AD8618
5V REF
5V REF
5V
10µF
±10V INPUT
4kΩ
ADR391
100nF
1kΩ
5V
REF VDD VIO
IN+
IN– GND
IN OUT
GND
1kΩ
2V REF
4kΩ
SDO
AD7686
2V REF
5V
SCK
CNV
10µF
100nF
SDI
1/4 AD8618
Figure 47. A True 16-Bit Isolated Simultaneous Sampling Acquisition System
Rev. C | Page 24 of 28
02969-048
±10V INPUT
100nF
Data Sheet
AD7686
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
091709-A
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
TOP VIEW
0.80
0.75
0.70
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Rev. C | Page 25 of 28
02-05-2013-C
PIN 1 INDEX
AREA
AD7686
Data Sheet
ORDERING GUIDE
Model1, 2, 3
AD7686BCPZRL
AD7686BCPZRL7
AD7686BRMZ
AD7686BRMZRL7
AD7686CCPZRL
AD7686CCPZRL7
AD7686CRMZ
AD7686CRMZRL7
EVAL-AD7686SDZ
EVAL-SDP-CB1Z
Integral
Nonlinearity
±3 LSB max
±3 LSB max
±3 LSB max
±3 LSB max
±2 LSB max
±2 LSB max
±2 LSB max
±2 LSB max
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Ordering
Quantity
Reel, 5000
Reel, 1500
Tube, 50
Reel, 1000
Reel, 5000
Reel, 1500
Tube, 50
Reel, 1000
1
Package Description
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
Evaluation Board
Controller Board
Package Option
CP-10-9
CP-10-9
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
Branding
C02#
C02#
C3N
C3N
C2G#
C2G#
C3P
C3P
Z = RoHS Compliant Part, # denotes RoHS Compliant product may be top or bottom marked.
The EVAL-AD786SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation and/or demonstration purposes.
3
The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the SDZ designator.
2
Rev. C | Page 26 of 28
Data Sheet
AD7686
NOTES
Rev. C | Page 27 of 28
AD7686
Data Sheet
NOTES
©2005–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02969-0-8/14(C)
Rev. C | Page 28 of 28