TI1 MSP430FR2355TDBT Mixed-signal microcontroller Datasheet

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MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
SLASEC4A – MAY 2018 – REVISED JUNE 2018
MSP430FR235x, MSP430FR215x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 24 MHz
– Extended Temperature: –40°C to 105°C
– Wide Supply Voltage Range From 3.6 V Down
to 1.8 V (Operational Voltage is Restricted by
SVS Levels. See VSVSH- and VSVSH+ in PMM,
SVS and BOR.)
• Optimized Low-Power Modes (at 3 V)
– Active Mode: 142 µA/MHz
– Standby:
– LPM3 With 32768-Hz Crystal: 1.43 µA (With
SVS Enabled)
– LPM3.5 With 32768-Hz Crystal: 620 nA (With
SVS Enabled)
– Shutdown (LPM4.5): 42 nA (With SVS Disabled)
• Low-Power Ferroelectric RAM (FRAM)
– Up to 32KB of Nonvolatile Memory
– Built-In Error Correction Code (ECC)
– Configurable Write Protection
– Unified Memory of Program, Constants, and
Storage
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Ease of Use
– 20KB ROM Library Includes Driver Libraries and
FFT Libraries
• High-Performance Analog
– One 12-Channel 12-Bit Analog-to-Digital
Converter (ADC)
– Internal Shared Reference (1.5, 2.0, or 2.5 V)
– Sample-and-Hold 200 ksps
– Two Enhanced Comparators (eCOMP)
– Integrated 6-Bit Digital-to-Analog Converter
(DAC) as Reference Voltage
– Programmable Hysteresis
– Configurable High-Power and Low-Power
Modes
– One With Fast 100-ns Response Time
– One With 1-µs Response Time With 1.5-µA
Low Power
– Four Smart Analog Combo (SAC-L3)
(MSP430FR235x Devices Only)
– Supports General-Purpose Operational
Amplifier (OA)
– Rail-to-Rail Input and Output
– Multiple Input Selections
– Configurable High-Power and Low-Power
Modes
– Configurable PGA Mode Supports
– Noninverting Mode: ×1, ×2, ×3, ×5, ×9,
×17, ×26, ×33
– Inverting Mode: ×1, ×2, ×4, ×8, ×16, ×25,
×32
– Built-in 12-Bit Reference DAC for Offset and
Bias Settings
– 12-Bit Voltage DAC Mode With Optional
References
• Intelligent Digital Peripherals
– Three 16-Bit Timers With Three
Capture/Compare Registers Each (Timer_B3)
– One 16-Bit Timer With Seven Capture/Compare
Registers Each (Timer_B7)
– One 16-Bit Counter-Only Real-Time Clock
Counter (RTC)
– 16-Bit Cyclic Redundancy Checker (CRC)
– Interrupt Compare Controller (ICC) Enabling
Nested Hardware Interrupts
– 32-Bit Hardware Multiplier (MPY32)
– Manchester Codec (MFM)
• Enhanced Serial Communications
– Two Enhanced USCI_A (eUSCI_A) Modules
Support UART, IrDA, and SPI
– Two Enhanced USCI_B (eUSCI_B) Modules
Support SPI and I2C
• Clock System (CS)
– On-Chip 32-kHz RC Oscillator (REFO)
– On-Chip 24-MHz Digitally Controlled Oscillator
(DCO) With Frequency Locked Loop (FLL)
– ±1% Accuracy With On-Chip Reference at
Room Temperature
– On-Chip Very Low-Frequency 10-kHz Oscillator
(VLO)
– On-Chip High-Frequency Modulation Oscillator
(MODOSC)
– External 32-kHz Crystal Oscillator (LFXT)
– External High-Frequency Crystal Oscillator up to
24 MHz (HFXT)
– Programmable MCLK Prescaler of 1 to 128
– SMCLK Derived From MCLK With
Programmable Prescaler of 1, 2, 4, or 8
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
SLASEC4A – MAY 2018 – REVISED JUNE 2018
• General Input/Output and Pin Functionality
– 44 I/Os on 48-Pin Package
– 32 Interrupt Pins (P1, P2, P3, and P4) Can
Wake MCU From LPMs
• Development Tools and Software
– LaunchPad™ Development Kit
(MSP‑EXP430FR2355)
– Target Development Board (MSP‑TS43048PT)
– Free Professional Development Environments
• Family Members (Also See Device Comparison)
– MSP430FR2355: 32KB of Program FRAM +
512B of Data FRAM + 4KB of RAM
1.2
•
•
•
•
– MSP430FR2353: 16KB of Program FRAM +
512B of Data FRAM + 2KB of RAM
– MSP430FR2155: 32KB of Program FRAM +
512B of Data FRAM + 4KB of RAM
– MSP430FR2153: 16KB of Program FRAM +
512B of Data FRAM + 2KB of RAM
• Package Options
– 48-Pin: LQFP (PT)
– 40-Pin: VQFN (RHA)
– 38-Pin: TSSOP (DBT)
• For Complete Module Descriptions, See the
MSP430FR4xx and MSP430FR2xx Family User's
Guide
Applications
Smoke and Heat Detectors
Sensor Transmitters
Circuit Breakers
Sensor Signal Conditioning
1.3
www.ti.com
•
•
•
•
Wired Industrial Communications
Optical Modules
Battery Pack Management
Toll Tags
Description
MSP430FR215x and MSP430FR235x microcontrollers (MCUs) include configurable signal-chain elements
and an extended operating temperature up to 105°C to meet the requirements of industrial systems. The
devices are part of the MSP430™ MCU value line portfolio of ultra-low-power low-cost devices for sensing
and measurement applications. The MSP430FR235x devices integrate four smart analog combos, each of
which can be used as a 12-bit DAC or a configurable programmable gain Op-Amp to meet the specific
needs of a system while reducing the BOM and PCB size. The device also includes a 12-bit SAR ADC
and two comparators. The MSP430FR215x and MSP430FR235x MCUs all support an extended
temperature range from –40° up to 105°C, so higher temperature industrial applications can benefit from
the devices' FRAM data-logging capabilities. The extended temperature range allows developers to meet
requirements of applications such as smoke detectors, sensor transmitters, and circuit breakers.
The MSP430FR215x and MSP430FR235x MCUs feature a powerful 16-bit RISC CPU, 16-bit registers,
and a constant generator that contribute to maximum code efficiency. The digitally controlled oscillator
(DCO) allows the device to wake up from low-power modes to active mode typically in less than 10 µs.
The MSP430 ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM
and a holistic ultra-low-power system architecture, allowing system designers to increase performance
while lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and
endurance of RAM with the nonvolatile behavior of flash.
MSP430FR215x and MSP430FR235x MCUs are supported by an extensive hardware and software
ecosystem with reference designs and code examples to get your design started quickly. Development
kits include the MSP-EXP430FR2355 LaunchPad™ development kit and the MSP-TS430PT48 48-pin
target development board. TI also provides free MSP430Ware™ software, which is available as a
component of Code Composer Studio™ IDE desktop and cloud versions within TI Resource Explorer. The
MSP430 MCUs are also supported by extensive online collateral, training, and online support through the
E2E™ Community Forum.
2
Device Overview
Copyright © 2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR2355 MSP430FR2353 MSP430FR2155 MSP430FR2153
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Device Information (1)
PART NUMBER
OPERATING
TEMPERATURE
PACKAGE
BODY SIZE (2)
–40°C to 105°C
LQFP (48)
7 mm × 7 mm
–40°C to 105°C
VQFN (40)
6 mm × 6 mm
–40°C to 105°C
TSSOP (38)
9.7 mm × 4.4 mm
MSP430FR2355TPT
MSP430FR2353TPT
MSP430FR2155TPT
MSP430FR2153TPT
MSP430FR2355TRHA
MSP430FR2353TRHA
MSP430FR2155TRHA
MSP430FR2153TRHA
MSP430FR2355TDBT
MSP430FR2353TDBT
MSP430FR2155TDBT
MSP430FR2153TDBT
(1)
(2)
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI web site at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
CAUTION
System-level ESD protection must be applied in compliance with the devicelevel ESD specification to prevent electrical overstress or disturbing of data or
code memory. See MSP430™ System-Level ESD Considerations for more
information.
1.4
Functional Block Diagrams
Figure 1-1 shows the MSP430FR235x functional block diagram.
Figure 1-2 shows the MSP430FR215x functional block diagram.
XIN XOUT
HF, LF XT1
ADC
FRAM
DVCC
DVSS
Power
Management
Module
ROM
RAM
24-MHz
Clock
System
32KB + 512B
16KB + 512B
24KB
4KB
2KB
SYS
Infrared
MFM
CRC16
MPY32
ICC
Up to 12-ch
Single-end
12 bit
200 ksps
RST/NMI
SAC0, SAC1,
SAC2, SAC3
eCOMP0
eCOMP1
Configurable
OA, PGA,
12-bit DAC
Combo
Enhanced
Comparator
with 6-bit
DAC
TB3
Timer_B
eUSCI_A0
eUSCI_A1
7 CC
Registers
(UART,
IrDA, SPI)
P1.x, P2.x
P3.x, P4.x
P5.x, P6.x
I/O Ports
P1, P2
2×8 IOs
Interrupt
and Wakeup
PA
1×16 IOs
I/O Ports
P3, P4
2×8 IOs
Interrupt
and Wakeup
PB
1×16 IOs
I/O Ports
P5, P6
1×5 IOs
1×7 IOs
PC
1×12 IOs
RTC
Counter
BAKMEM
MAB
24-MHz CPU
including
16 registers
MDB
EEM
TCK
TMS
TDI/TCLK
TDO
SBWTCK
SBWTDIO
JTAG
SBW
Watchdog
16-bit
Cyclic
Redundancy
Check
32-bit
Hardware
Multiplier
Interrupt
Compare
Controller
TB0
TB1
TB2
Timer_B
3 CC
Registers
eUSCI_B0
eUSCI_B1
2
(SPI, I C)
16-bit
Real-Time
Clock
32 Bytes
Backup
Memory
LPM3.5 Domain
Figure 1-1. MSP430FR235x Functional Block Diagram
Device Overview
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3
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
SLASEC4A – MAY 2018 – REVISED JUNE 2018
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XIN XOUT
HF, LF XT1
eCOMP0
eCOMP1
ADC
FRAM
DVCC
Power
Management
Module
DVSS
ROM
RAM
24-MHz
Clock
System
32KB + 512B
16KB + 512B
24KB
4KB
2KB
SYS
Infrared
MFM
CRC16
MPY32
ICC
Up to 12-ch
Single-end
12 bit
200 ksps
Enhanced
Comparator
with 6-bit
DAC
RST/NMI
P1.x, P2.x
P3.x, P4.x
P5.x, P6.x
I/O Ports
P1, P2
2×8 IOs
Interrupt
and Wakeup
PA
1×16 IOs
I/O Ports
P3, P4
2×8 IOs
Interrupt
and Wakeup
PB
1×16 IOs
I/O Ports
P5, P6
1×5 IOs
1×7 IOs
PC
1×12 IOs
RTC
Counter
BAKMEM
MAB
24-MHz CPU
including
16 registers
MDB
EEM
TCK
TMS
TDI/TCLK
TDO
SBWTCK
SBWTDIO
JTAG
•
•
•
•
4
Watchdog
SBW
16-bit
Cyclic
Redundancy
Check
32-bit
Hardware
Multiplier
Interrupt
Compare
Controller
TB0
TB1
TB2
Timer_B
3 CC
Registers
TB3
Timer_B
eUSCI_A0
eUSCI_A1
7 CC
Registers
(UART,
IrDA, SPI)
eUSCI_B0
eUSCI_B1
2
(SPI, I C)
16-bit
Real-Time
Clock
32 Bytes
Backup
Memory
LPM3.5 Domain
Figure 1-2. MSP430FR215x Functional Block Diagram
The MCU has one main power pair of DVCC and DVSS pins that supplies digital and analog modules.
Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with
±5% accuracy.
P1, P2, P3, and P4 feature the pin-interrupt function and can wake the MCU from all LPMs, including
LPM4, LPM3.5, and LPM4.5.
Each Timer_B3 has three capture/compare registers. Only CCR1 and CCR2 are externally connected.
Timer_B7 has seven capture/compare registers. Only CCR1 to CCR6 are externally connected. CCR0
registers can be used only for internal period timing and interrupt generation.
In LPM3.5, the RTC counter and backup memory can be functional while the rest of peripherals are off.
Device Overview
Copyright © 2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR2355 MSP430FR2353 MSP430FR2155 MSP430FR2153
MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
www.ti.com
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table of Contents
1
2
3
Device Overview ......................................... 1
1.2
Applications ........................................... 2
6.1
CPU
1.3
Description ............................................ 2
6.2
Operating Modes .................................... 55
1.4
6
Detailed Description ................................... 55
.................................................
55
Functional Block Diagrams ........................... 3
6.3
Interrupt Vector Addresses.......................... 57
Revision History ......................................... 5
Device Comparison ..................................... 6
6.4
Memory Organization ............................... 59
6.5
Bootloader (BSL) .................................... 59
Related Products ..................................... 6
6.6
JTAG Standard Interface............................ 60
Terminal Configuration and Functions .............. 7
6.7
Spy-Bi-Wire Interface (SBW)........................ 60
4.1
Pin Diagrams ......................................... 7
6.8
FRAM................................................ 60
4.2
Pin Attributes ........................................ 13
6.9
Memory Protection .................................. 61
4.3
Signal Descriptions .................................. 17
6.10
Peripherals
21
6.11
Input/Output Diagrams .............................. 88
21
6.12
Device Descriptors (TLV) .......................... 100
21
6.13
Identification........................................ 102
.....................................
4.5
Buffer Type ..........................................
4.6
Connection of Unused Pins .........................
Specifications ...........................................
5.1
Absolute Maximum Ratings ........................
5.2
ESD Ratings ........................................
5.3
Recommended Operating Conditions ...............
4.4
5
Timing and Switching Characteristics ............... 27
Features .............................................. 1
3.1
4
5.13
1.1
Pin Multiplexing
22
7
22
22
22
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 23
5.4
Active Mode Supply Current Per MHz .............. 23
Low-Power Mode LPM0 Supply Currents Into VCC
Excluding External Current.......................... 23
Low-Power Mode LPM3 and LPM4 Supply Currents
(Into VCC) Excluding External Current .............. 24
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
8
..........................................
61
Applications, Implementation, and Layout ...... 103
7.1
7.2
Device Connection and Layout Fundamentals .... 103
Peripheral- and Interface-Specific Design
Information ......................................... 106
7.3
ROM Libraries
7.4
Typical Applications ................................ 107
.....................................
107
Device and Documentation Support .............. 108
...................
8.1
Getting Started and Next Steps
8.2
Device Nomenclature .............................. 108
8.3
Tools and Software ................................ 109
Production Distribution of LPM3 Supply Currents .. 25
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current .................... 25
8.4
Documentation Support ............................ 110
8.5
Related Links
8.6
Trademarks ........................................ 111
Production Distribution of LPMx.5 Supply Currents 26
Typical Characteristics - Current Consumption Per
Module .............................................. 26
8.7
Electrostatic Discharge Caution
Thermal Resistance Characteristics ................ 26
8.8
9
......................................
...................
Glossary............................................
108
111
111
111
Mechanical, Packaging, and Orderable
Information ............................................. 112
2 Revision History
Changes from May 11, 2018 to June 19, 2018
•
•
•
•
•
Page
Changed the document status to Production Data ............................................................................... 1
Added missing UCB0SCL signal to P1.3/UCB0SOMI/UCB0SCL/OA0+/A3 in pinout figures .............................. 8
Added row for "Driver Library and FFT Library" in Table 6-4, Memory Organization ..................................... 59
Added Section 7.3, ROM Libraries ............................................................................................. 107
Corrected the title and link to reference design in Table 7-1, TI Reference Designs ..................................... 107
Revision History
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Copyright © 2018, Texas Instruments Incorporated
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MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
SLASEC4A – MAY 2018 – REVISED JUNE 2018
www.ti.com
3 Device Comparison
Table 3-1 summarizes the features of the available family members.
12-BIT ADC
CHANNELS
SAC
2
2
12
4
2
12
4
DEVICE
PROGRAM
FRAM (Kbytes)
SRAM
(bytes)
TB0, TB1,
TB2
TB3
MSP430FR2355PT
32KB + 512B
4096
3 × CCR (3)
7 × CCR (3)
(3)
7 × CCR (3)
2
eCOMP
eUSCI_B
(2)
eUSCI_A
Table 3-1. Device Comparison (1)
I/Os
PACKAGE
2
44
48 PT (LQFP)
2
44
48 PT (LQFP)
40 RHA (VQFN)
MSP430FR2353PT
16KB + 512B
2048
3 × CCR
MSP430FR2355RHA
32KB + 512B
4096
3 × CCR (3)
7 × CCR (3)
2
2
10
4
2
36
MSP430FR2353RHA
16KB + 512B
2048
3 × CCR (3)
7 × CCR (3)
2
2
10
4
2
36
40 RHA (VQFN)
(3)
7 × CCR (3)
2
2
10
4
2
34
38 DBT (TSSOP)
MSP430FR2355DBT
32KB + 512B
4096
3 × CCR
MSP430FR2353DBT
16KB + 512B
2048
3 × CCR (3)
7 × CCR (3)
2
2
10
4
2
34
38 DBT (TSSOP)
(3)
7 × CCR (3)
2
2
12
–
2
44
48 PT (LQFP)
MSP430FR2155PT
32KB + 512B
4096
3 × CCR
MSP430FR2153PT
16KB + 512B
2048
3 × CCR (3)
7 × CCR (3)
2
2
12
–
2
44
48 PT (LQFP)
MSP430FR2155RHA
32KB + 512B
4096
3 × CCR (3)
7 × CCR (3)
2
2
10
–
2
36
40 RHA (VQFN)
MSP430FR2153RHA
16KB + 512B
2048
3 × CCR (3)
7 × CCR (3)
2
2
10
–
2
36
40 RHA (VQFN)
(3)
7 × CCR (3)
2
2
10
–
2
34
38 DBT (TSSOP)
7 × CCR (3)
2
2
10
–
2
34
38 DBT (TSSOP)
MSP430FR2155DBT
32KB + 512B
4096
3 × CCR
MSP430FR2153DBT
16KB + 512B
2048
3 × CCR (3)
(1)
(2)
(3)
3.1
For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI web site
at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs. Not all CCR channels are package specific. See the definition in Section 4.
Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit Microcontrollers High-performance, low-power solutions to enable the autonomous
future
Products for MSP430 Ultra-Low-Power Sensing and Measurement Microcontrollers
One ecosystem. Endless possibilities.
One platform.
Products for MSP430 Value Line Microcontrollers Low-cost, ultra-low-power MCUs for simple sensing
and measurement applications
Companion Products for MSP430FR2355 Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430FR2355 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
6
Device Comparison
Copyright © 2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR2355 MSP430FR2353 MSP430FR2155 MSP430FR2153
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www.ti.com
SLASEC4A – MAY 2018 – REVISED JUNE 2018
4 Terminal Configuration and Functions
4.1
Pin Diagrams
48
47
46
45
44
43
42
41
40
39
38
37
P1.3/UCB0SOMI/UCB0SCL/OA0+/A3
P3.0/MCLK
P3.1/OA2O
P3.2/OA2P3.3/OA2+
P5.0/TB2.1/MFM.RX/A8
P5.1/TB2.2/MFM.TX/A9
P5.2/TB2CLK/A10
P5.3/TB2TRG/A11
P5.4
P3.4/SMCLK
P3.5/OA3O
Figure 4-1 shows the pinout of the 48-pin PT package for the MSP430FR235x MCUs.
1
2
3
4
5
6
7
8
9
10
11
12
MSP430FR2355TPT
MSP430FR2353TPT
36
35
34
33
32
31
30
29
28
27
26
25
P3.6/OA3P3.7/OA3+
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/OA1O/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+
P2.0/TB1.1/COMP0.O
P2.1/TB1.2/COMP1.O
P2.2/TB1CLK
P2.3/TB1TRG
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4.6/UCB1SIMO/UCB1SDA
P4.5/UCB1CLK
P4.4/UCB1STE
P6.6/TB3CLK
P6.5/TB3.6
P6.4/TB3.5
P6.3/TB3.4
P6.2/TB3.3
P6.1/TB3.2
P6.0/TB3.1
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
13
14
15
16
17
18
19
20
21
22
23
24
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/VerefP1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DVSS
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
P2.5/COMP1.0
P2.4/COMP1.1
P4.7/UCB1SOMI/UCB1SCL
Figure 4-1. 48-Pin PT (LQFP) (Top View) – MSP430FR235x
Terminal Configuration and Functions
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P5.1/TB2.2/MFM.TX/A9
P3.4/SMCLK
P3.5/OA3O
33
32
31
P3.3/OA2+
P5.0/TB2.1/MFM.RX/A8
35
34
P3.1/OA2O
P3.2/OA2-
37
P3.0/MCLK
38
36
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
P1.3/UCB0SOMI/UCB0SCL/OA0+/A3
40
39
Figure 4-2 shows the pinout of the 40-pin RHA package for the MSP430FR235x MCUs.
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1
1
30
P3.6/OA3-
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
2
29
P3.7/OA3+
TEST/SBWTCK
3
28
P1.4/UCA0STE/TCK/A4
RST/NMI/SBWTDIO
4
27
P1.5/UCA0CLK/TMS/OA1O/A5
DVCC
5
26
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6
MSP430FR2355TRHA
MSP430FR2353TRHA
16
17
18
19
20
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
P4.1/UCA1CLK
P4.0/UCA1STE/ISOTXD/ISORXD
P2.3/TB1TRG
P6.0/TB3.1
21
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
P2.4/COMP1.1
15
P2.2/TB1CLK
10
P6.1/TB3.2
P2.1/TB1.2/COMP1.O
22
13
23
9
14
8
P2.5/COMP1.0
P4.4/UCB1STE
P2.6/MCLK/XOUT
P4.5/UCB1CLK
P2.0/TB1.1/COMP0.O
11
24
12
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+
7
P4.7/UCB1SOMI/UCB1SCL
25
P2.7/TB0CLK/XIN
P4.6/UCB1SIMO/UCB1SDA
DVSS
6
Figure 4-2. 40-Pin RHA (VQFN) (Top View) – MSP430FR235x
8
Terminal Configuration and Functions
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Figure 4-3 shows the pinout of the 38-pin DBT package for the MSP430FR235x MCUs.
P3.2/OA2P3.1/OA2O
P3.0/MCLK
P1.3/UCB0SOMI/UCB0SCL/OA0+/A3
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/VerefP1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DVSS
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
P2.5/COMP1.0
P2.4/COMP1.1
P4.7/UCB1SOMI/UCB1SCL
P4.6/UCB1SIMO/UCB1SDA
P4.5/UCB1CLK
P4.4/UCB1STE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
MSP430FR2355TDBT
MSP430FR2353TDBT
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P3.3/OA2+
P5.0/TB2.1/MFM.RX/A8
P5.1/TB2.2/MFM.TX/A9
P3.4/SMCLK
P3.5/OA3O
P3.6/OA3P3.7/OA3+
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/OA1O/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+
P2.0/TB1.1/COMP0.O
P2.1/TB1.2/COMP1.O
P2.2/TB1CLK
P2.3/TB1TRG
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
Figure 4-3. 38-Pin DBT (TSSOP) (Top View) – MSP430FR235x
Terminal Configuration and Functions
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
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48
47
46
45
44
43
42
41
40
39
38
37
P1.3/UCB0SOMI/UCB0SCL/A3
P3.0/MCLK
P3.1
P3.2
P3.3
P5.0/TB2.1/MFM.RX/A8
P5.1/TB2.2/MFM.TX/A9
P5.2/TB2CLK/A10
P5.3/TB2TRG/A11
P5.4
P3.4/SMCLK
P3.5
Figure 4-4 shows the pinout of the 48-pin PT package for the MSP430FR215x MCUs.
1
2
3
4
5
6
7
8
9
10
11
12
MSP430FR2155TPT
MSP430FR2153TPT
36
35
34
33
32
31
30
29
28
27
26
25
P3.6
P3.7
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
P2.0/TB1.1/COMP0.O
P2.1/TB1.2/COMP1.O
P2.2/TB1CLK
P2.3/TB1TRG
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4.6/UCB1SIMO/UCB1SDA
P4.5/UCB1CLK
P4.4/UCB1STE
P6.6/TB3CLK
P6.5/TB3.6
P6.4/TB3.5
P6.3/TB3.4
P6.2/TB3.3
P6.1/TB3.2
P6.0/TB3.1
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
13
14
15
16
17
18
19
20
21
22
23
24
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/A2/VerefP1.1/UCB0CLK/ACLK/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DVSS
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
P2.5/COMP1.0
P2.4/COMP1.1
P4.7/UCB1SOMI/UCB1SCL
Figure 4-4. 48-Pin PT (LQFP) (Top View) – MSP430FR215x
10
Terminal Configuration and Functions
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
P5.0/TB2.1/MFM.RX/A8
P5.1/TB2.2/MFM.TX/A9
P3.4/SMCLK
P3.5
32
31
P3.3
34
P3.2
36
35
33
P3.0/MCLK
P3.1
38
37
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/A2/Veref-
P1.3/UCB0SOMI/UCB0SCL/A3
40
39
Figure 4-5 shows the pinout of the 40-pin RHA package for the MSP430FR215x MCUs.
P1.1/UCB0CLK/ACLK/COMP0.1/A1
1
30
P3.6
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
2
29
P3.7
TEST/SBWTCK
3
28
P1.4/UCA0STE/TCK/A4
RST/NMI/SBWTDIO
4
27
P1.5/UCA0CLK/TMS/A5
DVCC
5
26
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
DVSS
6
P2.7/TB0CLK/XIN
MSP430FR2155TRHA
MSP430FR2153TRHA
17
18
19
20
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
P4.1/UCA1CLK
P4.0/UCA1STE/ISOTXD/ISORXD
P2.3/TB1TRG
15
21
16
P2.2/TB1CLK
10
P6.0/TB3.1
22
P2.4/COMP1.1
P6.1/TB3.2
P2.5/COMP1.0
13
P2.1/TB1.2/COMP1.O
14
23
9
P4.4/UCB1STE
8
P4.5/UCB1CLK
P2.6/MCLK/XOUT
11
P2.0/TB1.1/COMP0.O
12
24
P4.7/UCB1SOMI/UCB1SCL
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
7
P4.6/UCB1SIMO/UCB1SDA
25
Figure 4-5. 40-Pin RHA (VQFN) (Top View) – MSP430FR215x
Terminal Configuration and Functions
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Figure 4-6 shows the pinout of the 38-pin DBT package for the MSP430FR215x MCUs.
P3.2
P3.1
P3.0/MCLK
P1.3/UCB0SOMI/UCB0SCL/A3
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/A2/VerefP1.1/UCB0CLK/ACLK/COMP0.1/A1
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DVSS
P2.7/TB0CLK/XIN
P2.6/MCLK/XOUT
P2.5/COMP1.0
P2.4/COMP1.1
P4.7/UCB1SOMI/UCB1SCL
P4.6/UCB1SIMO/UCB1SDA
P4.5/UCB1CLK
P4.4/UCB1STE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
MSP430FR2155TDBT
MSP430FR2153TDBT
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P3.3
P5.0/TB2.1/MFM.RX/A8
P5.1/TB2.2/MFM.TX/A9
P3.4/SMCLK
P3.5
P3.6
P3.7
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
P2.0/TB1.1/COMP0.O
P2.1/TB1.2/COMP1.O
P2.2/TB1CLK
P2.3/TB1TRG
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
Figure 4-6. 38-Pin DBT (TSSOP) (Top View) – MSP430FR215x
12
Terminal Configuration and Functions
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4.2
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Pin Attributes
Table 4-1 lists the attributes of all pins.
Table 4-1. Pin Attributes
PIN NUMBER
PT
1
RHA
40
DBT
5
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE
RESET STATE
AFTER BOR (5)
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
–
UCB0SDA
I/O
LVCMOS
DVCC
–
I
LVCMOS
DVCC
–
SIGNAL NAME (1)
TB0TRG
OA0-
2
3
1
2
6
7
4
3
8
5
4
9
(6)
I
Analog
DVCC
–
A2
I
Analog
DVCC
–
Veref-
I
Analog
DVCC
–
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
I/O
LVCMOS
DVCC
–
ACLK
O
LVCMOS
DVCC
–
OA0O (6)
O
Analog
DVCC
–
COMP0_1
I
Analog
DVCC
–
A1
I
Analog
DVCC
–
P1.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
I/O
LVCMOS
DVCC
–
SMCLK
O
LVCMOS
DVCC
–
COMP0_0
I
Analog
DVCC
–
A0
I
Analog
DVCC
–
Veref+
I
Analog
DVCC
–
TEST (RD)
I
LVCMOS
DVCC
OFF
SBWTCK
I
LVCMOS
DVCC
–
RST (RD)
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
–
N/A
NMI
SBWTDIO
6
5
10
DVCC
P
Power
DVCC
7
6
11
DVSS
P
Power
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
–
P2.7 (RD)
8
7
12
TB0CLK
XIN
9
(1)
(2)
(3)
(4)
(5)
(6)
(2)
8
13
10
9
14
11
10
15
I
LVCMOS
DVCC
–
P2.6 (RD)
I/O
LVCMOS
DVCC
OFF
MCLK
O
LVCMOS
DVCC
–
XOUT
O
LVCMOS
DVCC
–
P2.5 (RD)
I/O
LVCMOS
DVCC
OFF
COMP1.0
I
Analog
DVCC
–
P2.4 (RD)
I/O
LVCMOS
DVCC
OFF
COMP1.1
I
Analog
DVCC
–
Signals names with (RD) denote the reset default pin name.
To determine the pin mux encodings for each pin, see Section 6.11.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
MSP430FR235x devices only
Terminal Configuration and Functions
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
PT
RHA
DBT
12
11
16
13
14
13
17
18
15
14
19
16
–
–
17
–
–
18
–
–
19
–
–
20
–
–
21
15
–
22
23
24
25
26
16
17
18
19
20
–
20
21
22
23
27
21
24
28
22
25
29
14
12
23
26
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE
RESET STATE
AFTER BOR (5)
P4.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
–
UCB1SCL
I/O
LVCMOS
DVCC
–
P4.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
–
UCB1SDA
I/O
LVCMOS
DVCC
–
P4.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
–
P4.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
–
P6.6 (RD)
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
–
P6.5 (RD)
I/O
LVCMOS
DVCC
OFF
TB3.6
I/O
LVCMOS
DVCC
–
P6.4 (RD)
I/O
LVCMOS
DVCC
OFF
TB3.5
I/O
LVCMOS
DVCC
–
P6.3 (RD)
I/O
LVCMOS
DVCC
OFF
TB3.4
I/O
LVCMOS
DVCC
–
P6.2 (RD)
I/O
LVCMOS
DVCC
OFF
TB3.3
I/O
LVCMOS
DVCC
–
P6.1 (RD)
I/O
LVCMOS
DVCC
OFF
TB3.2
I/O
LVCMOS
DVCC
–
P6.0 (RD)
I/O
LVCMOS
DVCC
OFF
TB3.1
I/O
LVCMOS
DVCC
–
P4.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1TXD
O
LVCMOS
DVCC
–
UCA1SIMO
I/O
LVCMOS
DVCC
–
UCA1TXD
O
LVCMOS
DVCC
–
P4.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1RXD
I
LVCMOS
DVCC
–
UCA1SOMI
I/O
LVCMOS
DVCC
–
UCA1RXD
I
LVCMOS
DVCC
–
P4.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1CLK
I/O
LVCMOS
DVCC
–
P4.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1STE
I/O
LVCMOS
DVCC
–
ISOTXD
O
LVCMOS
DVCC
–
ISORXD
I
LVCMOS
DVCC
–
P2.3 (RD)
I/O
LVCMOS
DVCC
OFF
TB1TRG
I
LVCMOS
DVCC
–
P2.2 (RD)
OFF
SIGNAL NAME (1)
TB3CLK
(2)
I/O
LVCMOS
DVCC
TB1CLK
I
LVCMOS
DVCC
–
P2.1(RD)
I/O
LVCMOS
DVCC
OFF
TB1.2
I/O
LVCMOS
DVCC
–
COMP1.O
O
LVCMOS
DVCC
–
Terminal Configuration and Functions
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 4-1. Pin Attributes (continued)
PIN NUMBER
PT
RHA
DBT
30
24
27
31
32
33
25
26
27
28
29
30
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE
RESET STATE
AFTER BOR (5)
P2.0 (RD)
I/O
LVCMOS
DVCC
OFF
TB1.1
I/O
LVCMOS
DVCC
–
COMP0.O
O
LVCMOS
DVCC
–
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
–
UCA0SIMO
I/O
LVCMOS
DVCC
–
TB0.2
I/O
LVCMOS
DVCC
–
TDO
O
LVCMOS
DVCC
–
OA1+ (6)
I
Analog
DVCC
–
A7
I
Analog
DVCC
–
SIGNAL NAME (1)
VREF+
O
Analog
DVCC
–
P1.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
–
UCA0SOMI
I/O
LVCMOS
DVCC
–
TB0.1
I/O
LVCMOS
DVCC
–
TDI
I
LVCMOS
DVCC
–
TCLK
I
LVCMOS
DVCC
–
OA1- (6)
I
Analog
DVCC
–
A6
I
Analog
DVCC
–
P1.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
–
TMS
I
LVCMOS
DVCC
–
OA1O (6)
O
Analog
DVCC
-
A5
34
28
31
35
29
32
36
30
33
37
31
34
38
32
35
39
–
–
40
–
–
I
Analog
DVCC
–
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
–
TCK
I
LVCMOS
DVCC
–
A4
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
P3.7 (RD)
OA3+ (6)
P3.6 (RD)
OA3- (6)
P3.5 (RD)
OA3O (6)
O
Analog
DVCC
–
P3.4 (RD)
I/O
LVCMOS
DVCC
OFF
SMCLK
O
LVCMOS
DVCC
–
P5.4 (RD)
I/O
LVCMOS
DVCC
OFF
P5.3 (RD)
I/O
LVCMOS
DVCC
OFF
TB2TRG
I
LVCMOS
DVCC
–
A11
I
Analog
DVCC
–
P5.2 (RD)
41
–
–
(2)
I/O
LVCMOS
DVCC
OFF
TB2CLK
I
LVCMOS
DVCC
–
A10
I
Analog
DVCC
–
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
PT
42
RHA
33
DBT
36
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE
RESET STATE
AFTER BOR (5)
P5.1 (RD)
I/O
LVCMOS
DVCC
OFF
TB2.2
I/O
LVCMOS
DVCC
–
MFM.TX
O
LVCMOS
DVCC
–
SIGNAL NAME (1)
A9
43
37
44
35
38
45
36
1
46
47
48
16
34
37
38
39
2
3
4
(2)
I
Analog
DVCC
–
P5.0 (RD)
I/O
LVCMOS
DVCC
OFF
TB2.1
I/O
LVCMOS
DVCC
–
MFM.RX
I
LVCMOS
DVCC
–
A8
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
P3.3 (RD)
OA2+ (6)
P3.2 (RD)
OA2- (6)
P3.1 (RD)
OA2O (6)
O
Analog
DVCC
–
P3.0 (RD)
I/O
LVCMOS
DVCC
OFF
MCLK
O
LVCMOS
DVCC
–
P1.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
–
UCB0SCL
I/O
LVCMOS
DVCC
–
OA0+ (6)
I
Analog
DVCC
–
A3
I
Analog
DVCC
–
Terminal Configuration and Functions
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4.3
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
ADC
eCOMP0
eCOMP1
SAC0
SAC1
(2)
(2)
SAC2 (2)
SAC3 (2)
RHA
DBT
PIN
TYPE
A0
3
2
7
I
Analog input A0
A1
2
1
6
I
Analog input A1
A2
1
40
5
I
Analog input A2
A3
48
39
4
I
Analog input A3
A4
34
28
31
I
Analog input A4
A5
33
27
30
I
Analog input A5
A6
32
26
29
I
Analog input A6
A7
31
25
28
I
Analog input A7
A8
43
34
37
I
Analog input A8
A9
42
33
36
I
Analog input A9
A10
41
–
–
I
Analog input A10
A11
40
–
–
I
Analog input A11
Veref+
3
2
7
I
ADC positive reference
Veref-
1
40
5
I
ADC negative reference
C0
3
2
7
I
Comparator input channel C0
C1
2
1
6
I
Comparator input channel C1
COUT
30
24
27
O
Comparator output channel COUT
C0
10
9
14
I
Comparator input channel C0
C1
11
10
15
I
Comparator input channel C1
COUT
29
23
26
O
Comparator output channel COUT
OA0+
48
39
4
I
SAC0, OA positive input
OA0-
1
40
5
I
SAC0, OA negative input
OA0O
2
1
6
O
SAC0, OA output
OA1+
31
25
28
I
SAC1, OA positive input
OA1-
32
26
29
I
SAC1, OA negative input
OA1O
33
27
30
O
SAC1, OA output
OA2+
44
35
38
I
SAC2, OA positive input
OA2-
45
36
1
I
SAC2, OA negative input
OA2O
46
37
2
O
SAC2, OA output
OA3+
35
29
32
I
SAC3, OA positive input
OA3-
36
30
33
I
SAC3, OA negative input
OAO
37
31
34
O
SAC3, OA output
ACLK
2
1
6
O
ACLK output
9
8
13
O
47
38
3
O
SIGNAL NAME
MCLK
Clock
(1)
(2)
PIN NUMBER (1)
PT
FUNCTION
DESCRIPTION
MCLK output
3
2
7
O
38
32
35
O
XIN
8
7
12
I
Input terminal for crystal oscillator
XOUT
9
8
13
O
Output terminal for crystal oscillator
SMCLK
SMCLK output
Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
MSP430FR235x devices only
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
Debug
System
Power
GPIO, Port 1
GPIO, Port 2
GPIO, Port 3
(3)
18
SIGNAL NAME
PIN NUMBER (1)
PIN
TYPE
DESCRIPTION
PT
RHA
DBT
SBWTCK
4
3
8
I
SBWTDIO
5
4
9
I/O
TCK
34
28
31
I
Test clock
TCLK
32
26
29
I
Test clock input
TDI
32
26
29
I
Test data input
TDO
31
25
28
O
Test data output
TMS
33
27
30
I
Test mode select
TEST
4
3
8
I
Test mode pin – selected digital I/O on JTAG pins
NMI
5
4
9
I
Nonmaskable interrupt input
RST
5
4
9
I/O
DVCC
6
5
10
P
Power supply
DVSS
7
6
11
P
Power ground
VREF+
31
25
28
P
Output of positive reference voltage with ground as reference
P1.0
3
2
7
I/O
General-purpose I/O
P1.1
2
1
6
I/O
General-purpose I/O
P1.2
1
40
5
I/O
General-purpose I/O
P1.3
48
39
4
I/O
General-purpose I/O
P1.4
34
28
31
I/O
General-purpose I/O
(3)
(3)
Spy-Bi-Wire input clock
Spy-Bi-Wire data input/output
Reset input, active-low
P1.5
33
27
30
I/O
General-purpose I/O
P1.6
32
26
29
I/O
General-purpose I/O (3)
P1.7
31
25
28
I/O
General-purpose I/O (3)
P2.0
30
24
27
I/O
General-purpose I/O
P2.1
29
23
26
I/O
General-purpose I/O
P2.2
28
22
25
I/O
General-purpose I/O
P2.3
27
21
24
I/O
General-purpose I/O
P2.4
11
10
15
I/O
General-purpose I/O
P2.5
10
9
14
I/O
General-purpose I/O
P2.6
9
8
13
I/O
General-purpose I/O
P2.7
8
7
12
I/O
General-purpose I/O
P3.0
47
38
3
I/O
General-purpose I/O
P3.1
46
37
2
I/O
General-purpose I/O
P3.2
45
36
1
I/O
General-purpose I/O
P3.3
44
35
38
I/O
General-purpose I/O
P3.4
38
32
35
I/O
General-purpose I/O
P3.5
37
31
34
I/O
General-purpose I/O
P3.6
36
30
33
I/O
General-purpose I/O
P3.7
35
29
32
I/O
General-purpose I/O
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
Functions shared with these four pins cannot be debugged if 4-wire JTAG is used for debug.
Terminal Configuration and Functions
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 4-2. Signal Descriptions (continued)
FUNCTION
GPIO, Port 4
GPIO, Port 5
GPIO, Port 6
UART
ISO
SPI
I2C
PIN NUMBER (1)
PT
RHA
DBT
PIN
TYPE
P4.0
26
20
23
I/O
General-purpose I/O
P4.1
25
19
22
I/O
General-purpose I/O
P4.2
24
18
21
I/O
General-purpose I/O
P4.3
23
17
20
I/O
General-purpose I/O
P4.4
15
14
19
I/O
General-purpose I/O
P4.5
14
13
18
I/O
General-purpose I/O
P4.6
13
12
17
I/O
General-purpose I/O
P4.7
12
11
16
I/O
General-purpose I/O
P5.0
43
34
37
I/O
General-purpose I/O
P5.1
42
33
36
I/O
General-purpose I/O
P5.2
41
–
–
I/O
General-purpose I/O
P5.3
40
–
–
I/O
General-purpose I/O
P5.4
39
–
–
I/O
General-purpose I/O
P6.0
22
16
–
I/O
General-purpose I/O
P6.1
21
15
–
I/O
General-purpose I/O
P6.2
20
–
–
I/O
General-purpose I/O
P6.3
19
–
–
I/O
General-purpose I/O
P6.4
18
–
–
I/O
General-purpose I/O
P6.5
17
–
–
I/O
General-purpose I/O
P6.6
16
–
–
I/O
General-purpose I/O
UCA0TXD
31
25
28
O
eUSCI_A0 UART transmit data
UCA0RXD
32
26
29
I
eUSCI_A0 UART receive data
UCA1TXD
23
17
20
O
eUSCI_A1 UART transmit data
UCA1RXD
24
18
21
I
eUSCI_A1 UART receive data
ISOTXD
26
20
23
O
ISO transmit data (the logical AND product of UCA1TXD and
TB3.2B)
ISORXD
26
20
23
I
ISO receive data (to UCA1RXD and TB3.CCI2B)
UCA0STE
34
28
31
I/O
eUSCI_A0 SPI slave transmit enable
UCA0CLK
33
27
30
I/O
eUSCI_A0 SPI clock input/output
UCA0SOMI
32
26
29
I/O
eUSCI_A0 SPI slave out/master in
UCA0SIMO
31
25
28
I/O
eUSCI_A0 SPI slave in/master out
UCA1STE
26
20
23
I/O
eUSCI_A1 SPI slave transmit enable
UCA1CLK
25
19
22
I/O
eUSCI_A1 SPI clock input/output
UCA1SOMI
24
18
21
I/O
eUSCI_A1 SPI slave out/master in
UCA1SIMO
23
17
20
I/O
eUSCI_A1 SPI slave in/master out
UCB0STE
3
2
7
I/O
eUSCI_B0 slave transmit enable
UCB0CLK
2
1
6
I/O
eUSCI_B0 clock input/output
UCB0SIMO
1
40
5
I/O
eUSCI_B0 SPI slave in/master out
UCB0SOMI
48
39
4
I/O
eUSCI_B0 SPI slave out/master in
UCB1STE
15
14
19
I/O
eUSCI_B1 slave transmit enable
UCB1CLK
14
13
18
I/O
eUSCI_B1 clock input/output
UCB1SIMO
13
12
17
I/O
eUSCI_B1 SPI slave in/master out
UCB1SOMI
12
11
16
I/O
eUSCI_B1 SPI slave out/master in
UCB0SCL
48
39
4
I/O
eUSCI_B0 I2C clock
UCB0SDA
1
40
5
I/O
eUSCI_B0 I2C data
UCB1SCL
12
11
16
I/O
eUSCI_B1 I2C clock
UCB1SDA
13
12
17
I/O
eUSCI_B1 I2C data
SIGNAL NAME
DESCRIPTION
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
Timer_B
MFM
20
PIN NUMBER (1)
PT
RHA
DBT
PIN
TYPE
TB0.1
32
26
29
I/O
Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.2
31
25
28
I/O
Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
TB0TRG
1
40
5
I
TB0 external trigger input for TB0OUTH
Timer clock input TBCLK for TB0
FUNCTION
SIGNAL NAME
DESCRIPTION
TB0CLK
8
7
12
I
TB1.1
30
24
27
I/O
Timer TB1 CCR1 capture: CCI1A input, compare: Out1 outputs
TB1.2
29
23
26
I/O
Timer TB1 CCR2 capture: CCI2A input, compare: Out2 outputs
TB1CLK
28
22
25
I
Timer clock input TBCLK for TB1
TB1TRG
27
21
24
I
TB1 external trigger input for TB1OUTH
TB2.1
43
34
37
I/O
Timer TB2 CCR1 capture: CCI1A input, compare: Out1 outputs
TB2.2
42
33
36
I/O
Timer TB2 CCR2 capture: CCI2A input, compare: Out2 outputs
TB2CLK
41
–
–
I
Timer clock input TBCLK for TB2
TB2TRG
40
–
–
I
TB2 external trigger input for TB2OUTH
TB3.1
22
16
–
I/O
Timer TB3 CCR1 capture: CCI1A input, compare: Out1 outputs
TB3.2
21
15
–
I/O
Timer TB3 CCR2 capture: CCI2A input, compare: Out2 outputs
TB3.3
20
–
–
I/O
Timer TB3 CCR3 capture: CCI3A input, compare: Out3 outputs
TB3.4
19
–
–
I/O
Timer TB3 CCR4 capture: CCI4A input, compare: Out4 outputs
TB3.5
18
–
–
I/O
Timer TB3 CCR5 capture: CCI5A input, compare: Out5 outputs
TB3.6
17
–
–
I/O
Timer TB3 CCR6 capture: CCI6A input, compare: Out6 outputs
TB3CLK
16
–
–
I
Timer clock input TBCLK for TB3
TX
42
33
36
O
Manchester function module transmit
RX
43
34
37
I
Manchester function module receive
Terminal Configuration and Functions
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4.4
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and diagrams of the
multiplexed ports, see Section 6.11.
4.5
Buffer Type
Table 4-3 defines the pin buffer types that are listed in Table 4-1.
Table 4-3. Buffer Type
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT DRIVE
STRENGTH
(mA)
LVCMOS
3.0 V
Y (1)
Programmable
See
Section 5.13.5
See
Section 5.13.5
Analog
3.0 V
N
N/A
N/A
N/A
See the analog modules in
Section 5 for details.
Power (DVCC)
3.0 V
N
N/A
N/A
N/A
SVS enables hysteresis on
DVCC.
Power (AVCC)
3.0 V
N
N/A
N/A
N/A
BUFFER TYPE
(STANDARD)
(1)
4.6
OTHER
CHARACTERISTICS
Only for input pins
Connection of Unused Pins
Table 4-4 lists the correct termination of unused pins.
Table 4-4. Connection of Unused Pins (1)
(1)
(2)
PIN
POTENTIAL
Px.0 to Px.7
Open
Set to port function, output direction (PxDIR.n = 1)
COMMENT
RST/NMI
DVCC
47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown (2)
TEST
Open
This pin always has an internal pulldown enabled.
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC pin to VSS
Voltage applied to any pin
(2)
DEVICE
GRADE
MIN
T
–0.3
4.1
V
–0.3
VCC + 0.3
4.1 V Max
V
T
Current across the whole chip including IO currents
T
Diode current at any device pin
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
(3)
MAX
UNIT
+50
mA
T
±2
mA
T
115
°C
125
°C
T
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
over operating free-air temperature range (unless otherwise noted)
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
DEVICE
GRADE
VALUE
T
±1000
T
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.
5.3
Recommended Operating Conditions
(1) (2) (3)
DEVICE
GRADE
MIN
T
1.8
NOM
MAX
VCC
Supply voltage applied at DVCC pin
VSS
Supply voltage applied at DVSS pin
T
TA
Operating free-air temperature
T
–40
TJ
Operating junction temperature
T
–40
CDVCC
Recommended capacitor at DVCC (4)
T
4.7
T
0
8
0
16
0
24 (7)
No FRAM wait states
(NWAITSx = 0)
fSYSTEM
Processor frequency (maximum MCLK frequency) (3) (5)
With FRAM wait states
(NWAITSx = 1) (6)
With FRAM wait states
(NWAITSx = 2) (6)
fACLK
fSMCLK
(1)
(2)
(3)
(4)
(5)
(6)
(7)
22
Maximum ACLK frequency
Maximum SMCLK frequency
T
T
UNIT
3.6
V
105
°C
0
V
115
10
°C
µF
MHz
T
40
kHz
T
(7)
MHz
24
Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-1.
A capacitor tolerance of ±20% or better is required.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
If clock sources such as HF crystals or the DCO with frequencies >24 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
Specifications
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5.4
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Active Mode Supply Current Into VCC Excluding External Current
over operating free-air temperature range (unless otherwise noted) (1)
Frequency (fMCLK = fSMCLK)
PARAMETER
IAM,
EXECUTION
MEMORY
FRAM
0% cache hit ratio
FRAM(0%)
IAM,
FRAM(100%)
FRAM
100% cache hit ratio
IAM,
RAM
(2)
RAM
(1)
(2)
1 MHz
0 WAIT
STATES
(NWAITSx
= 0)
8 MHz
0 WAIT
STATES
(NWAITSx
= 0)
16 MHz
1 WAIT
STATE
(NWAITSx
= 1)
24 MHz
2 WAIT
STATES
(NWAITSx
= 2)
TEST
CONDITIONS
DEVICE
GRADE
TYP MAX
TYP MAX
TYP MAX
TYP MAX
3.0 V, 25°C
T
555
3084
3411
3692
3.0 V, 85°C
T
575
3207
3519
3807
3.0 V, 105°C
T
583
3233
3545
3833
3.0 V, 25°C
T
261
724
1245
1772
3.0 V, 85°C
T
272
742
1267
1800
3.0 V, 105°C
T
283
753
1281
1817
3.0 V, 25°C
T
285
917
1627
2355
UNIT
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5
Active Mode Supply Current Per MHz
VCC = 3.0 V, TA = 25°C (unless otherwise noted)
PARAMETER
dIAM,FRAM/df
(1)
DEVICE
GRADE
TEST CONDITIONS
Active mode current consumption
(IAM, 75% cache hit rate at 8 MHz –
per MHz, execution from FRAM, no wait IAM, 75% cache hit rate at 1 MHz)
states (1)
/ 7 MHz
MIN
T
TYP
MAX
142
UNIT
µA/MHz
All peripherals are turned on in default settings.
5.6
Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
VCC = 3.0 V, TA = 25°C (unless otherwise noted) (1)
(2)
FREQUENCY (fSMCLK)
PARAMETER
ILPM0
(1)
(2)
Low-power mode 0 supply current
VCC
DEVICE
GRADE
1 MHz
8 MHz
16 MHz
24 MHz
TYP MAX
TYP MAX
TYP MAX
TYP MAX
2.0 V
T
199
312
437
637
3.0 V
T
211
324
449
649
UNIT
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
5.7
www.ti.com
Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
DEVIC
E
GRADE
VCC
–40°C
TYP
MAX
25°C
TYP
85°C
MAX
(1)
105°C
TYP
MAX
TYP
MAX
21.85
13.29
47.87
UNIT
ILPM3,XT1
Low-power mode 3,
includes SVS (2) (3) (4)
T
3.0 V
1.21
1.49
6.35
ILPM3,XT1
Low-power mode 3,
includes SVS (2) (3) (4)
T
2.0 V
1.18
1.45
6.28
ILPM3,VLO
Low-power mode 3, VLO,
excludes SVS (5)
T
3.0 V
1.01
1.29
6.15
ILPM3,VLO
Low-power mode 3, VLO,
excludes SVS (5)
T
2.0 V
0.99
1.26
6.09
12.98
µA
ILPM3,
RTC
Low-power mode 3, RTC,
excludes SVS (6)
T
3.0 V
1.15
1.43
6.29
13.24
µA
ILPM3,
RTC
Low-power mode 3, RTC,
excludes SVS (6)
T
2.0 V
1.13
1.41
6.23
13.13
µA
ILPM4,
SVS
Low-power mode 4,
includes SVS
T
3.0 V
0.74
1.00
5.83
12.73
µA
ILPM4,
SVS
Low-power mode 4,
includes SVS
T
2.0 V
0.72
0.98
5.77
12.62
µA
ILPM4,
Low-power mode 4,
excludes SVS
T
3.0 V
0.56
0.82
5.64
12.54
µA
ILPM4,
Low-power mode 4,
excludes SVS
T
2.0 V
0.55
0.81
5.59
12.45
µA
ILPM4, RTC, VLO
Low-power mode 4, RTC is
sourced from VLO,
excludes SVS (7)
T
3.0 V
0.66
0.93
5.76
12.67
µA
ILPM4, RTC, VLO
Low-power mode 4, RTC is
sourced from VLO,
excludes SVS (7)
T
2.0 V
0.66
0.92
5.71
12.58
µA
ILPM4, RTC, XT1
Low-power mode 4, RTC is
sourced from XT1,
excludes SVS (8)
T
3.0 V
1.06
1.34
6.21
13.15
µA
ILPM4, RTC, XT1
Low-power mode 4, RTC is
sourced from XT1,
excludes SVS (8)
T
2.0 V
1.05
1.33
6.16
13.05
µA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
24
13.17
21.65
13.1
µA
µA
47.67
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current
Not applicable for devices with HF crystal oscillator only.
Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
RTC wakes every second with external 32768-Hz clock as source.
Low-power mode 4, VLO, excludes SVS test conditions:
Current for RTC clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Low-power mode 4, XT1, excludes SVS test conditions:
Current for RTC clocked by XT1 included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Specifications
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5.8
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Production Distribution of LPM3 Supply Currents
16
16
14
14
LPM4 Supply Current (µA)
LPM3 Supply Current (µA)
3V LPM3 Supply Currents
12
10
8
6
4
12
10
8
6
4
2
2
0
0
-40 -30 -20 -10 0 10 25 30 40 50 60 70 85 95 105
-40 -30 -20 -10 0 10 25 30 40 50 60 70 85 95 105
Temperature (°C)
Temperature (°C)
Figure 5-1. Population vs Low-Power Mode 3
Supply Current, RTC Enabled With 12.5-pF Crystal,
SVS Enabled
5.9
Figure 5-2. Population vs Low-Power Mode 4
Supply Current, RTC Enabled With 12.5-pF Crystal,
SVS Disabled
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
DEVICE
GRADE
VCC
–40°C
TYP
MAX
25°C
TYP
MAX
85°C
MAX
TYP
MAX
2.06
1.27
3.21
ILPM3.5,
XT1
Low-power mode 3.5,
includes SVS (1) (2) (3)
(also see Figure 5-3)
T
3.0 V
0.57
0.62
0.89
ILPM3.5,
XT1
Low-power mode 3.5,
includes SVS (1) (2) (3)
(also see Figure 5-3)
T
2.0 V
0.55
0.59
0.84
ILPM4.5,
SVS
Low-power mode 4.5,
includes SVS (4)
T
3.0 V
0.27
0.29
0.41
ILPM4.5,
SVS
Low-power mode 4.5,
includes SVS (4)
T
2.0 V
0.25
0.27
0.37
ILPM4.5
Low-power mode 4.5,
excludes SVS (5)
T
3.0 V
0.031
0.042
0.153
ILPM4.5
Low-power mode 4.5,
excludes SVS (5)
T
2.0 V
0.025
0.036
0.128
(1)
(2)
(3)
(4)
(5)
105°C
TYP
1.19
0.63
0.61
0.337
µA
µA
1.13
0.55
0.343
UNIT
µA
µA
0.832
0.289
µA
µA
Not applicable for devices with HF crystal oscillator only
Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3.5, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
www.ti.com
5.10 Production Distribution of LPMx.5 Supply Currents
3V LPMx.5 Supply Currents
0.4
LPM4.5 Supply Current (µA)
LPM3.5 Supply Current (µA)
4
3.5
3
2.5
2
1.5
1
0.5
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0
-40 -30 -20 -10 0 10 25 30 40 50 60 70 85 95 105
-40 -30 -20 -10 0 10 25 30 40 50 60 70 85 95 105
Temperature (°C)
Temperature (°C)
Figure 5-3. LPM3.5 Supply Current vs Temperature, Figure 5-4. LPM4.5 Supply Current vs Temperature,
RTC Enabled With 12.5-pF Crystal, SVS Enabled
RTC Disabled, SVS Disabled
5.11 Typical Characteristics - Current Consumption Per Module
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MODULE
TEST CONDITIONS
REFERENCE CLOCK
Timer_B
DEVICE
GRADE
MIN
TYP
MAX
UNIT
Module input clock
T
5
µA/MHz
eUSCI_A
UART mode
Module input clock
T
7
µA/MHz
eUSCI_A
SPI mode
Module input clock
T
5
µA/MHz
eUSCI_B
SPI mode
Module input clock
T
5
µA/MHz
eUSCI_B
I2C mode, 100 kbaud
Module input clock
T
5
µA/MHz
32 kHz
T
85
nA
MCLK
T
8.5
µA/MHz
RTC
CRC
From start to end of operation
5.12 Thermal Resistance Characteristics
THERMAL METRIC (1)
RθJA
RθJC
RθJB
(1)
(2)
26
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
VALUE (2)
QFP 48 pin (PT)
67.6
QFN 40 pin (RHA)
31.6
TSSOP 38 pin (DBT)
67.0
QFP 48 pin (PT)
24.0
QFN 40 pin (RHA)
24.1
TSSOP 38 pin (DBT)
19.8
QFP 48 pin (PT)
31.6
QFN 40 pin (RHA)
12.6
TSSOP 38 pin (DBT)
27.3
UNIT
ºC/W
ºC/W
ºC/W
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Specifications
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
5.13 Timing and Switching Characteristics
5.13.1 Power Supply Sequencing
Figure 5-5 shows the power cycle and reset conditions.
V
Power Cycle Reset
SVS Reset
VSVS+
BOR Reset
VSVS–
V BOR
t BOR
t
Figure 5-5. Power Cycle, SVS, and BOR Reset Conditions
Table 5-1 lists the characteristics of the SVS and BOR.
Table 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
(1)
DEVICE
GRADE
MIN
T
0.1
V
T
10
ms
VBOR, safe
Safe BOR power-down level
tBOR, safe
Safe BOR reset delay (2)
ISVSH,AM
SVSH current consumption, active mode
VCC = 3.6 V
T
ISVSH,LPM
SVSH current consumption, low-power modes
VCC = 3.6 V
T
VSVSH-
SVSH power-down level (3)
(3)
TYP
MAX
1.5
240
UNIT
µA
nA
T
1.71
1.80
1.87
T
1.76
1.88
1.99
V
VSVSH+
SVSH power-up level
VSVSH_hys
SVSH hysteresis
T
tPD,SVSH, AM
SVSH propagation delay, active mode
T
10
µs
tPD,SVSH, LPM
SVSH propagation delay, low-power modes
T
100
µs
(1)
(2)
(3)
100
V
mV
A safe BOR can only be correctly generated only if DVCC must drop below this voltage before it rises.
When an BOR occurs, a safe BOR can only be correctly generated only if DVCC is kept low longer than this period before it reaches
VSVSH+.
For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
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5.13.2 Reset Timing
Table 5-2 lists the device wake-up times.
Table 5-2. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
VCC
tWAKE-UP FRAM
(Additional) wake-up time to activate
the FRAM in AM if previously
disabled through the FRAM
controller or from a LPM if
immediate activation is selected for
wake-up (1)
T
3V
tWAKE-UP LPM0
Wake-up time from LPM0 to active
mode (1)
T
3V
tWAKE-UP LPM3
Wake-up time from LPM3 to active
mode (1)
T
3V
10
µs
tWAKE-UP LPM4
Wake-up time from LPM4 to active
mode (2)
T
3V
10
µs
tWAKE-UP LPM3.5
Wake-up time from LPM3.5 to
active mode (2)
T
3V
350
µs
tWAKE-UP LPM4.5
Wake-up time from LPM4.5 to
active mode (2)
SVSHE = 1
T
3V
350
µs
SVSHE = 0
T
3V
1
ms
tWAKE-UP-RESET
Wake-up time from RST or BOR
event to active mode (2)
T
3V
1
ms
tRESET
Pulse duration required at RST/NMI
pin to accept a reset
T
PARAMETER
(1)
(2)
28
TEST
CONDITIONS
MIN
TYP
MAX
10
UNIT
µs
200 ns +
2.5 / fDCO
2
µs
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Specifications
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
5.13.3 Clock Specifications
Table 5-3 lists the characteristics of XT1 in low-frequency mode.
Table 5-3. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
fXT1, LF
TEST CONDITIONS
XT1 oscillator crystal, low frequency LFXTBYPASS = 0
DEVICE
GRADE
VCC
MIN
T
TYP
MAX
32768
UNIT
Hz
DCXT1, LF
XT1 oscillator LF duty cycle
Measured at MCLK,
fLFXT = 32768 Hz
fXT1,SW
XT1 oscillator logic-level squarewave input frequency
LFXTBYPASS = 1
DCXT1, SW
LFXT oscillator logic-level squarewave input duty cycle
LFXTBYPASS = 1
T
LFXTBYPASS = 0,
LFXTDRIVE = {3},
fLFXT = 32768 Hz,
CL,eff = 12.5 pF
T
200
kΩ
(6)
1
pF
fOSC = 32768 Hz,
LFXTBYPASS = 0,
LFXTDRIVE = {3},
TA = 25°C,
CL,eff = 12.5 pF
T
1000
ms
XTS = 0 (9)
T
OALFXT
CL,eff
Oscillation allowance for LF crystals
(4)
Integrated effective load
capacitance (5)
tSTART,LFXT Start-up time
fFault,LFXT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
30%
T
70%
32768
40%
(8)
Hz
60%
T
(7)
Oscillator fault frequency
(2) (3)
T
0
3500
Hz
To improve EMI on the LFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
• For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Includes startup counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications may set the
flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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Table 5-4 lists the characteristics of XT1 in high-frequency mode.
Table 5-4. XT1 Crystal Oscillator (High Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
HFXT oscillator
crystal frequency,
crystal mode
fHFXT
TEST CONDITIONS
DEVICE
GRADE
VCC
MIN
TYP
MAX
XT1BYPASS = 0, XTS = 1,
XT1HFFREQ = 00
T
1
4
XT1BYPASS = 0, XTS = 1,
XT1HFFREQ = 01
T
4.01
6
XT1BYPASS = 0, XTS = 1,
XT1HFFREQ = 10
T
6.01
16
XT1BYPASS = 0, XTS = 1,
XT1HFFREQ = 11
T
16.01
24
T
1
24
MHz
fHFXT,SW
HFXT oscillator
logic-level squarewave input
frequency, bypass
mode
XT1BYPASS = 1, XTS = 1
DCHFXT
HFXT oscillator duty
cycle.
Measured at ACLK
fHFXT,HF = 4 MHz (4)
T
40%
60%
HFXT oscillator
logic-level squarewave input duty
cycle
XT1BYPASS = 1
T
40%
60%
DCHFXT,
SW
OAHFXT
UNIT
(2) (3)
Oscillation allowance XT1BYPASS = 0, XT1HFSEL = 1
for HFXT crystals (5) fHFXT,HF = 24 MHz, CL,eff = 18 pF
T
3.1
fOSC = 4 MHz, XTS = 1
XT1BYPASS = 0, XT1HFFREQ = 00,
XT1DRIVE = 3, TA = 25°C,
CL,eff = 18 pF
T
1.6
fOSC = 24 MHz, XTS = 1 (4)
XT1BYPASS = 0, XT1HFFREQ = 00,
XT1DRIVE = 3, TA = 25°C,
CL,eff = 18 pF
T
1.1
T
1
MHz
Ω
(4)
tSTART,HFXT
Start-up time (6)
CL,eff
Integrated effective
load capacitance (7)
fFault,HFXT
Oscillator fault
frequency (9) (10)
(8)
ms
T
0
pF
800
kHz
(1)
To improve EMI on the HFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCHFXT, SW.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) 4-MHz crystal use for lab characterization: Abracon HC49/U AB-4.000MHZ-B2, 16MHz crystal use for lab characterization: Abracon
HC49/U AB-16.000MHZ-B2
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes startup counter of 4096 clock cycles.
(7) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the oscillator frequency through
MCLK or SMCLK. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 14
pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
(9) Frequencies above the MAX secification do not set the fault flag. Frequencies in between the MIN and MAX might set the flag. A static
condition or stuck at fault condition sets the flag.
(10) Measured with logic-level input fequency but also applieds to operation with crystals.
30
Specifications
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 5-5 lists the frequency characteristics of the DCO FLL.
Table 5-5. DCO FLL, Frequency
Over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
VCC
MIN
TYP
MAX
fDCO,
FLL
FLL lock frequency, 24 MHz, 25°C
Measured at MCLK, internal
trimmed REFO as reference
T
3.0 V
–1.0%
1.0%
fDCO,
FLL
FLL lock frequency, 24 MHz
Measured at MCLK, internal
trimmed REFO as reference
T
3.0 V
–2.0%
2.0%
fDCO,
FLL
FLL lock frequency, 24 MHz
Measured at MCLK, XT1
crystal as reference
T
3.0 V
–0.5%
0.5%
fDUTY
Duty cycle
Measured at MCLK, XT1
crystal as reference
T
3.0 V
40%
Jittercc
Cycle-to-cycle jitter, 24 MHz
Measured at MCLK, XT1
crystal as reference
T
3.0 V
0.50%
Jitterlong
Long-term Jitter, 24 MHz
Measured at MCLK, XT1
crystal as reference
T
3.0 V
0.022%
tFLL, lock
FLL lock time
Measured at MCLK, XT1
crystal as reference
T
3.0 V
200
50%
UNIT
60%
ms
Table 5-6 lists the frequency characteristics of the DCO.
Table 5-6. DCO Frequency
Over recommended operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
VCC
DCORSEL = 111b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
3.0 V
12.6
DCORSEL = 111b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
T
3.0 V
20.5
DCORSEL = 111b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
T
3.0 V
29.9
DCORSEL = 111b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
T
3.0 V
48.2
DCORSEL = 110b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
3.0 V
10.5
DCORSEL = 110b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
T
3.0 V
17.2
DCORSEL = 110b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
T
3.0 V
25.1
DCORSEL = 110b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
T
3.0 V
40.4
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
3.0 V
8.3
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
T
3.0 V
13.6
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
T
3.0 V
19.9
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
T
3.0 V
32.2
PARAMETER
fDCO,
fDCO,
fDCO,
24MHz
20MHz
16MHz
DCO frequency 24 MHz
DCO frequency 20 MHz
DCO frequency 16 MHz
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
MHz
MHz
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Table 5-6. DCO Frequency (continued)
Over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
fDCO,
fDCO,
fDCO,
fDCO,
fDCO,
32
12MHz
8MHz
4MHz
2MHz
1MHz
DCO frequency 12 MHz
DCO frequency 8 MHz
DCO frequency 4 MHz
DCO frequency 2 MHz
DCO frequency 1 MHz
Specifications
DEVICE
GRADE
VCC
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
3.0 V
6.2
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
T
3.0 V
10.2
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
T
3.0 V
15
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
T
3.0 V
24.3
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
3.0 V
4.2
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
T
3.0 V
6.9
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
T
3.0 V
10
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
T
3.0 V
16.4
DCORSEL = 010b,, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
3.0 V
2
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
T
3.0 V
3.4
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
T
3.0 V
5
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
T
3.0 V
8.2
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
3.0 V
1
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
T
3.0 V
1.7
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
T
3.0 V
2.5
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
T
3.0 V
4.2
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
T
3.0 V
0.5
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
T
3.0 V
0.85
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
T
3.0 V
1.2
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
T
3.0 V
2.1
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
MHz
MHz
MHz
MHz
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
50
DCOFTRIM = 7
40
DCOFTRIM = 7
Frequency (MHz)
DCOFTRIM = 7
30
DCOFTRIM = 7
20
DCOFTRIM = 7
DCOFTRIM = 0
10
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 7
0
DCO
DCORSEL
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 0
0
511
0
(1MHz)
DCOFTRIM = 0
0
511
1
(2MHz)
0
511
2
(4MHz)
0
511
3
(8MHz)
0
511
4
(12MHz)
0
511
5
(16MHz)
0
511
6
(20MHz)
0
511
7
(24MHz)
Figure 5-6. Typical DCO Frequency
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Table 5-7 lists the characteristics of the REFO.
Table 5-7. REFO
over recommended operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
DEVICE
GRADE
VCC
REFO oscillator current
consumption
TA = 25°C, HP mode (REFLP = 0)
T
3.0 V
15
REFO oscillator current
consumption
TA = 25°C, LP mode (REFLP = 1)
T
3.0 V
1
REFO calibrated
frequency
Measured at MCLK
T
3.0 V
32768
REFO absolute
calibrated tolerance
–40°C to 105°C
T
1.8 V to
3.6 V
dfREFO/dT
REFO frequency
temperature drift
Measured at MCLK (1)
T
3.0 V
dfREFO/dVCC
REFO frequency supply
voltage drift
Measured at MCLK at 25°C (2)
T
1.8 V to
3.6 V
fDC
REFO duty cycle
Measured at MCLK
T
1.8 V to
3.6 V
40% to 60% duty cycle, HP mode
(REFLP = 0)
T
3.0 V
72
40% to 60% duty cycle, LP mode
(REFLP = 1)
T
3.0 V
75
PARAMETER
IREFO
fREFO
tSTART
(1)
(2)
REFO start-up time
MIN
TYP
MAX
UNIT
µA
Hz
–3.5%
40%
+3.5%
0.01
%/°C
1
%/V
50%
60%
µs
Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-8 lists the characteristics of the VLO.
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
VCC
MIN
TYP
MAX
UNIT
fVLO
VLO frequency
Measured at MCLK
T
3.0 V
10
kHz
dfVLO/dT
VLO frequency temperature drift
Measured at MCLK (1)
T
3.0 V
0.5
%/°C
dfVLO/dVCC VLO frequency supply voltage drift
Measured at MCLK (2)
T
1.8 V to
3.6 V
4
%/V
fVLO,DC
Measured at MCLK
T
3.0 V
(1)
(2)
Duty cycle
50%
Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
NOTE
The VLO clock frequency is reduced by 15% (typical) when the device switches from active
mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a
violation of the VLO specifications (see Table 5-8).
34
Specifications
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Table 5-9 lists the characteristics of the MODOSC.
Table 5-9. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
DEVICE
GRADE
VCC
MIN
3.0
TYP
MAX
3.8
4.6
UNIT
fMODOSC
MODOSC frequency
T
3.0 V
fMODOSC/dT
MODOSC frequency temperature drift (1)
T
3.0 V
0.102
%/℃
fMODOSC/dVCC
MODOSC frequency supply voltage drift
T
1.8 V to
3.6 V
1.17
%/V
fMODOSC,DC
Duty cycle
T
3.0 V
(1)
40%
50%
MHz
60%
Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
5.13.4 Internal Shared Reference
Table 5-10 lists the characteristics of the internal shared reference.
Table 5-10. Internal Shared Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
VCC
2.0 V,
3.0 V
VSENSOR
Temperature sensor
voltage
TJ = 30℃
T
TCSENSOR
Temperature sensor
coefficient
TJ = 30℃
T
VeCOMP,
Low-power threshold
for eCOMP
TJ = 30℃
T
Positive output
TJ = 30℃
reference at VREF+ pin
VREF+,
LP
Output
VREF+, built-in
Positive built-in
reference voltage as
internal reference
(1)
MIN
TYP
MAX
UNIT
788
mV
2.32
mV/°C
2.0 V,
3.0 V
1.20
V
T
2.0 V,
3.0 V
1.20
V
REFVSEL = {2} for 2.5 V,
INTREFEN = 1
T
3.0 V
2.5
±1.5%
REFVSEL = {1} for 2.0 V,
INTREFEN = 1
T
2.5 V
2.0
±1.5%
REFVSEL = {0} for 1.5 V,
INTREFEN = 1
T
1.8 V
1.5
±1.8%
From 0.1 Hz to 10 Hz,
REFVSEL = {0}
T
30
130
µV
V
Noise
RMS noise at VREF
VOS_BUF_INT
VREF ADC BUF_INT
buffer offset (2)
TA = 25 °C , ADC ON,
REFVSEL = {0}, INTREFEN = 1,
EXTREFEN=0
T
–16
+16
mV
VOS_BUF_EXT
VREF ADC BUF_EXT
buffer offset (3)
TA = 25 °C, REFVSEL = {0} ,
EXTREFEN = 1,
INTREFEN = 1 or ADC ON
T
–16
+16
mV
REFVSEL = {0} for 1.5 V
DVCC minimum
voltage, Positive built-in REFVSEL = {1} for 2.0 V
reference active
REFVSEL = {2} for 2.5 V
T
1.8
DVCC(min)
T
2.2
T
2.7
V
IREF+
Operating supply
current into DVCC
terminal (4)
INTREFEN = 1
T
3V
19
26
µA
IREF+_ADC_BUF
Operating supply
current into DVCC
terminal (4)
ADC ON, EXTREFEN = 0,
REFVSEL = {0, 1, 2}
T
3V
247
400
µA
(1)
(2)
(3)
(4)
Internal reference noise affects ADC performance when ADC uses internal reference.
Buffer offset affects ADC gain error and thus total unadjusted error.
Buffer offset affects ADC gain error and thus total unadjusted error.
The internal reference current is supplied through the DVCC terminal.
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Table 5-10. Internal Shared Reference (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REFVSEL = {0, 1, 2}, DVCC =
DVCC(min) for each reference
level,
INTREFEN = EXTREFEN = 1
DEVICE
GRADE
VCC
MIN
T
3V
–1000
TYP
MAX
UNIT
+10
µA
1500
µV/mA
100
pF
IO(VREF+)
VREF maximum load
current, VREF+
terminal
ΔVout/
ΔIo(VREF+)
REFVSEL = {0, 1, 2},
I
= +10 µA or –1000 µA,
Load-current regulation, O(VREF+)
DVCC = DVCC(min) for each
VREF+ terminal
reference level,
INTREFEN = EXTREFEN = 1
T
3V
CVREF+/-
Capacitance at VREF+
and VREF- terminals
INTREFEN = EXTREFEN = 1
T
3V
TCREF+
REFVSEL = {0, 1, 2},
Temperature coefficient
INTREFEN = EXTREFEN = 1,
of built-in reference
TA = –40°C to 105°C (5)
T
3V
24
50
ppm/K
PSRR_DC
Power supply rejection
ratio (DC)
DVCC = DVCC (min) to DVCC(max),
TA = 25°C, REFVSEL = {0, 1, 2},
INTREFEN = EXTREFEN = 1
T
3V
100
400
µV/V
PSRR_AC
Power supply rejection
ratio (ac)
dDVCC= 0.1 V at 1 kHz
T
3V
3.0
tSETTLE
Settling time of
reference voltage (6)
DVCC = DVCC (min) to DVCC(max),
REFVSEL = {0, 1, 2},
INTREFEN = 0 → 1
T
3V
75
(5)
(6)
36
0
mV/V
100
µs
Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
Specifications
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5.13.5 General-Purpose I/Os
Table 5-11 lists the characteristics of the digital inputs.
Table 5-11. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
VCC
MIN
T
2.0 V
0.90
1.50
T
3.0 V
1.35
2.25
T
2.0 V
0.50
1.10
T
3.0 V
0.75
1.65
T
2.0 V
0.3
0.8
T
3.0 V
0.4
1.2
TYP
MAX
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
T
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
T
3
pF
CI,ana
Input capacitance, port pins with shared
analog functions
VIN = VSS or VCC
T
5
pF
Ilkg(Px.y)
High-impedance leakage current (1) (2)
t(int)
External interrupt timing (external trigger
pulse duration to set interrupt flag) (3)
(1)
(2)
(3)
Ports with interrupt
capability (see
Section 1.4 and
Section 4.3)
20
T
2.0 V,
3.0 V
–30
T
2.0 V,
3.0 V
50
35
50
+30
V
V
V
kΩ
nA
ns
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Table 5-12 lists the characteristics of the digital outputs.
Table 5-12. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
DEVICE
GRADE
VCC
MIN
I(OHmax) = –3 mA (1)
T
2.0 V
1.4
2.0
(1)
T
3.0 V
2.4
3.0
I(OLmax) = 3 mA (1)
T
2.0 V
0.0
0.60
I(OLmax) = 5 mA (1)
T
3.0 V
0.0
0.60
Applicable to all IO ports, CL = 20
pF (2)
T
2.0 V
16
T
3.0 V
16
IOs multiplexed with MCLK and
SMCLK, CL = 10 pF (2)
T
2.0 V
24
T
3.0 V
24
T
2.0 V
10
T
3.0 V
7
T
2.0 V
10
T
3.0 V
5
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
I(OHmax) = –5 mA
fPort_CLK Clock output frequency
trise,dig
Port output rise time, digital
only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital
only port pins
CL = 20 pF
(1)
(2)
TYP
MAX
UNIT
V
V
MHz
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The port can output frequencies at least up to the specified limit and might support higher frequencies.
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5.13.6 Digital I/O Typical Characteristics
25
10
Low-Level Output Current (mA)
Low-Level Output Current (mA)
20
15
10
TA = -40°C
TA = 25°C
5
TA = 85°C
7.5
5
TA = -40°C
2.5
TA = 25°C
TA = 85°C
TA = 105°C
TA = 105°C
0
0
0
0.5
1
1.5
2
2.5
0
3
0.25
0.5
Figure 5-7. Typical Low-Level Output Current
vs
Low-Level Output Voltage
1.5
1.75
2
Figure 5-8. Typical Low-Level Output Current
vs
Low-Level Output Voltage
0
0
TA = -40°C
TA = -40°C
TA = 25°C
High-Level Output Current (mA)
TA = 25°C
-5
High-Level Output Current (mA)
1.25
DVCC = 2 V
DVCC = 3 V
TA = 85°C
-10
TA = 105°C
-15
-20
-25
-2.5
TA = 85°C
TA = 105°C
-5
-7.5
-10
-30
0
0.5
1
1.5
2
2.5
High-Level Output Voltage (V)
DVCC = 3 V
Figure 5-9. Typical High-Level Output Current
vs
High-Level Output Voltage
38
1
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
-
0.75
Specifications
3
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
High-Level Output Voltage (V)
DVCC = 2 V
Figure 5-10. Typical High-Level Output Current
vs
High-Level Output Voltage
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5.13.7 Timer_B
Table 5-13 lists the frequency characteristics of Timer_B.
Table 5-13. Timer_B Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fTB
TEST CONDITIONS
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
DEVICE
GRADE
VCC
T
2.0 V,
3.0 V
MIN
TYP
MAX
UNIT
24
MHz
MAX
UNIT
5.13.8 eUSCI
Table 5-14 lists the supported frequencies of the eUSCI in UART mode.
Table 5-14. eUSCI (UART Mode) Clock Frequencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in Mbaud)
Internal: SMCLK or MODCLK,
External: UCLK,
Duty cycle = 50% ±10%
DEVICE
GRADE
VCC
T
2.0 V,
3.0 V
24
MHz
T
2.0 V,
3.0 V
5
MHz
MAX
UNIT
MIN
TYP
Table 5-15 lists the switching characteristics of the eUSCI in UART mode.
Table 5-15. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
VCC
MIN
UCGLITx = 0
tt
UART receive deglitch time
(1)
UCGLITx = 1
UCGLITx = 2
12
T
2.0 V,
3.0 V
UCGLITx = 3
(1)
TYP
40
68
ns
110
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
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Table 5-16 lists the supported frequencies of the eUSCI in SPI master mode.
Table 5-16. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCI
eUSCI input clock frequency
TEST CONDITIONS
DEVICE
GRADE
Internal: SMCLK,
Duty cycle = 50% ±10%
VCC
MIN
TYP
MAX
UNIT
8
MHz
T
Table 5-17 lists the switching characteristics of the eUSCI in SPI master mode.
Table 5-17. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
T
1
UCxCLK
cycles
tSTE,LAG
STE lag time, Last clock to STE
inactive
UCSTEM = 1,
UCMODEx = 01 or 10
T
1
UCxCLK
cycles
tSU,MI
SOMI input data setup time
T
tHD,MI
SOMI input data hold time
T
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO
valid,
CL = 20 pF
T
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
T
(1)
(2)
(3)
40
2.0 V
60
3.0 V
42
2.0 V
0
3.0 V
0
ns
ns
2.0 V
20
3.0 V
20
2.0 V
–9.0
3.0 V
–6.0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-11 and Figure 5-12.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 511 and Figure 5-12.
Specifications
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-12. SPI Master Mode, CKPH = 1
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Table 5-18 lists the switching characteristics of the eUSCI in SPI slave mode.
Table 5-18. eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
tSTE,LEAD
STE lead time, STE active to clock
T
tSTE,LAG
STE lag time, last clock to STE
inactive
T
tSTE,ACC
STE access time, STE active to SOMI
data out
T
tSTE,DIS
STE disable time, STE inactive to
SOMI high impedance
T
tSU,SI
SIMO input data setup time
T
tHD,SI
SIMO input data hold time
T
tVALID,SO
SOMI output data valid time (2)
tHD,SO
SOMI output data hold time
(1)
(2)
(3)
42
(3)
UCLK edge to SOMI valid,
CL = 20 pF
T
CL = 20 pF
T
VCC
MIN
2.0 V
55
3.0 V
45
2.0 V
20
3.0 V
20
TYP
MAX
ns
ns
2.0 V
65
3.0 V
40
2.0 V
40
3.0 V
35
2.0 V
10
3.0 V
6
2.0 V
12
3.0 V
12
69
42
5
5
ns
ns
3.0 V
3.0 V
ns
ns
2.0 V
2.0 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13
and Figure 5-14.
Specifications
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tVALID,SOMI
tACC
tDIS
SOMI
Figure 5-13. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tVALID,SO
tDIS
SOMI
Figure 5-14. SPI Slave Mode, CKPH = 1
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Table 5-19 lists the switching characteristics of the eUSCI in I2C mode.
Table 5-19. eUSCI (I2C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
VCC
Internal: SMCLK or MODCLK,
External: UCLK
Duty cycle = 50% ±10%
T
2.0 V,
3.0 V
T
2.0 V,
3.0 V
T
2.0 V,
3.0 V
4.0
T
2.0 V,
3.0 V
4.7
MIN
TYP
MAX
UNIT
24
MHz
400
kHz
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated
START
tHD,DAT
Data hold time
T
2.0 V,
3.0 V
0
ns
tSU,DAT
Data setup time
T
2.0 V,
3.0 V
250
ns
tSU,STO
Setup time for STOP
T
2.0 V,
3.0 V
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
Pulse duration of spikes
suppressed by input filter
tSP
fSCL = 100 kHz
0
4.0
µs
0.6
UCGLITx = 0
50
600
ns
UCGLITx = 1
25
300
ns
12.5
150
ns
T
UCGLITx = 2
2.0 V,
3.0 V
6.3
UCCLTOx = 1
Clock low time-out
µs
0.6
UCGLITx = 3
tTIMEOUT
µs
0.6
UCCLTOx = 2
T
2.0 V,
3.0 V
UCCLTOx = 3
tSU,STA
tHD,STA
75
ns
36
ms
40
ms
44
ms
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-15. I2C Mode Timing
44
Specifications
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
5.13.9 ADC
Table 5-20 lists the input characteristics of the ADC.
Table 5-20. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
DVCC
ADC supply voltage (1)
V(Ax)
Analog input voltage range
All ADC pins
IADC
Operating supply current into
DVCC terminal, reference
current not included, repeatsingle-channel mode
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0,
SHT1 = 0, ADCDIV = 0,
ADCCONSEQx = 10b
T
CI
Input capacitance
Only one terminal Ax can be
selected at one time from the
pad to the ADC capacitor
array, including wiring and pad
T
RI
Input MUX ON resistance
DVCC = 2 V, 0 V = VAx = DVCC
T
(1)
VCC
MIN
TYP
MAX
UNIT
T
2.0
3.6
V
T
0
DVCC
V
2.0 V
185
3.0 V
280
2.2 V
4.5
µA
5.5
pF
2
kΩ
This specifies the ADC functional range with 8-bit resolution at 8-bit ENOB. Table 5-22 specifies 10- and 12-bit linearity parameters for
better ENOB requirements.
Table 5-21 lists the timing parameters of the ADC.
Table 5-21. ADC, Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC clock
fADCCLK frequency
tSettling
tSample
(1)
ADC clock, 10-bit mode
ADC clock, 12-bit mode
Turn-on settling
time of the ADC (1)
Sampling time
DEVICE
GRADE
VCC
T
2.4 V to
3.6 V
The error in a conversion started after
tADCON is less than ±0.5 LSB,
Reference and input signal already settled
T
RS = 1000 Ω, RI = 4000 Ω,
CI = 5.5 pF, Cexternal = 8.0 pF,
Approximately 7.62 Tau (t) are required for
an error of less than ±0.5 LSB, 10-bit mode
T
RS = 1000 Ω, RI = 4000 Ω,
CI = 5.5 pF, Cexternal = 8.0 pF,
Approximately 9.01 Tau (t) are required for
an error of less than ±0.5 LSB, 12-bit mode
T
MIN
TYP
MAX
6.0
4.4
100
2.4 V to
3.6 V
UNIT
MHz
ns
0.52
µs
2.4 V to
3.6 V
0.61
This excludes the ADC conversion time. The ADC conversion time is specified as (N + 2) × ADCDIV × 1/fADCCLK.
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Table 5-22 lists the linearity parameters of the ADC.
Table 5-22. ADC, Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
EI
ED
EO
EG
ET
46
TEST CONDITIONS
Integral linearity error(12-bit mode)
Veref+ reference
Integral linearity error (10-bit mode)
Veref+ reference
Differential linearity error(12-bit mode)
Veref+ reference
Differential linearity error (10-bit mode)
Veref+ reference
Offset error(12-bit mode)
Veref+ reference
Offset error (10-bit mode)
Veref+ reference
Gain error (12-bit mode)
Veref+ as reference
Gain error (10-bit mode)
Veref+ as reference
Total unadjusted error (12-bit mode)
Veref+ as reference
Total unadjusted error (10-bit mode)
Veref+ as reference
Specifications
DEVICE
GRADE
VCC
MIN
T
2.4 V to
3.6 V
–2.5
2.5
–2
2
T
2.4 V to
3.6 V
–1
1
–1
1
T
2.4 V to
3.6 V
–1.5
1.5
–6.0
6.0
T
2.4 V to
3.6 V
–3.0
3.0
–1.5
1.5
T
2.4 V to
3.6 V
–4.0
4.0
–2.0
2.0
TYP
MAX
UNIT
LSB
LSB
mV
LSB
LSB
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
5.13.10 Enhanced Comparator (eCOMP)
Table 5-23 lists the characteristics of eCOMP0.
Table 5-23. eCOMP0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
MIN
TYP
MAX
UNIT
VCC
Supply voltage
T
2.0
3.6
V
VIC
Common mode input range
T
0
VCC
V
CPEN = 1, CPHSEL= 00
VHYS
DC input hysteresis
CPEN = 1, CPHSEL= 01
CPEN = 1, CPHSEL= 10
0
10
T
CPEN = 1, CPHSEL= 11
VOFFSET
Input offset voltage
ICOMP
Quiescent current draw from
VCC, only Comparator
CIN
Input channel capacitance (1)
CPEN = 1, CPMSEL = 0
CPEN = 1, CPMSEL = 1
VIC = VCC/2, CPEN = 1, CPMSEL = 0
VIC = VCC/2, CPEN = 1, CPMSEL = 1
RIN
Input channel series
resistance
tPD
CPMSEL = 0, CPFLT = 0,
Propagation delay, response Overdrive = 20 mV
time
CPMSEL = 1, CPFLT = 0,
Overdrive = 20 mV
tEN_CP
tEN_CP_DAC
Comparator enable time
Comparator with reference
DAC enable time
30
T
–30
+30
–40
+40
T
T
On (switch closed)
Off (switch open)
CPEN = 0→1, CPMSEL = 0,
V+ and V- from pads, Overdrive = 20 mV
CPEN = 0→1, CPMSEL = 1,
V+ and V- from pads, Overdrive = 20 mV
T
tFDLY
CPMSEL = 0, CPFLTDY = 01,
Overdrive = 20 mV, CPFLT = 1
CPMSEL = 0, CPFLTDY = 10,
Overdrive = 20 mV, CPFLT = 1
35
5
1
mV
µA
pF
20
50
kΩ
MΩ
1
T
µs
3.2
8.5
T
µs
1.4
8.5
T
µs
101
CPMSEL = 0, CPFLTDY = 00,
Overdrive = 20 mV, CPFLT = 1
Propagation delay with
analog filter active
24
1.6
10
CPEN = 0→1, CPDACEN = 0→1,
CPMSEL = 0, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV
CPEN = 0→1, CPDACEN = 0→1,
CPMSEL = 1,
CPDACREFS = 1, CPDACBUF1 = 0F,
Overdrive = 20 mV
mV
20
0.7
1.1
T
µs
1.9
CPMSEL = 0, CPFLTDY = 11,
Overdrive = 20 mV, CPFLT = 1
3.4
INL
Integral nonlinearity
T
–0.5
0.5
LSB
DNL
Differential nonlinearity
T
–0.5
0.5
LSB
(1)
For details on the eCOMP CIN, model , see Figure 5-16.
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Table 5-24 lists the characteristics of eCOMP1.
Table 5-24. eCOMP1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
MIN
TYP
MAX
UNIT
VCC
Supply voltage
T
2.0
3.6
V
VIC
Common mode input range
T
0
VCC
V
CPEN = 1, CPHSEL= 00
VHYS
0
CPEN = 1, CPHSEL= 01
DC input hysteresis
10
T
CPEN = 1, CPHSEL= 10
CPEN = 1, CPHSEL= 11
Input offset voltage
ICOMP
Quiescent current draw from
VCC, only Comparator
CIN
Input channel capacitance (1)
RIN
Propagation delay, response
time
tEN_CP
VIC = VCC/2, CPEN = 1, CPMSEL = 0
VIC = VCC/2, CPEN = 1, CPMSEL = 1
+30
–40
+40
T
T
Off (switch open)
CPMSEL = 0, CPFLT = 0,
Overdrive = 20 mV, DVCC = 3.0 V
CPMSEL = 1, CPFLT = 0,
Overdrive = 20 mV
tFDLY
DNL
(1)
30
1
µA
pF
5
50
kΩ
MΩ
0.1
T
µs
CPEN = 0→1, CPDACEN = 0→1,
CPMSEL = 0, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV
CPEN = 0→1, CPDACEN = 0→1,
CPMSEL = 1, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV
8.5
T
µs
4.8
8.5
T
µs
101
CPMSEL = 0, CPFLTDY = 01,
Overdrive = 20 mV, CPFLT = 1
CPMSEL = 0, CPFLTDY = 10,
Overdrive = 20 mV, CPFLT = 1
150
350
T
ns
1000
CPMSEL = 0, CPFLTDY = 11,
Overdrive = 20 mV, CPFLT = 1
INL
209
20
1
CPMSEL = 0, CPFLTDY = 00,
Overdrive = 20 mV, CPFLT = 1
Propagation delay with analog
filter active
162
mV
0.32
CPEN = 0→1, CPMSEL = 1,
V+ and V- from pads, Overdrive = 20 mV
Comparator with reference DAC
enable time
–30
T
On (switch closed)
CPEN = 0→1, CPMSEL = 0,
V+ and V- from pads, Overdrive = 20 mV
Comparator enable time
tEN_CP_DAC
T
CPEN = 1, CPMSEL = 1
Input channel series resistance
tPD
30
CPEN = 1, CPMSEL = 0
VOFFSET
mV
20
1900
Integral nonlinearity
T
–0.5
0.5
LSB
Differential nonlinearity
T
–0.5
0.5
LSB
For details on the eCOMP CIN, model, see Figure 5-16.
MSP430
RS
RI
VI
VC
Cpext
CPAD
CIN
VI = External source voltage
RS = External source resistance
RI = Internal MUX-on input resistance
CIN = Input capacitance
CPAD = PAD capacitance
CPext = Parasitic capacitance, external
VC = Capacitance-charging voltage
Figure 5-16. eCOMP Input Circuit
48
Specifications
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
5.13.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
Table 5-25 lists the characteristics of the SAC OA.
Table 5-25. SAC, OA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
MIN
TYP
MAX
VCC
Supply voltage
T
2.0
3.6
VOS
Input offset voltage
T
–5
5
dVOS/dT
Offset drift
IB
Input bias current
OAPM = 0 (1)
OAPM = 1
VCM
Input voltage range
IIDD
Quiescent current
Input noise voltage
ENI
(1)
T
OAPM = 0
OAPM = 1
f = 1 kHz, Vin = VCC/2, OAPM = 0
f = 10 kHz, Vin = VCC/2, OAPM = 0
PSRR
Power supply rejection ratio
GBW
Gain-bandwidth
AOL
Open-loop voltage gain
φM
Phase margin
Positive slew rate
OAPM = 0
OAPM = 1
OAPM = 0
OAPM = 1
OAPM = 0
OAPM = 1
OAPM = 0
OAPM = 1
CL = 50 pF , RL = 2 kΩ
CL = 50 pF, OAPM = 0, step = 1
CL = 50 pF, OAPM = 1, step = 1
350
40
T
70
70
T
2.8
100
T
65
T
RL = 10 kΩ
T
40
(1)
V/µs
1
VO
All gains
deg
3
3
Total harmonic distortion
dB
100
T
THD
MHz
1.0
Common mode
To 0.1% final value, G = +1, 1-V setup
CL = 50 pF, OAPM = 1
dB
80
T
T
dB
80
Voltage output swing from
supply rails
OA settling time
nV/Hz
28
Input capacitance
tST
nV
64
T
V
µA
120
Cin
To 0.1% final value, G = +1, 1-V setup
CL = 50 pF, OAPM = 0
pA
VCC +
0.1
f = 0.1 Hz to 10 Hz,
Vin = VCC/2, OAPM = 0
Input noise voltage
Common-mode rejection ratio
T
50
–0.1
V
mV
µV/℃
5
T
Input noise voltage density
CMRR
3
T
UNIT
pF
100
mV
1
T
µs
4.5
T
–60
dB
Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
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Table 5-25. SAC, OA (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Gclose loop
PGA closed-loop gain
DEVICE
GRADE
MIN
TYP
MAX
Gain = 1, inverting mode, follower mode
T
0.99
1
1.01
Gain = 2, noninverting mode
T
1.98
2
2.02
Gain = 2, inverting mode
T
1.98
2
2.02
Gain = 3, noninverting mode
T
2.97
3
3.03
Gain = 4, inverting mode
T
3.96
4
4.04
Gain = 5, noninverting mode
T
4.95
5
5.05
Gain = 8, inverting mode
T
7.92
8
8.08
Gain = 9, noninverting mode
T
8.91
9
9.09
Gain = 16, inverting mode
T
15.84
16
16.16
Gain = 17, noninverting mode
T
16.83
17
17.17
Gain = 25, inverting mode
T
24.75
25
25.25
Gain = 26, noninverting mode
T
25.74
26
26.26
Gain = 32, inverting mode
T
31.68
32
32.32
Gain = 33, noninverting mode
T
32.67
33
33.33
TYP
MAX
TEST CONDITIONS
UNIT
Table 5-26 lists the characteristics of the SAC DAC.
Table 5-26. SAC, DAC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
GRADE
MIN
2.4
VCC
Supply voltage
T
IIDDR
Quiescent current of resistor
ladder into VREF_INT
T
IIOAD
OA + DAC output load current
tST(FS)
OA + DAC settling time, full
scale
DACDAT =
0x80h→0xF7Fh→0x80h
OAPM = 1
tST(C-C)
DACDAT =
0x3F8h→408h→0x3F8h
or
DACDAT =
0xBF8h→C08h→0xBF8h
OAPM = 1
OA + DAC settling time, code
to code
INL
OA + DAC integral nonlinearity DACSREF = DVCC, DVCC = 3.0 V
T
–4
4
LSB
DNL
OA + DAC differential
nonlinearity
T
–1
1
LSB
0
0.005
0
0.1
DVCC –
0.1
DVCC
Low-power mode
OAPM = 0
OAPM = 0
DACSREF = DVCC, DVCC = 3.0 V
Output voltage range
RLOAD = 3 kΩ , DACSREF = DVCC,
DACDAT = 0
RLOAD = 3 kΩ , DACSREF = DVCC,
DACDAT = 0FFFh
50
Specifications
T
mA
1
477
160
T
V
µA
0.2
T
No load, DACSREF = DVCC, DACDAT = 0
VOUT
5
T
High-power mode
3.6
UNIT
2
10
2
5
µs
µs
V
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
5.13.12 FRAM
Table 5-27 lists the characteristics of the FRAM.
Table 5-27. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
DEVICE
GRADE
MIN
T
1015
TJ = 25°C
T
100
TJ = 70°C
T
40
TJ = 115°C
T
TEST CONDITIONS
Read and write endurance
tRetention
Data retention duration
IWRITE
Current to write into FRAM
IERASE
tWRITE
TREAD
Iref
(1)
(2)
(3)
(4)
T
Erase current
T
Write time
T
Read time
Iref trim
TYP
MAX
UNIT
cycles
years
10
IREAD
(1)
N/A
(2)
tREAD
(3)
(1)
IREAD (1)
nA
N/A
(2)
N/A (2)
nA
tREAD
(3)
(3)
ns
IREAD
tREAD
NWAITSx = 0
T
1/fSYSTEM (4)
1/fSYSTEM (4)
1/fSYSTEM (4)
NWAITSx = 1
T
2/fSYSTEM (4)
2/fSYSTEM (4)
2/fSYSTEM (4)
NWAITSx = 2
T
3/fSYSTEM (4)
3/fSYSTEM (4)
3/fSYSTEM (4)
MP = 1, T = 30°C
T
8
63
ns
µA
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption numbers IAM, FRAM.
FRAM does not require a special erase sequence.
Writing into FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
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5.13.13 Emulation and Debug
Table 5-28 lists the characteristics of the SBW interface.
Table 5-28. JTAG, Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETER
DEVICE
GRADE
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
T
2.0 V,
3.0 V
0
8
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
T
2.0 V,
3.0 V
0.028
15
µs
tSU,SBWTDIO
SBWTDIO setup time (before falling edge of SBWTCK in
TMS and TDI slot Spy-Bi-Wire )
T
2.0 V,
3.0 V
4
ns
tHD,SBWTDIO
SBWTDIO hold time (after rising edge of SBWTCK in TMS
and TDI slot Spy-Bi-Wire )
T
2.0 V,
3.0 V
19
ns
tValid,SBWTDIO
SBWTDIO data valid time (after falling edge of SBWTCK in
TDO slot Spy-Bi-Wire )
T
2.0 V,
3.0 V
31
ns
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first
clock edge) (1)
T
2.0 V,
3.0 V
110
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time (2)
T
2.0 V,
3.0 V
15
100
µs
Rinternal
Internal pulldown resistance on TEST
T
2.0 V,
3.0 V
20
50
kΩ
(1)
(2)
35
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
Maximum tSBW,Rst time after pulling or releasing the TEST/SBWTCK pin low, the Spy-Bi-Wire pins revert from their Spy-Bi-Wire function
to their application function. This time applies only if the Spy-Bi-Wire mode was selected.
tSBW,EN
1/fSBW
tSBW,Low
tSBW,High
tSBW,Ret
TEST/SBWTCK
tEN,SBWTDIO
tValid,SBWTDIO
RST/NMI/SBWTDIO
tSU,SBWTDIO
tHD,SBWTDIO
Figure 5-17. JTAG Spy-Bi-Wire Timing
52
Specifications
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 5-29 lists the characteristics of the 4-wire JTAG interface.
Table 5-29. JTAG, 4-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
(1)
DEVICE
GRADE
VCC
I, T
2.0 V,
3.0 V
0
MIN
TYP
MAX
UNIT
10
MHz
fTCK
TCK input frequency
tTCK,Low
Spy-Bi-Wire low clock pulse duration
I, T
2.0 V,
3.0 V
15
ns
tTCK,high
Spy-Bi-Wire high clock pulse duration
I, T
2.0 V,
3.0 V
15
ns
tSU,TMS
TMS setup time (before rising edge of TCK )
I, T
2.0 V,
3.0 V
11
ns
tHD,TMS
TMS hold time (after rising edge of TCK )
I, T
2.0 V,
3.0 V
3
ns
tSU,TDI
TDI setup time (before rising edge of TCK )
I, T
2.0 V,
3.0 V
13
ns
tHD,TDI
TDI hold time (after rising edge of TCK )
I, T
2.0 V,
3.0 V
5
ns
tz-Valid,TDO
TDO high impedance to valid output time (after falling edge of
TCK )
I, T
2.0 V,
3.0 V
26
ns
tValid,TDO
TDO to new valid output time (after falling edge of TCK )
I, T
2.0 V,
3.0 V
26
ns
tValid-Z,TDO
TDO valid to high impedance output time (after falling edge of
TCK )
I, T
2.0 V,
3.0 V
26
ns
tJTAG,Ret
Spy-Bi-Wire return to normal operation time
I, T
2.0 V,
3.0 V
15
100
µs
Rinternal
Internal pulldown resistance on TEST
I, T
2.0 V,
3.0 V
20
50
kΩ
(1)
35
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
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1/fTCK
tTCK,Low
tTCK,High
TCK
TMS
tSU,TMS
tHD,TMS
TDI
(or TDO as TDI)
tSU,TDI
tHD,TDI
TDO
tZ-Valid,TDO
tValid,TDO
tValid-Z,TDO
tJTAG,Ret
TEST
Figure 5-18. JTAG 4-Wire Timing
54
Specifications
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
6.2
Operating Modes
The MSP430 has one active mode and several software selectable low-power modes of operation. An
interrupt event can wake up the device from low-power mode LPM0, LPM3 or LPM4, service the request,
and restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5
and LPM4.5 disable the core supply to minimize power consumption.
Table 6-1. Operating Modes
AM
LPM0
LPM3
LPM4
LPM3.5
LPM4.5
ACTIVE
MODE
CPU OFF
STANDBY
OFF
ONLY RTC
COUNTER
SHUTDOWN
24 MHz
24 MHz
40 kHz
0
40 kHz
0
142 µA/MHz
40 µA/MHz
1.43 µA with
RTC counter
only in LFXT
0.82 µA
without SVS
620 nA with
RTC counter
only in LFXT
42 nA
without SVS
Wake-up time
N/A
Instant
10 µs
10 µs
350 µs
350 µs
Wake-up events
N/A
All
All
I/O
RTC counter,
I/O
I/O
Full
regulation
Full
regulation
Partial power
down
Partial power
down
Partial power
down
Power down
SVS
On
On
Optional
Optional
Optional
Optional
Brownout
On
On
On
On
On
On
Active
Off
Off
Off
Off
Off
MODE
Maximum system clock
Power consumption at 25°C, 3 V
Regulator
Power
MCLK
Clock (1)
SMCLK
Optional
Active
Off
Off
Off
Off
FLL
Optional
Optional
Off
Off
Off
Off
DCO
Optional
Optional
Off
Off
Off
Off
MODCLK
Optional
Optional
Off
Off
Off
Off
REFO
Optional
Optional
Optional
Off
Off
Off
ACLK
Optional
Optional
Active
Off
Off
Off
XT1HFCLK
(1)
(2)
(2)
Optional
Optional
Off
Off
Off
Off
XT1LFCLK
Optional
Optional
Optional
Off
Optional
Off
VLOCLK
Optional
Optional
Optional
Off
Optional
Off
The status shown for LPM4 applies to internal clocks only.
HFXT must be disabled before entering into LPM3, LPM4, or LPMx.5 mode.
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Table 6-1. Operating Modes (continued)
AM
LPM4
LPM3.5
LPM4.5
STANDBY
OFF
ONLY RTC
COUNTER
SHUTDOWN
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
On
On
On
On
Off
Off
On
On
On
On
On
Off
Timer0_B3
Optional
Optional
Optional
Off
Off
Off
Timer1_B3
Optional
Optional
Optional
Off
Off
Off
Timer2_B3
Optional
Optional
Optional
Off
Off
Off
Timer3_B7
Optional
Optional
Optional
Off
Off
Off
WDT
Optional
Optional
Optional
Off
Off
Off
eUSCI_A0
Optional
Optional
Optional
Off
Off
Off
eUSCI_A1
Optional
Optional
Optional
Off
Off
Off
eUSCI_B0
Optional
Optional
Optional
Off
Off
Off
eUSCI_B1
Optional
Optional
Optional
Off
Off
Off
CRC
Optional
Optional
Off
Off
Off
Off
ICC
Optional
Optional
Off
Off
Off
Off
MPY32
Optional
Optional
Off
Off
Off
Off
ADC
Optional
Optional
Optional
Off
Off
Off
eCOMP0
Optional
Optional
Optional
Optional
Off
Off
eCOMP1
Optional
Optional
Optional
Optional
Off
Off
(4)
MODE
Core
Peripherals
CPU OFF
CPU
On
FRAM
On
RAM
Backup Memory (3)
SAC0
(3)
(4)
LPM3
Optional
Optional
Optional
Optional
Off
Off
SAC1 (4)
Optional
Optional
Optional
Optional
Off
Off
SAC2 (4)
Optional
Optional
Optional
Optional
Off
Off
(4)
Optional
Optional
Optional
Optional
Off
Off
RTC Counter
Optional
Optional
Optional
Optional
Optional
Off
On
Optional
State held
State held
State held
State held
SAC3
I/O
LPM0
ACTIVE
MODE
General digital input/output
Backup memory contains one 32-byte register in the peripheral memory space. See Table 6-33 and Table 6-54 for its memory
allocation.
MSP430FR235x devices only
NOTE
XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals.
56
Detailed Description
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6.3
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-2). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-2. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power up, brownout, supply supervisor
External reset RST
Watchdog time-out, key violation
FRAM uncorrectable bit error detection
Software POR, BOR
FLL unlock error
SVSHIFG
PMMRSTIFG
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLULPUC
Reset
FFFEh
63, Highest
Non-Maskable
FFFCh
62
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM bit-error detection
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
User NMI
External NMI
Oscillator fault
NMIIFG
OFIFG
Non-Maskable
FFFAh
61
Timer0_B3
TB0CCR0 CCIFG0
Maskable
FFF8h
60
Timer0_B3
TB0CCR1 CCIFG1, TB0CCR2
CCIFG2, TB0IFG (TB0IV)
Maskable
FFF6h
59
Timer1_B3
TB1CCR0 CCIFG0
Maskable
FFF4h
58
Timer1_B3
TB1CCR1 CCIFG1, TB1CCR2
CCIFG2, TB1IFG (TB1IV)
Maskable
FFF2h
57
Timer2_B3
TB2CCR0 CCIFG0
Maskable
FFF0h
56
Timer2_B3
TB2CCR1 CCIFG1, TB2CCR2
CCIFG2, TB2IFG (TB2IV)
Maskable
FFEEh
55
Timer3_B7
TB3CCR0 CCIFG0
Maskable
FFECh
54
Timer3_B7
TB3CCR1 CCIFG1, TB3CCR2
CCIFG2, TB3CCR3 CCIFG3,
TB3CCR4 CCIFG4, TB3CCR5
CCIFG5, TB3CCR6 CCIFG6, TB3IFG
(TB3IV)
Maskable
FFEAh
53
RTC counter
RTCIFG
Maskable
FFE8h
52
Watchdog timer interval mode
WDTIFG
Maskable
FFE6h
51
eUSCI_A0 receive or transmit
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
Maskable
FFE4h
50
eUSCI_A1 receive or transmit
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
Maskable
FFE2h
49
eUSCI_B0 receive or transmit
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG,
UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)
Maskable
FFE0h
48
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Table 6-2. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
eUSCI_B1 receive or transmit
UCB1RXIFG, UCB1TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG,
UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)
Maskable
FFDEh
47
ADC
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
Maskable
FFDCh
46
eCOMP0_eCOMP1
CPIIFG, CPIFG (CP1IV, CP0IV)
Maskable
FFDAh
45
(1)
SAC2DACSTS DACIFG (SAC2IV)
SAC0DACSTS DACIFG, SAC0IV)
Maskable
FFD8h
44
SAC1_SAC3 (1)
SAC3DACSTS DACIFG (SAC3IV)
SAC1DACSTS DACIFG, SAC1IV)
Maskable
FFD6h
43
P1
P1IFG.0 to P1IFG.7 (P1IV)
Maskable
FFD4h
42
P2
P2IFG.0 to P2IFG.7 (P2IV)
Maskable
FFD2h
41
P3
P3IFG.0 to P3IFG.7 (P3IV)
Maskable
FFD0h
40
P4
P4IFG.0 to P4IFG.7 (P4IV)
Maskable
FFCEh
39
Reserved
Reserved
Maskable
FFCCh to FF88h
SAC0_SAC2
(1)
MSP430FR235x devices only
Table 6-3 lists the BSL signature settings. The BSL setting on MSP430FR2355 can be customized by
using BSL configuration and I2C address. See the MSP430 FRAM Device Bootloader (BSL) User's Guide
for more details.
Table 6-3. BSL Signatures
SIGNATURE
BSL I2C Address
(1)
58
WORD ADDRESS
(1)
FFA0h
BSL Config
0FF8Ah
BSL Config Signature
0FF88h
BSL Signature2
0FF86h
BSL Signature1
0FF84h
JTAG Signature2
0FF82h
JTAG Signature1
0FF80h
2
It is 7-bit address BSL I C interface.
Detailed Description
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6.4
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Memory Organization
Table 6-4 summarizes the memory map of the MSP430FR235x devices.
Table 6-4. Memory Organization
ACCESS
MSP430FR2355
MSP430FR2353
Read/Write
(Optional Write Protect) (1)
32KB
FFFFh to FF80h
FFFFh to 8000h
16KB
FFFFh to FF80h
FFFFh to C000h
Read/Write
4KB
2FFFh to 2000h
2KB
27FFh to 2000h
Read/Write (2)
512 bytes
19FFh to 1800h
512 bytes
19FFh to 1800h
Driver Library and FFT Library (ROM)
Read only
20KB
FAC00h to FFBFFh
20KB
FAC00h to FFBFFh
Peripherals
Read/Write
4KB
0FFFh to 0020h
4KB
0FFFh to 0020h
Tiny RAM
Read/Write
26 bytes
001Fh to 0006h
26 bytes
001Fh to 0006h
Read
6 bytes
0005h to 0000h
6 bytes
0005h to 0000h
Memory (FRAM)
Main: interrupt vectors and signatures
Main: code memory
RAM
Information Memory (FRAM)
Reserved (3)
(1)
(2)
(3)
6.5
The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in MSP430FR4xx and
MSP430FR2xx Family User's Guide for more details
The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in MSP430FR4xx and
MSP430FR2xx Family User's Guide for more details
Reads as: D032h at 00h (Opcode: BIS.W LPM4, SR), 00F0h at 02h (Opcode: BIS.W LPM4, SR), 3FFFh at 04h (Opcode: JMP$)
Bootloader (BSL)
The BSL enables users to program the FRAM memory or RAM using a UART or I2C serial interface.
Access to the device memory through the BSL is protected by an user-defined password. Use of the BSL
requires four pins (see Table 6-5 and Table 6-6). BSL entry requires a specific entry sequence on the
RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the BSL and its
implementation, see MSP430 FRAM Device Bootloader (BSL) User's Guide.
Table 6-5. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.7
Data transmit
P1.6
Data receive
DVCC
Power supply
DVSS
Ground supply
Table 6-6. I2C BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.2
Data receive and transmit
P1.3
Clock
DVCC
Power supply
DVSS
Ground supply
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6.6
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JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-7 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide.
Table 6-7. JTAG Pin Requirements and Function
6.7
DEVICE SIGNAL
DIRECTION
P1.4/UCA0STE/TCK/A4
IN
JTAG FUNCTION
JTAG clock input
P1.5/UCA0CLK/TMS/OA1O/A5
IN
JTAG state control
JTAG data input, TCLK input
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6
IN
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
DVCC
–
Power supply
DVSS
–
Ground supply
Spy-Bi-Wire Interface (SBW)
The MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface
with MSP430 development tools and device programmers. Table 6-8 shows the Spy-Bi-Wire interface pin
requirements. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide.
Table 6-8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
6.8
DIRECTION
SBW FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
DVCC
–
Power supply
DVSS
–
Ground supply
FRAM
The FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
60
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6.9
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Memory Protection
The device features memory protection of user access authority and write protection include:
• Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
• Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control
bits with accordingly password in System Configuration register 0. For more detailed information, see
the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.10.1 Power Management Module (PMM) and On-chip Reference Voltages
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power-on and power-off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains three on-chip references:
•
•
•
Internal shared reference (1.5 V, 2.0 V, or 2.5 V)
1.2 V for external reference (VREF pin)
1.2 V low-power reference for eCOMP
The internal shared reference is controlled by PMM settings to select 1.5 V, 2.0 V, or 2.5 V. This reference
is internally connected to ADC channel 13. DVCC is internally connected to ADC channel 15. When
DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily represent as
Equation 1 by using ADC sampling reference without any external components support.
DVCC = (4095 × reference voltage) ÷ ADC result
(1)
The internal shared reference (1.5 V, 2.0 V, or 2.5 V ) is also internally connected to the built-in DAC of
the comparator and SAC (MSP430FR235x devices only) built-in 12-bit DAC as the reference voltage. The
source can be selected by setting the specific register configuration of each module For more information,
see the MSP430FR4xx and MSP430FR2xx Family User's Guide.
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+ can support a buffered external 1.2V output,
when EXTREFEN = 1 in the PMMCTL2 register. ADC channel 7 can also be selected to monitor this
voltage. For more information, see the MSP430FR4xx and MSP430FR2xx Family User's Guide.
An additional low-power 1.2-V reference is internally connected to eCOMP0 and eCOMP1. This reference
is activated by enabling eCOMP with the channel as threshold source. See Section 6.10.13 for more
details.
6.10.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz low-frequency or up to 24-MHz high-frequency crystal oscillator
(XT1), an internal very low-power low-frequency oscillator (VLO), an integrated 32-kHz RC oscillator
(REFO), an integrated internal digitally controlled oscillator (DCO) that may use frequency-locked loop
(FLL) locking with internal or external 32-kHz reference clock, and on-chip asynchronous high-speed clock
(MODOSC). The clock system is designed to target cost-effective designs with minimal external
components. A fail-safe mechanism is designed for XT1. The clock system module offers the following
clock signals.
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•
•
•
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Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the
bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,
16, 32, 64, or 128.
Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from
the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
Auxiliary Clock (ACLK): this clock derived from the external XT1 clock, internal VLO or internal REFO
clock up to 40 kHz.
All peripherals may have one or several clock sources depending on specific functionality. Table 6-9shows
the Clock Distribution used in this device.
Table 6-9. Clock Distribution
CLOCK
SOURCE
SELECT BITS
Frequency
Range
MCLK
SMCLK
ACLK
MODCLK
VLOCLK
EXTERNAL
PIN
DC to 24 MHz
DC to 24 MHz
DC to 40 kHz
3.8 MHz ±21%
10 kHz ±50%
–
CPU
N/A
Default
–
–
–
–
–
FRAM
N/A
Default
–
–
–
–
–
RAM
N/A
Default
–
–
–
–
–
CRC
N/A
Default
–
–
–
–
–
MPY32
N/A
Default
–
–
–
–
–
ICC
N/A
Default
–
–
–
–
–
I/O
N/A
Default
–
–
–
–
–
TB0
TBSSEL
–
10b
01b
–
–
00b (TB0CLK
pin)
TB1
TBSSEL
–
10b
01b
–
–
00b (TB1CLK
pin)
TB2
TBSSEL
–
10b
01b
–
–
00b (TB2CLK
pin)
TB3
TBSSEL
–
10b
01b
–
–
00b (TB3CLK
pin)
eUSCI_A0
UCSSEL
–
10b or 11b
01b
–
–
00b (UCA0CLK
pin)
eUSCI_A1
UCSSEL
–
10b or 11b
01b
–
–
00b (UCA1CLK
pin)
eUSCI_B0
UCSSEL
–
10b or 11b
01b
–
–
00b (UCB0CLK
pin)
eUSCI_B1
UCSSEL
–
10b or 11b
01b
–
–
00b (UCB1CLK
pin)
MFM
N/A
–
Default
–
–
–
–
WDT
WDTSSEL
–
00b
01b
–
10b
–
ADC
ADCSSEL
–
10b or 11b
01b
00b
–
–
RTCSS
–
01b (1)
01b (1)
–
11b
–
RTC Counter
(1)
Controlled by the RTCCLK bit in the SYSCFG2 register.
Table 6-10. XTCLK Distribution
CLOCK SOURCE
SELECT BITS
XTHFCLK
XTLFCLK
XTLFCLK (LPMx.5)
AM to LPM0
AM to LPM3
AM to LPM3.5
SELMS
10b
10b
10b
SMCLK
SELMS
10b
10b
10b
REFO
SELREF
0b
0b
0b
ACLK
SELA
0b
0b
0b
RTC
RTCSS
–
10b
10b
OPERATION MODE
MCLK
62
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6.10.3 General-Purpose Input/Output Port (I/O)
Up to 44 I/O ports are implemented.
• P1, P2, P3, and P4 are full 8-bit ports; P5 and P6 feature up to 5-bit and 7-bit ports, respectively.
• All individual I/O bits are independently programmable.
• Any combination of input, output, is possible for P1, P2, P3, P4, P5, and P6. Interrupt conditions are
possible in P1, P2, P3, and P4.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5, LPM4 and LPM4.5 wake-up input capability is available in P1,
P2, P3, and P4.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, see the Configuration After Reset section in the Digital I/O chapter of the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.10.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as interval timer and can generate interrupts at
selected time intervals.
Table 6-11 lists the clock sources that can be used by the WDT.
Table 6-11. WDT Clocks
WDTSSEL
NORMAL OPERATION
(WATCHDOG AND INTERVAL
TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
Reserved
6.10.5 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators (see Table 6-12), bootloader entry mechanisms, and configuration management (device
descriptors). SYS also includes a data exchange mechanism through SBW called a JTAG mailbox that
can be used in the application.
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Table 6-12. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
SYSRSTIV, System Reset
SYSSNIV, System NMI
SYSUNIV, User NMI
ADDRESS
015Eh
015Ch
015Ah
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wake up (BOR)
08h
Security violation (BOR)
0Ah
Reserved
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
Uncorrectable FRAM bit error detection
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation
(PUC)
20h
Reserved
22h
FLL unlock (PUC)
24h
Reserved
26h to 3Eh
No interrupt pending
00h
SVS low-power reset entry
02h
Uncorrectable FRAM bit error detection
04h
Reserved
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
Reserved
0Eh
Reserved
10h
VMAIFG Vacant memory access
12h
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
16h
Correctable FRAM bit error detection
18h
Reserved
1Ah to 1Eh
No interrupt pending
00h
NMIIFG NMI pin or SVSH event
02h
OFIFG oscillator fault
04h
Reserved
06h to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
6.10.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x16 + x12 + x5 + 1.
64
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6.10.7 Interrupt Compare Controller (ICC)
The Interrupt Compare Controller (ICC) allows all maskable interrupt sources to be scheduled in a
preemptive mechanism. Each interrupt source is specified as a source of ICC module. Each source
supports a 4-level software interrupt priority other than the one tired with interrupt vector. When ICC
module is enabled, the ISR in lower software priority can be interrupted by higher priority. It is required to
enable GIE in ISR for proper ICC operation. For details, see the ICC chapter of the MSP430FR4xx and
MSP430FR2xx Family User's Guide. Table 6-13 specifies the ICC source configurations.
Table 6-13. ICC Interrupt Source Assignments
REGISTER
BITS
INTERRUPT
SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
ILSR0
P4
P4IFG.0 to P4IFG.7 (P4IV)
Maskable
FFCEh
39
ILSR1
P3
P3IFG.0 to P3IFG.7 (P3IV)
Maskable
FFD0h
40
ILSR2
P2
P2IFG.0 to P2IFG.7 (P2IV)
Maskable
FFD2h
41
ILSR3
P1
P1IFG.0 to P1IFG.7 (P1IV)
Maskable
FFD4h
42
ILSR4
SAC3 DAC,
SAC1 DAC (1)
DACIFG, (SAC3IV, SAC1IV) (1)
Maskable
FFD6h
43
ILSR5
SAC2 DAC,
SAC0 DAC (1)
DACIFG (SAC2IV, SAC0IV) (1)
Maskable
FFD8h
44
ILSR6
eCOMP1,
eCOMP0
CPIIFG, CPIFG (CP1IV, CP0IV)
Maskable
FFDAh
45
ILSR7
ADC
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
Maskable
FFDCh
46
eUSCI_B1
Receive or
Transmit
UCB1RXIFG, UCB1TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG,
UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)
Maskable
FFDEh
47
ILSR9
eUSCI_B0
Receive or
Transmit
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG,
UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)
Maskable
FFE0h
48
ILSR10
eUSCI_A1
Receive or
Transmit
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
Maskable
FFE2h
49
ILSR11
eUSCI_A0
Receive or
Transmit
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
Maskable
FFE4h
50
ILSR12
Watchdog Timer
Interval mode
WDTIFG
Maskable
FFE6h
51
ILSR13
RTC Counter
RTCIFG
Maskable
FFE8h
52
ILSR14
Timer3_B7
TB3CCR1 CCIFG1, TB3CCR2
CCIFG2, TB3CCR3 CCIFG3,
TB3CCR4 CCIFG4, TB3CCR5
CCIFG5, TB3CCR6 CCIFG6, TB3IFG
(TB3IV)
Maskable
FFEAh
53
ILSR15
Timer3_B7
TB3CCR0 CCIFG0
Maskable
FFECh
54
ICCILRS0
ILSR8
ICCILRS1
(1)
MSP430FR235x devices only
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Table 6-13. ICC Interrupt Source Assignments (continued)
REGISTER
ICCILRS2
ICCILRS3
BITS
INTERRUPT
SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
ILSR16
Timer2_B3
TB2CCR1 CCIFG1, TB2CCR2
CCIFG2, TB2IFG (TB2IV)
Maskable
FFEEh
55
ILSR17
Timer2_B3
TB2CCR0 CCIFG0
Maskable
FFF0h
56
ILSR18
Timer1_B3
TB1CCR1 CCIFG1, TB1CCR2
CCIFG2, TB1IFG (TB1IV)
Maskable
FFF2h
57
ILSR19
Timer1_B3
TB1CCR0 CCIFG0
Maskable
FFF4h
58
ILSR20
Timer0_B3
TB0CCR1 CCIFG1, TB0CCR2
CCIFG2, TB0IFG (TB0IV)
Maskable
FFF6h
59
ILSR21
Timer0_B3
TB0CCR0 CCIFG0
Maskable
FFF8h
60
ILSR22
N/A
N/A
N/A
N/A
N/A
ILSR23
N/A
N/A
N/A
N/A
N/A
ILSR24
N/A
N/A
N/A
N/A
N/A
ILSR25
N/A
N/A
N/A
N/A
N/A
ILSR26
N/A
N/A
N/A
N/A
N/A
ILSR27
N/A
N/A
N/A
N/A
N/A
ILSR28
N/A
N/A
N/A
N/A
N/A
ILSR29
N/A
N/A
N/A
N/A
N/A
ILSR30
N/A
N/A
N/A
N/A
N/A
ILSR31
N/A
N/A
N/A
N/A
N/A
6.10.8 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1,
eUSCI_B0, eUSCI_B1)
The eUSCI modules are used for serial data communications (see Table 6-14). The eUSCI_A module
supports either UART or SPI communications. The eUSCI_B module supports either SPI or I2C
communications. Additionally, eUSCI_A supports automatic baud-rate detection and IrDA..
Table 6-14. eUSCI Pin Configurations
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
66
Detailed Description
PIN
UART
SPI
P1.7
TXD
SIMO
P1.6
RXD
SOMI
P1.5
–
SCLK
P1.4
–
STE
PIN
UART
SPI
P4.3
TXD or TXD
SIMO
P4.2
RXD or RXD
SOMI
P4.1
–
SCLK
P4.0
–
STE
2
PIN
I C
SPI
P1.3
SCL
SOMI
P1.2
SDA
SIMO
P1.1
–
SCLK
P1.0
–
STE
PIN
I2C
SPI
P4.7
SCL
SOMI
P4.6
SDA
SIMO
P4.5
–
SCLK
P4.4
–
STE
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The eUSCI_A1 can work as UART in inverting polarity mode by port settings (see Table 6-15). When
PSEL = 01b, the normal UART or SPI mode is used. When PSEL = 10b, the inverted UART mode is
enabled to transmit and receive data in inverted polarity. In this mode, eUSCI_A1 can also wake up the
device from LPM3 by detecting a rising edge of start bit according the falling edge in normal mode.
Table 6-15. eUSCI_A1 UART Polarity Configurations
eUSCI_A1
PSEL = 01b
P4.3
TXD
PSEL = 10b
TXD
P4.4
RXD
RXD
6.10.9 Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
The Timer0_B3, Timer1_B3, and Timer2_B3 modules are 16-bit timers and counters with three
capture/compare registers each. Timer3_B7 is a 16-bit timers with seven capture/compare registers each.
Each can support multiple captures or compares, PWM outputs, and interval timing (see Table 6-16,
Table 6-17, Table 6-18, and Table 6-19). Each has extensive interrupt capabilities. Interrupts may be
generated from the counter on overflow conditions and from each of the capture/compare registers. The
CCR0 registers on all timers are not externally connected and can only be used for hardware period timing
and interrupt generation. In Up Mode, they can be used to set the overflow value of the counter.
Table 6-16. Timer0_B3 Signal Connections
PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
P2.7
TB0CLK
TBCLK
P1.6
P1.7
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
N/A
INCLK
from RTC (internal)
CCI0A
ACLK (internal)
CCI0B
DVSS
GND
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
SIGNAL
Not used
CCR0
TB0
Timer1_B3 CCI0B
input
TB1
DVCC
VCC
TB0.1
CCI1A
TB0.1
from eCOMP0.O
(internal)
CCI1B
Timer1_B3 CCI1B
input
DVSS
GND
CCR1
DVCC
VCC
TB0.2
CCI2A
TB0.2
N/A
CCI2B
Timer1_B3 INCLK
Timer1_B3 CCI2B
input,
IR carrier input
DVSS
GND
DVCC
VCC
CCR2
TB2
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Table 6-17. Timer1_B3 Signal Connections
PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
P2.2
TB1CLK
TBCLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
Timer0_B3 CCR2B
output (internal)
INCLK
Timer3_B7 CCR0B
output (internal)
CCI0A
Timer0_B3 CCR0B
output (internal)
CCI0B
DVSS
GND
DVCC
VCC
TB1.1
CCI1A
Timer0_B3 CCR1B
output (internal)
CCI1B
P2.0
P2.1
DVSS
GND
DVCC
VCC
TB1.2
CCI2A
Timer0_B3 CCR2B
output (internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
SIGNAL
Not used
CCR0
TB0
Not used
TB1.1
CCR1
TB1
To ADC trigger
TB1.2
CCR2
TB2
IR coding input
Table 6-18. Timer2_B3 Signal Connections
PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
P2.7
TB2CLK
TBCLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
CCI0A
DVSS
GND
VCC
MFM Complete Event
CCI0B
TB2.1
MODULE OUTPUT
SIGNAL
Timer
N/A
CCR0
TB0
DEVICE OUTPUT
SIGNAL
Not used
MFM start trigger
CCI1A
TB2.1
from eCOMP1.O
(internal)
CCI1B
TB1
To SAC DAC update
trigger 10b (1)
DVSS
GND
TB2
P5.1
68
INCLK
DVCC
P5.0
(1)
TB2CLK
Not Used
MODULE BLOCK
CCR1
DVCC
VCC
TB2.2
CCI2A
TB2.2
Not Used
CCI2B
To SAC DAC update
trigger 11b (1)
DVSS
GND
DVCC
VCC
CCR2
MSP430FR235x devices only
Detailed Description
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-19. Timer3_B7 Signal Connections
PORT PIN
P6.6
P6.0
P6.1
P4.0
P6.2
P6.3
P6.4
P6.5
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
TB3CLK
TBCLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
TB3CLK
INCLK
Not Used
CCI0A
Not Used
CCI0B
DVSS
GND
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
SIGNAL
Not used
CCR0
TB0
To Timer1_B3 CCI0A
DVCC
VCC
TB3.1
CCI1A
Not Used
CCI1B
DVSS
GND
DVCC
VCC
TB3.2
CCI2A
TB3.2
ISORXD
CCI2B
AND UCA1TXD
ISOTXD
DVSS
GND
DVCC
VCC
TB3.3
CCI3A
Not Used
CCI3B
DVSS
GND
DVCC
VCC
TB3.4
CCI4A
Not Used
CCI4B
DVSS
GND
DVCC
VCC
Tb3.1
CCR1
CCR2
TB1
TB2
TB3.3
CCR3
TB3
TB3.4
CCR4
TB4
Not used
TB3.5
CCI5A
TB3.5
Not Used
CCI5B
Not used
DVSS
GND
DVCC
VCC
CCR5
TB5
TB3.6
CCI6A
TB3.6
Not Used
CCI6B
Not used
DVSS
GND
DVCC
VCC
CCR6
TB6
The interconnection of Timer0_B3 and Timer1_B3 can be used to modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated
infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS
configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select),
IRDSSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
The Timer_B module feature the function to put Timer_B all outputs into a high impedance state when the
selected source is triggered. The source can be selected from external pin or internal of the device, it is
controlled by TBxTRG in SYS. For more information, see the SYS chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
The Timer2_B3 CCR0 is tied with the MFM (Manchester Function Module).
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Table 6-20 lists the Timer_B high-impedance trigger sources.
Table 6-20. TBxOUTH
TBxTRGSEL
TBxOUTH TRIGGER SOURCE
SELECTION
TB0TRGSEL = 0
eCOMP0 output (internal)
TB0TRGSEL= 1
P1.2
TB1TRGSEL = 0
eCOMP0 output (internal)
TB1TRGSEL = 1
P2.3
TB2TRGSEL = 0
eCOMP1 output (internal)
TB2TRGSEL = 1
P5.3
TB3TRGSEL = 0
eCOMP1 output (internal)
TB3TRGSEL = 1
N/A
TIMER_B PAD OUTPUT HIGH
IMPEDANCE
P1.6, P1.7
P2.0, P2.1
P5.0, P5.1
P6.0, P6.1, P6.2, P6.3, P6.4, P6.5
6.10.10 Backup Memory (BKMEM)
The BKMEM supports data retention functionality during LPM3.5 mode. This device provides up to
32 bytes that are retained during LPM3.5.
6.10.11 Real-Time Clock (RTC) Counter
The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, LPM4, and LPM3.5.
This module may periodically wake up the CPU from LPM0, LPM3, LPM4, and LPM3.5 based on timing
from a low-power clock source such as the XT1, ACLK, and VLO clocks. In AM, RTC can be driven by
SMCLK to generate high-frequency timing events and interrupts. ACLK and SMCLK both can source to
the RTC; however, only one of them can be selected at a time. The RTC overflow events can trigger:
• Timer0_B3 CCI0A
• ADC conversion trigger when ADCSHSx bits are set as 01b
70
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6.10.12 12-Bit Analog-to-Digital Converter (ADC)
The 12-bit ADC module supports fast 12-bit analog-to-digital conversions with single-ended input. The
module implements a 12-bit SAR core, sample select control, reference generator and a conversion result
buffer. A window comparator with a lower and upper limits allows CPU-independent result monitoring with
three window comparator interrupt flags.
The ADC supports 12 external inputs and four internal inputs (see Table 6-21).
Table 6-21. ADC Channel Connections
ADCINCHx
ADC CHANNELS
EXTERNAL PIN OUTPUT
0
A0/Veref+
P1.0
1
A1/
P1.1
2
A2/Veref-
P1.2
3
A3
P1.3
4
A4
P1.4
5
A5
P1.5
6
A6
P1.6
7
(1)
A7
(1)
P1.7
8
A8
P5.0
9
A9
P5.1
10
A10
P5.2
11
A11
P5.3
12
On-chip temperature sensor
N/A
13
Internal shared reference voltage (1.5,
2.0, or 2.5-V)
N/A
14
DVSS
N/A
15
DVCC
N/A
When A7 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM
control register. The 1.2-V voltage can be measured by channel A7.
The analog-to-digital conversion can be started by software or a hardware trigger. Table 6-22 shows the
trigger sources that are available.
Table 6-22. ADC Trigger Signal Connections
ADCSHSx
TRIGGER SOURCE
BINARY
DECIMAL
00
0
ADCSC bit (software trigger)
01
1
RTC event
10
2
TB1.1B
11
3
eCOMP0 COUT
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6.10.13 eCOMP0, eCOMP1
This device features two enhanced comparators. The enhanced comparator is an analog voltage
comparator with a built-in 6-bit DAC as an internal voltage reference. The integrated 6-bit DAC can be set
to 64 steps for the comparator reference voltage. This module has 4-level programmable hysteresis and
configurable power modes: high-power and low-power modes.
The eCOMP0 supports a propagation delay up to 1 µs in high-power mode. In low-power mode, eCOMP0
supports 3.2-µs delay with 1.5-µA leakage at room temperature, which can be an ideal wake-up source in
LPM3 for a voltage monitor.
The eCOMP1 supports a propagation delay up to 100 ns in high-power mode. In low-power mode,
eCOMP1 supports 320-ns delay with 10-µA leakage at room temperature.
Both eCOMP0 and eCOMP1 contains a programmable 6-bit DAC that can use internal shared reference
(1.5, 2.0, or 2.5-V) for high precision comparison threshold. In addition to internal shared reference, a lowpower 1.2-V reference is fixed at channel 2 of both inverting and non-inverting path that allows the DAC
turned off for saving powers.
The eCOMP0 supports external inputs and internal inputs (see Table 6-23) and outputs (see Table 6-25)
Table 6-23. eCOMP0 Input Channel Connections
CPPSEL
eCOMP0 CHANNELS
CPNSEL
000
P1.0/COMP0.0/A0
000
eCOMP0 CHANNELS
P1.0/COMP0.0/A0
001
P1.1/OA0O/COMP0.1/A1
001
P1.1/OA0O/COMP0.1/A1
010
Low-power 1.2-V reference
010
Low-power 1.2-V reference
011
N/A
011
N/A
100
N/A
100
N/A
101
P1.1/OA0O/COMP0.1/A1
101
P3.1/OA2O
110
eCOMP0 6-bit DAC
110
eCOMP0 6-bit DAC
Table 6-24. eCOMP1 Input Channel Connections
CPPSEL
eCOMP1 CHANNELS
CPNSEL
eCOMP1 CHANNELS
000
P2.5/COMP1.0
000
P2.5/COMP1.0
001
P2.4/COMP1.1
001
P2.4/COMP1.1
010
Low-power 1.2-V reference
010
Low-power 1.2-V reference
011
N/A
011
N/A
100
N/A
100
N/A
101
P1.5/OA1O/A5
101
P3.5/OA3O
110
eCOMP1 6-bit DAC
110
eCOMP1 6-bit DAC
Table 6-25. eCOMP0 Output Channel Connections
ECOMP0 OUT
72
Detailed Description
EXTERNAL PINOUT, MODULE
1
P2.0
2
TB0.1B, TB0 (TB0OUTH), TB1 (TB1OUTH), ADC trigger
3
Reserved
4
Reserved
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-26. eCOMP1 Output Channel Connections
ECOMP1 OUT
EXTERNAL PINOUT, MODULE
1
P2.1
2
TB2.1B, TB2 (TB2OUTH), TB3 (TB3OUTH)
3
Reserved
4
MFM input
6.10.14 MFM
MFM (Manchester Function Module) is a dedicated module residing between a pair of pins and eUSCI_B1
to encode and decode Manchester-coded data. For more information, see the MFM chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide.
When enabled by setting PSEL, MFM module receives and transmits data through
P5.0/TB2.1/MFM.RX/A8 and P5.1/TB2.2/MFM.TX/A9, respectively. The MFM always works SPI master
mode, and the eUSCI_B1 must be configured in 4-wire SPI slave mode.
6.10.15 SAC0, SAC1, SAC2, SAC3 (MSP430FR235x Devices Only)
The Smart Analog Combo (SAC) integrates a high-performance low-power operational amplifier. SAC-L3
supports a hybrid configuration of general-purpose amplifier, 12-bit voltage reference DAC, and a
multiplex switch array. For more information, see the SAC chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide. Only MSP430FR235x devices implement four SAC modules on chip.
MSP430FR215x devices do not support SAC modules.
The SAC0 and SAC2 are interconnected and support external inputs and internal inputs (see Table 6-27
and Table 6-28).
Table 6-27. SAC0 Channel Connections
PSEL
SAC0 OA NONINVERTING CHANNELS
NSEL
00
P1.3/OA0+/A3
00
SAC0 OA INVERTING CHANNELS
P1.2/OA0-/A2
01
SAC0 12-bit DAC
01
PGA feedback
10
P3.1/OA2O, SAC2 OA output
10
P3.1/OA2O, SAC2 OA output
11
N/A
11
N/A
Table 6-28. SAC2 Channel Connections
PSEL
SAC2 OA NONINVERTING CHANNELS
NSEL
00
P3.3/OA2+
00
SAC2 OA INVERTING CHANNELS
P3.2/OA2-
01
SAC2 12-bit DAC
01
PGA feedback
10
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1, SAC0 OA output
10
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1, SAC0 OA output
11
N/A
11
N/A
The SAC1 and SAC3 are interconnected and support external inputs and internal inputs (see Table 6-29
and Table 6-30).
Table 6-29. SAC1 Channel Connections
PSEL
SAC1 OA NONINVERTING CHANNELS
NSEL
00
P1.7/OA1+/A7
00
SAC1 OA INVERTING CHANNELS
P1.6/OA1-/A6
01
SAC1 12-bit DAC
01
PGA feedback
10
P3.5/OA3O, SAC3 OA output
10
P3.5/OA3O, SAC3 OA output
11
N/A
11
N/A
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Table 6-30. SAC3 Channel Connections
PSEL
SAC3 OA NONINVERTING CHANNELS
NSEL
00
P3.7/OA3+
00
SAC3 OA INVERTING CHANNELS
P3.6/OA3-
01
SAC3 12-bit DAC
01
PGA feedback
10
P1.5/OA1O/A5, SAC1 OA output
10
P1.5/OA1O/A5, SAC1 OA output
11
N/A
11
N/A
Each SAC DAC supports two selectable voltage references (see Table 6-31).
Table 6-31. SACx DAC Reference Selection
DACSREF
SACx DAC Reference Selection
0
DVCC
1
Internal shared reference (1.5-, 2.0-, or 2.5-V )
DACSREF
SAC1 DAC REFERENCE
0
DVCC
1
Internal shared reference (1.5-, 2.0-, or 2.5-V )
DACSREF
SAC2 DAC REFERENCE
0
DVCC
1
Internal shared reference (1.5-, 2.0-, or 2.5-V )
DACSREF
SAC3 DAC REFERENCE
0
DVCC
1
Internal shared reference (1.5-, 2.0-, or 2.5-V )
Each SAC DAC supports one software trigger and two hardware trigger from chip signals.
Table 6-32. SACx DAC Hardware Trigger Selection
74
DACLSEL
SAC0 DAC HARDWARE TRIGGER
DACLSEL
SAC1 DAC HARDWARE TRIGGER
00
Writing SAC0DACDAT register
00
Writing SAC1DACDAT register
01
N/A
01
N/A
10
TB2.1
10
TB2.1
11
TB2.2
11
TB2.2
DACLSEL
SAC2 DAC HARDWARE TRIGGER
DACLSEL
SAC3 DAC HARDWARE TRIGGER
00
Writing SAC2DACDAT register
00
Writing SAC3DACDAT register
01
N/A
01
N/A
10
TB2.1
10
TB2.1
11
TB2.2
11
TB2.2
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6.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection
(MSP430FR235x Devices Only)
The high-performance analog modules of eCOMP0, SAC0, and SAC2 are internally connected (see
Figure 6-1).
P2.0/COMP0.O
P1.0/COMP0.0/A0
P1.1/OA0O/COMP0.1/A1
00
P1.3/OA0+/A3
01
10
SAC0
12-bit DAC
+
SAC0
OA
–
00
P1.2/OA0-/A2
01
10
000
001
010
101
eCOMP0
6-bit DAC
SAC0
PGA
110
+
eCOMP0
–
P3.1/OA2O
Polarity
Selection
To Timer
Capture
000
001
Low-power
1.2V
010
101
110
00
P3.3/OA2+
01
10
SAC2
12-bit DAC
+
SAC2
OA
–
00
P3.2/OA2-
01
10
SAC2
PGA
Figure 6-1. eCOMP0, SAC0, SAC2 Interconnection
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The high-performance analog modules of eCOMP1, SAC1, and SAC3 are internally connected (see
Figure 6-2):
P2.1/COMP1.O
P2.5/COMP1.0
P2.4/COMP1.1
P1.5/OA1O/A5
00
P1.7/OA1+/A7
01
10
SAC1
12-bit
DAC
+
SAC1
OA
–
00
P1.6/OA1-/A6
01
10
000
001
010
eCOMP1
6-bit
DAC
SAC1
PGA
101
110
+
eCOMP1
–
P3.5/OA3O
Polarity
Selection
To Timer
Capture
000
001
Low-power
1.2 V
010
101
110
00
P3.7/OA3+
01
10
SAC3
12-bit
DAC
+
SAC3
OA
–
00
P3.6/OA3-
01
10
SAC3
PGA
Figure 6-2. eCOMP1, SAC1, SAC3 Interconnection
76
Detailed Description
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6.10.17 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
6.10.18 Peripheral File Map
Table 6-33 lists the base address and the memory size of each peripheral's registers.
Table 6-33. Peripherals Summary
BASE ADDRESS
SIZE
Special Functions (see Table 6-34)
MODULE NAME
0100h
0010h
PMM (see Table 6-35)
0120h
0020h
SYS (see Table 6-36)
0140h
0040h
CS (see Table 6-37)
0180h
0020h
FRAM (see Table 6-38)
01A0h
0010h
CRC (see Table 6-39)
01C0h
0008h
WDT (see Table 6-40)
01CCh
0002h
Port P1, P2 (see Table 6-41)
0200h
0020h
Port P3, P4 (see Table 6-42)
0220h
0020h
Port P5, P6 (see Table 6-43)
0240h
0020h
RTC (see Table 6-44)
0300h
0010h
Timer0_B3 (see Table 6-45)
0380h
0030h
Timer1_B3 (see Table 6-46)
03C0h
0030h
Timer2_B3 (see Table 6-47)
0400h
0030h
Timer3_B7 (see Table 6-48)
0440h
0030h
MPY32 (see Table 6-49)
04C0h
0030h
eUSCI_A0 (see Table 6-50)
0500h
0020h
eUSCI_B0 (see Table 6-51)
0540h
0030h
eUSCI_A1 (see Table 6-52)
0580h
0020h
eUSCI_B1 (see Table 6-53)
05C0h
0030h
Backup Memory (see Table 6-54)
0660h
0020h
ICC (see Table 6-55)
06C0h
0010h
ADC (see Table 6-56)
0700h
0040h
eCOMP0 (see Table 6-57)
08E0h
0020h
eCOMP1 (see Table 6-58)
0900h
0020h
(1)
0C80h
0010h
SAC1 (see Table 6-60) (1)
0C90h
0010h
SAC2 (see Table 6-61) (1)
0CA0h
0010h
(1)
0CB0h
0010h
SAC0 (see Table 6-59)
SAC3 (see Table 6-62)
(1)
MSP430FR235x devices only
Detailed Description
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Table 6-34. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
SFR interrupt enable
SFR interrupt flag
SFR reset pin control
ACRONYM
OFFSET
SFRIE1
00h
SFRIFG1
02h
SFRRPCR
04h
Table 6-35. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
PMM control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
PMM control 2
PMMCTL2
04h
PMM interrupt flags
PMMIFG
0Ah
PM5 control 0
PM5CTL0
10h
Table 6-36. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
SYSCTL
00h
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
System control
Bootloader configuration area
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
System configuration 0
SYSCFG0
20h
System configuration 1
SYSCFG1
22h
System configuration 2
SYSCFG2
24h
System configuration 3
SYSCFG3
26h
Table 6-37. CS Registers (Base Address: 0180h)
ACRONYM
OFFSET
CS control 0
REGISTER DESCRIPTION
CSCTL0
00h
CS control 1
CSCTL1
02h
CS control 2
CSCTL2
04h
CS control 3
CSCTL3
06h
CS control 4
CSCTL4
08h
CS control 5
CSCTL5
0Ah
CS control 6
CSCTL6
0Ch
CS control 7
CSCTL7
0Eh
CS control 8
CSCTL8
10h
78
Detailed Description
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Table 6-38. FRAM Registers (Base Address: 01A0h)
ACRONYM
OFFSET
FRAM control 0
REGISTER DESCRIPTION
FRCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
Table 6-39. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 6-40. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
Watchdog timer control
ACRONYM
OFFSET
WDTCTL
00h
Table 6-41. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
P1IN
00h
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pulling enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
P1SEL1
0Ch
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
P1IE
1Ah
P1IFG
1Ch
P2IN
01h
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pulling enable
P2REN
07h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1
P2SEL1
0Dh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
P2IE
1Bh
P2IFG
1Dh
Port P1 input
Port P1 output
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
Port P2 output
Port P2 interrupt enable
Port P2 interrupt flag
Detailed Description
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Table 6-42. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 input
Port P3 pulling enable
P3REN
06h
Port P3 selection 0
P3SEL0
0Ah
Port P3 selection 1
P3SEL1
0Ch
Port P3 interrupt vector word
P3IV
0Eh
Port P3 interrupt edge select
P3IES
18h
P3IE
1Ah
P3IFG
1Ch
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P3 interrupt enable
Port P3 interrupt flag
Port P4 input
Port P4 pulling enable
P4REN
07h
Port P4 selection 0
P4SEL0
0Bh
Port P4 selection 1
P4SEL1
0Dh
Port P4 interrupt vector word
P4IV
1Eh
Port P4 interrupt edge select
P4IES
19h
P4IE
1Bh
P4IFG
1Dh
Port P4 interrupt enable
Port P4 interrupt flag
Table 6-43. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
Port P5 input
ACRONYM
OFFSET
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pulling enable
P5REN
06h
Port P5 selection 0
P5SEL0
0Ah
Port P5 selection 1
P5SEL1
0Ch
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pulling enable
P6REN
07h
Port P6 selection 0
P6SEL0
0Bh
Port P6 selection 1
P6SEL1
0Dh
Table 6-44. RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTION
RTC control
RTC interrupt vector
ACRONYM
OFFSET
RTCCTL
00h
RTCIV
04h
RTC modulo
RTCMOD
08h
RTC counter
RTCCNT
0Ch
80
Detailed Description
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-45. Timer0_B3 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
TB0R
10h
Capture/compare 0
TB0CCR0
12h
Capture/compare 1
TB0CCR1
14h
Capture/compare 2
TB0CCR2
16h
TB0EX0
20h
TB0IV
2Eh
TB0 control
TB0 counter
TB0 expansion 0
TB0 interrupt vector
Table 6-46. Timer1_B3 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
TB1 control
ACRONYM
OFFSET
TB1CTL
00h
Capture/compare control 0
TB1CCTL0
02h
Capture/compare control 1
TB1CCTL1
04h
Capture/compare control 2
TB1CCTL2
06h
TB1R
10h
Capture/compare 0
TB1CCR0
12h
Capture/compare 1
TB1CCR1
14h
Capture/compare 2
TB1CCR2
16h
TB1 counter
TB1 expansion 0
TB1 interrupt vector
TB1EX0
20h
TB1IV
2Eh
Table 6-47. Timer2_B3 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
TB2 control
ACRONYM
OFFSET
TB2CTL
00h
Capture/compare control 0
TB2CCTL0
02h
Capture/compare control 1
TB2CCTL1
04h
Capture/compare control 2
TB2CCTL2
06h
TB2R
10h
Capture/compare 0
TB2CCR0
12h
Capture/compare 1
TB2CCR1
14h
Capture/compare 2
TB2CCR2
16h
TB2 counter
TB2 expansion 0
TB2 interrupt vector
TB2EX0
20h
TB2IV
2Eh
Detailed Description
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Table 6-48. Timer3_B7 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TB3CTL
00h
Capture/compare control 0
TB3CCTL0
02h
Capture/compare control 1
TB3CCTL1
04h
Capture/compare control 2
TB3CCTL2
06h
Capture/compare control 3
TB3CCTL3
08h
Capture/compare control 4
TB3CCTL4
0Ah
Capture/compare control 5
TB3CCTL5
0Ch
Capture/compare control 6
TB3CCTL6
0Eh
TB3R
10h
Capture/compare 0
TB3CCR0
12h
Capture/compare 1
TB3CCR1
14h
Capture/compare 2
TB3CCR2
16h
Capture/compare 3
TB3CCR3
18h
Capture/compare 4
TB3CCR4
1Ah
Capture/compare 5
TB3CCR5
1Ch
Capture/compare 6
TB3CCR6
1Eh
TB3 control
TB3 counter
TB3 expansion 0
TB3 interrupt vector
TB3EX0
20h
TB3IV
2Eh
Table 6-49. MPY32 Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
16-bit operand 1 – multiply
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
ACRONYM
OFFSET
MPY
00h
MPYS
02h
MAC
04h
MACS
06h
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
16 × 16 sum extension
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32CTL0
2Ch
MPY32 control 0
82
Detailed Description
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-50. eUSCI_A0 Registers (Base Address: 0500h)
ACRONYM
OFFSET
eUSCI_A control word 0
REGISTER DESCRIPTION
UCA0CTLW0
00h
eUSCI_A control word 1
UCA0CTLW1
02h
eUSCI_A control rate 0
UCA0BR0
06h
UCA0BR1
07h
eUSCI_A control rate 1
eUSCI_A modulation control
UCA0MCTLW
08h
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
lUCA0IRTCTL
12h
eUSCI_A IrDA receive control
IUCA0IRRCTL
13h
UCA0IE
1Ah
UCA0IFG
1Ch
UCA0IV
1Eh
eUSCI_A status
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
Table 6-51. eUSCI_B0 Registers (Base Address: 0540h)
ACRONYM
OFFSET
eUSCI_B control word 0
REGISTER DESCRIPTION
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
UCB0ADDRX
1Ch
UCB0ADDMASK
1Eh
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
UCB0I2CSA
20h
UCB0IE
2Ah
UCB0IFG
2Ch
UCB0IV
2Eh
Detailed Description
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Table 6-52. eUSCI_A1 Registers (Base Address: 0580h)
ACRONYM
OFFSET
eUSCI_A control word 0
REGISTER DESCRIPTION
UCA1CTLW0
00h
eUSCI_A control word 1
UCA1CTLW1
02h
eUSCI_A control rate 0
UCA1BR0
06h
UCA1BR1
07h
eUSCI_A control rate 1
eUSCI_A modulation control
UCA1MCTLW
08h
UCA1STAT
0Ah
eUSCI_A receive buffer
UCA1RXBUF
0Ch
eUSCI_A transmit buffer
UCA1TXBUF
0Eh
eUSCI_A LIN control
UCA1ABCTL
10h
eUSCI_A IrDA transmit control
lUCA1IRTCTL
12h
eUSCI_A IrDA receive control
IUCA1IRRCTL
13h
UCA1IE
1Ah
UCA1IFG
1Ch
UCA1IV
1Eh
eUSCI_A status
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
Table 6-53. eUSCI_B1 Registers (Base Address: 05C0h)
ACRONYM
OFFSET
eUSCI_B control word 0
REGISTER DESCRIPTION
UCB1CTLW0
00h
eUSCI_B control word 1
UCB1CTLW1
02h
eUSCI_B bit rate 0
UCB1BR0
06h
eUSCI_B bit rate 1
UCB1BR1
07h
eUSCI_B status word
UCB1STATW
08h
eUSCI_B byte counter threshold
UCB1TBCNT
0Ah
eUSCI_B receive buffer
UCB1RXBUF
0Ch
eUSCI_B transmit buffer
UCB1TXBUF
0Eh
eUSCI_B I2C own address 0
UCB1I2COA0
14h
eUSCI_B I2C own address 1
UCB1I2COA1
16h
eUSCI_B I2C own address 2
UCB1I2COA2
18h
eUSCI_B I2C own address 3
UCB1I2COA3
1Ah
UCB1ADDRX
1Ch
UCB1ADDMASK
1Eh
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
84
Detailed Description
UCB1I2CSA
20h
UCB1IE
2Ah
UCB1IFG
2Ch
UCB1IV
2Eh
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-54. Backup Memory Registers (Base Address: 0660h)
ACRONYM
OFFSET
Backup memory 0
REGISTER DESCRIPTION
BAKMEM0
00h
Backup memory 1
BAKMEM1
02h
Backup memory 2
BAKMEM2
04h
Backup memory 3
BAKMEM3
06h
Backup memory 4
BAKMEM4
08h
Backup memory 5
BAKMEM5
0Ah
Backup memory 6
BAKMEM6
0Ch
Backup memory 7
BAKMEM7
0Eh
Backup memory 8
BAKMEM8
10h
Backup memory 9
BAKMEM9
12h
Backup memory 10
BAKMEM10
14h
Backup memory 11
BAKMEM11
16h
Backup memory 12
BAKMEM12
18h
Backup memory 13
BAKMEM13
1Ah
Backup memory 14
BAKMEM14
1Ch
Backup memory 15
BAKMEM15
1Eh
Table 6-55. ICC Registers (Base Address: 06C0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
ICC status and control
ICCSC
00h
ICC mask virtual stack
ICCMVS
02h
ICC interrupt level setting 0
ICCILSR0
04h
ICC interrupt level setting 1
ICCILSR1
06h
ICC interrupt level setting 2
ICCILSR2
08h
ICC interrupt level setting 3
ICCILSR3
0Ah
Table 6-56. ADC Registers (Base Address: 0700h)
ACRONYM
OFFSET
ADC control 0
REGISTER DESCRIPTION
ADCCTL0
00h
ADC control 1
ADCCTL1
02h
ADC control 2
ADCCTL2
04h
ADC window comparator low threshold
ADCLO
06h
ADC window comparator high threshold
ADCHI
08h
ADC memory control 0
ADCMCTL0
0Ah
ADC conversion memory
ADCMEM0
12h
ADCIE
1Ah
ADCIFG
1Ch
ADCIV
1Eh
ADC interrupt enable
ADC interrupt flags
ADC interrupt vector word
Detailed Description
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Table 6-57. eCOMP0 Registers (Base Address: 08E0h)
ACRONYM
OFFSET
Comparator control 0
REGISTER DESCRIPTION
CP0CTL0
00h
Comparator control 1
CP0CTL1
02h
Comparator interrupt
CP0INT
06h
Comparator interrupt vector
Comparator built-in DAC control
Comparator built-in DAC data
CP0IV
08h
CP0DACCTL
10h
CP0DACDATA
12h
Table 6-58. eCOMP1 Registers (Base Address: 0900h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
Comparator control 0
CP1CTL0
00h
Comparator control 1
CP1CTL1
02h
Comparator interrupt
CP1INT
06h
CP1IV
08h
CP1DACCTL
10h
CP1DACDATA
12h
Comparator interrupt vector
Comparator built-in DAC control
Comparator built-in DAC data
Table 6-59. SAC0 Registers (Base Address: 0C80h, MSP430FR235x Devices Only)
REGISTER DESCRIPTION
ACRONYM
OFFSET
SAC0OA
00h
SAC0 PGA control
SAC0PGA
02h
SAC0 DAC control
SAC0DAC
04h
SAC0 DAC data
SAC0DAT
06h
SAC0DATSTS
08h
SAC0IV
0Ah
SAC0 OA control
SAC0 DAC status
SAC0 interrupt vector
Table 6-60. SAC1 Registers (Base Address: 0C90h, MSP430FR235x Devices Only)
REGISTER DESCRIPTION
ACRONYM
OFFSET
SAC1OA
00h
SAC1 PGA control
SAC1PGA
02h
SAC1 DAC control
SAC1DAC
04h
SAC1 DAC data
SAC1DAT
06h
SAC1 OA control
SAC1 DAC status
SAC1 interrupt vector
SAC1DATSTS
08h
SAC1IV
0Ah
Table 6-61. SAC2 Registers (Base Address: 0CA0h, MSP430FR235x Devices Only)
REGISTER DESCRIPTION
SAC2 OA control
ACRONYM
OFFSET
SAC2OA
00h
SAC2 PGA control
SAC2PGA
02h
SAC2 DAC control
SAC2DAC
04h
SAC2DAT
06h
SAC2 DAC data
SAC2 DAC status
SAC2 interrupt vector
86
Detailed Description
SAC2DATSTS
08h
SAC2IV
0Ah
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-62. SAC3 Registers (Base Address: 0CB0h, MSP430FR235x Devices Only)
REGISTER DESCRIPTION
ACRONYM
OFFSET
SAC3OA
00h
SAC3 PGA control
SAC3PGA
02h
SAC3 DAC control
SAC3DAC
04h
SAC3DAT
06h
SAC3 OA control
SAC3 DAC data
SAC3 DAC status
SAC3 interrupt vector
SAC3DATSTS
08h
SAC3IV
0Ah
Detailed Description
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6.11 Input/Output Diagrams
6.11.1 Port P1 Input/Output With Schmitt Trigger
Figure 6-3 shows the port diagram. Table 6-63 summarizes the selection of the port function.
A0..A7
OA0+, OA0-, OA0O
OA1+, OA1-, OA1O
COMP0.0, COMP0.1
P1REN.x
00
01
10
P1DIR.x
From Module 1
From Module 2
DVSS
0
DVCC
1
P1OUT.x
From Module 1
From Module 2
00
01
10
P1SEL0
P1SEL1
EN
D
To module
P1IN.x
P1IE.x
P1 Interrupt
Q
D
S
P1IFG.x
Edge
Select
P1IES.x
From JTAG
Bus
Keeper
P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+
P1.1/UCB0CLK/ACLK/OA0O/COMP0.1/A1
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/VerefP1.3/UCB0SOMI/UCB0SCL/A3
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
To JTAG
Figure 6-3. Port P1 Input/Output With Schmitt Trigger
88
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-63. Port P1 Pin Functions
PIN NAME (P1.x)
x
P1.0/UCB0STE/SMCLK/
COMP0.0/A0/Veref+
P1.1/UCB0CLK/ACLK/
OA0O/COMP0.1/A1
0
1
FUNCTION
P1DIR.x
P1SELx
JTAG
P1.0 (I/O)
I: 0; O: 1
00
N/A
UCB0STE
X
01
N/A
SMCLK
1
VSS
0
10
N/A
COMP0.0, A0/Veref+
X
11
N/A
P1.1 (I/O)
I: 0; O: 1
0
N/A
UCB0CLK
X
01
N/A
ACLK
1
VSS
0
10
N/A
OA0O (2), COMP0.1, A1
X
11
N/A
I: 0; O: 1
00
N/A
X
01
N/A
TB0TRG
0
10
N/A
OA0- (2), A2/Veref-
X
11
N/A
I: 0; O: 1
00
N/A
UCB0SOMI/UCB0SCL
X
01
N/A
OA0+ (2), A3
X
11
N/A
P1.4 (I/O)
I: 0; O: 1
00
Disabled
UCA0STE
X
01
Disabled
A4
X
11
Disabled
JTAG TCK
X
X
TCK
P1.5 (I/O)
I: 0; O: 1
00
Disabled
UCA0CLK
X
01
Disabled
OA1O (2), A5
X
11
Disabled
JTAG TMS
X
X
TMS
P1.2 (I/O)
P1.2/UCB0SIMO/
UCB0SDA/TB0TRG/
OA0-/A2/Veref-
2
UCB0SIMO/UCB0SDA
P1.3 (I/O)
P1.3/UCB0SOMI/
UCB0SCL/OA0+/A3
3
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/
OA1O/A5
4
5
P1.6 (I/O)
P1.6/UCA0RXD/
UCA0SOMI/TB0.1/TDI/
TCLK/OA1-/A6
6
I: 0; O: 1
00
Disabled
UCA0RXD/UCA0SOMI
X
01
Disabled
TB0.CCI1A
0
TB0.1
1
10
Disabled
OA1- (2), A6
X
11
Disabled
JTAG TDI/TCLK
X
X
TDI/TCLK
I: 0; O: 1
00
Disabled
UCA0TXD/UCA0SIMO
X
01
Disabled
TB0.CCI2A
0
TB0.2
1
10
Disabled
OA1+ (2), A7, VREF+
X
11
Disabled
JTAG TDO
X
X
TDO
P1.7 (I/O)
P1.7/UCA0TXD/
UCA0SIMO/TB0.2/TDO/
OA1+/A7/VREF+
(1)
(2)
7
CONTROL BITS AND SIGNALS (1)
X = don't care
MSP430FR235x devices only
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6.11.2 Port P2 Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-64 summarizes the selection of the port function.
COMP1.0, COMP1.1
P2REN.x
00
01
10
P2DIR.x
From Module 1
From Module 2
DVSS
0
DVCC
1
P2OUT.x
From Module 1
From Module 2
00
01
10
P2SEL0
P2SEL1
EN
D
To module
P2IN.x
P2IE.x
P2 Interrupt
Q
D
S
P2IFG.x
Edge
Select
P2IES.x
Bus
Keeper
P2.0/TB1.1/COMP0.O
P2.1/TB1.2/COMP1.O
P2.2/TB1CLK
P2.3/TB1TRG
P2.4/COMP1.1
P2.5/COMP1.0
P2.6/MCLK/XOUT
P2.7/TB0CLK/XIN
Figure 6-4. Port P2 Input/Output With Schmitt Trigger
90
Detailed Description
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-64. Port P2 Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
P2.0/TB1.1/COMP0.O
0
P2.1/TB1.2
1
P2.2/TB1CLK
2
P2.3/UCB0CLK/TB1TRG
3
P2.4/COMP1.1
4
P2.5/COMP1.0
5
P2.6/MCLK/XOUT
6
(1)
7
P2DIR.x
P2SELx
I: 0; O: 1
00
TB1.CCI1A
0
TB1.1
1
01
COMP0.O
1
10
P2.1 (I/O)0
I: 0; O: 1
00
TB1.CCI2A
0
TB1.2
1
COMP1.O
1
10
P2.2 (I/O)
I: 0; O: 1
00
TB1CLK
0
01
P2.3 (I/O)
I: 0; O: 1
00
TB1TRG
0
VSS
1
01
01
P2.4 (I/O)
I: 0; O: 1
00
COMP1.1
X
11
P2.5 (I/O)
I: 0; O: 1
00
COMP1.0
X
11
P2.6 (I/O)
I: 0; O: 1
00
MCLK
1
VSS
0
XOUT
P2.7/TB0CLK/XIN
CONTROL BITS AND SIGNALS (1)
01
X
10
P2.7 (I/O)
I: 0; O: 1
00
TB0CLK
0
VSS
1
XIN
X
01
10
X = don't care
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6.11.3 Port P3 Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-65 summarizes the selection of the port function.
OA2O, OA2-, OA2+
OA3O, OA3-, OA3+
P3REN.x
00
01
10
P3DIR.x
From Module 1
From Module 2
DVSS
0
DVCC
1
P3OUT.x
From Module 1
From Module 2
00
01
10
P3SEL0
P3SEL1
EN
D
To module
P3IN.x
P3IE.x
P3 Interrupt
Q
D
S
P3IFG.x
Edge
Select
P3IES.x
Bus
Keeper
P3.0/MCLK
P3.1/OA2O
P3.2/OA2P3.3/OA2+
P3.4/SMCLK
P3.5/OA3O
P3.6/OA3P3.7/OA3+
Figure 6-5. Port P3 Input/Output With Schmitt Trigger
92
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-65. Port P3 Pin Functions
PIN NAME (P3.x)
x
FUNCTION
P3.0 (I/O)
P3.0/MCLK
0
P3.1/OA2O
1
P3.2/OA2-
2
P3.3/OA2+
3
P3.5/OA3O
P3.6/OA3P3.7/OA3+
(1)
(2)
4
5
6
7
P3DIR.x
P3SELx
I: 0; O: 1
00
MCLK
1
VSS
0
01
P3.1 (I/O)
I: 0; O: 1
00
OA2O (2)
X
11
P3.2 (I/O)
I: 0; O: 1
00
X
11
I: 0; O: 1
00
X
11
I: 0; O: 1
00
OA2- (2)
P3.3 (I/O)
OA2+
(2)
P3.4 (I/O)
P3.4/SMCLK
CONTROL BITS AND SIGNALS (1)
SMCLK
1
VSS
0
01
P3.5 (I/O)
I: 0; O: 1
00
OA3O (2)
X
11
P3.6 (I/O)
I: 0; O: 1
00
OA3-
(2)
P3.7 (I/O)
OA3+ (2)
X
11
I: 0; O: 1
00
X
11
X = don't care
MSP430FR235x devices only
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6.11.4 Port P4 Input/Output With Schmitt Trigger
Figure 6-6 shows the port diagram. Table 6-66 summarizes the selection of the port function.
P4REN.x
00
01
10
P4DIR.x
From Module 1
From Module 2
DVSS
0
DVCC
1
P4OUT.x
From Module 1
From Module 2
00
01
10
P4SEL0
P4SEL1
EN
D
To module
P4IN.x
P4IE.x
P4 Interrupt
Q
D
S
P4IFG.x
Edge
Select
P4IES.x
Bus
Keeper
P4.0/UCA1STE/ISOTXD/ISORXD
P4.1/UCA1CLK
P4.2/UCA1RXD/UCA1SOMI/UCA1RXD
P4.3/UCA1TXD/UCA1SIMO/UCA1TXD
P4.4/UCB1STE
P4.5/UCB1CLK
P4.6/UCB1SIMO/UCB1SDA
P4.7/UCB1SOMI/UCB1SCL
Figure 6-6. Port P4 Input/Output With Schmitt Trigger
94
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-66. Port P4 Pin Functions
PIN NAME (P4.x)
x
P4.0/UCA1STE
0
P4.1/UCA1CLK
1
P4.2/UCA1RXD/
UCA1SOMI/UCA1RXD
2
P4.3/UCA1TXD/
UCA1SIMO/UCA1TXD
3
P4.4/UCB1STE
4
P4.5/UCB1CLK
5
P4.6/UCB1SIMO/UCB1SDA
6
P4.7/UCB1SOMI/UCB1SCL
7
(1)
FUNCTION
CONTROL BITS AND SIGNALS (1)
P4DIR.x
P4SELx
P4.0 (I/O)
I: 0; O: 1
00
UCA1STE
X
01
UCA1RXD, TB3.CCI2B
0
UCA1TXD logic-AND TB3.2B
1
P4.1 (I/O)
10
I: 0; O: 1
00
UCA1CLK
X
01
P4.2 (I/O)
I: 0; O: 1
00
X
01
UCA1RXD
X
10
P4.3 (I/O)
I: 0; O: 1
00
UCA1TXD/UCA1SIMO
X
01
UCA1TXD
X
10
P4.4 (I/O)
I: 0; O: 1
00
UCB1STE
X
01
P4.5 (I/O)
I: 0; O: 1
00
UCB1CLK
X
01
P4.6 (I/O)
I: 0; O: 1
00
X
01
I: 0; O: 1
00
X
01
UCA1RXD/UCA1SOMI
UCB1SIMO/UCB1SDA
P4.7 (I/O)
UCB1SOMI/UCB1SCL
X = don't care
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6.11.5 Port P5 Input/Output With Schmitt Trigger
Figure 6-7 shows the port diagram. Table 6-67 summarizes the selection of the port function.
A8, A9, A10, A11
P5REN.x
00
01
10
P5DIR.x
From Module 1
From Module 2
DVSS
0
DVCC
1
P5OUT.x
From Module 1
From Module 2
00
01
10
P5SEL0
P5SEL1
EN
D
To module
P5IN.x
Bus
Keeper
P5.0/TB2.1/MFM.RX/A8
P5.1/TB2.2/MFM.TX/A9
P5.2/TB2CLK/A10
P5.3/TB2TRG/A11
P5.4
Figure 6-7. Port P5 Input/Output With Schmitt Trigger
96
Detailed Description
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-67. Port P5 Pin Functions
PIN NAME (P5.x)
x
FUNCTION
P5.0 (I/O)
P5.0/TB2.1/MFM.RX/A8
0
P5.2/TB2CLK/A10
1
2
P5.4
(1)
4
00
TB2.1
O
MFM.RX
X
10
A8
X
11
I: 0; O: 1
00
01
TB2.CCI2A
I
TB2.2
O
MFM.TX
X
10
A9
X
11
P5.2 (I/O)
I: 0; O: 1
00
TB2CLK
I
VSS
O
P5.3 (I/O)
3
P5SELx
I
A10
P5.3/TB2TRG/A11
P5DIR.x
I: 0; O: 1
TB2.CCI1A
P5.1 (I/O)
P5.1/TB2.2/MFM.TX/A9
CONTROL BITS AND SIGNALS (1)
01
01
X
11
I: 0; O: 1
00
TB2TRG
I
VSS
O
A11
X
11
I: 0; O: 1
00
P5.4 (I/O)
01
X = don't care
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6.11.6 Port P6 Input/Output With Schmitt Trigger
Figure 6-8 shows the port diagram. Table 6-68 summarizes the selection of the port function.
P6REN.x
00
01
10
P6DIR.x
From Module 1
From Module 2
DVSS
0
DVCC
1
P6OUT.x
From Module 1
From Module 2
00
01
10
P6SEL0
P6SEL1
EN
D
To module
P6IN.x
Bus
Keeper
P6.0/TB3.1
P6.1/TB3.2
P6.2/TB3.3
P6.3/TB3.4
P6.4/TB3.5
P6.5/TB3.6
P6.6/TB3CLK
Figure 6-8. Port P6 Input/Output With Schmitt Trigger
98
Detailed Description
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-68. Port P6 Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.0 (I/O)
P6.0/TB3.1
0
1
2
3
1
4
0
TB3.2
1
P6.6/TB3CLK
(1)
5
6
I: 0; O: 1
TB3.CCI3A
0
TB3.3
1
I: 0; O: 1
TB3.CCI4A
0
TB3.4
1
I: 0; O: 1
TB3.CCI5A
0
TB3.5
1
P6.5 (I/O)
P6.5/TB3.6
I: 0; O: 1
TB3.CCI2A
P6.4 (I/O)
P6.4/TB3.5
00
TB3.1
P6.3 (I/O)
P6.3/TB3.4
P6SELx
0
P6.2 (I/O)
P6.2/TB3.3
P6DIR.x
I: 0; O: 1
TB3.CCI1A
P6.1 (I/O)
P6.1/TB3.2
CONTROL BITS AND SIGNALS (1)
I: 0; O: 1
TB3.CCI6A
0
TB3.6
1
P6.6 (I/O)
I: 0; O: 1
TB3CLK
0
VSS
1
01
00
01
00
01
00
01
00
01
00
01
00
01
X = don't care
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6.12 Device Descriptors (TLV)
Table 6-69 lists the Device IDs. Table 6-70 lists the contents of the device descriptor tag-length-value
(TLV) structure.
Table 6-69. Device IDs
DEVICE ID
DEVICE
1A04h
1A05h
MSP430FR2355
0C
83
MSP430FR2353
0D
83
MSP430FR2155
1E
83
MSP430FR2153
1D
83
Table 6-70. Device Descriptors
DESCRIPTION
VALUE
Info length
1A00h
06h
CRC length
1A01h
06h
1A02h
Per unit
1A03h
Per unit
CRC value (1)
Information block
Device ID
1A05h
See
(2)
1A06h
Per unit
Firmware revision
1A07h
Per unit
Die record tag
1A08h
08h
Die record length
1A09h
0Ah
1A0Ah
Per unit
1A0Bh
Per unit
1A0Ch
Per unit
1A0Dh
Per unit
1A0Eh
Per unit
1A0Fh
Per unit
1A10h
Per unit
1A11h
Per unit
1A12h
Per unit
1A13h
Per unit
Die record
Die X position
Die Y position
Test result
100
1A04h
Hardware revision
Lot wafer ID
(1)
(2)
MSP430FR235x, MSP430FR215x
ADDRESS
CRC value covers the checksum from 0x1A04h to 0x1A07h by applying CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1
MSP430FR235x devices only
Detailed Description
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Table 6-70. Device Descriptors (continued)
MSP430FR235x, MSP430FR215x
DESCRIPTION
ADDRESS
VALUE
ADC calibration tag
1A14h
11h
ADC calibration length
1A15h
10h
1A16h
Per unit
1A17h
Per unit
1A18h
Per unit
1A19h
Per unit
1A1Ah
Per unit
1A1Bh
Per unit
1A1Ch
Per unit
1A1Dh
Per unit
1A1Eh
Per unit
1A1Fh
Per unit
1A20h
Per unit
1A21h
Per unit
1A22h
Per unit
1A23h
Per unit
1A24h
Per unit
1A25h
Per unit
ADC gain factor
ADC offset
ADC internal shared 1.5-V reference, temperature 30°C
ADC calibration
ADC internal shared 1.5-V reference, high temperature (3)
ADC internal shared 2.0-V reference, temperature 30°C
ADC internal shared 2.0-V reference, high temperature (3)
ADC internal shared 2.5-V reference, temperature 30°C
ADC internal shared 2.5-V reference, high temperature (3)
Calibration tag
1A26h
12h
Calibration length
1A27h
0Ah
1A28h
Per unit
1A29h
Per unit
1A2Ah
Per unit
Internal shared 1.5-V reference factor
Internal shared 2.0-V reference factor
Reference and DCO
calibration
Internal shared 2.5-V reference factor
DCO tap settings for 16 MHz, temperature 30°C
DCO tap settings for 24 MHz, temperature 30°C
(3)
(4)
(4)
1A2Bh
Per unit
1A2Ch
Per unit
1A2Dh
Per unit
1A2Eh
Per unit
1A2Fh
Per unit
1A30h
Per unit
1A31h
Per unit
The calibration value is device dependent at 105°C.
This value can be directly loaded into the DCO bits in the CSCTL0 register to get an accurate 24-MHz frequency at room temperature,
especially when MCU exits from LPM3 and below. TI also suggests to use a predivider to decrease the frequency if the temperature drift
might result an overshoot faster than 24 MHz.
Detailed Description
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6.13 Identification
6.13.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see Section 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.12.
6.13.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see Section 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.12.
6.13.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming With the JTAG Interface.
102
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430 MCU. These
guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
It is recommended to connect a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling
capacitor to the DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up time.
Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few
millimeters).
DVCC
Digital
Power Supply
Decoupling
+
10 µF
100 nF
DVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
Depending on the device variant (see Table 3-1), the device can support a low-frequency crystal (32 kHz)
on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they
are left unused, they must be terminated according to Section 4.6.
Figure 7-2 shows a typical connection diagram.
LFXIN
or
HFXIN
CL1
LFXOUT
or
HFXOUT
CL2
Figure 7-2. Typical Crystal Connection
Applications, Implementation, and Layout
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See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430™ devices.
7.1.3
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target
board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the
jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide.
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDI
TDO/TDI
TDI
TMS
TMS
TCK
TCK
GND
RST
TEST/SBWTCK
C1
1 nF
(see Note B)
DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
104
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
1 nF
(see Note B)
DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The deviceRST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown
capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced
control registers and bits.
7.1.5
Unused Pins
For details on the connection of unused pins, seeSection 4.6.
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7.1.6
www.ti.com
General Layout Recommendations
•
•
•
•
7.1.7
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
Do's and Don'ts
During power up, power down, and device operation, the voltage difference between AVCC and DVCC
must not exceed the limits specified in the Absolute Maximum Ratings section. Exceeding the specified
limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC Peripheral
7.2.1.1
Partial Schematic
DVSS
Using an external
positive reference
VREF+/VEREF+
+
10 µF
100 nF
Using an external
negative reference
VEREF+
10 µF
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. This current can generate small unwanted offset voltages that can add to
or subtract from the reference or input voltages of the ADC. The general guidelines in Section 7.1.1
combined with the connections shown in Section 7.2.1.1 prevent these offset voltages.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.
106
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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency
ripple. A 100-nF bypass capacitor filters out any high-frequency noise.
7.2.1.3
Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins to avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
7.3
ROM Libraries
The MSP430FR235x and MSP430FR215x devices in the MSP430FR4xx family have MSP430 Driver
Library and FFT Library in ROM.
MSP430 software libraries in ROM are tested to work with both Code Composer Studio and IAR
Embedded Workbench toolchains.
• For the ROM image to be compatible between CCS and IAR toolchains, there are certain project
properties restrictions. See the TI.com attribute guide for more details.
• To use DriverLib in ROM, #include "rom_driverlib.h". Header file checks continue to provide helpful
hints at build time until the user application adheres to __cc_rom.
• To use FFTLib in ROM, #include "DSPLib.h". FFTLib is a subset of the MSP software library DSPLib.
• For more information, see the MSP430 Driver Library for MSP430FR2xx_4xx ROM README and
MSP DSP Library ROM README in MSP430Ware. The library ROM image is located above the 64KB
memory address. Application code using ROM must be large code model (20-bit address pointer rather
than 16-bit address pointer).
Benefits of ROM library use include:
• Code execution at clock speeds that exceed 8 MHz is faster from ROM than from FRAM, because the
code avoids FRAM wait states (except FRAM controller cache hits). Without FRAM wait states, code
execution performance is limited by only the processor clock, which is generally faster than other
subsystems. Executing code from RAM gives comparable performance, but the available RAM size is
typically more limited.
• More nonvolatile storage (FRAM) available in the device is left for application code.
7.4
Typical Applications
Table 7-1 lists TI reference designs that use the MSP430FR235x devices in real-world application
scenarios. Consult these designs for additional guidance regarding schematic, layout, and software
implementation. For the most up-to-date list of available TI reference designs, visit the TI Reference
Designs Library.
Table 7-1. TI Reference Designs
DESIGN NAME
LINK
4- to 20-mA Loop-Powered RTD Temperature Transmitter Reference Design With MSP430 Smart Analog Combo
TIDM-01000
MSP430FR2355 LaunchPad Development Kit
MSP-EXP430FR2355
Applications, Implementation, and Layout
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8 Device and Documentation Support
8.1
Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
8.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. Figure 8-1 provides a legend for reading the
complete device name.
MSP 430 FR 2 355 T PT R
Processor Family
Distribution Format
Packaging
Platform
Memory Type
Series
Temperature Range
Feature Set
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
Platform
Memory Type
Series
Feature Set
430 = MSP430 16-Bit Low-Power Microcontroller
FR = FRAM
2 = FRAM 2 Series, up to 24 MHz without LCD
First and Second Digits:
SAC Level / ADC Channels / COMP / 16-bit Timers / I/Os
35 = SAC-L3 / Up to 12 / 2 / 4 / Up to 44
15 = No SAC / Up to 12 / 2 / 4 / Up to 44
T = –40°C to 105°C
http://www.ti.com/packaging
Temperature Range
Packaging
Distribution Format
Third Digit:
FRAM (KB) / SRAM (KB)
5 = 32 / 4
3 = 16 / 2
T = Small reel
R = Large reel
No marking = Tube or tray
Figure 8-1. Device Nomenclature
108
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8.3
SLASEC4A – MAY 2018 – REVISED JUNE 2018
Tools and Software
See the Code Composer Studio for MSP430 User's Guide for details on the available features.
Table 8-1 lists the debug features supported by the MSP430FR235x microcontrollers.
Table 8-1. Hardware Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
EEM
VERSION
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
No
S
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430FR235x Code Examples C Code examples are available for every MSP device that configures
each of the integrated peripherals for various application needs.
MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that
free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough
documentation is delivered through a helpful API Guide, which includes details on each
function call and the recognized parameters. Developers can use Driver Library functions to
write complete projects with minimal overhead.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the energy profile of the application
and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully use the unique ultra-low-power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and
remarks to highlight areas of your code that can be further optimized for lower power.
FRAM Embedded Software Utilities for MSP Ultra-Low-Power Microcontrollers The FRAM Utilities is
designed to grow as a collection of embedded software utilities that leverage the ultra-lowpower and virtually unlimited write endurance of FRAM. The utilities are available for
MSP430FRxx FRAM microcontrollers and provide example code to help start application
development. Included utilities include Compute Through Power Loss (CTPL). CTPL is utility
API set that enables ease of use with LPMx.5 low-power modes and a powerful shutdown
mode that allows an application to save and restore critical system components when a
power loss is detected.
IEC60730 Software Package The IEC60730 MSP430 software package was developed to help
customers comply with IEC 60730-1:2010 (Automatic Electrical Controls for Household and
Similar Use – Part 1: General Requirements) for up to Class B products, which includes
home appliances, arc detectors, power converters, power tools, e-bikes, and many others.
The IEC60730 MSP430 software package can be embedded in customer applications
running on MSP430 MCUs to help simplify the customer's certification efforts of functional
safety-compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
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Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost
microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating-point math library of scalar functions that are up to 26 times faster
than the standard MSP430 math functions. Mathlib is easy to integrate into your designs.
This library is free and is integrated in both Code Composer Studio IDE and IAR Embedded
Workbench IDE.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio (CCS) integrated development environment (IDE) supports all MSP
microcontroller devices. CCS comprises a suite of embedded software utilities used to
develop and debug embedded applications. It includes an optimizing C/C++ compiler, source
code editor, project build environment, debugger, profiler, and many other features.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the
MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which lets users quickly begin application development on MSP lowpower MCUs. Creating MCU software usually requires downloading the resulting binary
program to the MSP device for validation and debugging.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
8.4
Documentation Support
The following documents describe the MSP430FR235x microcontrollers. Copies of these documents are
available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for links to the product folders, see Section 8.5). In the upper right corner, click the
"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if
any). For change details, check the revision history of any revised document.
User's Guides
MSP430FR4xx and MSP430FR2xx Family User's Guide
peripherals available in this device family.
Detailed description of all modules and
MSP430 FRAM Device Bootloader (BSL) User's Guide The bootloader (BSL) on MSP430 MCUs lets
users communicate with embedded memory in the MSP430 MCU during the prototyping
phase, final production, and in service. Both the programmable memory (FRAM memory)
and the data memory (RAM) can be modified as required.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
110
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SLASEC4A – MAY 2018 – REVISED JUNE 2018
Application Reports
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs: (1) Component-level ESD testing and system-level ESD testing, their differences
and why component-level ESD rating does not ensure system-level robustness. (2) General
design guidelines for system-level ESD protection at different levels including enclosures,
cables, PCB layout, and on-board ESD protection devices. (3) Introduction to System
Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD
protection to achieve system-level ESD robustness, with example simulations and test
results. A few real-world system-level ESD protection design examples and their results are
also discussed.
8.5
Related Links
Table 8-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 8-2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FR2355
Click here
Click here
Click here
Click here
Click here
MSP430FR2353
Click here
Click here
Click here
Click here
Click here
MSP430FR2155
Click here
Click here
Click here
Click here
Click here
MSP430FR2153
Click here
Click here
Click here
Click here
Click here
8.6
Trademarks
LaunchPad, MSP430, MSP430Ware, Code Composer Studio, E2E, EnergyTrace, ULP Advisor are
trademarks of Texas Instruments.
8.7
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation.
112
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PACKAGE OPTION ADDENDUM
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9-Jun-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR2153TDBT
PREVIEW
TSSOP
DBT
38
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
430FR2153
MSP430FR2153TDBTR
PREVIEW
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
430FR2153
MSP430FR2153TPT
PREVIEW
LQFP
PT
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
430FR2153
MSP430FR2153TPTR
PREVIEW
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
430FR2153
MSP430FR2153TRHAR
PREVIEW
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
FR2153
MSP430FR2153TRHAT
PREVIEW
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
FR2153
MSP430FR2155TDBT
PREVIEW
TSSOP
DBT
38
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
430FR2155
MSP430FR2155TDBTR
PREVIEW
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
430FR2155
MSP430FR2155TPT
PREVIEW
LQFP
PT
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
430FR2155
MSP430FR2155TPTR
PREVIEW
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
430FR2155
MSP430FR2155TRHAR
PREVIEW
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
FR2155
MSP430FR2155TRHAT
PREVIEW
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
FR2155
MSP430FR2353TDBT
PREVIEW
TSSOP
DBT
38
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
430FR2353
MSP430FR2353TDBTR
PREVIEW
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
430FR2353
MSP430FR2353TPT
PREVIEW
LQFP
PT
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
430FR2353
MSP430FR2353TPTR
PREVIEW
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
430FR2353
MSP430FR2353TRHAR
PREVIEW
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
FR2353
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
9-Jun-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR2353TRHAT
PREVIEW
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
FR2353
MSP430FR2355TDBT
PREVIEW
TSSOP
DBT
38
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
430FR2355
MSP430FR2355TDBTR
PREVIEW
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
430FR2355
MSP430FR2355TPT
PREVIEW
LQFP
PT
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
430FR2355
MSP430FR2355TPTR
PREVIEW
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
430FR2355
MSP430FR2355TRHAR
PREVIEW
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
FR2355
MSP430FR2355TRHAT
PREVIEW
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
FR2355
XMS430FR2355TDBTR
ACTIVE
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
X430FR2355
XMS430FR2355TPTR
ACTIVE
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
XFR2355
XMS430FR2355TRHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
X430
FR2355
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
9-Jun-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MSP430FR2155TDBTR
Package Package Pins
Type Drawing
TSSOP
DBT
38
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FR2155TDBTR
TSSOP
DBT
38
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
1,45
1,35
Seating Plane
1,60 MAX
0°– 7°
0,75
0,45
0,10
4040052 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
This may also be a thermally enhanced plastic package with leads conected to the die pads.
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• DALLAS, TEXAS 75265
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